From: Your Name <you@example.com>
Date: Thu, 17 Jun 2021 02:58:45 +0000 (+0200)
Subject: init
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e6688bedda4ec368c37fff415b975e4690a20f91;p=clocked_tdc.git

init
---

e6688bedda4ec368c37fff415b975e4690a20f91
diff --git a/._s1.clpf b/._s1.clpf
new file mode 100644
index 0000000..e86ce85
--- /dev/null
+++ b/._s1.clpf
@@ -0,0 +1,18 @@
+U trig_gate0 110 244 73
+U tdc_ch0 247 119 138
+U tdc2 66 26 255
+U tdc0 115 59 252
+U tdc22 101 224 55
+U gate2 238 76 83
+U tdc3 112 247 17
+U trig3 53 219 7
+U dec3 86 255 151
+U tdc0_neg 170 243 245
+U hades_trig 216 167 1
+U hades_tdc_pos 224 5 46
+U hades_tdc_neg 0 76 253
+U hades_dec_pos 122 134 206
+U hades_dec_neg 57 6 226
+U lvl1_dec 47 253 157
+U lvl1_pad 249 5 48
+U lvl1_tdc 253 230 130
diff --git a/.floorplanner.ini b/.floorplanner.ini
new file mode 100644
index 0000000..bb36624
--- /dev/null
+++ b/.floorplanner.ini
@@ -0,0 +1,14 @@
+[General]
+showNCD=true
+showPgroups=true
+showCongestion=false
+showConnsSelect=true
+showConnsBetween=true
+showConnsOutside=true
+showLPF=true
+showREGIONs=true
+showUGROUPs=true
+showPARITIONs=true
+showLogicalConnections=false
+dontShowBBoxOverlapWarning=false
+sceneInViewRect=@Variant(\0\0\0\x14\0\0\0\0\0\0\0\0@\xf1\x63\xce\xc1%a\xc2@\xfa! X\n8N@\xe6\x42PSc\f~)
diff --git a/.recovery b/.recovery
new file mode 100644
index 0000000..c259e92
--- /dev/null
+++ b/.recovery
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="s1" device="LFE5UM5G-45F-8BG381C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="trb5_tb" top="top_tf"/>
+        <Source name="top.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="pll0/pll0.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="pll1/pll1.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="fifo32dc/fifo32dc.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/intface.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/modem.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/rxcver.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/txmitt.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/uart_top.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/UART_VerilogWrapper_TOP.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="pll8/pll8.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="pll_random/pll_random.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="modules.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="modules2.v" type="Verilog" type_short="Verilog">
+            <Options>
+                <Option name="include path" value="tdc_channel_fifo_out"/>
+            </Options>
+        </Source>
+        <Source name="fifo_colector.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="fifo40_dc/fifo40_dc.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="top2.v" type="Verilog" type_short="Verilog">
+            <Options top_module="top_tf"/>
+        </Source>
+        <Source name="trb5_tb.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="endp_dummy.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="endp_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="hades_modules.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="hades_modules2.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="hades_colector.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="s1.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="s11.sty"/>
+</BaliProject>
diff --git a/.run_manager.ini b/.run_manager.ini
new file mode 100644
index 0000000..06e8e36
--- /dev/null
+++ b/.run_manager.ini
@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1f\0\0\x1\x1c\0\0\0\xf3\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/.setting.ini b/.setting.ini
new file mode 100644
index 0000000..8ba7e6f
--- /dev/null
+++ b/.setting.ini
@@ -0,0 +1,5 @@
+[General]
+PAR.auto_tasks=PARTrace, IOTiming
+Map.auto_tasks=MapTrace
+Export.auto_tasks=TimingSimFileVlg, TimingSimFileVHD
+AutoAssign=true
diff --git a/.spread_sheet.ini b/.spread_sheet.ini
new file mode 100644
index 0000000..6c511f4
--- /dev/null
+++ b/.spread_sheet.ini
@@ -0,0 +1,3 @@
+[General]
+COLUMN_POS_INFO_NAME_-1_0=Prioritize
+COLUMN_POS_INFO_NAME_-1_1=PIO Register
diff --git a/.spreadsheet_view.ini b/.spreadsheet_view.ini
new file mode 100644
index 0000000..9e5c03f
--- /dev/null
+++ b/.spreadsheet_view.ini
@@ -0,0 +1,78 @@
+[General]
+pin_sort_type=0
+pin_sort_ascending=true
+sig_sort_type=0
+sig_sort_ascending=true
+active_Sheet=Port Assignments
+
+[Port%20Assignments]
+Name="296,0"
+Group%20By="72,1"
+Pin="69,2"
+BANK="55,3"
+BANK_VCC="76,4"
+VREF="51,5"
+IO_TYPE="151,6"
+PULLMODE="99,7"
+DRIVE="57,8"
+SLEWRATE="91,9"
+CLAMP="60,10"
+OPENDRAIN="83,11"
+DIFFRESISTOR="94,12"
+DIFFDRIVE="76,13"
+HYSTERESIS="84,14"
+TERMINATION="90,15"
+Outload%20%28pF%29="88,16"
+MaxSkew="70,17"
+Clock%20Load%20Only="103,18"
+SwitchingID="85,19"
+Ground%20plane%20PCB%20noise%20%28mV%29="166,20"
+Power%20plane%20PCB%20noise%20%28mV%29="159,21"
+SSO%20Allowance%28%25%29="113,22"
+sort_columns="Name,Ascending"
+
+[Pin%20Assignments]
+Pin="92,0"
+Pad%20Name="77,1"
+Dual%20Function="184,2"
+Polarity="65,3"
+BANK="0,4"
+BANK_VCC="76,5"
+IO_TYPE="151,6"
+Signal%20Name="323,7"
+Signal%20Type="111,8"
+sort_columns="Pin,Ascending"
+
+[Clock%20Resource]
+Clock%20Type="100,ELLIPSIS"
+Clock%20Name="100,ELLIPSIS"
+Selection="100,ELLIPSIS"
+Quadrant="100,ELLIPSIS"
+
+[Global%20Preferences]
+Preference%20Name="241,ELLIPSIS"
+Preference%20Value="268,ELLIPSIS"
+
+[Cell%20Mapping]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Din\Dout="100,ELLIPSIS"
+PIO%20Register="100,ELLIPSIS"
+
+[Route%20Priority]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Prioritize="100,ELLIPSIS"
+
+[Timing%20Preferences]
+Preference%20Name="168,ELLIPSIS"
+Preference%20Value="88,ELLIPSIS"
+Preference%20Unit="79,ELLIPSIS"
+
+[Group]
+Group%20Type\Name="689,ELLIPSIS"
+Value="177,ELLIPSIS"
+
+[Misc%20Preferences]
+Preference%20Name="207,ELLIPSIS"
+Preference%20Value="84,ELLIPSIS"
diff --git a/endp_dummy.vhd b/endp_dummy.vhd
new file mode 100644
index 0000000..a31ea22
--- /dev/null
+++ b/endp_dummy.vhd
@@ -0,0 +1,83 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.math_real.uniform;
+use IEEE.math_real.floor;
+
+entity endp_dummy is
+port (
+    CLK : in std_logic;
+    RESET : in std_logic;
+    
+    TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+    
+    LVL1_TRG_DATA_VALID_IN : in std_logic;
+    LVL1_INVALID_TRG_IN : in std_logic;
+    
+    FEE_TRG_RELEASE_OUT : out std_logic;
+    FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+    FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+    FEE_DATA_WRITE_OUT : out std_logic;
+    FEE_DATAFINISHED_OUT : out std_logic;
+    FEE_DATA_ALMOST_FULL_IN : in std_logic
+);
+end endp_dummy;
+
+architecture Behavioral of endp_dummy is
+
+begin
+
+process
+    variable s1, s2 : positive := 123;
+    variable x : real;
+    variable y : integer;
+    variable t : time;
+begin
+
+    FEE_DATA_OUT <= x"0000_0000";
+    FEE_DATA_WRITE_OUT <= '0';
+    FEE_TRG_RELEASE_OUT <= '0';
+    FEE_DATAFINISHED_OUT <= '0';
+
+    wait until rising_edge(LVL1_TRG_DATA_VALID_IN);
+    
+    if (LVL1_INVALID_TRG_IN = '0') then
+    
+        uniform(s1, s2, x);
+        t := (x * 100.0 + 5.0) * (1 ns);
+        wait for t;
+        
+        uniform(s1, s2, x);
+        y := integer(floor(x * 100.0 + 1.0));
+        
+        for i in 1 to y loop
+            wait until rising_edge(CLK);
+            FEE_DATA_OUT <= std_logic_vector(to_unsigned(i, 32));
+            FEE_DATA_WRITE_OUT <= '1';
+        end loop;
+        
+        wait until rising_edge(CLK);
+        FEE_DATA_OUT <= x"abcd_abcd";
+        FEE_DATA_WRITE_OUT <= '1';
+        FEE_DATAFINISHED_OUT <= '1';
+        wait until rising_edge(CLK);
+        FEE_DATAFINISHED_OUT <= '0';
+        FEE_DATA_WRITE_OUT <= '0';
+        FEE_DATA_OUT <= x"0000_0000";
+        
+        wait until rising_edge(CLK);
+        wait until rising_edge(CLK);
+        wait until rising_edge(CLK);
+        FEE_TRG_RELEASE_OUT <= '1';
+        wait until rising_edge(CLK);
+        FEE_TRG_RELEASE_OUT <= '0';
+      
+        
+    end if;
+    
+end process;
+
+
+end Behavioral;
diff --git a/endp_handler.vhd b/endp_handler.vhd
new file mode 100644
index 0000000..e0b247e
--- /dev/null
+++ b/endp_handler.vhd
@@ -0,0 +1,72 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.math_real.uniform;
+use IEEE.math_real.floor;
+
+
+
+entity endp_handler is
+Port (
+    CLK : in std_logic;
+    RESET : in std_logic;
+    
+    TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+    
+    LVL1_TRG_DATA_VALID_OUT : out std_logic;
+    LVL1_INVALID_TRG_OUT : out std_logic;
+    
+    FEE_TRG_RELEASE_IN : in std_logic;
+    FEE_TRG_STATUSBITS_IN : in std_logic_vector(31 downto 0);
+    FEE_DATA_IN : in std_logic_vector(31 downto 0);
+    FEE_DATA_WRITE_IN : in std_logic;
+    FEE_DATAFINISHED_IN : in std_logic;
+    FEE_DATA_ALMOST_FULL_OUT : out std_logic
+);
+end endp_handler;
+
+architecture Behavioral of endp_handler is
+
+begin
+
+
+process
+    variable s1, s2 : positive := 123;
+    variable x : real;
+    variable y : integer;
+    variable y_slv : std_logic_vector(7 downto 0);
+begin
+
+    LVL1_TRG_DATA_VALID_OUT <= '0';
+    LVL1_INVALID_TRG_OUT <= '0';
+    
+    wait until rising_edge(TRG_TIMING_TRG_RECEIVED_IN);
+    
+    uniform(s1, s2, x);
+    y := integer(floor(x * 5.0 + 1.0));
+    for i in 0 to y loop
+        wait until rising_edge(CLK);
+    end loop;
+    
+    
+    uniform(s1, s2, x);
+    y := integer(floor(x * 5.0 + 1.0));
+    y_slv := std_logic_vector(to_unsigned(y, 8));
+    
+    
+    wait until rising_edge(CLK);
+    LVL1_TRG_DATA_VALID_OUT <= '1';
+    
+    if (y_slv(0) = '1') then
+        LVL1_INVALID_TRG_OUT <= '0';
+    else
+        LVL1_INVALID_TRG_OUT <= '1';
+    end if;
+    
+    wait until rising_edge(CLK);
+    
+end process;
+
+end Behavioral;
diff --git a/fifo32dc/fifo32dc.cst b/fifo32dc/fifo32dc.cst
new file mode 100644
index 0000000..300db0f
--- /dev/null
+++ b/fifo32dc/fifo32dc.cst
@@ -0,0 +1,3 @@
+Date=09/13/2020
+Time=16:38:25
+
diff --git a/fifo32dc/fifo32dc.edn b/fifo32dc/fifo32dc.edn
new file mode 100644
index 0000000..f97f809
--- /dev/null
+++ b/fifo32dc/fifo32dc.edn
@@ -0,0 +1,3089 @@
+(edif fifo32dc
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 9 13 16 38 29)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell OR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell PDPW16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DI35
+            (direction INPUT))
+          (port DI34
+            (direction INPUT))
+          (port DI33
+            (direction INPUT))
+          (port DI32
+            (direction INPUT))
+          (port DI31
+            (direction INPUT))
+          (port DI30
+            (direction INPUT))
+          (port DI29
+            (direction INPUT))
+          (port DI28
+            (direction INPUT))
+          (port DI27
+            (direction INPUT))
+          (port DI26
+            (direction INPUT))
+          (port DI25
+            (direction INPUT))
+          (port DI24
+            (direction INPUT))
+          (port DI23
+            (direction INPUT))
+          (port DI22
+            (direction INPUT))
+          (port DI21
+            (direction INPUT))
+          (port DI20
+            (direction INPUT))
+          (port DI19
+            (direction INPUT))
+          (port DI18
+            (direction INPUT))
+          (port DI17
+            (direction INPUT))
+          (port DI16
+            (direction INPUT))
+          (port DI15
+            (direction INPUT))
+          (port DI14
+            (direction INPUT))
+          (port DI13
+            (direction INPUT))
+          (port DI12
+            (direction INPUT))
+          (port DI11
+            (direction INPUT))
+          (port DI10
+            (direction INPUT))
+          (port DI9
+            (direction INPUT))
+          (port DI8
+            (direction INPUT))
+          (port DI7
+            (direction INPUT))
+          (port DI6
+            (direction INPUT))
+          (port DI5
+            (direction INPUT))
+          (port DI4
+            (direction INPUT))
+          (port DI3
+            (direction INPUT))
+          (port DI2
+            (direction INPUT))
+          (port DI1
+            (direction INPUT))
+          (port DI0
+            (direction INPUT))
+          (port ADW8
+            (direction INPUT))
+          (port ADW7
+            (direction INPUT))
+          (port ADW6
+            (direction INPUT))
+          (port ADW5
+            (direction INPUT))
+          (port ADW4
+            (direction INPUT))
+          (port ADW3
+            (direction INPUT))
+          (port ADW2
+            (direction INPUT))
+          (port ADW1
+            (direction INPUT))
+          (port ADW0
+            (direction INPUT))
+          (port BE3
+            (direction INPUT))
+          (port BE2
+            (direction INPUT))
+          (port BE1
+            (direction INPUT))
+          (port BE0
+            (direction INPUT))
+          (port CEW
+            (direction INPUT))
+          (port CLKW
+            (direction INPUT))
+          (port CSW2
+            (direction INPUT))
+          (port CSW1
+            (direction INPUT))
+          (port CSW0
+            (direction INPUT))
+          (port ADR13
+            (direction INPUT))
+          (port ADR12
+            (direction INPUT))
+          (port ADR11
+            (direction INPUT))
+          (port ADR10
+            (direction INPUT))
+          (port ADR9
+            (direction INPUT))
+          (port ADR8
+            (direction INPUT))
+          (port ADR7
+            (direction INPUT))
+          (port ADR6
+            (direction INPUT))
+          (port ADR5
+            (direction INPUT))
+          (port ADR4
+            (direction INPUT))
+          (port ADR3
+            (direction INPUT))
+          (port ADR2
+            (direction INPUT))
+          (port ADR1
+            (direction INPUT))
+          (port ADR0
+            (direction INPUT))
+          (port CER
+            (direction INPUT))
+          (port OCER
+            (direction INPUT))
+          (port CLKR
+            (direction INPUT))
+          (port CSR2
+            (direction INPUT))
+          (port CSR1
+            (direction INPUT))
+          (port CSR0
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port DO35
+            (direction OUTPUT))
+          (port DO34
+            (direction OUTPUT))
+          (port DO33
+            (direction OUTPUT))
+          (port DO32
+            (direction OUTPUT))
+          (port DO31
+            (direction OUTPUT))
+          (port DO30
+            (direction OUTPUT))
+          (port DO29
+            (direction OUTPUT))
+          (port DO28
+            (direction OUTPUT))
+          (port DO27
+            (direction OUTPUT))
+          (port DO26
+            (direction OUTPUT))
+          (port DO25
+            (direction OUTPUT))
+          (port DO24
+            (direction OUTPUT))
+          (port DO23
+            (direction OUTPUT))
+          (port DO22
+            (direction OUTPUT))
+          (port DO21
+            (direction OUTPUT))
+          (port DO20
+            (direction OUTPUT))
+          (port DO19
+            (direction OUTPUT))
+          (port DO18
+            (direction OUTPUT))
+          (port DO17
+            (direction OUTPUT))
+          (port DO16
+            (direction OUTPUT))
+          (port DO15
+            (direction OUTPUT))
+          (port DO14
+            (direction OUTPUT))
+          (port DO13
+            (direction OUTPUT))
+          (port DO12
+            (direction OUTPUT))
+          (port DO11
+            (direction OUTPUT))
+          (port DO10
+            (direction OUTPUT))
+          (port DO9
+            (direction OUTPUT))
+          (port DO8
+            (direction OUTPUT))
+          (port DO7
+            (direction OUTPUT))
+          (port DO6
+            (direction OUTPUT))
+          (port DO5
+            (direction OUTPUT))
+          (port DO4
+            (direction OUTPUT))
+          (port DO3
+            (direction OUTPUT))
+          (port DO2
+            (direction OUTPUT))
+          (port DO1
+            (direction OUTPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell fifo32dc
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(31:0)") 32)
+            (direction INPUT))
+          (port WrClock
+            (direction INPUT))
+          (port RdClock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port RPReset
+            (direction INPUT))
+          (port (array (rename Q "Q(31:0)") 32)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t20
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t19
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance OR2_t18
+            (viewRef view1 
+              (cellRef OR2)))
+          (instance XOR2_t17
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t16
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t15
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t14
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t13
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t12
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t11
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t10
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t9
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t8
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t7
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t6
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t5
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t4
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t3
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t1
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance LUT4_23
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_22
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_21
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_20
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_19
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_18
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_17
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_16
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_15
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_14
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_13
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_12
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_11
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_10
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_9
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_8
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_7
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_6
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_5
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_4
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_3
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0410")))
+          (instance LUT4_2
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x1004")))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0140")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x4001")))
+          (instance pdp_ram_0_0_0
+            (viewRef view1 
+              (cellRef PDPW16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo32dc.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_R
+              (string "0b000"))
+            (property CSDECODE_W
+              (string "0b001"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "SYNC"))
+            (property REGMODE
+              (string "NOREG"))
+            (property DATA_WIDTH_R
+              (string "36"))
+            (property DATA_WIDTH_W
+              (string "36")))
+          (instance FF_101
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_100
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_99
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_98
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_97
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_96
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_95
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_94
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_93
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_92
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_91
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_90
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_89
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_88
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_87
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_86
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_85
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_84
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_83
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance w_gctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance empty_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance empty_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance full_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance full_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t20))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_0))
+              (portRef B (instanceRef AND2_t19))))
+          (net w_g2b_xor_cluster_1
+            (joined
+              (portRef AD2 (instanceRef LUT4_14))
+              (portRef DO0 (instanceRef LUT4_22))
+              (portRef AD2 (instanceRef LUT4_16))
+              (portRef AD2 (instanceRef LUT4_15))))
+          (net r_g2b_xor_cluster_1
+            (joined
+              (portRef AD2 (instanceRef LUT4_4))
+              (portRef DO0 (instanceRef LUT4_12))
+              (portRef AD2 (instanceRef LUT4_6))
+              (portRef AD2 (instanceRef LUT4_5))))
+          (net w_gdata_0
+            (joined
+              (portRef D (instanceRef FF_91))
+              (portRef Z (instanceRef XOR2_t17))))
+          (net w_gdata_1
+            (joined
+              (portRef D (instanceRef FF_90))
+              (portRef Z (instanceRef XOR2_t16))))
+          (net w_gdata_2
+            (joined
+              (portRef D (instanceRef FF_89))
+              (portRef Z (instanceRef XOR2_t15))))
+          (net w_gdata_3
+            (joined
+              (portRef D (instanceRef FF_88))
+              (portRef Z (instanceRef XOR2_t14))))
+          (net w_gdata_4
+            (joined
+              (portRef D (instanceRef FF_87))
+              (portRef Z (instanceRef XOR2_t13))))
+          (net w_gdata_5
+            (joined
+              (portRef D (instanceRef FF_86))
+              (portRef Z (instanceRef XOR2_t12))))
+          (net w_gdata_6
+            (joined
+              (portRef D (instanceRef FF_85))
+              (portRef Z (instanceRef XOR2_t11))))
+          (net w_gdata_7
+            (joined
+              (portRef D (instanceRef FF_84))
+              (portRef Z (instanceRef XOR2_t10))))
+          (net w_gdata_8
+            (joined
+              (portRef D (instanceRef FF_83))
+              (portRef Z (instanceRef XOR2_t9))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_81))
+              (portRef ADW0 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_80))
+              (portRef ADW1 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_79))
+              (portRef ADW2 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_78))
+              (portRef ADW3 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_77))
+              (portRef ADW4 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_76))
+              (portRef ADW5 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_75))
+              (portRef ADW6 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_74))
+              (portRef ADW7 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_73))
+              (portRef ADW8 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_72))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))))
+          (net r_gdata_0
+            (joined
+              (portRef D (instanceRef FF_61))
+              (portRef Z (instanceRef XOR2_t8))))
+          (net r_gdata_1
+            (joined
+              (portRef D (instanceRef FF_60))
+              (portRef Z (instanceRef XOR2_t7))))
+          (net r_gdata_2
+            (joined
+              (portRef D (instanceRef FF_59))
+              (portRef Z (instanceRef XOR2_t6))))
+          (net r_gdata_3
+            (joined
+              (portRef D (instanceRef FF_58))
+              (portRef Z (instanceRef XOR2_t5))))
+          (net r_gdata_4
+            (joined
+              (portRef D (instanceRef FF_57))
+              (portRef Z (instanceRef XOR2_t4))))
+          (net r_gdata_5
+            (joined
+              (portRef D (instanceRef FF_56))
+              (portRef Z (instanceRef XOR2_t3))))
+          (net r_gdata_6
+            (joined
+              (portRef D (instanceRef FF_55))
+              (portRef Z (instanceRef XOR2_t2))))
+          (net r_gdata_7
+            (joined
+              (portRef D (instanceRef FF_54))
+              (portRef Z (instanceRef XOR2_t1))))
+          (net r_gdata_8
+            (joined
+              (portRef D (instanceRef FF_53))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net rptr_0
+            (joined
+              (portRef Q (instanceRef FF_51))
+              (portRef ADR5 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_1
+            (joined
+              (portRef Q (instanceRef FF_50))
+              (portRef ADR6 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_2
+            (joined
+              (portRef Q (instanceRef FF_49))
+              (portRef ADR7 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_3
+            (joined
+              (portRef Q (instanceRef FF_48))
+              (portRef ADR8 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_4
+            (joined
+              (portRef Q (instanceRef FF_47))
+              (portRef ADR9 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_5
+            (joined
+              (portRef Q (instanceRef FF_46))
+              (portRef ADR10 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_6
+            (joined
+              (portRef Q (instanceRef FF_45))
+              (portRef ADR11 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_7
+            (joined
+              (portRef Q (instanceRef FF_44))
+              (portRef ADR12 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_8
+            (joined
+              (portRef Q (instanceRef FF_43))
+              (portRef ADR13 (instanceRef pdp_ram_0_0_0))))
+          (net rptr_9
+            (joined
+              (portRef Q (instanceRef FF_42))
+              (portRef AD3 (instanceRef LUT4_3))
+              (portRef AD3 (instanceRef LUT4_2))))
+          (net w_gcount_0
+            (joined
+              (portRef D (instanceRef FF_41))
+              (portRef Q (instanceRef FF_91))))
+          (net w_gcount_1
+            (joined
+              (portRef D (instanceRef FF_40))
+              (portRef Q (instanceRef FF_90))))
+          (net w_gcount_2
+            (joined
+              (portRef D (instanceRef FF_39))
+              (portRef Q (instanceRef FF_89))))
+          (net w_gcount_3
+            (joined
+              (portRef D (instanceRef FF_38))
+              (portRef Q (instanceRef FF_88))))
+          (net w_gcount_4
+            (joined
+              (portRef D (instanceRef FF_37))
+              (portRef Q (instanceRef FF_87))))
+          (net w_gcount_5
+            (joined
+              (portRef D (instanceRef FF_36))
+              (portRef Q (instanceRef FF_86))))
+          (net w_gcount_6
+            (joined
+              (portRef D (instanceRef FF_35))
+              (portRef Q (instanceRef FF_85))))
+          (net w_gcount_7
+            (joined
+              (portRef D (instanceRef FF_34))
+              (portRef Q (instanceRef FF_84))))
+          (net w_gcount_8
+            (joined
+              (portRef D (instanceRef FF_33))
+              (portRef Q (instanceRef FF_83))))
+          (net w_gcount_9
+            (joined
+              (portRef D (instanceRef FF_32))
+              (portRef Q (instanceRef FF_82))))
+          (net r_gcount_0
+            (joined
+              (portRef D (instanceRef FF_31))
+              (portRef Q (instanceRef FF_61))))
+          (net r_gcount_1
+            (joined
+              (portRef D (instanceRef FF_30))
+              (portRef Q (instanceRef FF_60))))
+          (net r_gcount_2
+            (joined
+              (portRef D (instanceRef FF_29))
+              (portRef Q (instanceRef FF_59))))
+          (net r_gcount_3
+            (joined
+              (portRef D (instanceRef FF_28))
+              (portRef Q (instanceRef FF_58))))
+          (net r_gcount_4
+            (joined
+              (portRef D (instanceRef FF_27))
+              (portRef Q (instanceRef FF_57))))
+          (net r_gcount_5
+            (joined
+              (portRef D (instanceRef FF_26))
+              (portRef Q (instanceRef FF_56))))
+          (net r_gcount_6
+            (joined
+              (portRef D (instanceRef FF_25))
+              (portRef Q (instanceRef FF_55))))
+          (net r_gcount_7
+            (joined
+              (portRef D (instanceRef FF_24))
+              (portRef Q (instanceRef FF_54))))
+          (net r_gcount_8
+            (joined
+              (portRef D (instanceRef FF_23))
+              (portRef Q (instanceRef FF_53))))
+          (net r_gcount_9
+            (joined
+              (portRef D (instanceRef FF_22))
+              (portRef Q (instanceRef FF_52))))
+          (net w_gcount_r20
+            (joined
+              (portRef Q (instanceRef FF_21))
+              (portRef AD1 (instanceRef LUT4_14))))
+          (net w_gcount_r0
+            (joined
+              (portRef D (instanceRef FF_21))
+              (portRef Q (instanceRef FF_41))))
+          (net w_gcount_r21
+            (joined
+              (portRef Q (instanceRef FF_20))
+              (portRef AD1 (instanceRef LUT4_15))
+              (portRef AD0 (instanceRef LUT4_14))))
+          (net w_gcount_r1
+            (joined
+              (portRef D (instanceRef FF_20))
+              (portRef Q (instanceRef FF_40))))
+          (net w_gcount_r22
+            (joined
+              (portRef Q (instanceRef FF_19))
+              (portRef AD3 (instanceRef LUT4_22))))
+          (net w_gcount_r2
+            (joined
+              (portRef D (instanceRef FF_19))
+              (portRef Q (instanceRef FF_39))))
+          (net w_gcount_r23
+            (joined
+              (portRef Q (instanceRef FF_18))
+              (portRef AD2 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_17))))
+          (net w_gcount_r3
+            (joined
+              (portRef D (instanceRef FF_18))
+              (portRef Q (instanceRef FF_38))))
+          (net w_gcount_r24
+            (joined
+              (portRef Q (instanceRef FF_17))
+              (portRef AD1 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_18))
+              (portRef AD2 (instanceRef LUT4_17))))
+          (net w_gcount_r4
+            (joined
+              (portRef D (instanceRef FF_17))
+              (portRef Q (instanceRef FF_37))))
+          (net w_gcount_r25
+            (joined
+              (portRef Q (instanceRef FF_16))
+              (portRef AD0 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_19))
+              (portRef AD2 (instanceRef LUT4_18))
+              (portRef AD1 (instanceRef LUT4_17))))
+          (net w_gcount_r5
+            (joined
+              (portRef D (instanceRef FF_16))
+              (portRef Q (instanceRef FF_36))))
+          (net w_gcount_r26
+            (joined
+              (portRef Q (instanceRef FF_15))
+              (portRef AD3 (instanceRef LUT4_23))
+              (portRef AD2 (instanceRef LUT4_19))
+              (portRef AD1 (instanceRef LUT4_18))))
+          (net w_gcount_r6
+            (joined
+              (portRef D (instanceRef FF_15))
+              (portRef Q (instanceRef FF_35))))
+          (net w_gcount_r27
+            (joined
+              (portRef Q (instanceRef FF_14))
+              (portRef AD2 (instanceRef LUT4_23))
+              (portRef AD3 (instanceRef LUT4_20))
+              (portRef AD1 (instanceRef LUT4_19))))
+          (net w_gcount_r7
+            (joined
+              (portRef D (instanceRef FF_14))
+              (portRef Q (instanceRef FF_34))))
+          (net w_gcount_r28
+            (joined
+              (portRef Q (instanceRef FF_13))
+              (portRef AD1 (instanceRef LUT4_23))
+              (portRef AD3 (instanceRef LUT4_21))
+              (portRef AD2 (instanceRef LUT4_20))))
+          (net w_gcount_r8
+            (joined
+              (portRef D (instanceRef FF_13))
+              (portRef Q (instanceRef FF_33))))
+          (net w_gcount_r29
+            (joined
+              (portRef Q (instanceRef FF_12))
+              (portRef AD0 (instanceRef LUT4_23))
+              (portRef AD2 (instanceRef LUT4_21))
+              (portRef AD1 (instanceRef LUT4_20))
+              (portRef AD1 (instanceRef LUT4_3))
+              (portRef AD1 (instanceRef LUT4_2))))
+          (net w_gcount_r9
+            (joined
+              (portRef D (instanceRef FF_12))
+              (portRef Q (instanceRef FF_32))))
+          (net r_gcount_w20
+            (joined
+              (portRef Q (instanceRef FF_11))
+              (portRef AD1 (instanceRef LUT4_4))))
+          (net r_gcount_w0
+            (joined
+              (portRef D (instanceRef FF_11))
+              (portRef Q (instanceRef FF_31))))
+          (net r_gcount_w21
+            (joined
+              (portRef Q (instanceRef FF_10))
+              (portRef AD1 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_4))))
+          (net r_gcount_w1
+            (joined
+              (portRef D (instanceRef FF_10))
+              (portRef Q (instanceRef FF_30))))
+          (net r_gcount_w22
+            (joined
+              (portRef Q (instanceRef FF_9))
+              (portRef AD3 (instanceRef LUT4_12))))
+          (net r_gcount_w2
+            (joined
+              (portRef D (instanceRef FF_9))
+              (portRef Q (instanceRef FF_29))))
+          (net r_gcount_w23
+            (joined
+              (portRef Q (instanceRef FF_8))
+              (portRef AD2 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_7))))
+          (net r_gcount_w3
+            (joined
+              (portRef D (instanceRef FF_8))
+              (portRef Q (instanceRef FF_28))))
+          (net r_gcount_w24
+            (joined
+              (portRef Q (instanceRef FF_7))
+              (portRef AD1 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_8))
+              (portRef AD2 (instanceRef LUT4_7))))
+          (net r_gcount_w4
+            (joined
+              (portRef D (instanceRef FF_7))
+              (portRef Q (instanceRef FF_27))))
+          (net r_gcount_w25
+            (joined
+              (portRef Q (instanceRef FF_6))
+              (portRef AD0 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_9))
+              (portRef AD2 (instanceRef LUT4_8))
+              (portRef AD1 (instanceRef LUT4_7))))
+          (net r_gcount_w5
+            (joined
+              (portRef D (instanceRef FF_6))
+              (portRef Q (instanceRef FF_26))))
+          (net r_gcount_w26
+            (joined
+              (portRef Q (instanceRef FF_5))
+              (portRef AD3 (instanceRef LUT4_13))
+              (portRef AD2 (instanceRef LUT4_9))
+              (portRef AD1 (instanceRef LUT4_8))))
+          (net r_gcount_w6
+            (joined
+              (portRef D (instanceRef FF_5))
+              (portRef Q (instanceRef FF_25))))
+          (net r_gcount_w27
+            (joined
+              (portRef Q (instanceRef FF_4))
+              (portRef AD2 (instanceRef LUT4_13))
+              (portRef AD3 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_9))))
+          (net r_gcount_w7
+            (joined
+              (portRef D (instanceRef FF_4))
+              (portRef Q (instanceRef FF_24))))
+          (net r_gcount_w28
+            (joined
+              (portRef Q (instanceRef FF_3))
+              (portRef AD1 (instanceRef LUT4_13))
+              (portRef AD3 (instanceRef LUT4_11))
+              (portRef AD2 (instanceRef LUT4_10))))
+          (net r_gcount_w8
+            (joined
+              (portRef D (instanceRef FF_3))
+              (portRef Q (instanceRef FF_23))))
+          (net r_gcount_w29
+            (joined
+              (portRef Q (instanceRef FF_2))
+              (portRef AD0 (instanceRef LUT4_13))
+              (portRef AD2 (instanceRef LUT4_11))
+              (portRef AD1 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef AD1 (instanceRef LUT4_0))))
+          (net r_gcount_w9
+            (joined
+              (portRef D (instanceRef FF_2))
+              (portRef Q (instanceRef FF_22))))
+          (net rRst
+            (joined
+              (portRef PD (instanceRef FF_1))
+              (portRef Z (instanceRef OR2_t18))
+              (portRef PD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_101))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_100))))
+          (net w_gctr_ci
+            (joined
+              (portRef CIN (instanceRef w_gctr_0))
+              (portRef COUT (instanceRef w_gctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_99))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_98))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef w_gctr_1))
+              (portRef COUT (instanceRef w_gctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_gctr_2))
+              (portRef D (instanceRef FF_97))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_gctr_2))
+              (portRef D (instanceRef FF_96))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef w_gctr_2))
+              (portRef COUT (instanceRef w_gctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_gctr_3))
+              (portRef D (instanceRef FF_95))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_gctr_3))
+              (portRef D (instanceRef FF_94))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef w_gctr_3))
+              (portRef COUT (instanceRef w_gctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_gctr_4))
+              (portRef D (instanceRef FF_93))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_gctr_4))
+              (portRef D (instanceRef FF_92))))
+          (net co4
+            (joined
+              (portRef COUT (instanceRef w_gctr_4))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef w_gctr_4))
+              (portRef COUT (instanceRef w_gctr_3))))
+          (net wcount_9
+            (joined
+              (portRef A1 (instanceRef w_gctr_4))
+              (portRef B (instanceRef XOR2_t9))
+              (portRef AD2 (instanceRef LUT4_1))
+              (portRef AD2 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_92))
+              (portRef D (instanceRef FF_82))
+              (portRef D (instanceRef FF_72))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_71))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_70))))
+          (net r_gctr_ci
+            (joined
+              (portRef CIN (instanceRef r_gctr_0))
+              (portRef COUT (instanceRef r_gctr_cia))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_69))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_68))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_1))
+              (portRef COUT (instanceRef r_gctr_0))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_gctr_2))
+              (portRef D (instanceRef FF_67))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_gctr_2))
+              (portRef D (instanceRef FF_66))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_2))
+              (portRef COUT (instanceRef r_gctr_1))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_gctr_3))
+              (portRef D (instanceRef FF_65))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_gctr_3))
+              (portRef D (instanceRef FF_64))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_3))
+              (portRef COUT (instanceRef r_gctr_2))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_gctr_4))
+              (portRef D (instanceRef FF_63))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_gctr_4))
+              (portRef D (instanceRef FF_62))))
+          (net co4_1
+            (joined
+              (portRef COUT (instanceRef r_gctr_4))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_4))
+              (portRef COUT (instanceRef r_gctr_3))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_gctr_4))
+              (portRef B (instanceRef XOR2_t0))
+              (portRef AD2 (instanceRef LUT4_3))
+              (portRef AD2 (instanceRef LUT4_2))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_52))
+              (portRef D (instanceRef FF_42))))
+          (net rden_i
+            (joined
+              (portRef A1 (instanceRef empty_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t19))
+              (portRef OCER (instanceRef pdp_ram_0_0_0))
+              (portRef CER (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef B1 (instanceRef empty_cmp_ci_a))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef empty_cmp_0))
+              (portRef COUT (instanceRef empty_cmp_ci_a))))
+          (net wcount_r0
+            (joined
+              (portRef B0 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_14))))
+          (net wcount_r1
+            (joined
+              (portRef B1 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_15))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef empty_cmp_0))
+              (portRef A (instanceRef XOR2_t8))
+              (portRef Q (instanceRef FF_71))
+              (portRef D (instanceRef FF_51))
+              (portRef A0 (instanceRef r_gctr_0))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef empty_cmp_0))
+              (portRef B (instanceRef XOR2_t8))
+              (portRef A (instanceRef XOR2_t7))
+              (portRef Q (instanceRef FF_70))
+              (portRef D (instanceRef FF_50))
+              (portRef A1 (instanceRef r_gctr_0))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_1))
+              (portRef COUT (instanceRef empty_cmp_0))))
+          (net wcount_r2
+            (joined
+              (portRef B0 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_16))))
+          (net wcount_r3
+            (joined
+              (portRef B1 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_17))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef empty_cmp_1))
+              (portRef B (instanceRef XOR2_t7))
+              (portRef A (instanceRef XOR2_t6))
+              (portRef Q (instanceRef FF_69))
+              (portRef D (instanceRef FF_49))
+              (portRef A0 (instanceRef r_gctr_1))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef empty_cmp_1))
+              (portRef B (instanceRef XOR2_t6))
+              (portRef A (instanceRef XOR2_t5))
+              (portRef Q (instanceRef FF_68))
+              (portRef D (instanceRef FF_48))
+              (portRef A1 (instanceRef r_gctr_1))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_2))
+              (portRef COUT (instanceRef empty_cmp_1))))
+          (net wcount_r4
+            (joined
+              (portRef B0 (instanceRef empty_cmp_2))
+              (portRef DO0 (instanceRef LUT4_18))))
+          (net wcount_r5
+            (joined
+              (portRef B1 (instanceRef empty_cmp_2))
+              (portRef DO0 (instanceRef LUT4_19))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef empty_cmp_2))
+              (portRef B (instanceRef XOR2_t5))
+              (portRef A (instanceRef XOR2_t4))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_47))
+              (portRef A0 (instanceRef r_gctr_2))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef empty_cmp_2))
+              (portRef B (instanceRef XOR2_t4))
+              (portRef A (instanceRef XOR2_t3))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_46))
+              (portRef A1 (instanceRef r_gctr_2))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_3))
+              (portRef COUT (instanceRef empty_cmp_2))))
+          (net w_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef empty_cmp_3))
+              (portRef DO0 (instanceRef LUT4_23))
+              (portRef AD0 (instanceRef LUT4_17))
+              (portRef AD3 (instanceRef LUT4_16))
+              (portRef AD3 (instanceRef LUT4_15))
+              (portRef AD3 (instanceRef LUT4_14))))
+          (net wcount_r7
+            (joined
+              (portRef B1 (instanceRef empty_cmp_3))
+              (portRef DO0 (instanceRef LUT4_20))
+              (portRef AD0 (instanceRef LUT4_18))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef empty_cmp_3))
+              (portRef B (instanceRef XOR2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_45))
+              (portRef A0 (instanceRef r_gctr_3))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef empty_cmp_3))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef XOR2_t1))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_44))
+              (portRef A1 (instanceRef r_gctr_3))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_4))
+              (portRef COUT (instanceRef empty_cmp_3))))
+          (net wcount_r8
+            (joined
+              (portRef B0 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_21))
+              (portRef AD0 (instanceRef LUT4_19))))
+          (net empty_cmp_clr
+            (joined
+              (portRef B1 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_2))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef empty_cmp_4))
+              (portRef B (instanceRef XOR2_t1))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_43))
+              (portRef A0 (instanceRef r_gctr_4))))
+          (net empty_cmp_set
+            (joined
+              (portRef A1 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_3))))
+          (net empty_d
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef D (instanceRef FF_1))))
+          (net empty_d_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef empty_cmp_4))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef full_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t20))
+              (portRef CEW (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_101))
+              (portRef SP (instanceRef FF_100))
+              (portRef SP (instanceRef FF_99))
+              (portRef SP (instanceRef FF_98))
+              (portRef SP (instanceRef FF_97))
+              (portRef SP (instanceRef FF_96))
+              (portRef SP (instanceRef FF_95))
+              (portRef SP (instanceRef FF_94))
+              (portRef SP (instanceRef FF_93))
+              (portRef SP (instanceRef FF_92))
+              (portRef SP (instanceRef FF_91))
+              (portRef SP (instanceRef FF_90))
+              (portRef SP (instanceRef FF_89))
+              (portRef SP (instanceRef FF_88))
+              (portRef SP (instanceRef FF_87))
+              (portRef SP (instanceRef FF_86))
+              (portRef SP (instanceRef FF_85))
+              (portRef SP (instanceRef FF_84))
+              (portRef SP (instanceRef FF_83))
+              (portRef SP (instanceRef FF_82))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))
+              (portRef SP (instanceRef FF_77))
+              (portRef SP (instanceRef FF_76))
+              (portRef SP (instanceRef FF_75))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef B1 (instanceRef full_cmp_ci_a))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef full_cmp_0))
+              (portRef COUT (instanceRef full_cmp_ci_a))))
+          (net rcount_w0
+            (joined
+              (portRef B0 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_4))))
+          (net rcount_w1
+            (joined
+              (portRef B1 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_5))))
+          (net wcount_0
+            (joined
+              (portRef A0 (instanceRef full_cmp_0))
+              (portRef A (instanceRef XOR2_t17))
+              (portRef Q (instanceRef FF_101))
+              (portRef D (instanceRef FF_81))
+              (portRef A0 (instanceRef w_gctr_0))))
+          (net wcount_1
+            (joined
+              (portRef A1 (instanceRef full_cmp_0))
+              (portRef B (instanceRef XOR2_t17))
+              (portRef A (instanceRef XOR2_t16))
+              (portRef Q (instanceRef FF_100))
+              (portRef D (instanceRef FF_80))
+              (portRef A1 (instanceRef w_gctr_0))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_1))
+              (portRef COUT (instanceRef full_cmp_0))))
+          (net rcount_w2
+            (joined
+              (portRef B0 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_6))))
+          (net rcount_w3
+            (joined
+              (portRef B1 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_7))))
+          (net wcount_2
+            (joined
+              (portRef A0 (instanceRef full_cmp_1))
+              (portRef B (instanceRef XOR2_t16))
+              (portRef A (instanceRef XOR2_t15))
+              (portRef Q (instanceRef FF_99))
+              (portRef D (instanceRef FF_79))
+              (portRef A0 (instanceRef w_gctr_1))))
+          (net wcount_3
+            (joined
+              (portRef A1 (instanceRef full_cmp_1))
+              (portRef B (instanceRef XOR2_t15))
+              (portRef A (instanceRef XOR2_t14))
+              (portRef Q (instanceRef FF_98))
+              (portRef D (instanceRef FF_78))
+              (portRef A1 (instanceRef w_gctr_1))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_2))
+              (portRef COUT (instanceRef full_cmp_1))))
+          (net rcount_w4
+            (joined
+              (portRef B0 (instanceRef full_cmp_2))
+              (portRef DO0 (instanceRef LUT4_8))))
+          (net rcount_w5
+            (joined
+              (portRef B1 (instanceRef full_cmp_2))
+              (portRef DO0 (instanceRef LUT4_9))))
+          (net wcount_4
+            (joined
+              (portRef A0 (instanceRef full_cmp_2))
+              (portRef B (instanceRef XOR2_t14))
+              (portRef A (instanceRef XOR2_t13))
+              (portRef Q (instanceRef FF_97))
+              (portRef D (instanceRef FF_77))
+              (portRef A0 (instanceRef w_gctr_2))))
+          (net wcount_5
+            (joined
+              (portRef A1 (instanceRef full_cmp_2))
+              (portRef B (instanceRef XOR2_t13))
+              (portRef A (instanceRef XOR2_t12))
+              (portRef Q (instanceRef FF_96))
+              (portRef D (instanceRef FF_76))
+              (portRef A1 (instanceRef w_gctr_2))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_3))
+              (portRef COUT (instanceRef full_cmp_2))))
+          (net r_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef full_cmp_3))
+              (portRef DO0 (instanceRef LUT4_13))
+              (portRef AD0 (instanceRef LUT4_7))
+              (portRef AD3 (instanceRef LUT4_6))
+              (portRef AD3 (instanceRef LUT4_5))
+              (portRef AD3 (instanceRef LUT4_4))))
+          (net rcount_w7
+            (joined
+              (portRef B1 (instanceRef full_cmp_3))
+              (portRef DO0 (instanceRef LUT4_10))
+              (portRef AD0 (instanceRef LUT4_8))))
+          (net wcount_6
+            (joined
+              (portRef A0 (instanceRef full_cmp_3))
+              (portRef B (instanceRef XOR2_t12))
+              (portRef A (instanceRef XOR2_t11))
+              (portRef Q (instanceRef FF_95))
+              (portRef D (instanceRef FF_75))
+              (portRef A0 (instanceRef w_gctr_3))))
+          (net wcount_7
+            (joined
+              (portRef A1 (instanceRef full_cmp_3))
+              (portRef B (instanceRef XOR2_t11))
+              (portRef A (instanceRef XOR2_t10))
+              (portRef Q (instanceRef FF_94))
+              (portRef D (instanceRef FF_74))
+              (portRef A1 (instanceRef w_gctr_3))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_4))
+              (portRef COUT (instanceRef full_cmp_3))))
+          (net rcount_w8
+            (joined
+              (portRef B0 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_11))
+              (portRef AD0 (instanceRef LUT4_9))))
+          (net full_cmp_clr
+            (joined
+              (portRef B1 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wcount_8
+            (joined
+              (portRef A0 (instanceRef full_cmp_4))
+              (portRef B (instanceRef XOR2_t10))
+              (portRef A (instanceRef XOR2_t9))
+              (portRef Q (instanceRef FF_93))
+              (portRef D (instanceRef FF_73))
+              (portRef A0 (instanceRef w_gctr_4))))
+          (net full_cmp_set
+            (joined
+              (portRef A1 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+              (portRef BE3 (instanceRef pdp_ram_0_0_0))
+              (portRef BE2 (instanceRef pdp_ram_0_0_0))
+              (portRef BE1 (instanceRef pdp_ram_0_0_0))
+              (portRef BE0 (instanceRef pdp_ram_0_0_0))
+              (portRef C1 (instanceRef w_gctr_cia))
+              (portRef C0 (instanceRef w_gctr_cia))
+              (portRef D1 (instanceRef w_gctr_cia))
+              (portRef D0 (instanceRef w_gctr_cia))
+              (portRef B1 (instanceRef w_gctr_cia))
+              (portRef A1 (instanceRef w_gctr_cia))
+              (portRef D1 (instanceRef w_gctr_0))
+              (portRef D0 (instanceRef w_gctr_0))
+              (portRef C1 (instanceRef w_gctr_0))
+              (portRef C0 (instanceRef w_gctr_0))
+              (portRef D1 (instanceRef w_gctr_1))
+              (portRef D0 (instanceRef w_gctr_1))
+              (portRef C1 (instanceRef w_gctr_1))
+              (portRef C0 (instanceRef w_gctr_1))
+              (portRef D1 (instanceRef w_gctr_2))
+              (portRef D0 (instanceRef w_gctr_2))
+              (portRef C1 (instanceRef w_gctr_2))
+              (portRef C0 (instanceRef w_gctr_2))
+              (portRef D1 (instanceRef w_gctr_3))
+              (portRef D0 (instanceRef w_gctr_3))
+              (portRef C1 (instanceRef w_gctr_3))
+              (portRef C0 (instanceRef w_gctr_3))
+              (portRef D1 (instanceRef w_gctr_4))
+              (portRef D0 (instanceRef w_gctr_4))
+              (portRef C1 (instanceRef w_gctr_4))
+              (portRef C0 (instanceRef w_gctr_4))
+              (portRef C1 (instanceRef r_gctr_cia))
+              (portRef C0 (instanceRef r_gctr_cia))
+              (portRef D1 (instanceRef r_gctr_cia))
+              (portRef D0 (instanceRef r_gctr_cia))
+              (portRef B1 (instanceRef r_gctr_cia))
+              (portRef A1 (instanceRef r_gctr_cia))
+              (portRef D1 (instanceRef r_gctr_0))
+              (portRef D0 (instanceRef r_gctr_0))
+              (portRef C1 (instanceRef r_gctr_0))
+              (portRef C0 (instanceRef r_gctr_0))
+              (portRef D1 (instanceRef r_gctr_1))
+              (portRef D0 (instanceRef r_gctr_1))
+              (portRef C1 (instanceRef r_gctr_1))
+              (portRef C0 (instanceRef r_gctr_1))
+              (portRef D1 (instanceRef r_gctr_2))
+              (portRef D0 (instanceRef r_gctr_2))
+              (portRef C1 (instanceRef r_gctr_2))
+              (portRef C0 (instanceRef r_gctr_2))
+              (portRef D1 (instanceRef r_gctr_3))
+              (portRef D0 (instanceRef r_gctr_3))
+              (portRef C1 (instanceRef r_gctr_3))
+              (portRef C0 (instanceRef r_gctr_3))
+              (portRef D1 (instanceRef r_gctr_4))
+              (portRef D0 (instanceRef r_gctr_4))
+              (portRef C1 (instanceRef r_gctr_4))
+              (portRef C0 (instanceRef r_gctr_4))
+              (portRef C1 (instanceRef empty_cmp_ci_a))
+              (portRef C0 (instanceRef empty_cmp_ci_a))
+              (portRef D1 (instanceRef empty_cmp_ci_a))
+              (portRef D0 (instanceRef empty_cmp_ci_a))
+              (portRef D1 (instanceRef empty_cmp_0))
+              (portRef D0 (instanceRef empty_cmp_0))
+              (portRef C1 (instanceRef empty_cmp_0))
+              (portRef C0 (instanceRef empty_cmp_0))
+              (portRef D1 (instanceRef empty_cmp_1))
+              (portRef D0 (instanceRef empty_cmp_1))
+              (portRef C1 (instanceRef empty_cmp_1))
+              (portRef C0 (instanceRef empty_cmp_1))
+              (portRef D1 (instanceRef empty_cmp_2))
+              (portRef D0 (instanceRef empty_cmp_2))
+              (portRef C1 (instanceRef empty_cmp_2))
+              (portRef C0 (instanceRef empty_cmp_2))
+              (portRef D1 (instanceRef empty_cmp_3))
+              (portRef D0 (instanceRef empty_cmp_3))
+              (portRef C1 (instanceRef empty_cmp_3))
+              (portRef C0 (instanceRef empty_cmp_3))
+              (portRef D1 (instanceRef empty_cmp_4))
+              (portRef D0 (instanceRef empty_cmp_4))
+              (portRef C1 (instanceRef empty_cmp_4))
+              (portRef C0 (instanceRef empty_cmp_4))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef full_cmp_ci_a))
+              (portRef C0 (instanceRef full_cmp_ci_a))
+              (portRef D1 (instanceRef full_cmp_ci_a))
+              (portRef D0 (instanceRef full_cmp_ci_a))
+              (portRef D1 (instanceRef full_cmp_0))
+              (portRef D0 (instanceRef full_cmp_0))
+              (portRef C1 (instanceRef full_cmp_0))
+              (portRef C0 (instanceRef full_cmp_0))
+              (portRef D1 (instanceRef full_cmp_1))
+              (portRef D0 (instanceRef full_cmp_1))
+              (portRef C1 (instanceRef full_cmp_1))
+              (portRef C0 (instanceRef full_cmp_1))
+              (portRef D1 (instanceRef full_cmp_2))
+              (portRef D0 (instanceRef full_cmp_2))
+              (portRef C1 (instanceRef full_cmp_2))
+              (portRef C0 (instanceRef full_cmp_2))
+              (portRef D1 (instanceRef full_cmp_3))
+              (portRef D0 (instanceRef full_cmp_3))
+              (portRef C1 (instanceRef full_cmp_3))
+              (portRef C0 (instanceRef full_cmp_3))
+              (portRef D1 (instanceRef full_cmp_4))
+              (portRef D0 (instanceRef full_cmp_4))
+              (portRef C1 (instanceRef full_cmp_4))
+              (portRef C0 (instanceRef full_cmp_4))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD0 (instanceRef LUT4_21))
+              (portRef AD1 (instanceRef LUT4_21))
+              (portRef AD0 (instanceRef LUT4_20))
+              (portRef AD0 (instanceRef LUT4_16))
+              (portRef AD1 (instanceRef LUT4_16))
+              (portRef AD0 (instanceRef LUT4_15))
+              (portRef AD0 (instanceRef LUT4_11))
+              (portRef AD1 (instanceRef LUT4_11))
+              (portRef AD0 (instanceRef LUT4_10))
+              (portRef AD0 (instanceRef LUT4_6))
+              (portRef AD1 (instanceRef LUT4_6))
+              (portRef AD0 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_3))
+              (portRef AD0 (instanceRef LUT4_2))
+              (portRef AD0 (instanceRef LUT4_1))
+              (portRef AD0 (instanceRef LUT4_0))
+              (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+              (portRef DI35 (instanceRef pdp_ram_0_0_0))
+              (portRef DI34 (instanceRef pdp_ram_0_0_0))
+              (portRef DI33 (instanceRef pdp_ram_0_0_0))
+              (portRef DI32 (instanceRef pdp_ram_0_0_0))
+              (portRef B0 (instanceRef w_gctr_cia))
+              (portRef A0 (instanceRef w_gctr_cia))
+              (portRef B1 (instanceRef w_gctr_0))
+              (portRef B0 (instanceRef w_gctr_0))
+              (portRef B1 (instanceRef w_gctr_1))
+              (portRef B0 (instanceRef w_gctr_1))
+              (portRef B1 (instanceRef w_gctr_2))
+              (portRef B0 (instanceRef w_gctr_2))
+              (portRef B1 (instanceRef w_gctr_3))
+              (portRef B0 (instanceRef w_gctr_3))
+              (portRef B1 (instanceRef w_gctr_4))
+              (portRef B0 (instanceRef w_gctr_4))
+              (portRef B0 (instanceRef r_gctr_cia))
+              (portRef A0 (instanceRef r_gctr_cia))
+              (portRef B1 (instanceRef r_gctr_0))
+              (portRef B0 (instanceRef r_gctr_0))
+              (portRef B1 (instanceRef r_gctr_1))
+              (portRef B0 (instanceRef r_gctr_1))
+              (portRef B1 (instanceRef r_gctr_2))
+              (portRef B0 (instanceRef r_gctr_2))
+              (portRef B1 (instanceRef r_gctr_3))
+              (portRef B0 (instanceRef r_gctr_3))
+              (portRef B1 (instanceRef r_gctr_4))
+              (portRef B0 (instanceRef r_gctr_4))
+              (portRef B0 (instanceRef empty_cmp_ci_a))
+              (portRef A0 (instanceRef empty_cmp_ci_a))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B0 (instanceRef full_cmp_ci_a))
+              (portRef A0 (instanceRef full_cmp_ci_a))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))))
+          (net full_d_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef full_cmp_4))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_0))
+              (portRef A (instanceRef INV_1))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_1))
+              (portRef A (instanceRef INV_0))))
+          (net dataout31
+            (joined
+              (portRef (member Q 0))
+              (portRef DO13 (instanceRef pdp_ram_0_0_0))))
+          (net dataout30
+            (joined
+              (portRef (member Q 1))
+              (portRef DO12 (instanceRef pdp_ram_0_0_0))))
+          (net dataout29
+            (joined
+              (portRef (member Q 2))
+              (portRef DO11 (instanceRef pdp_ram_0_0_0))))
+          (net dataout28
+            (joined
+              (portRef (member Q 3))
+              (portRef DO10 (instanceRef pdp_ram_0_0_0))))
+          (net dataout27
+            (joined
+              (portRef (member Q 4))
+              (portRef DO9 (instanceRef pdp_ram_0_0_0))))
+          (net dataout26
+            (joined
+              (portRef (member Q 5))
+              (portRef DO8 (instanceRef pdp_ram_0_0_0))))
+          (net dataout25
+            (joined
+              (portRef (member Q 6))
+              (portRef DO7 (instanceRef pdp_ram_0_0_0))))
+          (net dataout24
+            (joined
+              (portRef (member Q 7))
+              (portRef DO6 (instanceRef pdp_ram_0_0_0))))
+          (net dataout23
+            (joined
+              (portRef (member Q 8))
+              (portRef DO5 (instanceRef pdp_ram_0_0_0))))
+          (net dataout22
+            (joined
+              (portRef (member Q 9))
+              (portRef DO4 (instanceRef pdp_ram_0_0_0))))
+          (net dataout21
+            (joined
+              (portRef (member Q 10))
+              (portRef DO3 (instanceRef pdp_ram_0_0_0))))
+          (net dataout20
+            (joined
+              (portRef (member Q 11))
+              (portRef DO2 (instanceRef pdp_ram_0_0_0))))
+          (net dataout19
+            (joined
+              (portRef (member Q 12))
+              (portRef DO1 (instanceRef pdp_ram_0_0_0))))
+          (net dataout18
+            (joined
+              (portRef (member Q 13))
+              (portRef DO0 (instanceRef pdp_ram_0_0_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 14))
+              (portRef DO35 (instanceRef pdp_ram_0_0_0))))
+          (net dataout16
+            (joined
+              (portRef (member Q 15))
+              (portRef DO34 (instanceRef pdp_ram_0_0_0))))
+          (net dataout15
+            (joined
+              (portRef (member Q 16))
+              (portRef DO33 (instanceRef pdp_ram_0_0_0))))
+          (net dataout14
+            (joined
+              (portRef (member Q 17))
+              (portRef DO32 (instanceRef pdp_ram_0_0_0))))
+          (net dataout13
+            (joined
+              (portRef (member Q 18))
+              (portRef DO31 (instanceRef pdp_ram_0_0_0))))
+          (net dataout12
+            (joined
+              (portRef (member Q 19))
+              (portRef DO30 (instanceRef pdp_ram_0_0_0))))
+          (net dataout11
+            (joined
+              (portRef (member Q 20))
+              (portRef DO29 (instanceRef pdp_ram_0_0_0))))
+          (net dataout10
+            (joined
+              (portRef (member Q 21))
+              (portRef DO28 (instanceRef pdp_ram_0_0_0))))
+          (net dataout9
+            (joined
+              (portRef (member Q 22))
+              (portRef DO27 (instanceRef pdp_ram_0_0_0))))
+          (net dataout8
+            (joined
+              (portRef (member Q 23))
+              (portRef DO26 (instanceRef pdp_ram_0_0_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 24))
+              (portRef DO25 (instanceRef pdp_ram_0_0_0))))
+          (net dataout6
+            (joined
+              (portRef (member Q 25))
+              (portRef DO24 (instanceRef pdp_ram_0_0_0))))
+          (net dataout5
+            (joined
+              (portRef (member Q 26))
+              (portRef DO23 (instanceRef pdp_ram_0_0_0))))
+          (net dataout4
+            (joined
+              (portRef (member Q 27))
+              (portRef DO22 (instanceRef pdp_ram_0_0_0))))
+          (net dataout3
+            (joined
+              (portRef (member Q 28))
+              (portRef DO21 (instanceRef pdp_ram_0_0_0))))
+          (net dataout2
+            (joined
+              (portRef (member Q 29))
+              (portRef DO20 (instanceRef pdp_ram_0_0_0))))
+          (net dataout1
+            (joined
+              (portRef (member Q 30))
+              (portRef DO19 (instanceRef pdp_ram_0_0_0))))
+          (net dataout0
+            (joined
+              (portRef (member Q 31))
+              (portRef DO18 (instanceRef pdp_ram_0_0_0))))
+          (net RPRst
+            (joined
+              (portRef RPReset)
+              (portRef B (instanceRef OR2_t18))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef A (instanceRef OR2_t18))
+              (portRef RST (instanceRef pdp_ram_0_0_0))
+              (portRef PD (instanceRef FF_101))
+              (portRef CD (instanceRef FF_100))
+              (portRef CD (instanceRef FF_99))
+              (portRef CD (instanceRef FF_98))
+              (portRef CD (instanceRef FF_97))
+              (portRef CD (instanceRef FF_96))
+              (portRef CD (instanceRef FF_95))
+              (portRef CD (instanceRef FF_94))
+              (portRef CD (instanceRef FF_93))
+              (portRef CD (instanceRef FF_92))
+              (portRef CD (instanceRef FF_91))
+              (portRef CD (instanceRef FF_90))
+              (portRef CD (instanceRef FF_89))
+              (portRef CD (instanceRef FF_88))
+              (portRef CD (instanceRef FF_87))
+              (portRef CD (instanceRef FF_86))
+              (portRef CD (instanceRef FF_85))
+              (portRef CD (instanceRef FF_84))
+              (portRef CD (instanceRef FF_83))
+              (portRef CD (instanceRef FF_82))
+              (portRef CD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef CD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t19))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t20))))
+          (net rclk
+            (joined
+              (portRef RdClock)
+              (portRef CLKR (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_1))))
+          (net wclk
+            (joined
+              (portRef WrClock)
+              (portRef CLKW (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_101))
+              (portRef CK (instanceRef FF_100))
+              (portRef CK (instanceRef FF_99))
+              (portRef CK (instanceRef FF_98))
+              (portRef CK (instanceRef FF_97))
+              (portRef CK (instanceRef FF_96))
+              (portRef CK (instanceRef FF_95))
+              (portRef CK (instanceRef FF_94))
+              (portRef CK (instanceRef FF_93))
+              (portRef CK (instanceRef FF_92))
+              (portRef CK (instanceRef FF_91))
+              (portRef CK (instanceRef FF_90))
+              (portRef CK (instanceRef FF_89))
+              (portRef CK (instanceRef FF_88))
+              (portRef CK (instanceRef FF_87))
+              (portRef CK (instanceRef FF_86))
+              (portRef CK (instanceRef FF_85))
+              (portRef CK (instanceRef FF_84))
+              (portRef CK (instanceRef FF_83))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 0))
+              (portRef DI31 (instanceRef pdp_ram_0_0_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 1))
+              (portRef DI30 (instanceRef pdp_ram_0_0_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 2))
+              (portRef DI29 (instanceRef pdp_ram_0_0_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 3))
+              (portRef DI28 (instanceRef pdp_ram_0_0_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 4))
+              (portRef DI27 (instanceRef pdp_ram_0_0_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 5))
+              (portRef DI26 (instanceRef pdp_ram_0_0_0))))
+          (net datain25
+            (joined
+              (portRef (member Data 6))
+              (portRef DI25 (instanceRef pdp_ram_0_0_0))))
+          (net datain24
+            (joined
+              (portRef (member Data 7))
+              (portRef DI24 (instanceRef pdp_ram_0_0_0))))
+          (net datain23
+            (joined
+              (portRef (member Data 8))
+              (portRef DI23 (instanceRef pdp_ram_0_0_0))))
+          (net datain22
+            (joined
+              (portRef (member Data 9))
+              (portRef DI22 (instanceRef pdp_ram_0_0_0))))
+          (net datain21
+            (joined
+              (portRef (member Data 10))
+              (portRef DI21 (instanceRef pdp_ram_0_0_0))))
+          (net datain20
+            (joined
+              (portRef (member Data 11))
+              (portRef DI20 (instanceRef pdp_ram_0_0_0))))
+          (net datain19
+            (joined
+              (portRef (member Data 12))
+              (portRef DI19 (instanceRef pdp_ram_0_0_0))))
+          (net datain18
+            (joined
+              (portRef (member Data 13))
+              (portRef DI18 (instanceRef pdp_ram_0_0_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 14))
+              (portRef DI17 (instanceRef pdp_ram_0_0_0))))
+          (net datain16
+            (joined
+              (portRef (member Data 15))
+              (portRef DI16 (instanceRef pdp_ram_0_0_0))))
+          (net datain15
+            (joined
+              (portRef (member Data 16))
+              (portRef DI15 (instanceRef pdp_ram_0_0_0))))
+          (net datain14
+            (joined
+              (portRef (member Data 17))
+              (portRef DI14 (instanceRef pdp_ram_0_0_0))))
+          (net datain13
+            (joined
+              (portRef (member Data 18))
+              (portRef DI13 (instanceRef pdp_ram_0_0_0))))
+          (net datain12
+            (joined
+              (portRef (member Data 19))
+              (portRef DI12 (instanceRef pdp_ram_0_0_0))))
+          (net datain11
+            (joined
+              (portRef (member Data 20))
+              (portRef DI11 (instanceRef pdp_ram_0_0_0))))
+          (net datain10
+            (joined
+              (portRef (member Data 21))
+              (portRef DI10 (instanceRef pdp_ram_0_0_0))))
+          (net datain9
+            (joined
+              (portRef (member Data 22))
+              (portRef DI9 (instanceRef pdp_ram_0_0_0))))
+          (net datain8
+            (joined
+              (portRef (member Data 23))
+              (portRef DI8 (instanceRef pdp_ram_0_0_0))))
+          (net datain7
+            (joined
+              (portRef (member Data 24))
+              (portRef DI7 (instanceRef pdp_ram_0_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 25))
+              (portRef DI6 (instanceRef pdp_ram_0_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 26))
+              (portRef DI5 (instanceRef pdp_ram_0_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 27))
+              (portRef DI4 (instanceRef pdp_ram_0_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 28))
+              (portRef DI3 (instanceRef pdp_ram_0_0_0))))
+          (net datain2
+            (joined
+              (portRef (member Data 29))
+              (portRef DI2 (instanceRef pdp_ram_0_0_0))))
+          (net datain1
+            (joined
+              (portRef (member Data 30))
+              (portRef DI1 (instanceRef pdp_ram_0_0_0))))
+          (net datain0
+            (joined
+              (portRef (member Data 31))
+              (portRef DI0 (instanceRef pdp_ram_0_0_0))))))))
+  (design fifo32dc
+    (cellRef fifo32dc
+      (libraryRef ORCLIB)))
+)
diff --git a/fifo32dc/fifo32dc.fdc b/fifo32dc/fifo32dc.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/fifo32dc/fifo32dc.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/fifo32dc/fifo32dc.lpc b/fifo32dc/fifo32dc.lpc
new file mode 100644
index 0000000..7709870
--- /dev/null
+++ b/fifo32dc/fifo32dc.lpc
@@ -0,0 +1,53 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=fifo32dc
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=09/13/2020
+Time=16:38:25
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=32
+RDepth=512
+RWidth=32
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1
diff --git a/fifo32dc/fifo32dc.sbx b/fifo32dc/fifo32dc.sbx
new file mode 100644
index 0000000..87557c3
--- /dev/null
+++ b/fifo32dc/fifo32dc.sbx
@@ -0,0 +1,264 @@
+<!DOCTYPE fifo32dc>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>FIFO_DC</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./fifo32dc.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./fifo32dc.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2020-09-13.04:38:29 PM</lattice:date>
+            <lattice:modified>2020-09-13.04:38:29 PM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">09/13/2020</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">fifo32dc</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">16:38:25</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ClockEn</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Depth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">512</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EmpFlg</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EnECC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FIFOImp</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FullFlg</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeAssert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeDeassert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeMode</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfAssert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfDeassert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfMode</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RDataCount</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RDepth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">512</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RWidth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">32</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Reset</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Reset1</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>WDataCount</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Width</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">32</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>regout</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>fifo32dc</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/fifo32dc/fifo32dc.srp b/fifo32dc/fifo32dc.srp
new file mode 100644
index 0000000..80bffa7
--- /dev/null
+++ b/fifo32dc/fifo32dc.srp
@@ -0,0 +1,40 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Sun Sep 13 16:38:29 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc 
+    Circuit name     : fifo32dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+	Inputs       : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+	Outputs      : Q[31:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo32dc.edn
+    Verilog output   : fifo32dc.v
+    Verilog template : fifo32dc_tmpl.v
+    Verilog testbench: tb_fifo32dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo32dc.srp
+    Element Usage    :
+          CCU2C : 26
+           AND2 : 2
+        FD1P3BX : 2
+        FD1P3DX : 58
+        FD1S3BX : 1
+        FD1S3DX : 41
+            INV : 2
+            OR2 : 1
+       ROM16X1A : 24
+           XOR2 : 18
+       PDPW16KD : 1
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 1
+            Reg : 102
diff --git a/fifo32dc/fifo32dc.v b/fifo32dc/fifo32dc.v
new file mode 100644
index 0000000..29bc35c
--- /dev/null
+++ b/fifo32dc/fifo32dc.v
@@ -0,0 +1,1076 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.8 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc  */
+/* Sun Sep 13 16:38:29 2020 */
+
+
+`timescale 1 ns / 1 ps
+module fifo32dc (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
+    Empty, Full)/* synthesis NGD_DRC_MASK=1 */;
+    input wire [31:0] Data;
+    input wire WrClock;
+    input wire RdClock;
+    input wire WrEn;
+    input wire RdEn;
+    input wire Reset;
+    input wire RPReset;
+    output wire [31:0] Q;
+    output wire Empty;
+    output wire Full;
+
+    wire invout_1;
+    wire invout_0;
+    wire w_g2b_xor_cluster_1;
+    wire r_g2b_xor_cluster_1;
+    wire w_gdata_0;
+    wire w_gdata_1;
+    wire w_gdata_2;
+    wire w_gdata_3;
+    wire w_gdata_4;
+    wire w_gdata_5;
+    wire w_gdata_6;
+    wire w_gdata_7;
+    wire w_gdata_8;
+    wire wptr_0;
+    wire wptr_1;
+    wire wptr_2;
+    wire wptr_3;
+    wire wptr_4;
+    wire wptr_5;
+    wire wptr_6;
+    wire wptr_7;
+    wire wptr_8;
+    wire wptr_9;
+    wire r_gdata_0;
+    wire r_gdata_1;
+    wire r_gdata_2;
+    wire r_gdata_3;
+    wire r_gdata_4;
+    wire r_gdata_5;
+    wire r_gdata_6;
+    wire r_gdata_7;
+    wire r_gdata_8;
+    wire rptr_0;
+    wire rptr_1;
+    wire rptr_2;
+    wire rptr_3;
+    wire rptr_4;
+    wire rptr_5;
+    wire rptr_6;
+    wire rptr_7;
+    wire rptr_8;
+    wire rptr_9;
+    wire w_gcount_0;
+    wire w_gcount_1;
+    wire w_gcount_2;
+    wire w_gcount_3;
+    wire w_gcount_4;
+    wire w_gcount_5;
+    wire w_gcount_6;
+    wire w_gcount_7;
+    wire w_gcount_8;
+    wire w_gcount_9;
+    wire r_gcount_0;
+    wire r_gcount_1;
+    wire r_gcount_2;
+    wire r_gcount_3;
+    wire r_gcount_4;
+    wire r_gcount_5;
+    wire r_gcount_6;
+    wire r_gcount_7;
+    wire r_gcount_8;
+    wire r_gcount_9;
+    wire w_gcount_r20;
+    wire w_gcount_r0;
+    wire w_gcount_r21;
+    wire w_gcount_r1;
+    wire w_gcount_r22;
+    wire w_gcount_r2;
+    wire w_gcount_r23;
+    wire w_gcount_r3;
+    wire w_gcount_r24;
+    wire w_gcount_r4;
+    wire w_gcount_r25;
+    wire w_gcount_r5;
+    wire w_gcount_r26;
+    wire w_gcount_r6;
+    wire w_gcount_r27;
+    wire w_gcount_r7;
+    wire w_gcount_r28;
+    wire w_gcount_r8;
+    wire w_gcount_r29;
+    wire w_gcount_r9;
+    wire r_gcount_w20;
+    wire r_gcount_w0;
+    wire r_gcount_w21;
+    wire r_gcount_w1;
+    wire r_gcount_w22;
+    wire r_gcount_w2;
+    wire r_gcount_w23;
+    wire r_gcount_w3;
+    wire r_gcount_w24;
+    wire r_gcount_w4;
+    wire r_gcount_w25;
+    wire r_gcount_w5;
+    wire r_gcount_w26;
+    wire r_gcount_w6;
+    wire r_gcount_w27;
+    wire r_gcount_w7;
+    wire r_gcount_w28;
+    wire r_gcount_w8;
+    wire r_gcount_w29;
+    wire r_gcount_w9;
+    wire empty_i;
+    wire rRst;
+    wire full_i;
+    wire iwcount_0;
+    wire iwcount_1;
+    wire w_gctr_ci;
+    wire iwcount_2;
+    wire iwcount_3;
+    wire co0;
+    wire iwcount_4;
+    wire iwcount_5;
+    wire co1;
+    wire iwcount_6;
+    wire iwcount_7;
+    wire co2;
+    wire iwcount_8;
+    wire iwcount_9;
+    wire co4;
+    wire co3;
+    wire wcount_9;
+    wire ircount_0;
+    wire ircount_1;
+    wire r_gctr_ci;
+    wire ircount_2;
+    wire ircount_3;
+    wire co0_1;
+    wire ircount_4;
+    wire ircount_5;
+    wire co1_1;
+    wire ircount_6;
+    wire ircount_7;
+    wire co2_1;
+    wire ircount_8;
+    wire ircount_9;
+    wire co4_1;
+    wire co3_1;
+    wire rcount_9;
+    wire rden_i;
+    wire cmp_ci;
+    wire wcount_r0;
+    wire wcount_r1;
+    wire rcount_0;
+    wire rcount_1;
+    wire co0_2;
+    wire wcount_r2;
+    wire wcount_r3;
+    wire rcount_2;
+    wire rcount_3;
+    wire co1_2;
+    wire wcount_r4;
+    wire wcount_r5;
+    wire rcount_4;
+    wire rcount_5;
+    wire co2_2;
+    wire w_g2b_xor_cluster_0;
+    wire wcount_r7;
+    wire rcount_6;
+    wire rcount_7;
+    wire co3_2;
+    wire wcount_r8;
+    wire empty_cmp_clr;
+    wire rcount_8;
+    wire empty_cmp_set;
+    wire empty_d;
+    wire empty_d_c;
+    wire wren_i;
+    wire cmp_ci_1;
+    wire rcount_w0;
+    wire rcount_w1;
+    wire wcount_0;
+    wire wcount_1;
+    wire co0_3;
+    wire rcount_w2;
+    wire rcount_w3;
+    wire wcount_2;
+    wire wcount_3;
+    wire co1_3;
+    wire rcount_w4;
+    wire rcount_w5;
+    wire wcount_4;
+    wire wcount_5;
+    wire co2_3;
+    wire r_g2b_xor_cluster_0;
+    wire rcount_w7;
+    wire wcount_6;
+    wire wcount_7;
+    wire co3_3;
+    wire rcount_w8;
+    wire full_cmp_clr;
+    wire wcount_8;
+    wire full_cmp_set;
+    wire full_d;
+    wire scuba_vhi;
+    wire scuba_vlo;
+    wire full_d_c;
+
+    AND2 AND2_t20 (.A(WrEn), .B(invout_1), .Z(wren_i));
+
+    INV INV_1 (.A(full_i), .Z(invout_1));
+
+    AND2 AND2_t19 (.A(RdEn), .B(invout_0), .Z(rden_i));
+
+    INV INV_0 (.A(empty_i), .Z(invout_0));
+
+    OR2 OR2_t18 (.A(Reset), .B(RPReset), .Z(rRst));
+
+    XOR2 XOR2_t17 (.A(wcount_0), .B(wcount_1), .Z(w_gdata_0));
+
+    XOR2 XOR2_t16 (.A(wcount_1), .B(wcount_2), .Z(w_gdata_1));
+
+    XOR2 XOR2_t15 (.A(wcount_2), .B(wcount_3), .Z(w_gdata_2));
+
+    XOR2 XOR2_t14 (.A(wcount_3), .B(wcount_4), .Z(w_gdata_3));
+
+    XOR2 XOR2_t13 (.A(wcount_4), .B(wcount_5), .Z(w_gdata_4));
+
+    XOR2 XOR2_t12 (.A(wcount_5), .B(wcount_6), .Z(w_gdata_5));
+
+    XOR2 XOR2_t11 (.A(wcount_6), .B(wcount_7), .Z(w_gdata_6));
+
+    XOR2 XOR2_t10 (.A(wcount_7), .B(wcount_8), .Z(w_gdata_7));
+
+    XOR2 XOR2_t9 (.A(wcount_8), .B(wcount_9), .Z(w_gdata_8));
+
+    XOR2 XOR2_t8 (.A(rcount_0), .B(rcount_1), .Z(r_gdata_0));
+
+    XOR2 XOR2_t7 (.A(rcount_1), .B(rcount_2), .Z(r_gdata_1));
+
+    XOR2 XOR2_t6 (.A(rcount_2), .B(rcount_3), .Z(r_gdata_2));
+
+    XOR2 XOR2_t5 (.A(rcount_3), .B(rcount_4), .Z(r_gdata_3));
+
+    XOR2 XOR2_t4 (.A(rcount_4), .B(rcount_5), .Z(r_gdata_4));
+
+    XOR2 XOR2_t3 (.A(rcount_5), .B(rcount_6), .Z(r_gdata_5));
+
+    XOR2 XOR2_t2 (.A(rcount_6), .B(rcount_7), .Z(r_gdata_6));
+
+    XOR2 XOR2_t1 (.A(rcount_7), .B(rcount_8), .Z(r_gdata_7));
+
+    XOR2 XOR2_t0 (.A(rcount_8), .B(rcount_9), .Z(r_gdata_8));
+
+    defparam LUT4_23.initval =  16'h6996 ;
+    ROM16X1A LUT4_23 (.AD3(w_gcount_r26), .AD2(w_gcount_r27), .AD1(w_gcount_r28), 
+        .AD0(w_gcount_r29), .DO0(w_g2b_xor_cluster_0));
+
+    defparam LUT4_22.initval =  16'h6996 ;
+    ROM16X1A LUT4_22 (.AD3(w_gcount_r22), .AD2(w_gcount_r23), .AD1(w_gcount_r24), 
+        .AD0(w_gcount_r25), .DO0(w_g2b_xor_cluster_1));
+
+    defparam LUT4_21.initval =  16'h6996 ;
+    ROM16X1A LUT4_21 (.AD3(w_gcount_r28), .AD2(w_gcount_r29), .AD1(scuba_vlo), 
+        .AD0(scuba_vlo), .DO0(wcount_r8));
+
+    defparam LUT4_20.initval =  16'h6996 ;
+    ROM16X1A LUT4_20 (.AD3(w_gcount_r27), .AD2(w_gcount_r28), .AD1(w_gcount_r29), 
+        .AD0(scuba_vlo), .DO0(wcount_r7));
+
+    defparam LUT4_19.initval =  16'h6996 ;
+    ROM16X1A LUT4_19 (.AD3(w_gcount_r25), .AD2(w_gcount_r26), .AD1(w_gcount_r27), 
+        .AD0(wcount_r8), .DO0(wcount_r5));
+
+    defparam LUT4_18.initval =  16'h6996 ;
+    ROM16X1A LUT4_18 (.AD3(w_gcount_r24), .AD2(w_gcount_r25), .AD1(w_gcount_r26), 
+        .AD0(wcount_r7), .DO0(wcount_r4));
+
+    defparam LUT4_17.initval =  16'h6996 ;
+    ROM16X1A LUT4_17 (.AD3(w_gcount_r23), .AD2(w_gcount_r24), .AD1(w_gcount_r25), 
+        .AD0(w_g2b_xor_cluster_0), .DO0(wcount_r3));
+
+    defparam LUT4_16.initval =  16'h6996 ;
+    ROM16X1A LUT4_16 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(wcount_r2));
+
+    defparam LUT4_15.initval =  16'h6996 ;
+    ROM16X1A LUT4_15 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(w_gcount_r21), .AD0(scuba_vlo), .DO0(wcount_r1));
+
+    defparam LUT4_14.initval =  16'h6996 ;
+    ROM16X1A LUT4_14 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(w_gcount_r20), .AD0(w_gcount_r21), .DO0(wcount_r0));
+
+    defparam LUT4_13.initval =  16'h6996 ;
+    ROM16X1A LUT4_13 (.AD3(r_gcount_w26), .AD2(r_gcount_w27), .AD1(r_gcount_w28), 
+        .AD0(r_gcount_w29), .DO0(r_g2b_xor_cluster_0));
+
+    defparam LUT4_12.initval =  16'h6996 ;
+    ROM16X1A LUT4_12 (.AD3(r_gcount_w22), .AD2(r_gcount_w23), .AD1(r_gcount_w24), 
+        .AD0(r_gcount_w25), .DO0(r_g2b_xor_cluster_1));
+
+    defparam LUT4_11.initval =  16'h6996 ;
+    ROM16X1A LUT4_11 (.AD3(r_gcount_w28), .AD2(r_gcount_w29), .AD1(scuba_vlo), 
+        .AD0(scuba_vlo), .DO0(rcount_w8));
+
+    defparam LUT4_10.initval =  16'h6996 ;
+    ROM16X1A LUT4_10 (.AD3(r_gcount_w27), .AD2(r_gcount_w28), .AD1(r_gcount_w29), 
+        .AD0(scuba_vlo), .DO0(rcount_w7));
+
+    defparam LUT4_9.initval =  16'h6996 ;
+    ROM16X1A LUT4_9 (.AD3(r_gcount_w25), .AD2(r_gcount_w26), .AD1(r_gcount_w27), 
+        .AD0(rcount_w8), .DO0(rcount_w5));
+
+    defparam LUT4_8.initval =  16'h6996 ;
+    ROM16X1A LUT4_8 (.AD3(r_gcount_w24), .AD2(r_gcount_w25), .AD1(r_gcount_w26), 
+        .AD0(rcount_w7), .DO0(rcount_w4));
+
+    defparam LUT4_7.initval =  16'h6996 ;
+    ROM16X1A LUT4_7 (.AD3(r_gcount_w23), .AD2(r_gcount_w24), .AD1(r_gcount_w25), 
+        .AD0(r_g2b_xor_cluster_0), .DO0(rcount_w3));
+
+    defparam LUT4_6.initval =  16'h6996 ;
+    ROM16X1A LUT4_6 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(rcount_w2));
+
+    defparam LUT4_5.initval =  16'h6996 ;
+    ROM16X1A LUT4_5 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(r_gcount_w21), .AD0(scuba_vlo), .DO0(rcount_w1));
+
+    defparam LUT4_4.initval =  16'h6996 ;
+    ROM16X1A LUT4_4 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(r_gcount_w20), .AD0(r_gcount_w21), .DO0(rcount_w0));
+
+    defparam LUT4_3.initval =  16'h0410 ;
+    ROM16X1A LUT4_3 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), 
+        .DO0(empty_cmp_set));
+
+    defparam LUT4_2.initval =  16'h1004 ;
+    ROM16X1A LUT4_2 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), 
+        .DO0(empty_cmp_clr));
+
+    defparam LUT4_1.initval =  16'h0140 ;
+    ROM16X1A LUT4_1 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), 
+        .DO0(full_cmp_set));
+
+    defparam LUT4_0.initval =  16'h4001 ;
+    ROM16X1A LUT4_0 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), 
+        .DO0(full_cmp_clr));
+
+    defparam pdp_ram_0_0_0.INIT_DATA = "STATIC" ;
+    defparam pdp_ram_0_0_0.ASYNC_RESET_RELEASE = "SYNC" ;
+    defparam pdp_ram_0_0_0.CSDECODE_R = "0b000" ;
+    defparam pdp_ram_0_0_0.CSDECODE_W = "0b001" ;
+    defparam pdp_ram_0_0_0.GSR = "ENABLED" ;
+    defparam pdp_ram_0_0_0.RESETMODE = "SYNC" ;
+    defparam pdp_ram_0_0_0.REGMODE = "NOREG" ;
+    defparam pdp_ram_0_0_0.DATA_WIDTH_R = 36 ;
+    defparam pdp_ram_0_0_0.DATA_WIDTH_W = 36 ;
+    PDPW16KD pdp_ram_0_0_0 (.DI35(scuba_vlo), .DI34(scuba_vlo), .DI33(scuba_vlo), 
+        .DI32(scuba_vlo), .DI31(Data[31]), .DI30(Data[30]), .DI29(Data[29]), 
+        .DI28(Data[28]), .DI27(Data[27]), .DI26(Data[26]), .DI25(Data[25]), 
+        .DI24(Data[24]), .DI23(Data[23]), .DI22(Data[22]), .DI21(Data[21]), 
+        .DI20(Data[20]), .DI19(Data[19]), .DI18(Data[18]), .DI17(Data[17]), 
+        .DI16(Data[16]), .DI15(Data[15]), .DI14(Data[14]), .DI13(Data[13]), 
+        .DI12(Data[12]), .DI11(Data[11]), .DI10(Data[10]), .DI9(Data[9]), 
+        .DI8(Data[8]), .DI7(Data[7]), .DI6(Data[6]), .DI5(Data[5]), .DI4(Data[4]), 
+        .DI3(Data[3]), .DI2(Data[2]), .DI1(Data[1]), .DI0(Data[0]), .ADW8(wptr_8), 
+        .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), .ADW4(wptr_4), .ADW3(wptr_3), 
+        .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), .BE3(scuba_vhi), .BE2(scuba_vhi), 
+        .BE1(scuba_vhi), .BE0(scuba_vhi), .CEW(wren_i), .CLKW(WrClock), 
+        .CSW2(scuba_vlo), .CSW1(scuba_vlo), .CSW0(scuba_vhi), .ADR13(rptr_8), 
+        .ADR12(rptr_7), .ADR11(rptr_6), .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), 
+        .ADR7(rptr_2), .ADR6(rptr_1), .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), 
+        .ADR2(scuba_vlo), .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), 
+        .OCER(rden_i), .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), 
+        .CSR0(scuba_vlo), .RST(Reset), .DO35(Q[17]), .DO34(Q[16]), .DO33(Q[15]), 
+        .DO32(Q[14]), .DO31(Q[13]), .DO30(Q[12]), .DO29(Q[11]), .DO28(Q[10]), 
+        .DO27(Q[9]), .DO26(Q[8]), .DO25(Q[7]), .DO24(Q[6]), .DO23(Q[5]), 
+        .DO22(Q[4]), .DO21(Q[3]), .DO20(Q[2]), .DO19(Q[1]), .DO18(Q[0]), 
+        .DO17(), .DO16(), .DO15(), .DO14(), .DO13(Q[31]), .DO12(Q[30]), 
+        .DO11(Q[29]), .DO10(Q[28]), .DO9(Q[27]), .DO8(Q[26]), .DO7(Q[25]), 
+        .DO6(Q[24]), .DO5(Q[23]), .DO4(Q[22]), .DO3(Q[21]), .DO2(Q[20]), 
+        .DO1(Q[19]), .DO0(Q[18]))
+             /* synthesis MEM_LPC_FILE="fifo32dc.lpc" */
+             /* synthesis MEM_INIT_FILE="" */;
+
+    FD1P3BX FF_101 (.D(iwcount_0), .SP(wren_i), .CK(WrClock), .PD(Reset), 
+        .Q(wcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_100 (.D(iwcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_99 (.D(iwcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_98 (.D(iwcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_97 (.D(iwcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_96 (.D(iwcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_95 (.D(iwcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_94 (.D(iwcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_93 (.D(iwcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_92 (.D(iwcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_91 (.D(w_gdata_0), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_90 (.D(w_gdata_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_89 (.D(w_gdata_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_88 (.D(w_gdata_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_87 (.D(w_gdata_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_86 (.D(w_gdata_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_85 (.D(w_gdata_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_84 (.D(w_gdata_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_83 (.D(w_gdata_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_82 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_81 (.D(wcount_0), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_80 (.D(wcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_79 (.D(wcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_78 (.D(wcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_77 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_76 (.D(wcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_75 (.D(wcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_74 (.D(wcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_73 (.D(wcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_72 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3BX FF_71 (.D(ircount_0), .SP(rden_i), .CK(RdClock), .PD(rRst), 
+        .Q(rcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_70 (.D(ircount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_69 (.D(ircount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_68 (.D(ircount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_67 (.D(ircount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_66 (.D(ircount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_65 (.D(ircount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_64 (.D(ircount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_63 (.D(ircount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_62 (.D(ircount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_61 (.D(r_gdata_0), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_60 (.D(r_gdata_1), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_59 (.D(r_gdata_2), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_58 (.D(r_gdata_3), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_57 (.D(r_gdata_4), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_56 (.D(r_gdata_5), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_55 (.D(r_gdata_6), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_54 (.D(r_gdata_7), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_53 (.D(r_gdata_8), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_52 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(r_gcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_51 (.D(rcount_0), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_50 (.D(rcount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_49 (.D(rcount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_48 (.D(rcount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_47 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_46 (.D(rcount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_45 (.D(rcount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_44 (.D(rcount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_43 (.D(rcount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_42 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_41 (.D(w_gcount_0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_40 (.D(w_gcount_1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_39 (.D(w_gcount_2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_38 (.D(w_gcount_3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_37 (.D(w_gcount_4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_36 (.D(w_gcount_5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_35 (.D(w_gcount_6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_34 (.D(w_gcount_7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_33 (.D(w_gcount_8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_32 (.D(w_gcount_9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_31 (.D(r_gcount_0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_30 (.D(r_gcount_1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_29 (.D(r_gcount_2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_28 (.D(r_gcount_3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_27 (.D(r_gcount_4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_26 (.D(r_gcount_5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_25 (.D(r_gcount_6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_24 (.D(r_gcount_7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_23 (.D(r_gcount_8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_22 (.D(r_gcount_9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_21 (.D(w_gcount_r0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r20))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_20 (.D(w_gcount_r1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r21))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_19 (.D(w_gcount_r2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r22))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_18 (.D(w_gcount_r3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r23))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_17 (.D(w_gcount_r4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r24))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_16 (.D(w_gcount_r5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r25))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_15 (.D(w_gcount_r6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r26))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_14 (.D(w_gcount_r7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r27))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_13 (.D(w_gcount_r8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r28))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_12 (.D(w_gcount_r9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r29))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_11 (.D(r_gcount_w0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w20))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_10 (.D(r_gcount_w1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w21))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_9 (.D(r_gcount_w2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w22))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_8 (.D(r_gcount_w3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w23))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_7 (.D(r_gcount_w4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w24))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_6 (.D(r_gcount_w5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w25))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_5 (.D(r_gcount_w6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w26))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_4 (.D(r_gcount_w7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w27))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_3 (.D(r_gcount_w8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w28))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_2 (.D(r_gcount_w9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w29))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3BX FF_1 (.D(empty_d), .CK(RdClock), .PD(rRst), .Q(empty_i))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_0 (.D(full_d), .CK(WrClock), .CD(Reset), .Q(full_i))
+             /* synthesis GSR="ENABLED" */;
+
+    defparam w_gctr_cia.INJECT1_1 = "NO" ;
+    defparam w_gctr_cia.INJECT1_0 = "NO" ;
+    defparam w_gctr_cia.INIT1 =  16'h66AA ;
+    defparam w_gctr_cia.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(w_gctr_ci));
+
+    defparam w_gctr_0.INJECT1_1 = "NO" ;
+    defparam w_gctr_0.INJECT1_0 = "NO" ;
+    defparam w_gctr_0.INIT1 =  16'h66AA ;
+    defparam w_gctr_0.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_0 (.A0(wcount_0), .A1(wcount_1), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(w_gctr_ci), .S0(iwcount_0), .S1(iwcount_1), .COUT(co0));
+
+    defparam w_gctr_1.INJECT1_1 = "NO" ;
+    defparam w_gctr_1.INJECT1_0 = "NO" ;
+    defparam w_gctr_1.INIT1 =  16'h66AA ;
+    defparam w_gctr_1.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_1 (.A0(wcount_2), .A1(wcount_3), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0), .S0(iwcount_2), .S1(iwcount_3), .COUT(co1));
+
+    defparam w_gctr_2.INJECT1_1 = "NO" ;
+    defparam w_gctr_2.INJECT1_0 = "NO" ;
+    defparam w_gctr_2.INIT1 =  16'h66AA ;
+    defparam w_gctr_2.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_2 (.A0(wcount_4), .A1(wcount_5), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1), .S0(iwcount_4), .S1(iwcount_5), .COUT(co2));
+
+    defparam w_gctr_3.INJECT1_1 = "NO" ;
+    defparam w_gctr_3.INJECT1_0 = "NO" ;
+    defparam w_gctr_3.INIT1 =  16'h66AA ;
+    defparam w_gctr_3.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_3 (.A0(wcount_6), .A1(wcount_7), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co2), .S0(iwcount_6), .S1(iwcount_7), .COUT(co3));
+
+    defparam w_gctr_4.INJECT1_1 = "NO" ;
+    defparam w_gctr_4.INJECT1_0 = "NO" ;
+    defparam w_gctr_4.INIT1 =  16'h66AA ;
+    defparam w_gctr_4.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_4 (.A0(wcount_8), .A1(wcount_9), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co3), .S0(iwcount_8), .S1(iwcount_9), .COUT(co4));
+
+    defparam r_gctr_cia.INJECT1_1 = "NO" ;
+    defparam r_gctr_cia.INJECT1_0 = "NO" ;
+    defparam r_gctr_cia.INIT1 =  16'h66AA ;
+    defparam r_gctr_cia.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(r_gctr_ci));
+
+    defparam r_gctr_0.INJECT1_1 = "NO" ;
+    defparam r_gctr_0.INJECT1_0 = "NO" ;
+    defparam r_gctr_0.INIT1 =  16'h66AA ;
+    defparam r_gctr_0.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_0 (.A0(rcount_0), .A1(rcount_1), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(r_gctr_ci), .S0(ircount_0), .S1(ircount_1), .COUT(co0_1));
+
+    defparam r_gctr_1.INJECT1_1 = "NO" ;
+    defparam r_gctr_1.INJECT1_0 = "NO" ;
+    defparam r_gctr_1.INIT1 =  16'h66AA ;
+    defparam r_gctr_1.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_1 (.A0(rcount_2), .A1(rcount_3), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_1), .S0(ircount_2), .S1(ircount_3), .COUT(co1_1));
+
+    defparam r_gctr_2.INJECT1_1 = "NO" ;
+    defparam r_gctr_2.INJECT1_0 = "NO" ;
+    defparam r_gctr_2.INIT1 =  16'h66AA ;
+    defparam r_gctr_2.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_2 (.A0(rcount_4), .A1(rcount_5), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_1), .S0(ircount_4), .S1(ircount_5), .COUT(co2_1));
+
+    defparam r_gctr_3.INJECT1_1 = "NO" ;
+    defparam r_gctr_3.INJECT1_0 = "NO" ;
+    defparam r_gctr_3.INIT1 =  16'h66AA ;
+    defparam r_gctr_3.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_3 (.A0(rcount_6), .A1(rcount_7), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co2_1), .S0(ircount_6), .S1(ircount_7), .COUT(co3_1));
+
+    defparam r_gctr_4.INJECT1_1 = "NO" ;
+    defparam r_gctr_4.INJECT1_0 = "NO" ;
+    defparam r_gctr_4.INIT1 =  16'h66AA ;
+    defparam r_gctr_4.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_4 (.A0(rcount_8), .A1(rcount_9), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co3_1), .S0(ircount_8), .S1(ircount_9), .COUT(co4_1));
+
+    defparam empty_cmp_ci_a.INJECT1_1 = "NO" ;
+    defparam empty_cmp_ci_a.INJECT1_0 = "NO" ;
+    defparam empty_cmp_ci_a.INIT1 =  16'h66AA ;
+    defparam empty_cmp_ci_a.INIT0 =  16'h66AA ;
+    CCU2C empty_cmp_ci_a (.A0(scuba_vlo), .A1(rden_i), .B0(scuba_vlo), .B1(rden_i), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(cmp_ci));
+
+    defparam empty_cmp_0.INJECT1_1 = "NO" ;
+    defparam empty_cmp_0.INJECT1_0 = "NO" ;
+    defparam empty_cmp_0.INIT1 =  16'h99AA ;
+    defparam empty_cmp_0.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_0 (.A0(rcount_0), .A1(rcount_1), .B0(wcount_r0), .B1(wcount_r1), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(cmp_ci), .S0(), .S1(), .COUT(co0_2));
+
+    defparam empty_cmp_1.INJECT1_1 = "NO" ;
+    defparam empty_cmp_1.INJECT1_0 = "NO" ;
+    defparam empty_cmp_1.INIT1 =  16'h99AA ;
+    defparam empty_cmp_1.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_1 (.A0(rcount_2), .A1(rcount_3), .B0(wcount_r2), .B1(wcount_r3), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_2), .S0(), .S1(), .COUT(co1_2));
+
+    defparam empty_cmp_2.INJECT1_1 = "NO" ;
+    defparam empty_cmp_2.INJECT1_0 = "NO" ;
+    defparam empty_cmp_2.INIT1 =  16'h99AA ;
+    defparam empty_cmp_2.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_2 (.A0(rcount_4), .A1(rcount_5), .B0(wcount_r4), .B1(wcount_r5), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_2), .S0(), .S1(), .COUT(co2_2));
+
+    defparam empty_cmp_3.INJECT1_1 = "NO" ;
+    defparam empty_cmp_3.INJECT1_0 = "NO" ;
+    defparam empty_cmp_3.INIT1 =  16'h99AA ;
+    defparam empty_cmp_3.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_3 (.A0(rcount_6), .A1(rcount_7), .B0(w_g2b_xor_cluster_0), 
+        .B1(wcount_r7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co2_2), .S0(), .S1(), .COUT(co3_2));
+
+    defparam empty_cmp_4.INJECT1_1 = "NO" ;
+    defparam empty_cmp_4.INJECT1_0 = "NO" ;
+    defparam empty_cmp_4.INIT1 =  16'h99AA ;
+    defparam empty_cmp_4.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_4 (.A0(rcount_8), .A1(empty_cmp_set), .B0(wcount_r8), 
+        .B1(empty_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co3_2), .S0(), .S1(), .COUT(empty_d_c));
+
+    defparam a0.INJECT1_1 = "NO" ;
+    defparam a0.INJECT1_0 = "NO" ;
+    defparam a0.INIT1 =  16'h66AA ;
+    defparam a0.INIT0 =  16'h66AA ;
+    CCU2C a0 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(empty_d_c), .S0(empty_d), .S1(), .COUT());
+
+    defparam full_cmp_ci_a.INJECT1_1 = "NO" ;
+    defparam full_cmp_ci_a.INJECT1_0 = "NO" ;
+    defparam full_cmp_ci_a.INIT1 =  16'h66AA ;
+    defparam full_cmp_ci_a.INIT0 =  16'h66AA ;
+    CCU2C full_cmp_ci_a (.A0(scuba_vlo), .A1(wren_i), .B0(scuba_vlo), .B1(wren_i), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(cmp_ci_1));
+
+    defparam full_cmp_0.INJECT1_1 = "NO" ;
+    defparam full_cmp_0.INJECT1_0 = "NO" ;
+    defparam full_cmp_0.INIT1 =  16'h99AA ;
+    defparam full_cmp_0.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_0 (.A0(wcount_0), .A1(wcount_1), .B0(rcount_w0), .B1(rcount_w1), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(cmp_ci_1), .S0(), .S1(), .COUT(co0_3));
+
+    defparam full_cmp_1.INJECT1_1 = "NO" ;
+    defparam full_cmp_1.INJECT1_0 = "NO" ;
+    defparam full_cmp_1.INIT1 =  16'h99AA ;
+    defparam full_cmp_1.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_1 (.A0(wcount_2), .A1(wcount_3), .B0(rcount_w2), .B1(rcount_w3), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_3), .S0(), .S1(), .COUT(co1_3));
+
+    defparam full_cmp_2.INJECT1_1 = "NO" ;
+    defparam full_cmp_2.INJECT1_0 = "NO" ;
+    defparam full_cmp_2.INIT1 =  16'h99AA ;
+    defparam full_cmp_2.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_2 (.A0(wcount_4), .A1(wcount_5), .B0(rcount_w4), .B1(rcount_w5), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_3), .S0(), .S1(), .COUT(co2_3));
+
+    defparam full_cmp_3.INJECT1_1 = "NO" ;
+    defparam full_cmp_3.INJECT1_0 = "NO" ;
+    defparam full_cmp_3.INIT1 =  16'h99AA ;
+    defparam full_cmp_3.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_3 (.A0(wcount_6), .A1(wcount_7), .B0(r_g2b_xor_cluster_0), 
+        .B1(rcount_w7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co2_3), .S0(), .S1(), .COUT(co3_3));
+
+    defparam full_cmp_4.INJECT1_1 = "NO" ;
+    defparam full_cmp_4.INJECT1_0 = "NO" ;
+    defparam full_cmp_4.INIT1 =  16'h99AA ;
+    defparam full_cmp_4.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_4 (.A0(wcount_8), .A1(full_cmp_set), .B0(rcount_w8), 
+        .B1(full_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co3_3), .S0(), .S1(), .COUT(full_d_c));
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam a1.INJECT1_1 = "NO" ;
+    defparam a1.INJECT1_0 = "NO" ;
+    defparam a1.INIT1 =  16'h66AA ;
+    defparam a1.INIT0 =  16'h66AA ;
+    CCU2C a1 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(full_d_c), .S0(full_d), .S1(), .COUT());
+
+    assign Empty = empty_i;
+    assign Full = full_i;
+
+
+    // exemplar begin
+    // exemplar attribute pdp_ram_0_0_0 MEM_LPC_FILE fifo32dc.lpc
+    // exemplar attribute pdp_ram_0_0_0 MEM_INIT_FILE 
+    // exemplar attribute FF_101 GSR ENABLED
+    // exemplar attribute FF_100 GSR ENABLED
+    // exemplar attribute FF_99 GSR ENABLED
+    // exemplar attribute FF_98 GSR ENABLED
+    // exemplar attribute FF_97 GSR ENABLED
+    // exemplar attribute FF_96 GSR ENABLED
+    // exemplar attribute FF_95 GSR ENABLED
+    // exemplar attribute FF_94 GSR ENABLED
+    // exemplar attribute FF_93 GSR ENABLED
+    // exemplar attribute FF_92 GSR ENABLED
+    // exemplar attribute FF_91 GSR ENABLED
+    // exemplar attribute FF_90 GSR ENABLED
+    // exemplar attribute FF_89 GSR ENABLED
+    // exemplar attribute FF_88 GSR ENABLED
+    // exemplar attribute FF_87 GSR ENABLED
+    // exemplar attribute FF_86 GSR ENABLED
+    // exemplar attribute FF_85 GSR ENABLED
+    // exemplar attribute FF_84 GSR ENABLED
+    // exemplar attribute FF_83 GSR ENABLED
+    // exemplar attribute FF_82 GSR ENABLED
+    // exemplar attribute FF_81 GSR ENABLED
+    // exemplar attribute FF_80 GSR ENABLED
+    // exemplar attribute FF_79 GSR ENABLED
+    // exemplar attribute FF_78 GSR ENABLED
+    // exemplar attribute FF_77 GSR ENABLED
+    // exemplar attribute FF_76 GSR ENABLED
+    // exemplar attribute FF_75 GSR ENABLED
+    // exemplar attribute FF_74 GSR ENABLED
+    // exemplar attribute FF_73 GSR ENABLED
+    // exemplar attribute FF_72 GSR ENABLED
+    // exemplar attribute FF_71 GSR ENABLED
+    // exemplar attribute FF_70 GSR ENABLED
+    // exemplar attribute FF_69 GSR ENABLED
+    // exemplar attribute FF_68 GSR ENABLED
+    // exemplar attribute FF_67 GSR ENABLED
+    // exemplar attribute FF_66 GSR ENABLED
+    // exemplar attribute FF_65 GSR ENABLED
+    // exemplar attribute FF_64 GSR ENABLED
+    // exemplar attribute FF_63 GSR ENABLED
+    // exemplar attribute FF_62 GSR ENABLED
+    // exemplar attribute FF_61 GSR ENABLED
+    // exemplar attribute FF_60 GSR ENABLED
+    // exemplar attribute FF_59 GSR ENABLED
+    // exemplar attribute FF_58 GSR ENABLED
+    // exemplar attribute FF_57 GSR ENABLED
+    // exemplar attribute FF_56 GSR ENABLED
+    // exemplar attribute FF_55 GSR ENABLED
+    // exemplar attribute FF_54 GSR ENABLED
+    // exemplar attribute FF_53 GSR ENABLED
+    // exemplar attribute FF_52 GSR ENABLED
+    // exemplar attribute FF_51 GSR ENABLED
+    // exemplar attribute FF_50 GSR ENABLED
+    // exemplar attribute FF_49 GSR ENABLED
+    // exemplar attribute FF_48 GSR ENABLED
+    // exemplar attribute FF_47 GSR ENABLED
+    // exemplar attribute FF_46 GSR ENABLED
+    // exemplar attribute FF_45 GSR ENABLED
+    // exemplar attribute FF_44 GSR ENABLED
+    // exemplar attribute FF_43 GSR ENABLED
+    // exemplar attribute FF_42 GSR ENABLED
+    // exemplar attribute FF_41 GSR ENABLED
+    // exemplar attribute FF_40 GSR ENABLED
+    // exemplar attribute FF_39 GSR ENABLED
+    // exemplar attribute FF_38 GSR ENABLED
+    // exemplar attribute FF_37 GSR ENABLED
+    // exemplar attribute FF_36 GSR ENABLED
+    // exemplar attribute FF_35 GSR ENABLED
+    // exemplar attribute FF_34 GSR ENABLED
+    // exemplar attribute FF_33 GSR ENABLED
+    // exemplar attribute FF_32 GSR ENABLED
+    // exemplar attribute FF_31 GSR ENABLED
+    // exemplar attribute FF_30 GSR ENABLED
+    // exemplar attribute FF_29 GSR ENABLED
+    // exemplar attribute FF_28 GSR ENABLED
+    // exemplar attribute FF_27 GSR ENABLED
+    // exemplar attribute FF_26 GSR ENABLED
+    // exemplar attribute FF_25 GSR ENABLED
+    // exemplar attribute FF_24 GSR ENABLED
+    // exemplar attribute FF_23 GSR ENABLED
+    // exemplar attribute FF_22 GSR ENABLED
+    // exemplar attribute FF_21 GSR ENABLED
+    // exemplar attribute FF_20 GSR ENABLED
+    // exemplar attribute FF_19 GSR ENABLED
+    // exemplar attribute FF_18 GSR ENABLED
+    // exemplar attribute FF_17 GSR ENABLED
+    // exemplar attribute FF_16 GSR ENABLED
+    // exemplar attribute FF_15 GSR ENABLED
+    // exemplar attribute FF_14 GSR ENABLED
+    // exemplar attribute FF_13 GSR ENABLED
+    // exemplar attribute FF_12 GSR ENABLED
+    // exemplar attribute FF_11 GSR ENABLED
+    // exemplar attribute FF_10 GSR ENABLED
+    // exemplar attribute FF_9 GSR ENABLED
+    // exemplar attribute FF_8 GSR ENABLED
+    // exemplar attribute FF_7 GSR ENABLED
+    // exemplar attribute FF_6 GSR ENABLED
+    // exemplar attribute FF_5 GSR ENABLED
+    // exemplar attribute FF_4 GSR ENABLED
+    // exemplar attribute FF_3 GSR ENABLED
+    // exemplar attribute FF_2 GSR ENABLED
+    // exemplar attribute FF_1 GSR ENABLED
+    // exemplar attribute FF_0 GSR ENABLED
+    // exemplar end
+
+endmodule
diff --git a/fifo32dc/fifo32dc_generate.log b/fifo32dc/fifo32dc_generate.log
new file mode 100644
index 0000000..24573c0
--- /dev/null
+++ b/fifo32dc/fifo32dc_generate.log
@@ -0,0 +1,49 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Sun Sep 13 16:38:25 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 
+    Circuit name     : fifo32dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+	Inputs       : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+	Outputs      : Q[31:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo32dc.edn
+    Verilog output   : fifo32dc.v
+    Verilog template : fifo32dc_tmpl.v
+    Verilog testbench: tb_fifo32dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo32dc.srp
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 1
+            Reg : 102
+
+END   SCUBA Module Synthesis
+
+File: fifo32dc.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/fifo32dc/fifo32dc_tmpl.v b/fifo32dc/fifo32dc_tmpl.v
new file mode 100644
index 0000000..7f35eff
--- /dev/null
+++ b/fifo32dc/fifo32dc_tmpl.v
@@ -0,0 +1,7 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.8 */
+/* Sun Sep 13 16:38:29 2020 */
+
+/* parameterized module instance */
+fifo32dc __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
+    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ));
diff --git a/fifo32dc/generate_core.tcl b/fifo32dc/generate_core.tcl
new file mode 100644
index 0000000..6cb63b1
--- /dev/null
+++ b/fifo32dc/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "fifo32dc"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/fifo32dc/generate_ngd.tcl b/fifo32dc/generate_ngd.tcl
new file mode 100644
index 0000000..adc592e
--- /dev/null
+++ b/fifo32dc/generate_ngd.tcl
@@ -0,0 +1,74 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "fifo32dc"
+set Para(Module) "FIFO_DC"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/fifo32dc/msg_file.log b/fifo32dc/msg_file.log
new file mode 100644
index 0000000..bc796a7
--- /dev/null
+++ b/fifo32dc/msg_file.log
@@ -0,0 +1,33 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Sun Sep 13 16:38:25 2020
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 
+    Circuit name     : fifo32dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+    Inputs       : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+    Outputs      : Q[31:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo32dc.edn
+    Verilog output   : fifo32dc.v
+    Verilog template : fifo32dc_tmpl.v
+    Verilog testbench: tb_fifo32dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo32dc.srp
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 1
+            Reg : 102
+  
+END   SCUBA Module Synthesis
+
diff --git a/fifo32dc/tb_fifo32dc_tmpl.v b/fifo32dc/tb_fifo32dc_tmpl.v
new file mode 100644
index 0000000..1c08fc7
--- /dev/null
+++ b/fifo32dc/tb_fifo32dc_tmpl.v
@@ -0,0 +1,76 @@
+//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.11.2.446
+`timescale 1 ns / 1 ps
+module tb;
+    reg [31:0] Data = 32'b0;
+    reg WrClock = 0;
+    reg RdClock = 0;
+    reg WrEn = 0;
+    reg RdEn = 0;
+    reg Reset = 0;
+    reg RPReset = 0;
+    wire [31:0] Q;
+    wire Empty;
+    wire Full;
+
+    integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0;
+
+    GSR GSR_INST (.GSR(1'b1));
+    PUR PUR_INST (.PUR(1'b1));
+
+    fifo32dc u1 (.Data(Data), .WrClock(WrClock), .RdClock(RdClock), .WrEn(WrEn), 
+        .RdEn(RdEn), .Reset(Reset), .RPReset(RPReset), .Q(Q), .Empty(Empty), 
+        .Full(Full)
+    );
+
+    initial
+    begin
+       Data <= 0;
+      #100;
+      @(Reset == 1'b0);
+      for (i1 = 0; i1 < 515; i1 = i1 + 1) begin
+        @(posedge WrClock);
+        #1  Data <= Data + 1'b1;
+      end
+    end
+    always
+    #5.00 WrClock <= ~ WrClock;
+
+    always
+    #5.00 RdClock <= ~ RdClock;
+
+    initial
+    begin
+       WrEn <= 1'b0;
+      #100;
+      @(Reset == 1'b0);
+      for (i4 = 0; i4 < 515; i4 = i4 + 1) begin
+        @(posedge WrClock);
+        #1  WrEn <= 1'b1;
+      end
+       WrEn <= 1'b0;
+    end
+    initial
+    begin
+       RdEn <= 1'b0;
+      @(Reset == 1'b0);
+      @(WrEn == 1'b1);
+      @(WrEn == 1'b0);
+      for (i5 = 0; i5 < 515; i5 = i5 + 1) begin
+        @(posedge RdClock);
+        #1  RdEn <= 1'b1;
+      end
+       RdEn <= 1'b0;
+    end
+    initial
+    begin
+       Reset <= 1'b1;
+      #100;
+       Reset <= 1'b0;
+    end
+    initial
+    begin
+       RPReset <= 1'b1;
+      #100;
+       RPReset <= 1'b0;
+    end
+endmodule
\ No newline at end of file
diff --git a/fifo40_dc/fifo40_dc.cst b/fifo40_dc/fifo40_dc.cst
new file mode 100644
index 0000000..a32fb04
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.cst
@@ -0,0 +1,3 @@
+Date=02/09/2021
+Time=13:19:24
+
diff --git a/fifo40_dc/fifo40_dc.edn b/fifo40_dc/fifo40_dc.edn
new file mode 100644
index 0000000..51db303
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.edn
@@ -0,0 +1,3245 @@
+(edif fifo40_dc
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2021 2 9 13 19 26)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell OR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell PDPW16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DI35
+            (direction INPUT))
+          (port DI34
+            (direction INPUT))
+          (port DI33
+            (direction INPUT))
+          (port DI32
+            (direction INPUT))
+          (port DI31
+            (direction INPUT))
+          (port DI30
+            (direction INPUT))
+          (port DI29
+            (direction INPUT))
+          (port DI28
+            (direction INPUT))
+          (port DI27
+            (direction INPUT))
+          (port DI26
+            (direction INPUT))
+          (port DI25
+            (direction INPUT))
+          (port DI24
+            (direction INPUT))
+          (port DI23
+            (direction INPUT))
+          (port DI22
+            (direction INPUT))
+          (port DI21
+            (direction INPUT))
+          (port DI20
+            (direction INPUT))
+          (port DI19
+            (direction INPUT))
+          (port DI18
+            (direction INPUT))
+          (port DI17
+            (direction INPUT))
+          (port DI16
+            (direction INPUT))
+          (port DI15
+            (direction INPUT))
+          (port DI14
+            (direction INPUT))
+          (port DI13
+            (direction INPUT))
+          (port DI12
+            (direction INPUT))
+          (port DI11
+            (direction INPUT))
+          (port DI10
+            (direction INPUT))
+          (port DI9
+            (direction INPUT))
+          (port DI8
+            (direction INPUT))
+          (port DI7
+            (direction INPUT))
+          (port DI6
+            (direction INPUT))
+          (port DI5
+            (direction INPUT))
+          (port DI4
+            (direction INPUT))
+          (port DI3
+            (direction INPUT))
+          (port DI2
+            (direction INPUT))
+          (port DI1
+            (direction INPUT))
+          (port DI0
+            (direction INPUT))
+          (port ADW8
+            (direction INPUT))
+          (port ADW7
+            (direction INPUT))
+          (port ADW6
+            (direction INPUT))
+          (port ADW5
+            (direction INPUT))
+          (port ADW4
+            (direction INPUT))
+          (port ADW3
+            (direction INPUT))
+          (port ADW2
+            (direction INPUT))
+          (port ADW1
+            (direction INPUT))
+          (port ADW0
+            (direction INPUT))
+          (port BE3
+            (direction INPUT))
+          (port BE2
+            (direction INPUT))
+          (port BE1
+            (direction INPUT))
+          (port BE0
+            (direction INPUT))
+          (port CEW
+            (direction INPUT))
+          (port CLKW
+            (direction INPUT))
+          (port CSW2
+            (direction INPUT))
+          (port CSW1
+            (direction INPUT))
+          (port CSW0
+            (direction INPUT))
+          (port ADR13
+            (direction INPUT))
+          (port ADR12
+            (direction INPUT))
+          (port ADR11
+            (direction INPUT))
+          (port ADR10
+            (direction INPUT))
+          (port ADR9
+            (direction INPUT))
+          (port ADR8
+            (direction INPUT))
+          (port ADR7
+            (direction INPUT))
+          (port ADR6
+            (direction INPUT))
+          (port ADR5
+            (direction INPUT))
+          (port ADR4
+            (direction INPUT))
+          (port ADR3
+            (direction INPUT))
+          (port ADR2
+            (direction INPUT))
+          (port ADR1
+            (direction INPUT))
+          (port ADR0
+            (direction INPUT))
+          (port CER
+            (direction INPUT))
+          (port OCER
+            (direction INPUT))
+          (port CLKR
+            (direction INPUT))
+          (port CSR2
+            (direction INPUT))
+          (port CSR1
+            (direction INPUT))
+          (port CSR0
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port DO35
+            (direction OUTPUT))
+          (port DO34
+            (direction OUTPUT))
+          (port DO33
+            (direction OUTPUT))
+          (port DO32
+            (direction OUTPUT))
+          (port DO31
+            (direction OUTPUT))
+          (port DO30
+            (direction OUTPUT))
+          (port DO29
+            (direction OUTPUT))
+          (port DO28
+            (direction OUTPUT))
+          (port DO27
+            (direction OUTPUT))
+          (port DO26
+            (direction OUTPUT))
+          (port DO25
+            (direction OUTPUT))
+          (port DO24
+            (direction OUTPUT))
+          (port DO23
+            (direction OUTPUT))
+          (port DO22
+            (direction OUTPUT))
+          (port DO21
+            (direction OUTPUT))
+          (port DO20
+            (direction OUTPUT))
+          (port DO19
+            (direction OUTPUT))
+          (port DO18
+            (direction OUTPUT))
+          (port DO17
+            (direction OUTPUT))
+          (port DO16
+            (direction OUTPUT))
+          (port DO15
+            (direction OUTPUT))
+          (port DO14
+            (direction OUTPUT))
+          (port DO13
+            (direction OUTPUT))
+          (port DO12
+            (direction OUTPUT))
+          (port DO11
+            (direction OUTPUT))
+          (port DO10
+            (direction OUTPUT))
+          (port DO9
+            (direction OUTPUT))
+          (port DO8
+            (direction OUTPUT))
+          (port DO7
+            (direction OUTPUT))
+          (port DO6
+            (direction OUTPUT))
+          (port DO5
+            (direction OUTPUT))
+          (port DO4
+            (direction OUTPUT))
+          (port DO3
+            (direction OUTPUT))
+          (port DO2
+            (direction OUTPUT))
+          (port DO1
+            (direction OUTPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell fifo40_dc
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(39:0)") 40)
+            (direction INPUT))
+          (port WrClock
+            (direction INPUT))
+          (port RdClock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port RPReset
+            (direction INPUT))
+          (port (array (rename Q "Q(39:0)") 40)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t20
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t19
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance OR2_t18
+            (viewRef view1 
+              (cellRef OR2)))
+          (instance XOR2_t17
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t16
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t15
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t14
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t13
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t12
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t11
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t10
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t9
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t8
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t7
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t6
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t5
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t4
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t3
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t1
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance LUT4_23
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_22
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_21
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_20
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_19
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_18
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_17
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_16
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_15
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_14
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_13
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_12
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_11
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_10
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_9
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_8
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_7
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_6
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_5
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_4
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_3
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0410")))
+          (instance LUT4_2
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x1004")))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0140")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x4001")))
+          (instance pdp_ram_0_0_1
+            (viewRef view1 
+              (cellRef PDPW16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo40_dc.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_R
+              (string "0b000"))
+            (property CSDECODE_W
+              (string "0b001"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE
+              (string "NOREG"))
+            (property DATA_WIDTH_R
+              (string "36"))
+            (property DATA_WIDTH_W
+              (string "36")))
+          (instance pdp_ram_0_1_0
+            (viewRef view1 
+              (cellRef PDPW16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo40_dc.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_R
+              (string "0b000"))
+            (property CSDECODE_W
+              (string "0b001"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE
+              (string "NOREG"))
+            (property DATA_WIDTH_R
+              (string "36"))
+            (property DATA_WIDTH_W
+              (string "36")))
+          (instance FF_101
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_100
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_99
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_98
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_97
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_96
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_95
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_94
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_93
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_92
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_91
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_90
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_89
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_88
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_87
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_86
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_85
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_84
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_83
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance w_gctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_gctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_gctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance empty_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance empty_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance empty_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance full_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance full_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance full_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t20))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_0))
+              (portRef B (instanceRef AND2_t19))))
+          (net w_g2b_xor_cluster_1
+            (joined
+              (portRef AD2 (instanceRef LUT4_14))
+              (portRef DO0 (instanceRef LUT4_22))
+              (portRef AD2 (instanceRef LUT4_16))
+              (portRef AD2 (instanceRef LUT4_15))))
+          (net r_g2b_xor_cluster_1
+            (joined
+              (portRef AD2 (instanceRef LUT4_4))
+              (portRef DO0 (instanceRef LUT4_12))
+              (portRef AD2 (instanceRef LUT4_6))
+              (portRef AD2 (instanceRef LUT4_5))))
+          (net w_gdata_0
+            (joined
+              (portRef D (instanceRef FF_91))
+              (portRef Z (instanceRef XOR2_t17))))
+          (net w_gdata_1
+            (joined
+              (portRef D (instanceRef FF_90))
+              (portRef Z (instanceRef XOR2_t16))))
+          (net w_gdata_2
+            (joined
+              (portRef D (instanceRef FF_89))
+              (portRef Z (instanceRef XOR2_t15))))
+          (net w_gdata_3
+            (joined
+              (portRef D (instanceRef FF_88))
+              (portRef Z (instanceRef XOR2_t14))))
+          (net w_gdata_4
+            (joined
+              (portRef D (instanceRef FF_87))
+              (portRef Z (instanceRef XOR2_t13))))
+          (net w_gdata_5
+            (joined
+              (portRef D (instanceRef FF_86))
+              (portRef Z (instanceRef XOR2_t12))))
+          (net w_gdata_6
+            (joined
+              (portRef D (instanceRef FF_85))
+              (portRef Z (instanceRef XOR2_t11))))
+          (net w_gdata_7
+            (joined
+              (portRef D (instanceRef FF_84))
+              (portRef Z (instanceRef XOR2_t10))))
+          (net w_gdata_8
+            (joined
+              (portRef D (instanceRef FF_83))
+              (portRef Z (instanceRef XOR2_t9))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_81))
+              (portRef ADW0 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW0 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_80))
+              (portRef ADW1 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW1 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_79))
+              (portRef ADW2 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW2 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_78))
+              (portRef ADW3 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW3 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_77))
+              (portRef ADW4 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW4 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_76))
+              (portRef ADW5 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW5 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_75))
+              (portRef ADW6 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW6 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_74))
+              (portRef ADW7 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW7 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_73))
+              (portRef ADW8 (instanceRef pdp_ram_0_0_1))
+              (portRef ADW8 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_72))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))))
+          (net r_gdata_0
+            (joined
+              (portRef D (instanceRef FF_61))
+              (portRef Z (instanceRef XOR2_t8))))
+          (net r_gdata_1
+            (joined
+              (portRef D (instanceRef FF_60))
+              (portRef Z (instanceRef XOR2_t7))))
+          (net r_gdata_2
+            (joined
+              (portRef D (instanceRef FF_59))
+              (portRef Z (instanceRef XOR2_t6))))
+          (net r_gdata_3
+            (joined
+              (portRef D (instanceRef FF_58))
+              (portRef Z (instanceRef XOR2_t5))))
+          (net r_gdata_4
+            (joined
+              (portRef D (instanceRef FF_57))
+              (portRef Z (instanceRef XOR2_t4))))
+          (net r_gdata_5
+            (joined
+              (portRef D (instanceRef FF_56))
+              (portRef Z (instanceRef XOR2_t3))))
+          (net r_gdata_6
+            (joined
+              (portRef D (instanceRef FF_55))
+              (portRef Z (instanceRef XOR2_t2))))
+          (net r_gdata_7
+            (joined
+              (portRef D (instanceRef FF_54))
+              (portRef Z (instanceRef XOR2_t1))))
+          (net r_gdata_8
+            (joined
+              (portRef D (instanceRef FF_53))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net rptr_0
+            (joined
+              (portRef Q (instanceRef FF_51))
+              (portRef ADR5 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR5 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_1
+            (joined
+              (portRef Q (instanceRef FF_50))
+              (portRef ADR6 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR6 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_2
+            (joined
+              (portRef Q (instanceRef FF_49))
+              (portRef ADR7 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR7 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_3
+            (joined
+              (portRef Q (instanceRef FF_48))
+              (portRef ADR8 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR8 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_4
+            (joined
+              (portRef Q (instanceRef FF_47))
+              (portRef ADR9 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR9 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_5
+            (joined
+              (portRef Q (instanceRef FF_46))
+              (portRef ADR10 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR10 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_6
+            (joined
+              (portRef Q (instanceRef FF_45))
+              (portRef ADR11 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR11 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_7
+            (joined
+              (portRef Q (instanceRef FF_44))
+              (portRef ADR12 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR12 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_8
+            (joined
+              (portRef Q (instanceRef FF_43))
+              (portRef ADR13 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR13 (instanceRef pdp_ram_0_1_0))))
+          (net rptr_9
+            (joined
+              (portRef Q (instanceRef FF_42))
+              (portRef AD3 (instanceRef LUT4_3))
+              (portRef AD3 (instanceRef LUT4_2))))
+          (net w_gcount_0
+            (joined
+              (portRef D (instanceRef FF_41))
+              (portRef Q (instanceRef FF_91))))
+          (net w_gcount_1
+            (joined
+              (portRef D (instanceRef FF_40))
+              (portRef Q (instanceRef FF_90))))
+          (net w_gcount_2
+            (joined
+              (portRef D (instanceRef FF_39))
+              (portRef Q (instanceRef FF_89))))
+          (net w_gcount_3
+            (joined
+              (portRef D (instanceRef FF_38))
+              (portRef Q (instanceRef FF_88))))
+          (net w_gcount_4
+            (joined
+              (portRef D (instanceRef FF_37))
+              (portRef Q (instanceRef FF_87))))
+          (net w_gcount_5
+            (joined
+              (portRef D (instanceRef FF_36))
+              (portRef Q (instanceRef FF_86))))
+          (net w_gcount_6
+            (joined
+              (portRef D (instanceRef FF_35))
+              (portRef Q (instanceRef FF_85))))
+          (net w_gcount_7
+            (joined
+              (portRef D (instanceRef FF_34))
+              (portRef Q (instanceRef FF_84))))
+          (net w_gcount_8
+            (joined
+              (portRef D (instanceRef FF_33))
+              (portRef Q (instanceRef FF_83))))
+          (net w_gcount_9
+            (joined
+              (portRef D (instanceRef FF_32))
+              (portRef Q (instanceRef FF_82))))
+          (net r_gcount_0
+            (joined
+              (portRef D (instanceRef FF_31))
+              (portRef Q (instanceRef FF_61))))
+          (net r_gcount_1
+            (joined
+              (portRef D (instanceRef FF_30))
+              (portRef Q (instanceRef FF_60))))
+          (net r_gcount_2
+            (joined
+              (portRef D (instanceRef FF_29))
+              (portRef Q (instanceRef FF_59))))
+          (net r_gcount_3
+            (joined
+              (portRef D (instanceRef FF_28))
+              (portRef Q (instanceRef FF_58))))
+          (net r_gcount_4
+            (joined
+              (portRef D (instanceRef FF_27))
+              (portRef Q (instanceRef FF_57))))
+          (net r_gcount_5
+            (joined
+              (portRef D (instanceRef FF_26))
+              (portRef Q (instanceRef FF_56))))
+          (net r_gcount_6
+            (joined
+              (portRef D (instanceRef FF_25))
+              (portRef Q (instanceRef FF_55))))
+          (net r_gcount_7
+            (joined
+              (portRef D (instanceRef FF_24))
+              (portRef Q (instanceRef FF_54))))
+          (net r_gcount_8
+            (joined
+              (portRef D (instanceRef FF_23))
+              (portRef Q (instanceRef FF_53))))
+          (net r_gcount_9
+            (joined
+              (portRef D (instanceRef FF_22))
+              (portRef Q (instanceRef FF_52))))
+          (net w_gcount_r20
+            (joined
+              (portRef Q (instanceRef FF_21))
+              (portRef AD1 (instanceRef LUT4_14))))
+          (net w_gcount_r0
+            (joined
+              (portRef D (instanceRef FF_21))
+              (portRef Q (instanceRef FF_41))))
+          (net w_gcount_r21
+            (joined
+              (portRef Q (instanceRef FF_20))
+              (portRef AD1 (instanceRef LUT4_15))
+              (portRef AD0 (instanceRef LUT4_14))))
+          (net w_gcount_r1
+            (joined
+              (portRef D (instanceRef FF_20))
+              (portRef Q (instanceRef FF_40))))
+          (net w_gcount_r22
+            (joined
+              (portRef Q (instanceRef FF_19))
+              (portRef AD3 (instanceRef LUT4_22))))
+          (net w_gcount_r2
+            (joined
+              (portRef D (instanceRef FF_19))
+              (portRef Q (instanceRef FF_39))))
+          (net w_gcount_r23
+            (joined
+              (portRef Q (instanceRef FF_18))
+              (portRef AD2 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_17))))
+          (net w_gcount_r3
+            (joined
+              (portRef D (instanceRef FF_18))
+              (portRef Q (instanceRef FF_38))))
+          (net w_gcount_r24
+            (joined
+              (portRef Q (instanceRef FF_17))
+              (portRef AD1 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_18))
+              (portRef AD2 (instanceRef LUT4_17))))
+          (net w_gcount_r4
+            (joined
+              (portRef D (instanceRef FF_17))
+              (portRef Q (instanceRef FF_37))))
+          (net w_gcount_r25
+            (joined
+              (portRef Q (instanceRef FF_16))
+              (portRef AD0 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_19))
+              (portRef AD2 (instanceRef LUT4_18))
+              (portRef AD1 (instanceRef LUT4_17))))
+          (net w_gcount_r5
+            (joined
+              (portRef D (instanceRef FF_16))
+              (portRef Q (instanceRef FF_36))))
+          (net w_gcount_r26
+            (joined
+              (portRef Q (instanceRef FF_15))
+              (portRef AD3 (instanceRef LUT4_23))
+              (portRef AD2 (instanceRef LUT4_19))
+              (portRef AD1 (instanceRef LUT4_18))))
+          (net w_gcount_r6
+            (joined
+              (portRef D (instanceRef FF_15))
+              (portRef Q (instanceRef FF_35))))
+          (net w_gcount_r27
+            (joined
+              (portRef Q (instanceRef FF_14))
+              (portRef AD2 (instanceRef LUT4_23))
+              (portRef AD3 (instanceRef LUT4_20))
+              (portRef AD1 (instanceRef LUT4_19))))
+          (net w_gcount_r7
+            (joined
+              (portRef D (instanceRef FF_14))
+              (portRef Q (instanceRef FF_34))))
+          (net w_gcount_r28
+            (joined
+              (portRef Q (instanceRef FF_13))
+              (portRef AD1 (instanceRef LUT4_23))
+              (portRef AD3 (instanceRef LUT4_21))
+              (portRef AD2 (instanceRef LUT4_20))))
+          (net w_gcount_r8
+            (joined
+              (portRef D (instanceRef FF_13))
+              (portRef Q (instanceRef FF_33))))
+          (net w_gcount_r29
+            (joined
+              (portRef Q (instanceRef FF_12))
+              (portRef AD0 (instanceRef LUT4_23))
+              (portRef AD2 (instanceRef LUT4_21))
+              (portRef AD1 (instanceRef LUT4_20))
+              (portRef AD1 (instanceRef LUT4_3))
+              (portRef AD1 (instanceRef LUT4_2))))
+          (net w_gcount_r9
+            (joined
+              (portRef D (instanceRef FF_12))
+              (portRef Q (instanceRef FF_32))))
+          (net r_gcount_w20
+            (joined
+              (portRef Q (instanceRef FF_11))
+              (portRef AD1 (instanceRef LUT4_4))))
+          (net r_gcount_w0
+            (joined
+              (portRef D (instanceRef FF_11))
+              (portRef Q (instanceRef FF_31))))
+          (net r_gcount_w21
+            (joined
+              (portRef Q (instanceRef FF_10))
+              (portRef AD1 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_4))))
+          (net r_gcount_w1
+            (joined
+              (portRef D (instanceRef FF_10))
+              (portRef Q (instanceRef FF_30))))
+          (net r_gcount_w22
+            (joined
+              (portRef Q (instanceRef FF_9))
+              (portRef AD3 (instanceRef LUT4_12))))
+          (net r_gcount_w2
+            (joined
+              (portRef D (instanceRef FF_9))
+              (portRef Q (instanceRef FF_29))))
+          (net r_gcount_w23
+            (joined
+              (portRef Q (instanceRef FF_8))
+              (portRef AD2 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_7))))
+          (net r_gcount_w3
+            (joined
+              (portRef D (instanceRef FF_8))
+              (portRef Q (instanceRef FF_28))))
+          (net r_gcount_w24
+            (joined
+              (portRef Q (instanceRef FF_7))
+              (portRef AD1 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_8))
+              (portRef AD2 (instanceRef LUT4_7))))
+          (net r_gcount_w4
+            (joined
+              (portRef D (instanceRef FF_7))
+              (portRef Q (instanceRef FF_27))))
+          (net r_gcount_w25
+            (joined
+              (portRef Q (instanceRef FF_6))
+              (portRef AD0 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_9))
+              (portRef AD2 (instanceRef LUT4_8))
+              (portRef AD1 (instanceRef LUT4_7))))
+          (net r_gcount_w5
+            (joined
+              (portRef D (instanceRef FF_6))
+              (portRef Q (instanceRef FF_26))))
+          (net r_gcount_w26
+            (joined
+              (portRef Q (instanceRef FF_5))
+              (portRef AD3 (instanceRef LUT4_13))
+              (portRef AD2 (instanceRef LUT4_9))
+              (portRef AD1 (instanceRef LUT4_8))))
+          (net r_gcount_w6
+            (joined
+              (portRef D (instanceRef FF_5))
+              (portRef Q (instanceRef FF_25))))
+          (net r_gcount_w27
+            (joined
+              (portRef Q (instanceRef FF_4))
+              (portRef AD2 (instanceRef LUT4_13))
+              (portRef AD3 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_9))))
+          (net r_gcount_w7
+            (joined
+              (portRef D (instanceRef FF_4))
+              (portRef Q (instanceRef FF_24))))
+          (net r_gcount_w28
+            (joined
+              (portRef Q (instanceRef FF_3))
+              (portRef AD1 (instanceRef LUT4_13))
+              (portRef AD3 (instanceRef LUT4_11))
+              (portRef AD2 (instanceRef LUT4_10))))
+          (net r_gcount_w8
+            (joined
+              (portRef D (instanceRef FF_3))
+              (portRef Q (instanceRef FF_23))))
+          (net r_gcount_w29
+            (joined
+              (portRef Q (instanceRef FF_2))
+              (portRef AD0 (instanceRef LUT4_13))
+              (portRef AD2 (instanceRef LUT4_11))
+              (portRef AD1 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef AD1 (instanceRef LUT4_0))))
+          (net r_gcount_w9
+            (joined
+              (portRef D (instanceRef FF_2))
+              (portRef Q (instanceRef FF_22))))
+          (net rRst
+            (joined
+              (portRef PD (instanceRef FF_1))
+              (portRef Z (instanceRef OR2_t18))
+              (portRef PD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_101))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_100))))
+          (net w_gctr_ci
+            (joined
+              (portRef CIN (instanceRef w_gctr_0))
+              (portRef COUT (instanceRef w_gctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_99))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_98))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef w_gctr_1))
+              (portRef COUT (instanceRef w_gctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_gctr_2))
+              (portRef D (instanceRef FF_97))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_gctr_2))
+              (portRef D (instanceRef FF_96))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef w_gctr_2))
+              (portRef COUT (instanceRef w_gctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_gctr_3))
+              (portRef D (instanceRef FF_95))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_gctr_3))
+              (portRef D (instanceRef FF_94))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef w_gctr_3))
+              (portRef COUT (instanceRef w_gctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_gctr_4))
+              (portRef D (instanceRef FF_93))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_gctr_4))
+              (portRef D (instanceRef FF_92))))
+          (net co4
+            (joined
+              (portRef COUT (instanceRef w_gctr_4))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef w_gctr_4))
+              (portRef COUT (instanceRef w_gctr_3))))
+          (net wcount_9
+            (joined
+              (portRef A1 (instanceRef w_gctr_4))
+              (portRef B (instanceRef XOR2_t9))
+              (portRef AD2 (instanceRef LUT4_1))
+              (portRef AD2 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_92))
+              (portRef D (instanceRef FF_82))
+              (portRef D (instanceRef FF_72))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_71))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_70))))
+          (net r_gctr_ci
+            (joined
+              (portRef CIN (instanceRef r_gctr_0))
+              (portRef COUT (instanceRef r_gctr_cia))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_69))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_68))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_1))
+              (portRef COUT (instanceRef r_gctr_0))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_gctr_2))
+              (portRef D (instanceRef FF_67))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_gctr_2))
+              (portRef D (instanceRef FF_66))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_2))
+              (portRef COUT (instanceRef r_gctr_1))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_gctr_3))
+              (portRef D (instanceRef FF_65))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_gctr_3))
+              (portRef D (instanceRef FF_64))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_3))
+              (portRef COUT (instanceRef r_gctr_2))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_gctr_4))
+              (portRef D (instanceRef FF_63))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_gctr_4))
+              (portRef D (instanceRef FF_62))))
+          (net co4_1
+            (joined
+              (portRef COUT (instanceRef r_gctr_4))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef r_gctr_4))
+              (portRef COUT (instanceRef r_gctr_3))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_gctr_4))
+              (portRef B (instanceRef XOR2_t0))
+              (portRef AD2 (instanceRef LUT4_3))
+              (portRef AD2 (instanceRef LUT4_2))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_52))
+              (portRef D (instanceRef FF_42))))
+          (net rden_i
+            (joined
+              (portRef A1 (instanceRef empty_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t19))
+              (portRef OCER (instanceRef pdp_ram_0_0_1))
+              (portRef CER (instanceRef pdp_ram_0_0_1))
+              (portRef OCER (instanceRef pdp_ram_0_1_0))
+              (portRef CER (instanceRef pdp_ram_0_1_0))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef B1 (instanceRef empty_cmp_ci_a))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef empty_cmp_0))
+              (portRef COUT (instanceRef empty_cmp_ci_a))))
+          (net wcount_r0
+            (joined
+              (portRef B0 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_14))))
+          (net wcount_r1
+            (joined
+              (portRef B1 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_15))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef empty_cmp_0))
+              (portRef A (instanceRef XOR2_t8))
+              (portRef Q (instanceRef FF_71))
+              (portRef D (instanceRef FF_51))
+              (portRef A0 (instanceRef r_gctr_0))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef empty_cmp_0))
+              (portRef B (instanceRef XOR2_t8))
+              (portRef A (instanceRef XOR2_t7))
+              (portRef Q (instanceRef FF_70))
+              (portRef D (instanceRef FF_50))
+              (portRef A1 (instanceRef r_gctr_0))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_1))
+              (portRef COUT (instanceRef empty_cmp_0))))
+          (net wcount_r2
+            (joined
+              (portRef B0 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_16))))
+          (net wcount_r3
+            (joined
+              (portRef B1 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_17))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef empty_cmp_1))
+              (portRef B (instanceRef XOR2_t7))
+              (portRef A (instanceRef XOR2_t6))
+              (portRef Q (instanceRef FF_69))
+              (portRef D (instanceRef FF_49))
+              (portRef A0 (instanceRef r_gctr_1))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef empty_cmp_1))
+              (portRef B (instanceRef XOR2_t6))
+              (portRef A (instanceRef XOR2_t5))
+              (portRef Q (instanceRef FF_68))
+              (portRef D (instanceRef FF_48))
+              (portRef A1 (instanceRef r_gctr_1))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_2))
+              (portRef COUT (instanceRef empty_cmp_1))))
+          (net wcount_r4
+            (joined
+              (portRef B0 (instanceRef empty_cmp_2))
+              (portRef DO0 (instanceRef LUT4_18))))
+          (net wcount_r5
+            (joined
+              (portRef B1 (instanceRef empty_cmp_2))
+              (portRef DO0 (instanceRef LUT4_19))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef empty_cmp_2))
+              (portRef B (instanceRef XOR2_t5))
+              (portRef A (instanceRef XOR2_t4))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_47))
+              (portRef A0 (instanceRef r_gctr_2))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef empty_cmp_2))
+              (portRef B (instanceRef XOR2_t4))
+              (portRef A (instanceRef XOR2_t3))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_46))
+              (portRef A1 (instanceRef r_gctr_2))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_3))
+              (portRef COUT (instanceRef empty_cmp_2))))
+          (net w_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef empty_cmp_3))
+              (portRef DO0 (instanceRef LUT4_23))
+              (portRef AD0 (instanceRef LUT4_17))
+              (portRef AD3 (instanceRef LUT4_16))
+              (portRef AD3 (instanceRef LUT4_15))
+              (portRef AD3 (instanceRef LUT4_14))))
+          (net wcount_r7
+            (joined
+              (portRef B1 (instanceRef empty_cmp_3))
+              (portRef DO0 (instanceRef LUT4_20))
+              (portRef AD0 (instanceRef LUT4_18))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef empty_cmp_3))
+              (portRef B (instanceRef XOR2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_45))
+              (portRef A0 (instanceRef r_gctr_3))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef empty_cmp_3))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef XOR2_t1))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_44))
+              (portRef A1 (instanceRef r_gctr_3))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef empty_cmp_4))
+              (portRef COUT (instanceRef empty_cmp_3))))
+          (net wcount_r8
+            (joined
+              (portRef B0 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_21))
+              (portRef AD0 (instanceRef LUT4_19))))
+          (net empty_cmp_clr
+            (joined
+              (portRef B1 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_2))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef empty_cmp_4))
+              (portRef B (instanceRef XOR2_t1))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_43))
+              (portRef A0 (instanceRef r_gctr_4))))
+          (net empty_cmp_set
+            (joined
+              (portRef A1 (instanceRef empty_cmp_4))
+              (portRef DO0 (instanceRef LUT4_3))))
+          (net empty_d
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef D (instanceRef FF_1))))
+          (net empty_d_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef empty_cmp_4))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef full_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t20))
+              (portRef CEW (instanceRef pdp_ram_0_0_1))
+              (portRef CEW (instanceRef pdp_ram_0_1_0))
+              (portRef SP (instanceRef FF_101))
+              (portRef SP (instanceRef FF_100))
+              (portRef SP (instanceRef FF_99))
+              (portRef SP (instanceRef FF_98))
+              (portRef SP (instanceRef FF_97))
+              (portRef SP (instanceRef FF_96))
+              (portRef SP (instanceRef FF_95))
+              (portRef SP (instanceRef FF_94))
+              (portRef SP (instanceRef FF_93))
+              (portRef SP (instanceRef FF_92))
+              (portRef SP (instanceRef FF_91))
+              (portRef SP (instanceRef FF_90))
+              (portRef SP (instanceRef FF_89))
+              (portRef SP (instanceRef FF_88))
+              (portRef SP (instanceRef FF_87))
+              (portRef SP (instanceRef FF_86))
+              (portRef SP (instanceRef FF_85))
+              (portRef SP (instanceRef FF_84))
+              (portRef SP (instanceRef FF_83))
+              (portRef SP (instanceRef FF_82))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))
+              (portRef SP (instanceRef FF_77))
+              (portRef SP (instanceRef FF_76))
+              (portRef SP (instanceRef FF_75))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef B1 (instanceRef full_cmp_ci_a))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef full_cmp_0))
+              (portRef COUT (instanceRef full_cmp_ci_a))))
+          (net rcount_w0
+            (joined
+              (portRef B0 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_4))))
+          (net rcount_w1
+            (joined
+              (portRef B1 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_5))))
+          (net wcount_0
+            (joined
+              (portRef A0 (instanceRef full_cmp_0))
+              (portRef A (instanceRef XOR2_t17))
+              (portRef Q (instanceRef FF_101))
+              (portRef D (instanceRef FF_81))
+              (portRef A0 (instanceRef w_gctr_0))))
+          (net wcount_1
+            (joined
+              (portRef A1 (instanceRef full_cmp_0))
+              (portRef B (instanceRef XOR2_t17))
+              (portRef A (instanceRef XOR2_t16))
+              (portRef Q (instanceRef FF_100))
+              (portRef D (instanceRef FF_80))
+              (portRef A1 (instanceRef w_gctr_0))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_1))
+              (portRef COUT (instanceRef full_cmp_0))))
+          (net rcount_w2
+            (joined
+              (portRef B0 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_6))))
+          (net rcount_w3
+            (joined
+              (portRef B1 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_7))))
+          (net wcount_2
+            (joined
+              (portRef A0 (instanceRef full_cmp_1))
+              (portRef B (instanceRef XOR2_t16))
+              (portRef A (instanceRef XOR2_t15))
+              (portRef Q (instanceRef FF_99))
+              (portRef D (instanceRef FF_79))
+              (portRef A0 (instanceRef w_gctr_1))))
+          (net wcount_3
+            (joined
+              (portRef A1 (instanceRef full_cmp_1))
+              (portRef B (instanceRef XOR2_t15))
+              (portRef A (instanceRef XOR2_t14))
+              (portRef Q (instanceRef FF_98))
+              (portRef D (instanceRef FF_78))
+              (portRef A1 (instanceRef w_gctr_1))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_2))
+              (portRef COUT (instanceRef full_cmp_1))))
+          (net rcount_w4
+            (joined
+              (portRef B0 (instanceRef full_cmp_2))
+              (portRef DO0 (instanceRef LUT4_8))))
+          (net rcount_w5
+            (joined
+              (portRef B1 (instanceRef full_cmp_2))
+              (portRef DO0 (instanceRef LUT4_9))))
+          (net wcount_4
+            (joined
+              (portRef A0 (instanceRef full_cmp_2))
+              (portRef B (instanceRef XOR2_t14))
+              (portRef A (instanceRef XOR2_t13))
+              (portRef Q (instanceRef FF_97))
+              (portRef D (instanceRef FF_77))
+              (portRef A0 (instanceRef w_gctr_2))))
+          (net wcount_5
+            (joined
+              (portRef A1 (instanceRef full_cmp_2))
+              (portRef B (instanceRef XOR2_t13))
+              (portRef A (instanceRef XOR2_t12))
+              (portRef Q (instanceRef FF_96))
+              (portRef D (instanceRef FF_76))
+              (portRef A1 (instanceRef w_gctr_2))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_3))
+              (portRef COUT (instanceRef full_cmp_2))))
+          (net r_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef full_cmp_3))
+              (portRef DO0 (instanceRef LUT4_13))
+              (portRef AD0 (instanceRef LUT4_7))
+              (portRef AD3 (instanceRef LUT4_6))
+              (portRef AD3 (instanceRef LUT4_5))
+              (portRef AD3 (instanceRef LUT4_4))))
+          (net rcount_w7
+            (joined
+              (portRef B1 (instanceRef full_cmp_3))
+              (portRef DO0 (instanceRef LUT4_10))
+              (portRef AD0 (instanceRef LUT4_8))))
+          (net wcount_6
+            (joined
+              (portRef A0 (instanceRef full_cmp_3))
+              (portRef B (instanceRef XOR2_t12))
+              (portRef A (instanceRef XOR2_t11))
+              (portRef Q (instanceRef FF_95))
+              (portRef D (instanceRef FF_75))
+              (portRef A0 (instanceRef w_gctr_3))))
+          (net wcount_7
+            (joined
+              (portRef A1 (instanceRef full_cmp_3))
+              (portRef B (instanceRef XOR2_t11))
+              (portRef A (instanceRef XOR2_t10))
+              (portRef Q (instanceRef FF_94))
+              (portRef D (instanceRef FF_74))
+              (portRef A1 (instanceRef w_gctr_3))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef full_cmp_4))
+              (portRef COUT (instanceRef full_cmp_3))))
+          (net rcount_w8
+            (joined
+              (portRef B0 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_11))
+              (portRef AD0 (instanceRef LUT4_9))))
+          (net full_cmp_clr
+            (joined
+              (portRef B1 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wcount_8
+            (joined
+              (portRef A0 (instanceRef full_cmp_4))
+              (portRef B (instanceRef XOR2_t10))
+              (portRef A (instanceRef XOR2_t9))
+              (portRef Q (instanceRef FF_93))
+              (portRef D (instanceRef FF_73))
+              (portRef A0 (instanceRef w_gctr_4))))
+          (net full_cmp_set
+            (joined
+              (portRef A1 (instanceRef full_cmp_4))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef CSW0 (instanceRef pdp_ram_0_0_1))
+              (portRef BE3 (instanceRef pdp_ram_0_0_1))
+              (portRef BE2 (instanceRef pdp_ram_0_0_1))
+              (portRef BE1 (instanceRef pdp_ram_0_0_1))
+              (portRef BE0 (instanceRef pdp_ram_0_0_1))
+              (portRef CSW0 (instanceRef pdp_ram_0_1_0))
+              (portRef BE3 (instanceRef pdp_ram_0_1_0))
+              (portRef BE2 (instanceRef pdp_ram_0_1_0))
+              (portRef BE1 (instanceRef pdp_ram_0_1_0))
+              (portRef BE0 (instanceRef pdp_ram_0_1_0))
+              (portRef C1 (instanceRef w_gctr_cia))
+              (portRef C0 (instanceRef w_gctr_cia))
+              (portRef D1 (instanceRef w_gctr_cia))
+              (portRef D0 (instanceRef w_gctr_cia))
+              (portRef B1 (instanceRef w_gctr_cia))
+              (portRef A1 (instanceRef w_gctr_cia))
+              (portRef D1 (instanceRef w_gctr_0))
+              (portRef D0 (instanceRef w_gctr_0))
+              (portRef C1 (instanceRef w_gctr_0))
+              (portRef C0 (instanceRef w_gctr_0))
+              (portRef D1 (instanceRef w_gctr_1))
+              (portRef D0 (instanceRef w_gctr_1))
+              (portRef C1 (instanceRef w_gctr_1))
+              (portRef C0 (instanceRef w_gctr_1))
+              (portRef D1 (instanceRef w_gctr_2))
+              (portRef D0 (instanceRef w_gctr_2))
+              (portRef C1 (instanceRef w_gctr_2))
+              (portRef C0 (instanceRef w_gctr_2))
+              (portRef D1 (instanceRef w_gctr_3))
+              (portRef D0 (instanceRef w_gctr_3))
+              (portRef C1 (instanceRef w_gctr_3))
+              (portRef C0 (instanceRef w_gctr_3))
+              (portRef D1 (instanceRef w_gctr_4))
+              (portRef D0 (instanceRef w_gctr_4))
+              (portRef C1 (instanceRef w_gctr_4))
+              (portRef C0 (instanceRef w_gctr_4))
+              (portRef C1 (instanceRef r_gctr_cia))
+              (portRef C0 (instanceRef r_gctr_cia))
+              (portRef D1 (instanceRef r_gctr_cia))
+              (portRef D0 (instanceRef r_gctr_cia))
+              (portRef B1 (instanceRef r_gctr_cia))
+              (portRef A1 (instanceRef r_gctr_cia))
+              (portRef D1 (instanceRef r_gctr_0))
+              (portRef D0 (instanceRef r_gctr_0))
+              (portRef C1 (instanceRef r_gctr_0))
+              (portRef C0 (instanceRef r_gctr_0))
+              (portRef D1 (instanceRef r_gctr_1))
+              (portRef D0 (instanceRef r_gctr_1))
+              (portRef C1 (instanceRef r_gctr_1))
+              (portRef C0 (instanceRef r_gctr_1))
+              (portRef D1 (instanceRef r_gctr_2))
+              (portRef D0 (instanceRef r_gctr_2))
+              (portRef C1 (instanceRef r_gctr_2))
+              (portRef C0 (instanceRef r_gctr_2))
+              (portRef D1 (instanceRef r_gctr_3))
+              (portRef D0 (instanceRef r_gctr_3))
+              (portRef C1 (instanceRef r_gctr_3))
+              (portRef C0 (instanceRef r_gctr_3))
+              (portRef D1 (instanceRef r_gctr_4))
+              (portRef D0 (instanceRef r_gctr_4))
+              (portRef C1 (instanceRef r_gctr_4))
+              (portRef C0 (instanceRef r_gctr_4))
+              (portRef C1 (instanceRef empty_cmp_ci_a))
+              (portRef C0 (instanceRef empty_cmp_ci_a))
+              (portRef D1 (instanceRef empty_cmp_ci_a))
+              (portRef D0 (instanceRef empty_cmp_ci_a))
+              (portRef D1 (instanceRef empty_cmp_0))
+              (portRef D0 (instanceRef empty_cmp_0))
+              (portRef C1 (instanceRef empty_cmp_0))
+              (portRef C0 (instanceRef empty_cmp_0))
+              (portRef D1 (instanceRef empty_cmp_1))
+              (portRef D0 (instanceRef empty_cmp_1))
+              (portRef C1 (instanceRef empty_cmp_1))
+              (portRef C0 (instanceRef empty_cmp_1))
+              (portRef D1 (instanceRef empty_cmp_2))
+              (portRef D0 (instanceRef empty_cmp_2))
+              (portRef C1 (instanceRef empty_cmp_2))
+              (portRef C0 (instanceRef empty_cmp_2))
+              (portRef D1 (instanceRef empty_cmp_3))
+              (portRef D0 (instanceRef empty_cmp_3))
+              (portRef C1 (instanceRef empty_cmp_3))
+              (portRef C0 (instanceRef empty_cmp_3))
+              (portRef D1 (instanceRef empty_cmp_4))
+              (portRef D0 (instanceRef empty_cmp_4))
+              (portRef C1 (instanceRef empty_cmp_4))
+              (portRef C0 (instanceRef empty_cmp_4))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef full_cmp_ci_a))
+              (portRef C0 (instanceRef full_cmp_ci_a))
+              (portRef D1 (instanceRef full_cmp_ci_a))
+              (portRef D0 (instanceRef full_cmp_ci_a))
+              (portRef D1 (instanceRef full_cmp_0))
+              (portRef D0 (instanceRef full_cmp_0))
+              (portRef C1 (instanceRef full_cmp_0))
+              (portRef C0 (instanceRef full_cmp_0))
+              (portRef D1 (instanceRef full_cmp_1))
+              (portRef D0 (instanceRef full_cmp_1))
+              (portRef C1 (instanceRef full_cmp_1))
+              (portRef C0 (instanceRef full_cmp_1))
+              (portRef D1 (instanceRef full_cmp_2))
+              (portRef D0 (instanceRef full_cmp_2))
+              (portRef C1 (instanceRef full_cmp_2))
+              (portRef C0 (instanceRef full_cmp_2))
+              (portRef D1 (instanceRef full_cmp_3))
+              (portRef D0 (instanceRef full_cmp_3))
+              (portRef C1 (instanceRef full_cmp_3))
+              (portRef C0 (instanceRef full_cmp_3))
+              (portRef D1 (instanceRef full_cmp_4))
+              (portRef D0 (instanceRef full_cmp_4))
+              (portRef C1 (instanceRef full_cmp_4))
+              (portRef C0 (instanceRef full_cmp_4))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD0 (instanceRef LUT4_21))
+              (portRef AD1 (instanceRef LUT4_21))
+              (portRef AD0 (instanceRef LUT4_20))
+              (portRef AD0 (instanceRef LUT4_16))
+              (portRef AD1 (instanceRef LUT4_16))
+              (portRef AD0 (instanceRef LUT4_15))
+              (portRef AD0 (instanceRef LUT4_11))
+              (portRef AD1 (instanceRef LUT4_11))
+              (portRef AD0 (instanceRef LUT4_10))
+              (portRef AD0 (instanceRef LUT4_6))
+              (portRef AD1 (instanceRef LUT4_6))
+              (portRef AD0 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_3))
+              (portRef AD0 (instanceRef LUT4_2))
+              (portRef AD0 (instanceRef LUT4_1))
+              (portRef AD0 (instanceRef LUT4_0))
+              (portRef CSR2 (instanceRef pdp_ram_0_0_1))
+              (portRef CSW2 (instanceRef pdp_ram_0_0_1))
+              (portRef CSR1 (instanceRef pdp_ram_0_0_1))
+              (portRef CSW1 (instanceRef pdp_ram_0_0_1))
+              (portRef CSR0 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR4 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR3 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR2 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR1 (instanceRef pdp_ram_0_0_1))
+              (portRef ADR0 (instanceRef pdp_ram_0_0_1))
+              (portRef CSR2 (instanceRef pdp_ram_0_1_0))
+              (portRef CSW2 (instanceRef pdp_ram_0_1_0))
+              (portRef CSR1 (instanceRef pdp_ram_0_1_0))
+              (portRef CSW1 (instanceRef pdp_ram_0_1_0))
+              (portRef CSR0 (instanceRef pdp_ram_0_1_0))
+              (portRef ADR4 (instanceRef pdp_ram_0_1_0))
+              (portRef ADR3 (instanceRef pdp_ram_0_1_0))
+              (portRef ADR2 (instanceRef pdp_ram_0_1_0))
+              (portRef ADR1 (instanceRef pdp_ram_0_1_0))
+              (portRef ADR0 (instanceRef pdp_ram_0_1_0))
+              (portRef DI35 (instanceRef pdp_ram_0_1_0))
+              (portRef DI17 (instanceRef pdp_ram_0_1_0))
+              (portRef DI34 (instanceRef pdp_ram_0_1_0))
+              (portRef DI16 (instanceRef pdp_ram_0_1_0))
+              (portRef DI33 (instanceRef pdp_ram_0_1_0))
+              (portRef DI15 (instanceRef pdp_ram_0_1_0))
+              (portRef DI32 (instanceRef pdp_ram_0_1_0))
+              (portRef DI14 (instanceRef pdp_ram_0_1_0))
+              (portRef DI31 (instanceRef pdp_ram_0_1_0))
+              (portRef DI13 (instanceRef pdp_ram_0_1_0))
+              (portRef DI30 (instanceRef pdp_ram_0_1_0))
+              (portRef DI12 (instanceRef pdp_ram_0_1_0))
+              (portRef DI29 (instanceRef pdp_ram_0_1_0))
+              (portRef DI11 (instanceRef pdp_ram_0_1_0))
+              (portRef DI28 (instanceRef pdp_ram_0_1_0))
+              (portRef DI10 (instanceRef pdp_ram_0_1_0))
+              (portRef DI27 (instanceRef pdp_ram_0_1_0))
+              (portRef DI9 (instanceRef pdp_ram_0_1_0))
+              (portRef DI26 (instanceRef pdp_ram_0_1_0))
+              (portRef DI8 (instanceRef pdp_ram_0_1_0))
+              (portRef DI25 (instanceRef pdp_ram_0_1_0))
+              (portRef DI7 (instanceRef pdp_ram_0_1_0))
+              (portRef DI24 (instanceRef pdp_ram_0_1_0))
+              (portRef DI6 (instanceRef pdp_ram_0_1_0))
+              (portRef DI23 (instanceRef pdp_ram_0_1_0))
+              (portRef DI5 (instanceRef pdp_ram_0_1_0))
+              (portRef DI22 (instanceRef pdp_ram_0_1_0))
+              (portRef DI4 (instanceRef pdp_ram_0_1_0))
+              (portRef DI21 (instanceRef pdp_ram_0_1_0))
+              (portRef DI20 (instanceRef pdp_ram_0_1_0))
+              (portRef DI19 (instanceRef pdp_ram_0_1_0))
+              (portRef DI18 (instanceRef pdp_ram_0_1_0))
+              (portRef B0 (instanceRef w_gctr_cia))
+              (portRef A0 (instanceRef w_gctr_cia))
+              (portRef B1 (instanceRef w_gctr_0))
+              (portRef B0 (instanceRef w_gctr_0))
+              (portRef B1 (instanceRef w_gctr_1))
+              (portRef B0 (instanceRef w_gctr_1))
+              (portRef B1 (instanceRef w_gctr_2))
+              (portRef B0 (instanceRef w_gctr_2))
+              (portRef B1 (instanceRef w_gctr_3))
+              (portRef B0 (instanceRef w_gctr_3))
+              (portRef B1 (instanceRef w_gctr_4))
+              (portRef B0 (instanceRef w_gctr_4))
+              (portRef B0 (instanceRef r_gctr_cia))
+              (portRef A0 (instanceRef r_gctr_cia))
+              (portRef B1 (instanceRef r_gctr_0))
+              (portRef B0 (instanceRef r_gctr_0))
+              (portRef B1 (instanceRef r_gctr_1))
+              (portRef B0 (instanceRef r_gctr_1))
+              (portRef B1 (instanceRef r_gctr_2))
+              (portRef B0 (instanceRef r_gctr_2))
+              (portRef B1 (instanceRef r_gctr_3))
+              (portRef B0 (instanceRef r_gctr_3))
+              (portRef B1 (instanceRef r_gctr_4))
+              (portRef B0 (instanceRef r_gctr_4))
+              (portRef B0 (instanceRef empty_cmp_ci_a))
+              (portRef A0 (instanceRef empty_cmp_ci_a))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B0 (instanceRef full_cmp_ci_a))
+              (portRef A0 (instanceRef full_cmp_ci_a))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))))
+          (net full_d_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef full_cmp_4))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_0))
+              (portRef A (instanceRef INV_1))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_1))
+              (portRef A (instanceRef INV_0))))
+          (net dataout39
+            (joined
+              (portRef (member Q 0))
+              (portRef DO21 (instanceRef pdp_ram_0_1_0))))
+          (net dataout38
+            (joined
+              (portRef (member Q 1))
+              (portRef DO20 (instanceRef pdp_ram_0_1_0))))
+          (net dataout37
+            (joined
+              (portRef (member Q 2))
+              (portRef DO19 (instanceRef pdp_ram_0_1_0))))
+          (net dataout36
+            (joined
+              (portRef (member Q 3))
+              (portRef DO18 (instanceRef pdp_ram_0_1_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 4))
+              (portRef DO17 (instanceRef pdp_ram_0_0_1))))
+          (net dataout34
+            (joined
+              (portRef (member Q 5))
+              (portRef DO16 (instanceRef pdp_ram_0_0_1))))
+          (net dataout33
+            (joined
+              (portRef (member Q 6))
+              (portRef DO15 (instanceRef pdp_ram_0_0_1))))
+          (net dataout32
+            (joined
+              (portRef (member Q 7))
+              (portRef DO14 (instanceRef pdp_ram_0_0_1))))
+          (net dataout31
+            (joined
+              (portRef (member Q 8))
+              (portRef DO13 (instanceRef pdp_ram_0_0_1))))
+          (net dataout30
+            (joined
+              (portRef (member Q 9))
+              (portRef DO12 (instanceRef pdp_ram_0_0_1))))
+          (net dataout29
+            (joined
+              (portRef (member Q 10))
+              (portRef DO11 (instanceRef pdp_ram_0_0_1))))
+          (net dataout28
+            (joined
+              (portRef (member Q 11))
+              (portRef DO10 (instanceRef pdp_ram_0_0_1))))
+          (net dataout27
+            (joined
+              (portRef (member Q 12))
+              (portRef DO9 (instanceRef pdp_ram_0_0_1))))
+          (net dataout26
+            (joined
+              (portRef (member Q 13))
+              (portRef DO8 (instanceRef pdp_ram_0_0_1))))
+          (net dataout25
+            (joined
+              (portRef (member Q 14))
+              (portRef DO7 (instanceRef pdp_ram_0_0_1))))
+          (net dataout24
+            (joined
+              (portRef (member Q 15))
+              (portRef DO6 (instanceRef pdp_ram_0_0_1))))
+          (net dataout23
+            (joined
+              (portRef (member Q 16))
+              (portRef DO5 (instanceRef pdp_ram_0_0_1))))
+          (net dataout22
+            (joined
+              (portRef (member Q 17))
+              (portRef DO4 (instanceRef pdp_ram_0_0_1))))
+          (net dataout21
+            (joined
+              (portRef (member Q 18))
+              (portRef DO3 (instanceRef pdp_ram_0_0_1))))
+          (net dataout20
+            (joined
+              (portRef (member Q 19))
+              (portRef DO2 (instanceRef pdp_ram_0_0_1))))
+          (net dataout19
+            (joined
+              (portRef (member Q 20))
+              (portRef DO1 (instanceRef pdp_ram_0_0_1))))
+          (net dataout18
+            (joined
+              (portRef (member Q 21))
+              (portRef DO0 (instanceRef pdp_ram_0_0_1))))
+          (net dataout17
+            (joined
+              (portRef (member Q 22))
+              (portRef DO35 (instanceRef pdp_ram_0_0_1))))
+          (net dataout16
+            (joined
+              (portRef (member Q 23))
+              (portRef DO34 (instanceRef pdp_ram_0_0_1))))
+          (net dataout15
+            (joined
+              (portRef (member Q 24))
+              (portRef DO33 (instanceRef pdp_ram_0_0_1))))
+          (net dataout14
+            (joined
+              (portRef (member Q 25))
+              (portRef DO32 (instanceRef pdp_ram_0_0_1))))
+          (net dataout13
+            (joined
+              (portRef (member Q 26))
+              (portRef DO31 (instanceRef pdp_ram_0_0_1))))
+          (net dataout12
+            (joined
+              (portRef (member Q 27))
+              (portRef DO30 (instanceRef pdp_ram_0_0_1))))
+          (net dataout11
+            (joined
+              (portRef (member Q 28))
+              (portRef DO29 (instanceRef pdp_ram_0_0_1))))
+          (net dataout10
+            (joined
+              (portRef (member Q 29))
+              (portRef DO28 (instanceRef pdp_ram_0_0_1))))
+          (net dataout9
+            (joined
+              (portRef (member Q 30))
+              (portRef DO27 (instanceRef pdp_ram_0_0_1))))
+          (net dataout8
+            (joined
+              (portRef (member Q 31))
+              (portRef DO26 (instanceRef pdp_ram_0_0_1))))
+          (net dataout7
+            (joined
+              (portRef (member Q 32))
+              (portRef DO25 (instanceRef pdp_ram_0_0_1))))
+          (net dataout6
+            (joined
+              (portRef (member Q 33))
+              (portRef DO24 (instanceRef pdp_ram_0_0_1))))
+          (net dataout5
+            (joined
+              (portRef (member Q 34))
+              (portRef DO23 (instanceRef pdp_ram_0_0_1))))
+          (net dataout4
+            (joined
+              (portRef (member Q 35))
+              (portRef DO22 (instanceRef pdp_ram_0_0_1))))
+          (net dataout3
+            (joined
+              (portRef (member Q 36))
+              (portRef DO21 (instanceRef pdp_ram_0_0_1))))
+          (net dataout2
+            (joined
+              (portRef (member Q 37))
+              (portRef DO20 (instanceRef pdp_ram_0_0_1))))
+          (net dataout1
+            (joined
+              (portRef (member Q 38))
+              (portRef DO19 (instanceRef pdp_ram_0_0_1))))
+          (net dataout0
+            (joined
+              (portRef (member Q 39))
+              (portRef DO18 (instanceRef pdp_ram_0_0_1))))
+          (net RPRst
+            (joined
+              (portRef RPReset)
+              (portRef B (instanceRef OR2_t18))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef A (instanceRef OR2_t18))
+              (portRef RST (instanceRef pdp_ram_0_0_1))
+              (portRef RST (instanceRef pdp_ram_0_1_0))
+              (portRef PD (instanceRef FF_101))
+              (portRef CD (instanceRef FF_100))
+              (portRef CD (instanceRef FF_99))
+              (portRef CD (instanceRef FF_98))
+              (portRef CD (instanceRef FF_97))
+              (portRef CD (instanceRef FF_96))
+              (portRef CD (instanceRef FF_95))
+              (portRef CD (instanceRef FF_94))
+              (portRef CD (instanceRef FF_93))
+              (portRef CD (instanceRef FF_92))
+              (portRef CD (instanceRef FF_91))
+              (portRef CD (instanceRef FF_90))
+              (portRef CD (instanceRef FF_89))
+              (portRef CD (instanceRef FF_88))
+              (portRef CD (instanceRef FF_87))
+              (portRef CD (instanceRef FF_86))
+              (portRef CD (instanceRef FF_85))
+              (portRef CD (instanceRef FF_84))
+              (portRef CD (instanceRef FF_83))
+              (portRef CD (instanceRef FF_82))
+              (portRef CD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef CD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t19))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t20))))
+          (net rclk
+            (joined
+              (portRef RdClock)
+              (portRef CLKR (instanceRef pdp_ram_0_0_1))
+              (portRef CLKR (instanceRef pdp_ram_0_1_0))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_1))))
+          (net wclk
+            (joined
+              (portRef WrClock)
+              (portRef CLKW (instanceRef pdp_ram_0_0_1))
+              (portRef CLKW (instanceRef pdp_ram_0_1_0))
+              (portRef CK (instanceRef FF_101))
+              (portRef CK (instanceRef FF_100))
+              (portRef CK (instanceRef FF_99))
+              (portRef CK (instanceRef FF_98))
+              (portRef CK (instanceRef FF_97))
+              (portRef CK (instanceRef FF_96))
+              (portRef CK (instanceRef FF_95))
+              (portRef CK (instanceRef FF_94))
+              (portRef CK (instanceRef FF_93))
+              (portRef CK (instanceRef FF_92))
+              (portRef CK (instanceRef FF_91))
+              (portRef CK (instanceRef FF_90))
+              (portRef CK (instanceRef FF_89))
+              (portRef CK (instanceRef FF_88))
+              (portRef CK (instanceRef FF_87))
+              (portRef CK (instanceRef FF_86))
+              (portRef CK (instanceRef FF_85))
+              (portRef CK (instanceRef FF_84))
+              (portRef CK (instanceRef FF_83))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_0))))
+          (net datain39
+            (joined
+              (portRef (member Data 0))
+              (portRef DI3 (instanceRef pdp_ram_0_1_0))))
+          (net datain38
+            (joined
+              (portRef (member Data 1))
+              (portRef DI2 (instanceRef pdp_ram_0_1_0))))
+          (net datain37
+            (joined
+              (portRef (member Data 2))
+              (portRef DI1 (instanceRef pdp_ram_0_1_0))))
+          (net datain36
+            (joined
+              (portRef (member Data 3))
+              (portRef DI0 (instanceRef pdp_ram_0_1_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 4))
+              (portRef DI35 (instanceRef pdp_ram_0_0_1))))
+          (net datain34
+            (joined
+              (portRef (member Data 5))
+              (portRef DI34 (instanceRef pdp_ram_0_0_1))))
+          (net datain33
+            (joined
+              (portRef (member Data 6))
+              (portRef DI33 (instanceRef pdp_ram_0_0_1))))
+          (net datain32
+            (joined
+              (portRef (member Data 7))
+              (portRef DI32 (instanceRef pdp_ram_0_0_1))))
+          (net datain31
+            (joined
+              (portRef (member Data 8))
+              (portRef DI31 (instanceRef pdp_ram_0_0_1))))
+          (net datain30
+            (joined
+              (portRef (member Data 9))
+              (portRef DI30 (instanceRef pdp_ram_0_0_1))))
+          (net datain29
+            (joined
+              (portRef (member Data 10))
+              (portRef DI29 (instanceRef pdp_ram_0_0_1))))
+          (net datain28
+            (joined
+              (portRef (member Data 11))
+              (portRef DI28 (instanceRef pdp_ram_0_0_1))))
+          (net datain27
+            (joined
+              (portRef (member Data 12))
+              (portRef DI27 (instanceRef pdp_ram_0_0_1))))
+          (net datain26
+            (joined
+              (portRef (member Data 13))
+              (portRef DI26 (instanceRef pdp_ram_0_0_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 14))
+              (portRef DI25 (instanceRef pdp_ram_0_0_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 15))
+              (portRef DI24 (instanceRef pdp_ram_0_0_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 16))
+              (portRef DI23 (instanceRef pdp_ram_0_0_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 17))
+              (portRef DI22 (instanceRef pdp_ram_0_0_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 18))
+              (portRef DI21 (instanceRef pdp_ram_0_0_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 19))
+              (portRef DI20 (instanceRef pdp_ram_0_0_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 20))
+              (portRef DI19 (instanceRef pdp_ram_0_0_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 21))
+              (portRef DI18 (instanceRef pdp_ram_0_0_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 22))
+              (portRef DI17 (instanceRef pdp_ram_0_0_1))))
+          (net datain16
+            (joined
+              (portRef (member Data 23))
+              (portRef DI16 (instanceRef pdp_ram_0_0_1))))
+          (net datain15
+            (joined
+              (portRef (member Data 24))
+              (portRef DI15 (instanceRef pdp_ram_0_0_1))))
+          (net datain14
+            (joined
+              (portRef (member Data 25))
+              (portRef DI14 (instanceRef pdp_ram_0_0_1))))
+          (net datain13
+            (joined
+              (portRef (member Data 26))
+              (portRef DI13 (instanceRef pdp_ram_0_0_1))))
+          (net datain12
+            (joined
+              (portRef (member Data 27))
+              (portRef DI12 (instanceRef pdp_ram_0_0_1))))
+          (net datain11
+            (joined
+              (portRef (member Data 28))
+              (portRef DI11 (instanceRef pdp_ram_0_0_1))))
+          (net datain10
+            (joined
+              (portRef (member Data 29))
+              (portRef DI10 (instanceRef pdp_ram_0_0_1))))
+          (net datain9
+            (joined
+              (portRef (member Data 30))
+              (portRef DI9 (instanceRef pdp_ram_0_0_1))))
+          (net datain8
+            (joined
+              (portRef (member Data 31))
+              (portRef DI8 (instanceRef pdp_ram_0_0_1))))
+          (net datain7
+            (joined
+              (portRef (member Data 32))
+              (portRef DI7 (instanceRef pdp_ram_0_0_1))))
+          (net datain6
+            (joined
+              (portRef (member Data 33))
+              (portRef DI6 (instanceRef pdp_ram_0_0_1))))
+          (net datain5
+            (joined
+              (portRef (member Data 34))
+              (portRef DI5 (instanceRef pdp_ram_0_0_1))))
+          (net datain4
+            (joined
+              (portRef (member Data 35))
+              (portRef DI4 (instanceRef pdp_ram_0_0_1))))
+          (net datain3
+            (joined
+              (portRef (member Data 36))
+              (portRef DI3 (instanceRef pdp_ram_0_0_1))))
+          (net datain2
+            (joined
+              (portRef (member Data 37))
+              (portRef DI2 (instanceRef pdp_ram_0_0_1))))
+          (net datain1
+            (joined
+              (portRef (member Data 38))
+              (portRef DI1 (instanceRef pdp_ram_0_0_1))))
+          (net datain0
+            (joined
+              (portRef (member Data 39))
+              (portRef DI0 (instanceRef pdp_ram_0_0_1))))))))
+  (design fifo40_dc
+    (cellRef fifo40_dc
+      (libraryRef ORCLIB)))
+)
diff --git a/fifo40_dc/fifo40_dc.fdc b/fifo40_dc/fifo40_dc.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/fifo40_dc/fifo40_dc.lpc b/fifo40_dc/fifo40_dc.lpc
new file mode 100644
index 0000000..9deb02c
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.lpc
@@ -0,0 +1,53 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=fifo40_dc
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=02/09/2021
+Time=13:19:24
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=40
+RDepth=512
+RWidth=40
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1
diff --git a/fifo40_dc/fifo40_dc.sbx b/fifo40_dc/fifo40_dc.sbx
new file mode 100644
index 0000000..ec1e426
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.sbx
@@ -0,0 +1,264 @@
+<!DOCTYPE fifo40_dc>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>FIFO_DC</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./fifo40_dc.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./fifo40_dc.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2021-02-09.01:19:26 PM</lattice:date>
+            <lattice:modified>2021-02-09.01:19:26 PM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">02/09/2021</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">fifo40_dc</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">13:19:24</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ClockEn</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Depth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">512</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EmpFlg</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EnECC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FIFOImp</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FullFlg</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeAssert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeDeassert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PeMode</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfAssert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfDeassert</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PfMode</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RDataCount</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RDepth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">512</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>RWidth</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">40</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Reset</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Reset1</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>WDataCount</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Width</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">40</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>regout</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>fifo40_dc</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/fifo40_dc/fifo40_dc.srp b/fifo40_dc/fifo40_dc.srp
new file mode 100644
index 0000000..15f9727
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.srp
@@ -0,0 +1,40 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Tue Feb  9 13:19:26 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc 
+    Circuit name     : fifo40_dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+	Inputs       : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+	Outputs      : Q[39:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo40_dc.edn
+    Verilog output   : fifo40_dc.v
+    Verilog template : fifo40_dc_tmpl.v
+    Verilog testbench: tb_fifo40_dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo40_dc.srp
+    Element Usage    :
+          CCU2C : 26
+           AND2 : 2
+        FD1P3BX : 2
+        FD1P3DX : 58
+        FD1S3BX : 1
+        FD1S3DX : 41
+            INV : 2
+            OR2 : 1
+       ROM16X1A : 24
+           XOR2 : 18
+       PDPW16KD : 2
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 2
+            Reg : 102
diff --git a/fifo40_dc/fifo40_dc.v b/fifo40_dc/fifo40_dc.v
new file mode 100644
index 0000000..77ff46f
--- /dev/null
+++ b/fifo40_dc/fifo40_dc.v
@@ -0,0 +1,1114 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.8 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc  */
+/* Tue Feb  9 13:19:26 2021 */
+
+
+`timescale 1 ns / 1 ps
+module fifo40_dc (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
+    Empty, Full)/* synthesis NGD_DRC_MASK=1 */;
+    input wire [39:0] Data;
+    input wire WrClock;
+    input wire RdClock;
+    input wire WrEn;
+    input wire RdEn;
+    input wire Reset;
+    input wire RPReset;
+    output wire [39:0] Q;
+    output wire Empty;
+    output wire Full;
+
+    wire invout_1;
+    wire invout_0;
+    wire w_g2b_xor_cluster_1;
+    wire r_g2b_xor_cluster_1;
+    wire w_gdata_0;
+    wire w_gdata_1;
+    wire w_gdata_2;
+    wire w_gdata_3;
+    wire w_gdata_4;
+    wire w_gdata_5;
+    wire w_gdata_6;
+    wire w_gdata_7;
+    wire w_gdata_8;
+    wire wptr_0;
+    wire wptr_1;
+    wire wptr_2;
+    wire wptr_3;
+    wire wptr_4;
+    wire wptr_5;
+    wire wptr_6;
+    wire wptr_7;
+    wire wptr_8;
+    wire wptr_9;
+    wire r_gdata_0;
+    wire r_gdata_1;
+    wire r_gdata_2;
+    wire r_gdata_3;
+    wire r_gdata_4;
+    wire r_gdata_5;
+    wire r_gdata_6;
+    wire r_gdata_7;
+    wire r_gdata_8;
+    wire rptr_0;
+    wire rptr_1;
+    wire rptr_2;
+    wire rptr_3;
+    wire rptr_4;
+    wire rptr_5;
+    wire rptr_6;
+    wire rptr_7;
+    wire rptr_8;
+    wire rptr_9;
+    wire w_gcount_0;
+    wire w_gcount_1;
+    wire w_gcount_2;
+    wire w_gcount_3;
+    wire w_gcount_4;
+    wire w_gcount_5;
+    wire w_gcount_6;
+    wire w_gcount_7;
+    wire w_gcount_8;
+    wire w_gcount_9;
+    wire r_gcount_0;
+    wire r_gcount_1;
+    wire r_gcount_2;
+    wire r_gcount_3;
+    wire r_gcount_4;
+    wire r_gcount_5;
+    wire r_gcount_6;
+    wire r_gcount_7;
+    wire r_gcount_8;
+    wire r_gcount_9;
+    wire w_gcount_r20;
+    wire w_gcount_r0;
+    wire w_gcount_r21;
+    wire w_gcount_r1;
+    wire w_gcount_r22;
+    wire w_gcount_r2;
+    wire w_gcount_r23;
+    wire w_gcount_r3;
+    wire w_gcount_r24;
+    wire w_gcount_r4;
+    wire w_gcount_r25;
+    wire w_gcount_r5;
+    wire w_gcount_r26;
+    wire w_gcount_r6;
+    wire w_gcount_r27;
+    wire w_gcount_r7;
+    wire w_gcount_r28;
+    wire w_gcount_r8;
+    wire w_gcount_r29;
+    wire w_gcount_r9;
+    wire r_gcount_w20;
+    wire r_gcount_w0;
+    wire r_gcount_w21;
+    wire r_gcount_w1;
+    wire r_gcount_w22;
+    wire r_gcount_w2;
+    wire r_gcount_w23;
+    wire r_gcount_w3;
+    wire r_gcount_w24;
+    wire r_gcount_w4;
+    wire r_gcount_w25;
+    wire r_gcount_w5;
+    wire r_gcount_w26;
+    wire r_gcount_w6;
+    wire r_gcount_w27;
+    wire r_gcount_w7;
+    wire r_gcount_w28;
+    wire r_gcount_w8;
+    wire r_gcount_w29;
+    wire r_gcount_w9;
+    wire empty_i;
+    wire rRst;
+    wire full_i;
+    wire iwcount_0;
+    wire iwcount_1;
+    wire w_gctr_ci;
+    wire iwcount_2;
+    wire iwcount_3;
+    wire co0;
+    wire iwcount_4;
+    wire iwcount_5;
+    wire co1;
+    wire iwcount_6;
+    wire iwcount_7;
+    wire co2;
+    wire iwcount_8;
+    wire iwcount_9;
+    wire co4;
+    wire co3;
+    wire wcount_9;
+    wire ircount_0;
+    wire ircount_1;
+    wire r_gctr_ci;
+    wire ircount_2;
+    wire ircount_3;
+    wire co0_1;
+    wire ircount_4;
+    wire ircount_5;
+    wire co1_1;
+    wire ircount_6;
+    wire ircount_7;
+    wire co2_1;
+    wire ircount_8;
+    wire ircount_9;
+    wire co4_1;
+    wire co3_1;
+    wire rcount_9;
+    wire rden_i;
+    wire cmp_ci;
+    wire wcount_r0;
+    wire wcount_r1;
+    wire rcount_0;
+    wire rcount_1;
+    wire co0_2;
+    wire wcount_r2;
+    wire wcount_r3;
+    wire rcount_2;
+    wire rcount_3;
+    wire co1_2;
+    wire wcount_r4;
+    wire wcount_r5;
+    wire rcount_4;
+    wire rcount_5;
+    wire co2_2;
+    wire w_g2b_xor_cluster_0;
+    wire wcount_r7;
+    wire rcount_6;
+    wire rcount_7;
+    wire co3_2;
+    wire wcount_r8;
+    wire empty_cmp_clr;
+    wire rcount_8;
+    wire empty_cmp_set;
+    wire empty_d;
+    wire empty_d_c;
+    wire wren_i;
+    wire cmp_ci_1;
+    wire rcount_w0;
+    wire rcount_w1;
+    wire wcount_0;
+    wire wcount_1;
+    wire co0_3;
+    wire rcount_w2;
+    wire rcount_w3;
+    wire wcount_2;
+    wire wcount_3;
+    wire co1_3;
+    wire rcount_w4;
+    wire rcount_w5;
+    wire wcount_4;
+    wire wcount_5;
+    wire co2_3;
+    wire r_g2b_xor_cluster_0;
+    wire rcount_w7;
+    wire wcount_6;
+    wire wcount_7;
+    wire co3_3;
+    wire rcount_w8;
+    wire full_cmp_clr;
+    wire wcount_8;
+    wire full_cmp_set;
+    wire full_d;
+    wire scuba_vhi;
+    wire scuba_vlo;
+    wire full_d_c;
+
+    AND2 AND2_t20 (.A(WrEn), .B(invout_1), .Z(wren_i));
+
+    INV INV_1 (.A(full_i), .Z(invout_1));
+
+    AND2 AND2_t19 (.A(RdEn), .B(invout_0), .Z(rden_i));
+
+    INV INV_0 (.A(empty_i), .Z(invout_0));
+
+    OR2 OR2_t18 (.A(Reset), .B(RPReset), .Z(rRst));
+
+    XOR2 XOR2_t17 (.A(wcount_0), .B(wcount_1), .Z(w_gdata_0));
+
+    XOR2 XOR2_t16 (.A(wcount_1), .B(wcount_2), .Z(w_gdata_1));
+
+    XOR2 XOR2_t15 (.A(wcount_2), .B(wcount_3), .Z(w_gdata_2));
+
+    XOR2 XOR2_t14 (.A(wcount_3), .B(wcount_4), .Z(w_gdata_3));
+
+    XOR2 XOR2_t13 (.A(wcount_4), .B(wcount_5), .Z(w_gdata_4));
+
+    XOR2 XOR2_t12 (.A(wcount_5), .B(wcount_6), .Z(w_gdata_5));
+
+    XOR2 XOR2_t11 (.A(wcount_6), .B(wcount_7), .Z(w_gdata_6));
+
+    XOR2 XOR2_t10 (.A(wcount_7), .B(wcount_8), .Z(w_gdata_7));
+
+    XOR2 XOR2_t9 (.A(wcount_8), .B(wcount_9), .Z(w_gdata_8));
+
+    XOR2 XOR2_t8 (.A(rcount_0), .B(rcount_1), .Z(r_gdata_0));
+
+    XOR2 XOR2_t7 (.A(rcount_1), .B(rcount_2), .Z(r_gdata_1));
+
+    XOR2 XOR2_t6 (.A(rcount_2), .B(rcount_3), .Z(r_gdata_2));
+
+    XOR2 XOR2_t5 (.A(rcount_3), .B(rcount_4), .Z(r_gdata_3));
+
+    XOR2 XOR2_t4 (.A(rcount_4), .B(rcount_5), .Z(r_gdata_4));
+
+    XOR2 XOR2_t3 (.A(rcount_5), .B(rcount_6), .Z(r_gdata_5));
+
+    XOR2 XOR2_t2 (.A(rcount_6), .B(rcount_7), .Z(r_gdata_6));
+
+    XOR2 XOR2_t1 (.A(rcount_7), .B(rcount_8), .Z(r_gdata_7));
+
+    XOR2 XOR2_t0 (.A(rcount_8), .B(rcount_9), .Z(r_gdata_8));
+
+    defparam LUT4_23.initval =  16'h6996 ;
+    ROM16X1A LUT4_23 (.AD3(w_gcount_r26), .AD2(w_gcount_r27), .AD1(w_gcount_r28), 
+        .AD0(w_gcount_r29), .DO0(w_g2b_xor_cluster_0));
+
+    defparam LUT4_22.initval =  16'h6996 ;
+    ROM16X1A LUT4_22 (.AD3(w_gcount_r22), .AD2(w_gcount_r23), .AD1(w_gcount_r24), 
+        .AD0(w_gcount_r25), .DO0(w_g2b_xor_cluster_1));
+
+    defparam LUT4_21.initval =  16'h6996 ;
+    ROM16X1A LUT4_21 (.AD3(w_gcount_r28), .AD2(w_gcount_r29), .AD1(scuba_vlo), 
+        .AD0(scuba_vlo), .DO0(wcount_r8));
+
+    defparam LUT4_20.initval =  16'h6996 ;
+    ROM16X1A LUT4_20 (.AD3(w_gcount_r27), .AD2(w_gcount_r28), .AD1(w_gcount_r29), 
+        .AD0(scuba_vlo), .DO0(wcount_r7));
+
+    defparam LUT4_19.initval =  16'h6996 ;
+    ROM16X1A LUT4_19 (.AD3(w_gcount_r25), .AD2(w_gcount_r26), .AD1(w_gcount_r27), 
+        .AD0(wcount_r8), .DO0(wcount_r5));
+
+    defparam LUT4_18.initval =  16'h6996 ;
+    ROM16X1A LUT4_18 (.AD3(w_gcount_r24), .AD2(w_gcount_r25), .AD1(w_gcount_r26), 
+        .AD0(wcount_r7), .DO0(wcount_r4));
+
+    defparam LUT4_17.initval =  16'h6996 ;
+    ROM16X1A LUT4_17 (.AD3(w_gcount_r23), .AD2(w_gcount_r24), .AD1(w_gcount_r25), 
+        .AD0(w_g2b_xor_cluster_0), .DO0(wcount_r3));
+
+    defparam LUT4_16.initval =  16'h6996 ;
+    ROM16X1A LUT4_16 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(wcount_r2));
+
+    defparam LUT4_15.initval =  16'h6996 ;
+    ROM16X1A LUT4_15 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(w_gcount_r21), .AD0(scuba_vlo), .DO0(wcount_r1));
+
+    defparam LUT4_14.initval =  16'h6996 ;
+    ROM16X1A LUT4_14 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), 
+        .AD1(w_gcount_r20), .AD0(w_gcount_r21), .DO0(wcount_r0));
+
+    defparam LUT4_13.initval =  16'h6996 ;
+    ROM16X1A LUT4_13 (.AD3(r_gcount_w26), .AD2(r_gcount_w27), .AD1(r_gcount_w28), 
+        .AD0(r_gcount_w29), .DO0(r_g2b_xor_cluster_0));
+
+    defparam LUT4_12.initval =  16'h6996 ;
+    ROM16X1A LUT4_12 (.AD3(r_gcount_w22), .AD2(r_gcount_w23), .AD1(r_gcount_w24), 
+        .AD0(r_gcount_w25), .DO0(r_g2b_xor_cluster_1));
+
+    defparam LUT4_11.initval =  16'h6996 ;
+    ROM16X1A LUT4_11 (.AD3(r_gcount_w28), .AD2(r_gcount_w29), .AD1(scuba_vlo), 
+        .AD0(scuba_vlo), .DO0(rcount_w8));
+
+    defparam LUT4_10.initval =  16'h6996 ;
+    ROM16X1A LUT4_10 (.AD3(r_gcount_w27), .AD2(r_gcount_w28), .AD1(r_gcount_w29), 
+        .AD0(scuba_vlo), .DO0(rcount_w7));
+
+    defparam LUT4_9.initval =  16'h6996 ;
+    ROM16X1A LUT4_9 (.AD3(r_gcount_w25), .AD2(r_gcount_w26), .AD1(r_gcount_w27), 
+        .AD0(rcount_w8), .DO0(rcount_w5));
+
+    defparam LUT4_8.initval =  16'h6996 ;
+    ROM16X1A LUT4_8 (.AD3(r_gcount_w24), .AD2(r_gcount_w25), .AD1(r_gcount_w26), 
+        .AD0(rcount_w7), .DO0(rcount_w4));
+
+    defparam LUT4_7.initval =  16'h6996 ;
+    ROM16X1A LUT4_7 (.AD3(r_gcount_w23), .AD2(r_gcount_w24), .AD1(r_gcount_w25), 
+        .AD0(r_g2b_xor_cluster_0), .DO0(rcount_w3));
+
+    defparam LUT4_6.initval =  16'h6996 ;
+    ROM16X1A LUT4_6 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(rcount_w2));
+
+    defparam LUT4_5.initval =  16'h6996 ;
+    ROM16X1A LUT4_5 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(r_gcount_w21), .AD0(scuba_vlo), .DO0(rcount_w1));
+
+    defparam LUT4_4.initval =  16'h6996 ;
+    ROM16X1A LUT4_4 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), 
+        .AD1(r_gcount_w20), .AD0(r_gcount_w21), .DO0(rcount_w0));
+
+    defparam LUT4_3.initval =  16'h0410 ;
+    ROM16X1A LUT4_3 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), 
+        .DO0(empty_cmp_set));
+
+    defparam LUT4_2.initval =  16'h1004 ;
+    ROM16X1A LUT4_2 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), 
+        .DO0(empty_cmp_clr));
+
+    defparam LUT4_1.initval =  16'h0140 ;
+    ROM16X1A LUT4_1 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), 
+        .DO0(full_cmp_set));
+
+    defparam LUT4_0.initval =  16'h4001 ;
+    ROM16X1A LUT4_0 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), 
+        .DO0(full_cmp_clr));
+
+    defparam pdp_ram_0_0_1.INIT_DATA = "STATIC" ;
+    defparam pdp_ram_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
+    defparam pdp_ram_0_0_1.CSDECODE_R = "0b000" ;
+    defparam pdp_ram_0_0_1.CSDECODE_W = "0b001" ;
+    defparam pdp_ram_0_0_1.GSR = "ENABLED" ;
+    defparam pdp_ram_0_0_1.RESETMODE = "ASYNC" ;
+    defparam pdp_ram_0_0_1.REGMODE = "NOREG" ;
+    defparam pdp_ram_0_0_1.DATA_WIDTH_R = 36 ;
+    defparam pdp_ram_0_0_1.DATA_WIDTH_W = 36 ;
+    PDPW16KD pdp_ram_0_0_1 (.DI35(Data[35]), .DI34(Data[34]), .DI33(Data[33]), 
+        .DI32(Data[32]), .DI31(Data[31]), .DI30(Data[30]), .DI29(Data[29]), 
+        .DI28(Data[28]), .DI27(Data[27]), .DI26(Data[26]), .DI25(Data[25]), 
+        .DI24(Data[24]), .DI23(Data[23]), .DI22(Data[22]), .DI21(Data[21]), 
+        .DI20(Data[20]), .DI19(Data[19]), .DI18(Data[18]), .DI17(Data[17]), 
+        .DI16(Data[16]), .DI15(Data[15]), .DI14(Data[14]), .DI13(Data[13]), 
+        .DI12(Data[12]), .DI11(Data[11]), .DI10(Data[10]), .DI9(Data[9]), 
+        .DI8(Data[8]), .DI7(Data[7]), .DI6(Data[6]), .DI5(Data[5]), .DI4(Data[4]), 
+        .DI3(Data[3]), .DI2(Data[2]), .DI1(Data[1]), .DI0(Data[0]), .ADW8(wptr_8), 
+        .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), .ADW4(wptr_4), .ADW3(wptr_3), 
+        .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), .BE3(scuba_vhi), .BE2(scuba_vhi), 
+        .BE1(scuba_vhi), .BE0(scuba_vhi), .CEW(wren_i), .CLKW(WrClock), 
+        .CSW2(scuba_vlo), .CSW1(scuba_vlo), .CSW0(scuba_vhi), .ADR13(rptr_8), 
+        .ADR12(rptr_7), .ADR11(rptr_6), .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), 
+        .ADR7(rptr_2), .ADR6(rptr_1), .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), 
+        .ADR2(scuba_vlo), .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), 
+        .OCER(rden_i), .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), 
+        .CSR0(scuba_vlo), .RST(Reset), .DO35(Q[17]), .DO34(Q[16]), .DO33(Q[15]), 
+        .DO32(Q[14]), .DO31(Q[13]), .DO30(Q[12]), .DO29(Q[11]), .DO28(Q[10]), 
+        .DO27(Q[9]), .DO26(Q[8]), .DO25(Q[7]), .DO24(Q[6]), .DO23(Q[5]), 
+        .DO22(Q[4]), .DO21(Q[3]), .DO20(Q[2]), .DO19(Q[1]), .DO18(Q[0]), 
+        .DO17(Q[35]), .DO16(Q[34]), .DO15(Q[33]), .DO14(Q[32]), .DO13(Q[31]), 
+        .DO12(Q[30]), .DO11(Q[29]), .DO10(Q[28]), .DO9(Q[27]), .DO8(Q[26]), 
+        .DO7(Q[25]), .DO6(Q[24]), .DO5(Q[23]), .DO4(Q[22]), .DO3(Q[21]), 
+        .DO2(Q[20]), .DO1(Q[19]), .DO0(Q[18]))
+             /* synthesis MEM_LPC_FILE="fifo40_dc.lpc" */
+             /* synthesis MEM_INIT_FILE="" */;
+
+    defparam pdp_ram_0_1_0.INIT_DATA = "STATIC" ;
+    defparam pdp_ram_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
+    defparam pdp_ram_0_1_0.CSDECODE_R = "0b000" ;
+    defparam pdp_ram_0_1_0.CSDECODE_W = "0b001" ;
+    defparam pdp_ram_0_1_0.GSR = "ENABLED" ;
+    defparam pdp_ram_0_1_0.RESETMODE = "ASYNC" ;
+    defparam pdp_ram_0_1_0.REGMODE = "NOREG" ;
+    defparam pdp_ram_0_1_0.DATA_WIDTH_R = 36 ;
+    defparam pdp_ram_0_1_0.DATA_WIDTH_W = 36 ;
+    PDPW16KD pdp_ram_0_1_0 (.DI35(scuba_vlo), .DI34(scuba_vlo), .DI33(scuba_vlo), 
+        .DI32(scuba_vlo), .DI31(scuba_vlo), .DI30(scuba_vlo), .DI29(scuba_vlo), 
+        .DI28(scuba_vlo), .DI27(scuba_vlo), .DI26(scuba_vlo), .DI25(scuba_vlo), 
+        .DI24(scuba_vlo), .DI23(scuba_vlo), .DI22(scuba_vlo), .DI21(scuba_vlo), 
+        .DI20(scuba_vlo), .DI19(scuba_vlo), .DI18(scuba_vlo), .DI17(scuba_vlo), 
+        .DI16(scuba_vlo), .DI15(scuba_vlo), .DI14(scuba_vlo), .DI13(scuba_vlo), 
+        .DI12(scuba_vlo), .DI11(scuba_vlo), .DI10(scuba_vlo), .DI9(scuba_vlo), 
+        .DI8(scuba_vlo), .DI7(scuba_vlo), .DI6(scuba_vlo), .DI5(scuba_vlo), 
+        .DI4(scuba_vlo), .DI3(Data[39]), .DI2(Data[38]), .DI1(Data[37]), 
+        .DI0(Data[36]), .ADW8(wptr_8), .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), 
+        .ADW4(wptr_4), .ADW3(wptr_3), .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), 
+        .BE3(scuba_vhi), .BE2(scuba_vhi), .BE1(scuba_vhi), .BE0(scuba_vhi), 
+        .CEW(wren_i), .CLKW(WrClock), .CSW2(scuba_vlo), .CSW1(scuba_vlo), 
+        .CSW0(scuba_vhi), .ADR13(rptr_8), .ADR12(rptr_7), .ADR11(rptr_6), 
+        .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), .ADR7(rptr_2), .ADR6(rptr_1), 
+        .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), .ADR2(scuba_vlo), 
+        .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), .OCER(rden_i), 
+        .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), .CSR0(scuba_vlo), 
+        .RST(Reset), .DO35(), .DO34(), .DO33(), .DO32(), .DO31(), .DO30(), 
+        .DO29(), .DO28(), .DO27(), .DO26(), .DO25(), .DO24(), .DO23(), .DO22(), 
+        .DO21(Q[39]), .DO20(Q[38]), .DO19(Q[37]), .DO18(Q[36]), .DO17(), 
+        .DO16(), .DO15(), .DO14(), .DO13(), .DO12(), .DO11(), .DO10(), .DO9(), 
+        .DO8(), .DO7(), .DO6(), .DO5(), .DO4(), .DO3(), .DO2(), .DO1(), 
+        .DO0())
+             /* synthesis MEM_LPC_FILE="fifo40_dc.lpc" */
+             /* synthesis MEM_INIT_FILE="" */;
+
+    FD1P3BX FF_101 (.D(iwcount_0), .SP(wren_i), .CK(WrClock), .PD(Reset), 
+        .Q(wcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_100 (.D(iwcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_99 (.D(iwcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_98 (.D(iwcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_97 (.D(iwcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_96 (.D(iwcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_95 (.D(iwcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_94 (.D(iwcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_93 (.D(iwcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_92 (.D(iwcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_91 (.D(w_gdata_0), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_90 (.D(w_gdata_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_89 (.D(w_gdata_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_88 (.D(w_gdata_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_87 (.D(w_gdata_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_86 (.D(w_gdata_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_85 (.D(w_gdata_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_84 (.D(w_gdata_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_83 (.D(w_gdata_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_82 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(w_gcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_81 (.D(wcount_0), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_80 (.D(wcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_79 (.D(wcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_78 (.D(wcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_77 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_76 (.D(wcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_75 (.D(wcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_74 (.D(wcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_73 (.D(wcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_72 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), 
+        .Q(wptr_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3BX FF_71 (.D(ircount_0), .SP(rden_i), .CK(RdClock), .PD(rRst), 
+        .Q(rcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_70 (.D(ircount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_69 (.D(ircount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_68 (.D(ircount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_67 (.D(ircount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_66 (.D(ircount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_65 (.D(ircount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_64 (.D(ircount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_63 (.D(ircount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_62 (.D(ircount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(rcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_61 (.D(r_gdata_0), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_60 (.D(r_gdata_1), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_59 (.D(r_gdata_2), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_58 (.D(r_gdata_3), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_57 (.D(r_gdata_4), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_56 (.D(r_gdata_5), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_55 (.D(r_gdata_6), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_54 (.D(r_gdata_7), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_53 (.D(r_gdata_8), .SP(rden_i), .CK(RdClock), .CD(rRst), 
+        .Q(r_gcount_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_52 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(r_gcount_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_51 (.D(rcount_0), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_50 (.D(rcount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_49 (.D(rcount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_48 (.D(rcount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_47 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_46 (.D(rcount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_45 (.D(rcount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_44 (.D(rcount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_43 (.D(rcount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1P3DX FF_42 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_41 (.D(w_gcount_0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_40 (.D(w_gcount_1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_39 (.D(w_gcount_2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_38 (.D(w_gcount_3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_37 (.D(w_gcount_4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_36 (.D(w_gcount_5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_35 (.D(w_gcount_6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_34 (.D(w_gcount_7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_33 (.D(w_gcount_8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_32 (.D(w_gcount_9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_31 (.D(r_gcount_0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w0))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_30 (.D(r_gcount_1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w1))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_29 (.D(r_gcount_2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w2))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_28 (.D(r_gcount_3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w3))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_27 (.D(r_gcount_4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w4))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_26 (.D(r_gcount_5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w5))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_25 (.D(r_gcount_6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w6))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_24 (.D(r_gcount_7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w7))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_23 (.D(r_gcount_8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w8))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_22 (.D(r_gcount_9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w9))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_21 (.D(w_gcount_r0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r20))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_20 (.D(w_gcount_r1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r21))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_19 (.D(w_gcount_r2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r22))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_18 (.D(w_gcount_r3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r23))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_17 (.D(w_gcount_r4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r24))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_16 (.D(w_gcount_r5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r25))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_15 (.D(w_gcount_r6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r26))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_14 (.D(w_gcount_r7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r27))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_13 (.D(w_gcount_r8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r28))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_12 (.D(w_gcount_r9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r29))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_11 (.D(r_gcount_w0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w20))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_10 (.D(r_gcount_w1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w21))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_9 (.D(r_gcount_w2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w22))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_8 (.D(r_gcount_w3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w23))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_7 (.D(r_gcount_w4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w24))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_6 (.D(r_gcount_w5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w25))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_5 (.D(r_gcount_w6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w26))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_4 (.D(r_gcount_w7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w27))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_3 (.D(r_gcount_w8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w28))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_2 (.D(r_gcount_w9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w29))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3BX FF_1 (.D(empty_d), .CK(RdClock), .PD(rRst), .Q(empty_i))
+             /* synthesis GSR="ENABLED" */;
+
+    FD1S3DX FF_0 (.D(full_d), .CK(WrClock), .CD(Reset), .Q(full_i))
+             /* synthesis GSR="ENABLED" */;
+
+    defparam w_gctr_cia.INJECT1_1 = "NO" ;
+    defparam w_gctr_cia.INJECT1_0 = "NO" ;
+    defparam w_gctr_cia.INIT1 =  16'h66AA ;
+    defparam w_gctr_cia.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(w_gctr_ci));
+
+    defparam w_gctr_0.INJECT1_1 = "NO" ;
+    defparam w_gctr_0.INJECT1_0 = "NO" ;
+    defparam w_gctr_0.INIT1 =  16'h66AA ;
+    defparam w_gctr_0.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_0 (.A0(wcount_0), .A1(wcount_1), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(w_gctr_ci), .S0(iwcount_0), .S1(iwcount_1), .COUT(co0));
+
+    defparam w_gctr_1.INJECT1_1 = "NO" ;
+    defparam w_gctr_1.INJECT1_0 = "NO" ;
+    defparam w_gctr_1.INIT1 =  16'h66AA ;
+    defparam w_gctr_1.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_1 (.A0(wcount_2), .A1(wcount_3), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0), .S0(iwcount_2), .S1(iwcount_3), .COUT(co1));
+
+    defparam w_gctr_2.INJECT1_1 = "NO" ;
+    defparam w_gctr_2.INJECT1_0 = "NO" ;
+    defparam w_gctr_2.INIT1 =  16'h66AA ;
+    defparam w_gctr_2.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_2 (.A0(wcount_4), .A1(wcount_5), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1), .S0(iwcount_4), .S1(iwcount_5), .COUT(co2));
+
+    defparam w_gctr_3.INJECT1_1 = "NO" ;
+    defparam w_gctr_3.INJECT1_0 = "NO" ;
+    defparam w_gctr_3.INIT1 =  16'h66AA ;
+    defparam w_gctr_3.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_3 (.A0(wcount_6), .A1(wcount_7), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co2), .S0(iwcount_6), .S1(iwcount_7), .COUT(co3));
+
+    defparam w_gctr_4.INJECT1_1 = "NO" ;
+    defparam w_gctr_4.INJECT1_0 = "NO" ;
+    defparam w_gctr_4.INIT1 =  16'h66AA ;
+    defparam w_gctr_4.INIT0 =  16'h66AA ;
+    CCU2C w_gctr_4 (.A0(wcount_8), .A1(wcount_9), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co3), .S0(iwcount_8), .S1(iwcount_9), .COUT(co4));
+
+    defparam r_gctr_cia.INJECT1_1 = "NO" ;
+    defparam r_gctr_cia.INJECT1_0 = "NO" ;
+    defparam r_gctr_cia.INIT1 =  16'h66AA ;
+    defparam r_gctr_cia.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(r_gctr_ci));
+
+    defparam r_gctr_0.INJECT1_1 = "NO" ;
+    defparam r_gctr_0.INJECT1_0 = "NO" ;
+    defparam r_gctr_0.INIT1 =  16'h66AA ;
+    defparam r_gctr_0.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_0 (.A0(rcount_0), .A1(rcount_1), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(r_gctr_ci), .S0(ircount_0), .S1(ircount_1), .COUT(co0_1));
+
+    defparam r_gctr_1.INJECT1_1 = "NO" ;
+    defparam r_gctr_1.INJECT1_0 = "NO" ;
+    defparam r_gctr_1.INIT1 =  16'h66AA ;
+    defparam r_gctr_1.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_1 (.A0(rcount_2), .A1(rcount_3), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_1), .S0(ircount_2), .S1(ircount_3), .COUT(co1_1));
+
+    defparam r_gctr_2.INJECT1_1 = "NO" ;
+    defparam r_gctr_2.INJECT1_0 = "NO" ;
+    defparam r_gctr_2.INIT1 =  16'h66AA ;
+    defparam r_gctr_2.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_2 (.A0(rcount_4), .A1(rcount_5), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_1), .S0(ircount_4), .S1(ircount_5), .COUT(co2_1));
+
+    defparam r_gctr_3.INJECT1_1 = "NO" ;
+    defparam r_gctr_3.INJECT1_0 = "NO" ;
+    defparam r_gctr_3.INIT1 =  16'h66AA ;
+    defparam r_gctr_3.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_3 (.A0(rcount_6), .A1(rcount_7), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co2_1), .S0(ircount_6), .S1(ircount_7), .COUT(co3_1));
+
+    defparam r_gctr_4.INJECT1_1 = "NO" ;
+    defparam r_gctr_4.INJECT1_0 = "NO" ;
+    defparam r_gctr_4.INIT1 =  16'h66AA ;
+    defparam r_gctr_4.INIT0 =  16'h66AA ;
+    CCU2C r_gctr_4 (.A0(rcount_8), .A1(rcount_9), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co3_1), .S0(ircount_8), .S1(ircount_9), .COUT(co4_1));
+
+    defparam empty_cmp_ci_a.INJECT1_1 = "NO" ;
+    defparam empty_cmp_ci_a.INJECT1_0 = "NO" ;
+    defparam empty_cmp_ci_a.INIT1 =  16'h66AA ;
+    defparam empty_cmp_ci_a.INIT0 =  16'h66AA ;
+    CCU2C empty_cmp_ci_a (.A0(scuba_vlo), .A1(rden_i), .B0(scuba_vlo), .B1(rden_i), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(cmp_ci));
+
+    defparam empty_cmp_0.INJECT1_1 = "NO" ;
+    defparam empty_cmp_0.INJECT1_0 = "NO" ;
+    defparam empty_cmp_0.INIT1 =  16'h99AA ;
+    defparam empty_cmp_0.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_0 (.A0(rcount_0), .A1(rcount_1), .B0(wcount_r0), .B1(wcount_r1), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(cmp_ci), .S0(), .S1(), .COUT(co0_2));
+
+    defparam empty_cmp_1.INJECT1_1 = "NO" ;
+    defparam empty_cmp_1.INJECT1_0 = "NO" ;
+    defparam empty_cmp_1.INIT1 =  16'h99AA ;
+    defparam empty_cmp_1.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_1 (.A0(rcount_2), .A1(rcount_3), .B0(wcount_r2), .B1(wcount_r3), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_2), .S0(), .S1(), .COUT(co1_2));
+
+    defparam empty_cmp_2.INJECT1_1 = "NO" ;
+    defparam empty_cmp_2.INJECT1_0 = "NO" ;
+    defparam empty_cmp_2.INIT1 =  16'h99AA ;
+    defparam empty_cmp_2.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_2 (.A0(rcount_4), .A1(rcount_5), .B0(wcount_r4), .B1(wcount_r5), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_2), .S0(), .S1(), .COUT(co2_2));
+
+    defparam empty_cmp_3.INJECT1_1 = "NO" ;
+    defparam empty_cmp_3.INJECT1_0 = "NO" ;
+    defparam empty_cmp_3.INIT1 =  16'h99AA ;
+    defparam empty_cmp_3.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_3 (.A0(rcount_6), .A1(rcount_7), .B0(w_g2b_xor_cluster_0), 
+        .B1(wcount_r7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co2_2), .S0(), .S1(), .COUT(co3_2));
+
+    defparam empty_cmp_4.INJECT1_1 = "NO" ;
+    defparam empty_cmp_4.INJECT1_0 = "NO" ;
+    defparam empty_cmp_4.INIT1 =  16'h99AA ;
+    defparam empty_cmp_4.INIT0 =  16'h99AA ;
+    CCU2C empty_cmp_4 (.A0(rcount_8), .A1(empty_cmp_set), .B0(wcount_r8), 
+        .B1(empty_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co3_2), .S0(), .S1(), .COUT(empty_d_c));
+
+    defparam a0.INJECT1_1 = "NO" ;
+    defparam a0.INJECT1_0 = "NO" ;
+    defparam a0.INIT1 =  16'h66AA ;
+    defparam a0.INIT0 =  16'h66AA ;
+    CCU2C a0 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(empty_d_c), .S0(empty_d), .S1(), .COUT());
+
+    defparam full_cmp_ci_a.INJECT1_1 = "NO" ;
+    defparam full_cmp_ci_a.INJECT1_0 = "NO" ;
+    defparam full_cmp_ci_a.INIT1 =  16'h66AA ;
+    defparam full_cmp_ci_a.INIT0 =  16'h66AA ;
+    CCU2C full_cmp_ci_a (.A0(scuba_vlo), .A1(wren_i), .B0(scuba_vlo), .B1(wren_i), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(), .S0(), .S1(), .COUT(cmp_ci_1));
+
+    defparam full_cmp_0.INJECT1_1 = "NO" ;
+    defparam full_cmp_0.INJECT1_0 = "NO" ;
+    defparam full_cmp_0.INIT1 =  16'h99AA ;
+    defparam full_cmp_0.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_0 (.A0(wcount_0), .A1(wcount_1), .B0(rcount_w0), .B1(rcount_w1), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(cmp_ci_1), .S0(), .S1(), .COUT(co0_3));
+
+    defparam full_cmp_1.INJECT1_1 = "NO" ;
+    defparam full_cmp_1.INJECT1_0 = "NO" ;
+    defparam full_cmp_1.INIT1 =  16'h99AA ;
+    defparam full_cmp_1.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_1 (.A0(wcount_2), .A1(wcount_3), .B0(rcount_w2), .B1(rcount_w3), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co0_3), .S0(), .S1(), .COUT(co1_3));
+
+    defparam full_cmp_2.INJECT1_1 = "NO" ;
+    defparam full_cmp_2.INJECT1_0 = "NO" ;
+    defparam full_cmp_2.INIT1 =  16'h99AA ;
+    defparam full_cmp_2.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_2 (.A0(wcount_4), .A1(wcount_5), .B0(rcount_w4), .B1(rcount_w5), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(co1_3), .S0(), .S1(), .COUT(co2_3));
+
+    defparam full_cmp_3.INJECT1_1 = "NO" ;
+    defparam full_cmp_3.INJECT1_0 = "NO" ;
+    defparam full_cmp_3.INIT1 =  16'h99AA ;
+    defparam full_cmp_3.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_3 (.A0(wcount_6), .A1(wcount_7), .B0(r_g2b_xor_cluster_0), 
+        .B1(rcount_w7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co2_3), .S0(), .S1(), .COUT(co3_3));
+
+    defparam full_cmp_4.INJECT1_1 = "NO" ;
+    defparam full_cmp_4.INJECT1_0 = "NO" ;
+    defparam full_cmp_4.INIT1 =  16'h99AA ;
+    defparam full_cmp_4.INIT0 =  16'h99AA ;
+    CCU2C full_cmp_4 (.A0(wcount_8), .A1(full_cmp_set), .B0(rcount_w8), 
+        .B1(full_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), 
+        .D1(scuba_vhi), .CIN(co3_3), .S0(), .S1(), .COUT(full_d_c));
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam a1.INJECT1_1 = "NO" ;
+    defparam a1.INJECT1_0 = "NO" ;
+    defparam a1.INIT1 =  16'h66AA ;
+    defparam a1.INIT0 =  16'h66AA ;
+    CCU2C a1 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), 
+        .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), 
+        .CIN(full_d_c), .S0(full_d), .S1(), .COUT());
+
+    assign Empty = empty_i;
+    assign Full = full_i;
+
+
+    // exemplar begin
+    // exemplar attribute pdp_ram_0_0_1 MEM_LPC_FILE fifo40_dc.lpc
+    // exemplar attribute pdp_ram_0_0_1 MEM_INIT_FILE 
+    // exemplar attribute pdp_ram_0_1_0 MEM_LPC_FILE fifo40_dc.lpc
+    // exemplar attribute pdp_ram_0_1_0 MEM_INIT_FILE 
+    // exemplar attribute FF_101 GSR ENABLED
+    // exemplar attribute FF_100 GSR ENABLED
+    // exemplar attribute FF_99 GSR ENABLED
+    // exemplar attribute FF_98 GSR ENABLED
+    // exemplar attribute FF_97 GSR ENABLED
+    // exemplar attribute FF_96 GSR ENABLED
+    // exemplar attribute FF_95 GSR ENABLED
+    // exemplar attribute FF_94 GSR ENABLED
+    // exemplar attribute FF_93 GSR ENABLED
+    // exemplar attribute FF_92 GSR ENABLED
+    // exemplar attribute FF_91 GSR ENABLED
+    // exemplar attribute FF_90 GSR ENABLED
+    // exemplar attribute FF_89 GSR ENABLED
+    // exemplar attribute FF_88 GSR ENABLED
+    // exemplar attribute FF_87 GSR ENABLED
+    // exemplar attribute FF_86 GSR ENABLED
+    // exemplar attribute FF_85 GSR ENABLED
+    // exemplar attribute FF_84 GSR ENABLED
+    // exemplar attribute FF_83 GSR ENABLED
+    // exemplar attribute FF_82 GSR ENABLED
+    // exemplar attribute FF_81 GSR ENABLED
+    // exemplar attribute FF_80 GSR ENABLED
+    // exemplar attribute FF_79 GSR ENABLED
+    // exemplar attribute FF_78 GSR ENABLED
+    // exemplar attribute FF_77 GSR ENABLED
+    // exemplar attribute FF_76 GSR ENABLED
+    // exemplar attribute FF_75 GSR ENABLED
+    // exemplar attribute FF_74 GSR ENABLED
+    // exemplar attribute FF_73 GSR ENABLED
+    // exemplar attribute FF_72 GSR ENABLED
+    // exemplar attribute FF_71 GSR ENABLED
+    // exemplar attribute FF_70 GSR ENABLED
+    // exemplar attribute FF_69 GSR ENABLED
+    // exemplar attribute FF_68 GSR ENABLED
+    // exemplar attribute FF_67 GSR ENABLED
+    // exemplar attribute FF_66 GSR ENABLED
+    // exemplar attribute FF_65 GSR ENABLED
+    // exemplar attribute FF_64 GSR ENABLED
+    // exemplar attribute FF_63 GSR ENABLED
+    // exemplar attribute FF_62 GSR ENABLED
+    // exemplar attribute FF_61 GSR ENABLED
+    // exemplar attribute FF_60 GSR ENABLED
+    // exemplar attribute FF_59 GSR ENABLED
+    // exemplar attribute FF_58 GSR ENABLED
+    // exemplar attribute FF_57 GSR ENABLED
+    // exemplar attribute FF_56 GSR ENABLED
+    // exemplar attribute FF_55 GSR ENABLED
+    // exemplar attribute FF_54 GSR ENABLED
+    // exemplar attribute FF_53 GSR ENABLED
+    // exemplar attribute FF_52 GSR ENABLED
+    // exemplar attribute FF_51 GSR ENABLED
+    // exemplar attribute FF_50 GSR ENABLED
+    // exemplar attribute FF_49 GSR ENABLED
+    // exemplar attribute FF_48 GSR ENABLED
+    // exemplar attribute FF_47 GSR ENABLED
+    // exemplar attribute FF_46 GSR ENABLED
+    // exemplar attribute FF_45 GSR ENABLED
+    // exemplar attribute FF_44 GSR ENABLED
+    // exemplar attribute FF_43 GSR ENABLED
+    // exemplar attribute FF_42 GSR ENABLED
+    // exemplar attribute FF_41 GSR ENABLED
+    // exemplar attribute FF_40 GSR ENABLED
+    // exemplar attribute FF_39 GSR ENABLED
+    // exemplar attribute FF_38 GSR ENABLED
+    // exemplar attribute FF_37 GSR ENABLED
+    // exemplar attribute FF_36 GSR ENABLED
+    // exemplar attribute FF_35 GSR ENABLED
+    // exemplar attribute FF_34 GSR ENABLED
+    // exemplar attribute FF_33 GSR ENABLED
+    // exemplar attribute FF_32 GSR ENABLED
+    // exemplar attribute FF_31 GSR ENABLED
+    // exemplar attribute FF_30 GSR ENABLED
+    // exemplar attribute FF_29 GSR ENABLED
+    // exemplar attribute FF_28 GSR ENABLED
+    // exemplar attribute FF_27 GSR ENABLED
+    // exemplar attribute FF_26 GSR ENABLED
+    // exemplar attribute FF_25 GSR ENABLED
+    // exemplar attribute FF_24 GSR ENABLED
+    // exemplar attribute FF_23 GSR ENABLED
+    // exemplar attribute FF_22 GSR ENABLED
+    // exemplar attribute FF_21 GSR ENABLED
+    // exemplar attribute FF_20 GSR ENABLED
+    // exemplar attribute FF_19 GSR ENABLED
+    // exemplar attribute FF_18 GSR ENABLED
+    // exemplar attribute FF_17 GSR ENABLED
+    // exemplar attribute FF_16 GSR ENABLED
+    // exemplar attribute FF_15 GSR ENABLED
+    // exemplar attribute FF_14 GSR ENABLED
+    // exemplar attribute FF_13 GSR ENABLED
+    // exemplar attribute FF_12 GSR ENABLED
+    // exemplar attribute FF_11 GSR ENABLED
+    // exemplar attribute FF_10 GSR ENABLED
+    // exemplar attribute FF_9 GSR ENABLED
+    // exemplar attribute FF_8 GSR ENABLED
+    // exemplar attribute FF_7 GSR ENABLED
+    // exemplar attribute FF_6 GSR ENABLED
+    // exemplar attribute FF_5 GSR ENABLED
+    // exemplar attribute FF_4 GSR ENABLED
+    // exemplar attribute FF_3 GSR ENABLED
+    // exemplar attribute FF_2 GSR ENABLED
+    // exemplar attribute FF_1 GSR ENABLED
+    // exemplar attribute FF_0 GSR ENABLED
+    // exemplar end
+
+endmodule
diff --git a/fifo40_dc/fifo40_dc_generate.log b/fifo40_dc/fifo40_dc_generate.log
new file mode 100644
index 0000000..23a2972
--- /dev/null
+++ b/fifo40_dc/fifo40_dc_generate.log
@@ -0,0 +1,49 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Tue Feb  9 13:19:24 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 
+    Circuit name     : fifo40_dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+	Inputs       : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+	Outputs      : Q[39:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo40_dc.edn
+    Verilog output   : fifo40_dc.v
+    Verilog template : fifo40_dc_tmpl.v
+    Verilog testbench: tb_fifo40_dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo40_dc.srp
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 2
+            Reg : 102
+
+END   SCUBA Module Synthesis
+
+File: fifo40_dc.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/fifo40_dc/fifo40_dc_tmpl.v b/fifo40_dc/fifo40_dc_tmpl.v
new file mode 100644
index 0000000..64ab3eb
--- /dev/null
+++ b/fifo40_dc/fifo40_dc_tmpl.v
@@ -0,0 +1,7 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.8 */
+/* Tue Feb  9 13:19:26 2021 */
+
+/* parameterized module instance */
+fifo40_dc __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
+    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ));
diff --git a/fifo40_dc/generate_core.tcl b/fifo40_dc/generate_core.tcl
new file mode 100644
index 0000000..079d16b
--- /dev/null
+++ b/fifo40_dc/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "fifo40_dc"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/fifo40_dc/generate_ngd.tcl b/fifo40_dc/generate_ngd.tcl
new file mode 100644
index 0000000..9920deb
--- /dev/null
+++ b/fifo40_dc/generate_ngd.tcl
@@ -0,0 +1,74 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "fifo40_dc"
+set Para(Module) "FIFO_DC"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/fifo40_dc/msg_file.log b/fifo40_dc/msg_file.log
new file mode 100644
index 0000000..a9be101
--- /dev/null
+++ b/fifo40_dc/msg_file.log
@@ -0,0 +1,33 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Tue Feb  9 13:19:24 2021
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 
+    Circuit name     : fifo40_dc
+    Module type      : ebfifo
+    Module Version   : 5.8
+    Ports            : 
+    Inputs       : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+    Outputs      : Q[39:0], Empty, Full
+    I/O buffer       : not inserted
+    EDIF output      : fifo40_dc.edn
+    Verilog output   : fifo40_dc.v
+    Verilog template : fifo40_dc_tmpl.v
+    Verilog testbench: tb_fifo40_dc_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : fifo40_dc.srp
+    Estimated Resource Usage:
+            LUT : 97
+            EBR : 2
+            Reg : 102
+  
+END   SCUBA Module Synthesis
+
diff --git a/fifo40_dc/tb_fifo40_dc_tmpl.v b/fifo40_dc/tb_fifo40_dc_tmpl.v
new file mode 100644
index 0000000..d293983
--- /dev/null
+++ b/fifo40_dc/tb_fifo40_dc_tmpl.v
@@ -0,0 +1,76 @@
+//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.11.2.446
+`timescale 1 ns / 1 ps
+module tb;
+    reg [39:0] Data = 40'b0;
+    reg WrClock = 0;
+    reg RdClock = 0;
+    reg WrEn = 0;
+    reg RdEn = 0;
+    reg Reset = 0;
+    reg RPReset = 0;
+    wire [39:0] Q;
+    wire Empty;
+    wire Full;
+
+    integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0;
+
+    GSR GSR_INST (.GSR(1'b1));
+    PUR PUR_INST (.PUR(1'b1));
+
+    fifo40_dc u1 (.Data(Data), .WrClock(WrClock), .RdClock(RdClock), .WrEn(WrEn), 
+        .RdEn(RdEn), .Reset(Reset), .RPReset(RPReset), .Q(Q), .Empty(Empty), 
+        .Full(Full)
+    );
+
+    initial
+    begin
+       Data <= 0;
+      #100;
+      @(Reset == 1'b0);
+      for (i1 = 0; i1 < 515; i1 = i1 + 1) begin
+        @(posedge WrClock);
+        #1  Data <= Data + 1'b1;
+      end
+    end
+    always
+    #5.00 WrClock <= ~ WrClock;
+
+    always
+    #5.00 RdClock <= ~ RdClock;
+
+    initial
+    begin
+       WrEn <= 1'b0;
+      #100;
+      @(Reset == 1'b0);
+      for (i4 = 0; i4 < 515; i4 = i4 + 1) begin
+        @(posedge WrClock);
+        #1  WrEn <= 1'b1;
+      end
+       WrEn <= 1'b0;
+    end
+    initial
+    begin
+       RdEn <= 1'b0;
+      @(Reset == 1'b0);
+      @(WrEn == 1'b1);
+      @(WrEn == 1'b0);
+      for (i5 = 0; i5 < 515; i5 = i5 + 1) begin
+        @(posedge RdClock);
+        #1  RdEn <= 1'b1;
+      end
+       RdEn <= 1'b0;
+    end
+    initial
+    begin
+       Reset <= 1'b1;
+      #100;
+       Reset <= 1'b0;
+    end
+    initial
+    begin
+       RPReset <= 1'b1;
+      #100;
+       RPReset <= 1'b0;
+    end
+endmodule
\ No newline at end of file
diff --git a/fifo_colector.v b/fifo_colector.v
new file mode 100644
index 0000000..a9efe4a
--- /dev/null
+++ b/fifo_colector.v
@@ -0,0 +1,95 @@
+//`define IGNORE_VERILOG_BLACKBOX_GUTS
+
+module fifo_colector(	wr_clk,
+								rd_clk,
+								reset,
+								in_data,
+								in_empty,
+								in_read_enable,
+								out_data,
+								out_empty, 
+								out_read_enable,
+								discard,
+								//buffer_wr_enable,
+								raw_enable
+								);
+	parameter CHANNELS = 3;
+	parameter DATA_WIDTH = 32;
+	parameter ADDRESS_WIDTH = 8;
+	/* */
+	input wire wr_clk;
+	input wire rd_clk;
+	input wire reset;
+	//input wire [CHANNELS-1:0][DATA_WIDTH-1:0]in_data;
+	input wire [(CHANNELS*DATA_WIDTH-1):0]in_data;
+	input wire [CHANNELS-1:0]in_empty;
+	output reg [CHANNELS-1:0]in_read_enable;
+	//output wire [$clog2(CHANNELS)+DATA_WIDTH-1:0]out_data;
+	output wire [ADDRESS_WIDTH+DATA_WIDTH-1:0]out_data;
+	output wire out_empty;
+	input wire out_read_enable;
+	input wire discard;
+	input wire raw_enable;
+	
+	wire fifo_clear;
+	assign fifo_clear = discard | reset;
+	reg buffer_wr_enable;
+	//reg [$clog2(CHANNELS)+DATA_WIDTH-1:0]data_buffer
+	reg [ADDRESS_WIDTH+DATA_WIDTH-1:0]data_buffer;
+	reg [$clog2(CHANNELS)-1:0]iterator;	
+fifo40_dc fifo40_inst (
+						.Data( data_buffer), 
+						.WrClock( wr_clk),
+						.RdClock( rd_clk),						
+						.WrEn( buffer_wr_enable), 
+						.RdEn( out_read_enable), 
+						//.Reset( fifo_clear),
+						.Reset( 0),						
+						.Q( out_data),
+						.Empty( out_empty), 
+						.Full( )
+						);
+	
+	reg [31:0]test_cnt;
+	always @(posedge wr_clk)begin
+		if(reset)begin
+			test_cnt <= 'b0;
+		end else begin
+			test_cnt <= test_cnt +1;
+		end
+	end
+	//assign buffer_wr_enable =in_empty[0];
+/*always @(posedge clk)begin
+		if(~in_empty[0])begin
+			data_buffer[DATA_WIDTH+: $clog2(CHANNELS)] <= 0;
+			data_buffer[0 +: DATA_WIDTH] <=in_data[0];
+			//buffer_wr_enable<=1;
+			in_read_enable[0]<=1;
+		end else begin
+			//buffer_wr_enable<=0;
+			in_read_enable[0]<=0;
+		end
+		
+end*/
+//fifo0 fifo0_inst (.Data( data[i]), .Clock( pll_clks[0]), .WrEn( decoder_data_valid[i]), .RdEn( fifo_read[i]), .Reset( ), .Q( fifo_out[i]), .Empty( fifo_empty[i]), .Full( ), .AlmostEmpty( ), .AlmostFull( ));								
+						
+	always @( posedge wr_clk)begin
+		if(~in_empty[iterator])begin
+			data_buffer[DATA_WIDTH+: $clog2(CHANNELS)] = iterator;
+			data_buffer[0 +: DATA_WIDTH] = in_data[(iterator*DATA_WIDTH) +: DATA_WIDTH];
+			//data_buffer[0 +: DATA_WIDTH] = in_data[iterator];
+			//data_buffer[0 +: DATA_WIDTH] = test_cnt;
+			in_read_enable[iterator] ='b1;
+			buffer_wr_enable = 'b1;
+		end else begin
+			in_read_enable='b0;
+			buffer_wr_enable = 'b0;
+		end
+		if(iterator<CHANNELS-1)iterator <= iterator+'b1;
+		else iterator <= 'b0;
+	end		
+	
+								
+
+
+endmodule
diff --git a/hades_colector.v b/hades_colector.v
new file mode 100644
index 0000000..d98f74e
--- /dev/null
+++ b/hades_colector.v
@@ -0,0 +1,21 @@
+module hades_colector(	wr_clk,
+								rd_clk,
+								reset,
+								in_data,
+								in_empty,
+								in_read_enable,
+								out_data,
+								out_empty, 
+								out_read_enable,
+								discard,
+								//buffer_wr_enable,
+								raw_enable
+								);
+								
+								
+								
+								
+								
+								
+								
+endmodule
\ No newline at end of file
diff --git a/hades_modules.v b/hades_modules.v
new file mode 100644
index 0000000..bc0f036
--- /dev/null
+++ b/hades_modules.v
@@ -0,0 +1,195 @@
+
+module hades_tdc_bundle(
+										reset, 
+										pll_clks,
+										trig,
+										LVL1_trig,
+										LVL1_invalid,
+										referenced_out,
+										referenced_out_valid,
+										window_end,
+										LVL1_offset,
+										LVL1_offset_valid,
+										buf_out,
+										buf_out_valid,
+										buf_release,
+										buf_finished,
+										hit_out_i,
+										hit_valid,
+										discard,
+										invalid_dl,
+										buf_drop,
+										dbg2_out,
+										dbg2_coarse,
+										drop_cmp_buf,
+										drop_cmp_buf_coarse,
+										drop_cmp_buf_valid										
+										);
+										
+	parameter TRIG_WIDTH = 1;
+	parameter COARSE_WIDTH = 9;
+	parameter TDC_WIDTH = 3;
+	parameter HITBUFFER_DEPTH = 4;
+	parameter COARSE_WIDTH_INTERNAL = 9;
+
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire [TRIG_WIDTH-1:0]trig;		
+	input wire LVL1_trig;
+	input wire LVL1_invalid;
+	output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]referenced_out;
+	output reg referenced_out_valid;
+	output wire window_end;
+	output wire [(COARSE_WIDTH+TDC_WIDTH)-1 : 0]LVL1_offset;
+	output wire LVL1_offset_valid;
+	output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]buf_out;
+	output reg buf_out_valid;
+	output reg buf_release;
+	output reg buf_finished;
+	output wire discard;
+	output wire [3:0]invalid_dl;
+	output reg [3:0]buf_drop;
+
+
+	output reg [3:0]hit_out_i;
+	reg [1:0]hit_i;
+	output reg [HITBUFFER_DEPTH-1:0]hit_valid;
+	reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]hitbuffer[HITBUFFER_DEPTH-1:0];
+	wire [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]hades_raw_out;	
+	reg [COARSE_WIDTH_INTERNAL-1 : 0]coarse;
+
+
+	//output wire [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]dbg2_out;
+	output wire [31 : 0]dbg2_out;
+	output wire [COARSE_WIDTH_INTERNAL-1 : 0]dbg2_coarse;
+	assign dbg2_coarse = coarse;
+	//assign dbg2_out = {3'b000, hitbuffer[1][28:20], 1'b0, hitbuffer[1][18:16], 3'b000, hitbuffer[1][12:4], 1'b0, hitbuffer[1][2:0]};
+	assign dbg2_out[31:29] = 3'b000;
+	assign dbg2_out[28:20] = hitbuffer[1][23:15];
+	assign dbg2_out[19] = 1'b0;
+	assign dbg2_out[18:16] = hitbuffer[1][14:12];
+	assign dbg2_out[15:13] = 3'b000;
+	assign dbg2_out[12:4] = hitbuffer[1][11:3];
+	assign dbg2_out[3] = 1'b0;
+	assign dbg2_out[2:0] = hitbuffer[1][2:0];
+
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+			coarse <= 'b0;
+		end else begin
+			coarse <= coarse +'b1;
+		end
+	end
+	
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+			buf_finished <= 'b0;
+			buf_release <= 'b0;
+		end else begin
+			if(hit_out_i == HITBUFFER_DEPTH+1)buf_finished <= 'b1;
+			else buf_finished <= 'b0;
+			if(hit_out_i == HITBUFFER_DEPTH+2)buf_release <= 'b1;
+			else buf_release <= 'b0;
+		end
+	end
+	
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+			hit_out_i <= 'b0;
+		end else begin
+			if(window_end && !discard)begin
+				hit_out_i <=1;
+			end
+			if(discard)begin
+					hit_out_i <=HITBUFFER_DEPTH +1;
+			end
+			/**/
+			if(hit_out_i)begin
+				if((hit_out_i <= HITBUFFER_DEPTH) && hit_valid[hit_out_i-1])begin
+					buf_out <= hitbuffer[hit_out_i-1] - LVL1_offset;
+					buf_out_valid <= 'b1;
+				end else begin
+					buf_out_valid <= 'b0;
+				end
+				hit_out_i <= hit_out_i + 'b1;
+			end
+		end
+	end
+	output reg [11:0]drop_cmp_buf;
+	output reg [11:0]drop_cmp_buf_coarse;
+	output reg drop_cmp_buf_valid;
+	
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+				hit_i <='b0;
+				buf_drop <= 'b0;
+			end else begin
+				if( hades_raw_out_valid)begin
+					hitbuffer[hit_i] <= hades_raw_out;
+					hit_i <= hit_i + 'b1;
+					hit_valid[hit_i] <= 'b1;
+				end
+				if(hit_out_i == (HITBUFFER_DEPTH+3))hit_valid <= 'b0000;
+				if(hit_valid[1])begin
+					drop_cmp_buf <= (hitbuffer[1][11:3] );
+					drop_cmp_buf_coarse <= (coarse +12'b1);
+					drop_cmp_buf_valid <='b1;
+				end
+				if(drop_cmp_buf_valid)begin
+					//drop_cmp_buf_valid <='b0;
+					if(drop_cmp_buf == drop_cmp_buf_coarse)begin
+						hit_valid[1] <= 1'b0;
+						buf_drop[1] <= 'b1;
+						drop_cmp_buf_valid <='b0;
+					end else begin
+						buf_drop[1] <= 'b0;
+					end
+				end else begin
+						buf_drop[1] <= 'b0;
+				end
+			end
+	end
+		
+		always @(posedge pll_clks[3])begin
+			if(LVL1_offset_valid)begin
+				//referenced_out <= hades_raw_out - LVL1_offset;
+				referenced_out[ 0 +: (COARSE_WIDTH+TDC_WIDTH)] 												<= hades_raw_out[0 +: (COARSE_WIDTH+TDC_WIDTH)] 												- LVL1_offset;
+				referenced_out[(COARSE_WIDTH+TDC_WIDTH) +: (COARSE_WIDTH+TDC_WIDTH)] 	<= hades_raw_out[(COARSE_WIDTH+TDC_WIDTH) +: (COARSE_WIDTH+TDC_WIDTH)] 	- LVL1_offset;
+				referenced_out_valid <= 'b1;
+			end else begin
+				referenced_out_valid <= 'b0;
+			end
+		end
+		
+		hades_LVL1_raw_out hades_LVL1_raw_out_inst(
+										.reset(reset), 
+										.pll_clks(pll_clks), 
+										.coarse(coarse[8:0]), 
+										.trig(LVL1_trig),
+										.invalid(LVL1_invalid),
+										.offset(LVL1_offset),
+										.offset_valid(LVL1_offset_valid),
+										.window_end(window_end),
+										.discard(discard),
+										.invalid_dl(invalid_dl)
+										);
+		
+		
+		
+		hades_tdc_channel_raw_out hades_tdc_channel_raw_out_inst(
+																					.reset(reset), 
+																					.pll_clks(pll_clks), 
+																					.coarse(coarse[8:0]), 
+																					.trig(trig),
+																					.tdc_out(),
+																					.raw_out(hades_raw_out),
+																					.raw_out_valid(hades_raw_out_valid),
+																					.raw_valid_vect(hades_raw_valid_vect)
+																					);
+
+		
+		
+
+
+endmodule
+
diff --git a/hades_modules2.v b/hades_modules2.v
new file mode 100644
index 0000000..2f3f8c2
--- /dev/null
+++ b/hades_modules2.v
@@ -0,0 +1,216 @@
+
+module hades_LVL1_raw_out (
+										reset, 
+										pll_clks, 
+										coarse, 
+										trig,
+										invalid,
+										offset,
+										offset_valid,
+										window_end,
+										discard,
+										invalid_dl
+										//tdc_out,
+										//raw_out,
+										//raw_out_valid,
+										//raw_valid_vect
+										);
+							
+	parameter COARSE_WIDTH = 9;
+	parameter TDC_WIDTH = 3;
+
+	parameter WINDOW_LENGTH='hff;
+
+
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire trig;
+	input wire invalid;
+	input wire [COARSE_WIDTH-1:0]coarse;
+	
+	output reg [(COARSE_WIDTH+TDC_WIDTH)-1 : 0]offset;
+	output reg offset_valid;
+	output reg window_end;
+	output reg discard;
+	
+	reg [8:0]window;
+
+	reg [3:0] trig_dl;
+	output reg [3:0]invalid_dl;
+	wire trig_gate /* synthesis syn_preserve= 1*/;
+	assign trig_gate = ~trig;
+	//assign window_end = (window == 'b11);
+	wire [7:0]tdc_out;
+	wire [2:0]decoder_out;
+	
+	tdc4ddr_short tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks),
+						.out(tdc_out)
+	);			
+	output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out),
+						.out(decoder_out),
+						.valid(decoder_valid)
+						);
+								
+		
+		always @(posedge pll_clks[3])begin
+			invalid_dl <= {invalid_dl[2:0], invalid};
+			trig_dl <= {trig_dl[2:0],trig};
+		end
+	 
+	always @(posedge pll_clks[3])begin
+		if(window == 2)window_end='b1;
+		else window_end=0;
+	end
+	 
+	always @( posedge pll_clks[3])begin
+		if(offset_valid)begin
+			
+		end
+	end
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+			offset<= 'b0;
+			offset_valid <= 'b0;
+			discard <= 'b0;
+		end else begin
+			if(window)begin
+				window <= window -1;
+			end
+			if(window == 'b1)begin
+				discard <= 'b0;
+				offset <= 'b0;
+				offset_valid <= 'b0;
+			end
+			if(decoder_valid && !discard)begin
+				offset <= {coarse, decoder_out};
+				offset_valid <= 'b1;
+				window <= WINDOW_LENGTH;
+			end else begin
+				//
+			end
+			if(|invalid_dl[3:2] && |trig_dl[3:2] )begin
+				discard <= 'b1;
+				window <= 4;
+			end else begin
+				//
+			end
+			
+			
+		end
+end
+
+endmodule
+
+
+
+module hades_tdc_channel_raw_out (
+										reset, 
+										pll_clks, 
+										coarse, 
+										trig,
+										tdc_out,
+										raw_out,
+										raw_out_valid,
+										raw_valid_vect
+										);
+							
+	parameter COARSE_WIDTH = 9;
+	parameter TDC_WIDTH = 3;
+
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire trig;
+	input wire [COARSE_WIDTH-1:0]coarse;
+
+	output wire [7:0]tdc_out;
+	wire [7:0]tdc_out_neg;
+	output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]raw_out;
+	output reg raw_out_valid;
+	output wire [1:0]raw_valid_vect;
+	
+	wire trig_gate /* synthesis syn_preserve= 1*/;
+	assign trig_gate = ~trig;
+	wire trig_gate_neg /* synthesis syn_preserve= 1*/;
+	trig_inv trig_inv_inst1(
+							.in(trig_gate),
+							.out(trig_gate_neg)
+	) /* synthesis syn_black_box */;
+
+	tdc4ddr_short tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks),
+						.out(tdc_out)
+	);
+	tdc4ddr_short tdc_neg_inst(
+						.trigger(trig_gate_neg), 
+						.clks(pll_clks),
+						.out(tdc_out_neg)
+						) /* synthesis syn_preserve= 1*/;			
+	output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out),
+						.out(decoder_out),
+						.valid(decoder_valid)
+						);
+						
+	output_decoder8 dec_neg_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out_neg),
+						.out(decoder_out_neg),
+						.valid(decoder_valid_neg)
+						) /* synthesis syn_preserve= 1*/;
+		
+		
+	 reg [31:0]fifo_in_data;
+	 wire fifo_in_valid;
+	 wire [2:0]decoder_out;
+	 wire [2:0]decoder_out_neg;
+	 
+	 reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_positive;
+	 reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_negative;
+	 reg buf_positive_ready;
+	 reg buf_negative_ready;
+	 assign raw_valid_vect = {buf_positive_ready, buf_negative_ready};
+	
+	always @(posedge pll_clks[3])begin
+		if(reset)begin
+			raw_out <= 'b0;
+			raw_out_valid <= 'b0;
+		end else begin
+			if(decoder_valid)begin
+				buf_positive <= {coarse, decoder_out};
+				//raw_out[23:12] <= {coarse, decoder_out};
+				buf_positive_ready <= 'b1;
+				//buf_negative_ready <= 'b0;	// first edge  clears second buffer if gliched
+			end else begin
+				//buf_positive_ready <= 'b0;
+			end
+			if(decoder_valid_neg && buf_positive_ready)begin
+				buf_negative <= {coarse, decoder_out_neg};
+				//raw_out[11:0] <= {coarse, decoder_out};
+				buf_negative_ready <= 'b1;
+			end else begin
+				//buf_negative_ready <= 'b0;
+			end
+			if(buf_positive_ready && (buf_positive[COARSE_WIDTH-1 : TDC_WIDTH]) == coarse +'b1)begin
+				buf_positive_ready <= 'b0;
+			end
+			if(buf_negative_ready && (buf_negative[COARSE_WIDTH-1 : TDC_WIDTH]) == coarse +'b1)begin
+				buf_negative_ready <= 'b0;
+			end
+			if(buf_negative_ready & buf_positive_ready)begin
+				buf_negative_ready <= 'b0;
+				buf_positive_ready <= 'b0;
+				raw_out <= {buf_negative, buf_positive};
+				raw_out_valid <= 'b1;
+			end else begin
+				raw_out_valid <= 'b0;
+			end
+		end
+end
+
+endmodule
\ No newline at end of file
diff --git a/hades_wrong_inverter_5_1.dly b/hades_wrong_inverter_5_1.dly
new file mode 100644
index 0000000..6718f2d
--- /dev/null
+++ b/hades_wrong_inverter_5_1.dly
@@ -0,0 +1,8892 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Thu May 27 08:29:19 2021
+
+File: s1_impl1.dir/5_1.dly
+
+ The 20 worst nets by delay are:
+---------------------------------
+| Max Delay         | Netname   |
+---------------------------------
+   3.3                 reset_dl[2]
+   2.8                 fifo_rden_c
+   2.8                 trig_c[2]
+   2.7                 last_buf_empty_c
+   2.5                 genblk1[0].tdc_channel_fifo_out_inst/decoder_out[2]
+   2.5                 FEE_DATA_OUT_c[22]
+   2.5                 trig_c[1]
+   2.4                 FEE_DATA_OUT_c[27]
+   2.4                 FEE_DATA_OUT_c[16]
+   2.4                 fifo_colector_inst/N_16_i
+   2.3                 FEE_DATA_OUT_c[28]
+   2.3                 FEE_DATA_OUT_c[9]
+   2.2                 FEE_DATA_OUT_c[4]
+   2.2                 FEE_DATA_OUT_c[26]
+   2.2                 FEE_DATA_OUT_c[8]
+   2.2                 FEE_DATA_OUT_c[14]
+   2.2                 FEE_DATA_OUT_c[5]
+   2.2                 genblk1[0].tdc_channel_fifo_out_inst/decoder_valid
+   2.2                 FEE_DATA_OUT_c[19]
+   2.2                 coarse[0]
+---------------------------------
+
+-------------------------------------------------------------------------------
+                               Net Delays
+-------------------------------------------------------------------------------
+
+FEE_DATAFINISHED_OUT_c
+   trb_adapter_inst_FEE_DATAFINISHED_OUTio.IOLDO
+         0.0  FEE_DATAFINISHED_OUT_pad.IOLDO
+
+FEE_DATA_OUT_c[0]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA0
+         1.8  fifo_data_out_pad[0].PADDO
+         1.8  FEE_DATA_OUT_pad[0].PADDO
+
+FEE_DATA_OUT_c[10]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA10
+         1.8  FEE_DATA_OUT_pad[10].PADDO
+         1.8  fifo_data_out_pad[10].PADDO
+
+FEE_DATA_OUT_c[11]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA11
+         2.1  FEE_DATA_OUT_pad[11].PADDO
+         2.1  fifo_data_out_pad[11].PADDO
+
+FEE_DATA_OUT_c[12]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA12
+         1.8  FEE_DATA_OUT_pad[12].PADDO
+         2.0  fifo_data_out_pad[12].PADDO
+
+FEE_DATA_OUT_c[13]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA13
+         1.9  FEE_DATA_OUT_pad[13].PADDO
+         2.0  fifo_data_out_pad[13].PADDO
+
+FEE_DATA_OUT_c[14]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA14
+         2.1  FEE_DATA_OUT_pad[14].PADDO
+         2.2  fifo_data_out_pad[14].PADDO
+
+FEE_DATA_OUT_c[15]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA15
+         1.8  FEE_DATA_OUT_pad[15].PADDO
+         1.8  fifo_data_out_pad[15].PADDO
+
+FEE_DATA_OUT_c[16]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA16
+         2.3  FEE_DATA_OUT_pad[16].PADDO
+         2.4  fifo_data_out_pad[16].PADDO
+
+FEE_DATA_OUT_c[17]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA17
+         1.7  FEE_DATA_OUT_pad[17].PADDO
+         1.7  fifo_data_out_pad[17].PADDO
+
+FEE_DATA_OUT_c[18]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB0
+         1.8  FEE_DATA_OUT_pad[18].PADDO
+         2.0  fifo_data_out_pad[18].PADDO
+
+FEE_DATA_OUT_c[19]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB1
+         2.0  FEE_DATA_OUT_pad[19].PADDO
+         2.2  fifo_data_out_pad[19].PADDO
+
+FEE_DATA_OUT_c[1]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA1
+         1.7  FEE_DATA_OUT_pad[1].PADDO
+         1.9  fifo_data_out_pad[1].PADDO
+
+FEE_DATA_OUT_c[20]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB2
+         1.8  FEE_DATA_OUT_pad[20].PADDO
+         1.8  fifo_data_out_pad[20].PADDO
+
+FEE_DATA_OUT_c[21]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB3
+         1.8  FEE_DATA_OUT_pad[21].PADDO
+         1.8  fifo_data_out_pad[21].PADDO
+
+FEE_DATA_OUT_c[22]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB4
+         2.3  FEE_DATA_OUT_pad[22].PADDO
+         2.5  fifo_data_out_pad[22].PADDO
+
+FEE_DATA_OUT_c[23]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB5
+         1.7  FEE_DATA_OUT_pad[23].PADDO
+         1.7  fifo_data_out_pad[23].PADDO
+
+FEE_DATA_OUT_c[24]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB6
+         2.0  FEE_DATA_OUT_pad[24].PADDO
+         2.2  fifo_data_out_pad[24].PADDO
+
+FEE_DATA_OUT_c[25]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB7
+         1.9  FEE_DATA_OUT_pad[25].PADDO
+         2.1  fifo_data_out_pad[25].PADDO
+
+FEE_DATA_OUT_c[26]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB8
+         2.1  FEE_DATA_OUT_pad[26].PADDO
+         2.2  fifo_data_out_pad[26].PADDO
+
+FEE_DATA_OUT_c[27]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB9
+         2.4  FEE_DATA_OUT_pad[27].PADDO
+         2.4  fifo_data_out_pad[27].PADDO
+
+FEE_DATA_OUT_c[28]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB10
+         2.2  FEE_DATA_OUT_pad[28].PADDO
+         2.3  fifo_data_out_pad[28].PADDO
+
+FEE_DATA_OUT_c[29]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB11
+         1.7  FEE_DATA_OUT_pad[29].PADDO
+         1.8  fifo_data_out_pad[29].PADDO
+
+FEE_DATA_OUT_c[2]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA2
+         1.9  FEE_DATA_OUT_pad[2].PADDO
+         2.1  fifo_data_out_pad[2].PADDO
+
+FEE_DATA_OUT_c[30]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB12
+         1.8  FEE_DATA_OUT_pad[30].PADDO
+         1.8  fifo_data_out_pad[30].PADDO
+
+FEE_DATA_OUT_c[31]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB13
+         1.8  FEE_DATA_OUT_pad[31].PADDO
+         1.8  fifo_data_out_pad[31].PADDO
+
+FEE_DATA_OUT_c[3]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA3
+         1.7  FEE_DATA_OUT_pad[3].PADDO
+         1.7  fifo_data_out_pad[3].PADDO
+
+FEE_DATA_OUT_c[4]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA4
+         2.2  FEE_DATA_OUT_pad[4].PADDO
+         2.2  fifo_data_out_pad[4].PADDO
+
+FEE_DATA_OUT_c[5]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA5
+         2.0  FEE_DATA_OUT_pad[5].PADDO
+         2.2  fifo_data_out_pad[5].PADDO
+
+FEE_DATA_OUT_c[6]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA6
+         1.9  FEE_DATA_OUT_pad[6].PADDO
+         1.9  fifo_data_out_pad[6].PADDO
+
+FEE_DATA_OUT_c[7]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA7
+         1.7  FEE_DATA_OUT_pad[7].PADDO
+         1.7  fifo_data_out_pad[7].PADDO
+
+FEE_DATA_OUT_c[8]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA8
+         2.1  FEE_DATA_OUT_pad[8].PADDO
+         2.2  fifo_data_out_pad[8].PADDO
+
+FEE_DATA_OUT_c[9]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA9
+         2.3  FEE_DATA_OUT_pad[9].PADDO
+         2.3  fifo_data_out_pad[9].PADDO
+
+FEE_DATA_WRITE_OUT_c
+   trb_adapter_inst_FEE_DATA_WRITE_OUTio.IOLDO
+         0.0  FEE_DATA_WRITE_OUT_pad.IOLDO
+
+FEE_TRG_RELEASE_OUT_c
+   trb_adapter_inst_FEE_TRG_RELEASE_OUTio.IOLDO
+         0.0  FEE_TRG_RELEASE_OUT_pad.IOLDO
+
+LVL1_INVALID_TRG_IN_c
+   LVL1_INVALID_TRG_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALID_IN_c
+   LVL1_TRG_DATA_VALID_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALI_IN_rising_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F1
+         0.4  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B0
+         0.5  LVL1_TRG_DATA_VALI_IN_rising_pad.PADDO
+
+burst_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].F0
+         0.5  burst_pad.PADDO
+
+clk_c
+   clk_pad.PADDI
+         0.1  pll0inst/PLLInst_0.CLKI
+
+coarse[0]
+   coarse_RNO[0].Q0
+         0.7  un2_coarse_cry_0_0.A1
+         0.3  coarse_RNO[0].C0
+         1.9  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].M1
+         2.0  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].M1
+         2.2  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].M1
+         1.5  hades_tdc_channel_raw_out_inst/buf_negative[3].M1
+         1.6  hades_tdc_channel_raw_out_inst/buf_positive[3].M1
+
+coarse[1]
+   coarse[2].Q0
+         0.5  coarse[2].B0
+         1.1  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].M0
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].M0
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].M0
+         1.0  hades_tdc_channel_raw_out_inst/buf_negative[5].M0
+         1.0  hades_tdc_channel_raw_out_inst/buf_positive[5].M0
+
+coarse[2]
+   coarse[2].Q1
+         0.4  coarse[2].B1
+         1.5  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].M1
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].M1
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].M1
+         1.1  hades_tdc_channel_raw_out_inst/buf_negative[5].M1
+         1.1  hades_tdc_channel_raw_out_inst/buf_positive[5].M1
+
+coarse[3]
+   coarse[4].Q0
+         0.5  coarse[4].B0
+         1.4  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].M0
+         1.5  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].M0
+         1.5  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].M0
+         1.2  hades_tdc_channel_raw_out_inst/buf_negative[7].M0
+         1.2  hades_tdc_channel_raw_out_inst/buf_positive[7].M0
+
+coarse[4]
+   coarse[4].Q1
+         0.4  coarse[4].A1
+         1.1  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].M1
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].M1
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].M1
+         1.2  hades_tdc_channel_raw_out_inst/buf_negative[7].M1
+         1.2  hades_tdc_channel_raw_out_inst/buf_positive[7].M1
+
+coarse[5]
+   coarse[6].Q0
+         0.5  coarse[6].B0
+         1.4  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].M0
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].M0
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].M0
+         1.1  hades_tdc_channel_raw_out_inst/buf_negative[9].M0
+         1.1  hades_tdc_channel_raw_out_inst/buf_positive[9].M0
+
+coarse[6]
+   coarse[6].Q1
+         0.4  coarse[6].A1
+         1.4  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].M1
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].M1
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].M1
+         1.1  hades_tdc_channel_raw_out_inst/buf_negative[9].M1
+         1.1  hades_tdc_channel_raw_out_inst/buf_positive[9].M1
+
+coarse[7]
+   coarse[8].Q0
+         0.5  coarse[8].B0
+         1.2  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[10].M0
+         1.4  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[10].M0
+         1.2  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[10].M0
+         1.3  hades_tdc_channel_raw_out_inst/buf_negative[11].M0
+         1.1  hades_tdc_channel_raw_out_inst/buf_positive[11].M0
+
+coarse[8]
+   coarse[8].Q1
+         0.4  coarse[8].B1
+         1.1  hades_tdc_channel_raw_out_inst/buf_negative[11].M1
+         1.1  hades_tdc_channel_raw_out_inst/buf_positive[11].M1
+
+coarse_i[0]
+   coarse_RNO[0].F0
+         0.0  coarse_RNO[0].DI0
+
+discard_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].Q0
+         0.5  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.A0
+         0.9  fifo_colector_inst/N_16_i.B0
+         0.4  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].C0
+         0.9  discard_pad.PADDO
+
+fifo_colector_inst/N_16_i
+   fifo_colector_inst/N_16_i.F0
+         2.3  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.RSTA
+         2.4  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.RSTB
+         2.3  GSR_INST.GSR
+
+fifo_colector_inst/buffer_wr_enable
+   fifo_colector_inst/in_empty_pmux_0_RNIDRET.Q0
+         0.6  fifo_colector_inst/fifo40_inst/AND2_t20.D0
+
+fifo_colector_inst/data_buffer[0]
+   fifo_colector_inst/data_buffer_3[0].Q0
+         1.0  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA0
+
+fifo_colector_inst/data_buffer[10]
+   fifo_colector_inst/data_buffer_3_0[11].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA10
+
+fifo_colector_inst/data_buffer[11]
+   fifo_colector_inst/data_buffer_3_0[11].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA11
+
+fifo_colector_inst/data_buffer[12]
+   fifo_colector_inst/data_buffer_3_0[13].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA12
+
+fifo_colector_inst/data_buffer[13]
+   fifo_colector_inst/data_buffer_3_0[13].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA13
+
+fifo_colector_inst/data_buffer[14]
+   fifo_colector_inst/data_buffer_3_0[15].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA14
+
+fifo_colector_inst/data_buffer[15]
+   fifo_colector_inst/data_buffer_3_0[15].Q1
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA15
+
+fifo_colector_inst/data_buffer[16]
+   fifo_colector_inst/data_buffer_3_0[17].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA16
+
+fifo_colector_inst/data_buffer[17]
+   fifo_colector_inst/data_buffer_3_0[17].Q1
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA17
+
+fifo_colector_inst/data_buffer[18]
+   fifo_colector_inst/data_buffer_3_0[19].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB0
+
+fifo_colector_inst/data_buffer[19]
+   fifo_colector_inst/data_buffer_3_0[19].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB1
+
+fifo_colector_inst/data_buffer[1]
+   fifo_colector_inst/data_buffer_3[1].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA1
+
+fifo_colector_inst/data_buffer[20]
+   fifo_colector_inst/data_buffer_3_0[21].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB2
+
+fifo_colector_inst/data_buffer[21]
+   fifo_colector_inst/data_buffer_3_0[21].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB3
+
+fifo_colector_inst/data_buffer[22]
+   fifo_colector_inst/data_buffer_3_0[23].Q0
+         0.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB4
+
+fifo_colector_inst/data_buffer[23]
+   fifo_colector_inst/data_buffer_3_0[23].Q1
+         0.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB5
+
+fifo_colector_inst/data_buffer[24]
+   fifo_colector_inst/data_buffer_3_0[25].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB6
+
+fifo_colector_inst/data_buffer[25]
+   fifo_colector_inst/data_buffer_3_0[25].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB7
+
+fifo_colector_inst/data_buffer[26]
+   fifo_colector_inst/data_buffer_3_0[27].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB8
+
+fifo_colector_inst/data_buffer[27]
+   fifo_colector_inst/data_buffer_3_0[27].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB9
+
+fifo_colector_inst/data_buffer[28]
+   fifo_colector_inst/data_buffer_3_0[29].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB10
+
+fifo_colector_inst/data_buffer[29]
+   fifo_colector_inst/data_buffer_3_0[29].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB11
+
+fifo_colector_inst/data_buffer[2]
+   fifo_colector_inst/data_buffer_3[2].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA2
+
+fifo_colector_inst/data_buffer[30]
+   fifo_colector_inst/data_buffer_3_0[31].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB12
+
+fifo_colector_inst/data_buffer[31]
+   fifo_colector_inst/data_buffer_3_0[31].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB13
+
+fifo_colector_inst/data_buffer[32]
+   fifo_colector_inst/data_buffer[33].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB14
+
+fifo_colector_inst/data_buffer[33]
+   fifo_colector_inst/data_buffer[33].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB15
+
+fifo_colector_inst/data_buffer[3]
+   fifo_colector_inst/data_buffer_3[3].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA3
+
+fifo_colector_inst/data_buffer[4]
+   fifo_colector_inst/data_buffer_3[4].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA4
+
+fifo_colector_inst/data_buffer[5]
+   fifo_colector_inst/data_buffer_3[5].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA5
+
+fifo_colector_inst/data_buffer[6]
+   fifo_colector_inst/data_buffer_3[6].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA6
+
+fifo_colector_inst/data_buffer[7]
+   fifo_colector_inst/data_buffer_3[7].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA7
+
+fifo_colector_inst/data_buffer[8]
+   fifo_colector_inst/data_buffer_3_0[9].Q0
+         0.4  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA8
+
+fifo_colector_inst/data_buffer[9]
+   fifo_colector_inst/data_buffer_3_0[9].Q1
+         0.4  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA9
+
+fifo_colector_inst/data_buffer_3[0]
+   fifo_colector_inst/data_buffer_3[0].OFX0
+         0.0  fifo_colector_inst/data_buffer_3[0].DI0
+
+fifo_colector_inst/data_buffer_3[10]
+   fifo_colector_inst/data_buffer_3_0[11].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[11].DI0
+
+fifo_colector_inst/data_buffer_3[11]
+   fifo_colector_inst/data_buffer_3_0[11].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[11].DI1
+
+fifo_colector_inst/data_buffer_3[12]
+   fifo_colector_inst/data_buffer_3_0[13].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[13].DI0
+
+fifo_colector_inst/data_buffer_3[13]
+   fifo_colector_inst/data_buffer_3_0[13].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[13].DI1
+
+fifo_colector_inst/data_buffer_3[14]
+   fifo_colector_inst/data_buffer_3_0[15].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[15].DI0
+
+fifo_colector_inst/data_buffer_3[15]
+   fifo_colector_inst/data_buffer_3_0[15].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[15].DI1
+
+fifo_colector_inst/data_buffer_3[16]
+   fifo_colector_inst/data_buffer_3_0[17].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[17].DI0
+
+fifo_colector_inst/data_buffer_3[17]
+   fifo_colector_inst/data_buffer_3_0[17].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[17].DI1
+
+fifo_colector_inst/data_buffer_3[18]
+   fifo_colector_inst/data_buffer_3_0[19].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[19].DI0
+
+fifo_colector_inst/data_buffer_3[19]
+   fifo_colector_inst/data_buffer_3_0[19].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[19].DI1
+
+fifo_colector_inst/data_buffer_3[1]
+   fifo_colector_inst/data_buffer_3[1].OFX0
+         0.0  fifo_colector_inst/data_buffer_3[1].DI0
+
+fifo_colector_inst/data_buffer_3[20]
+   fifo_colector_inst/data_buffer_3_0[21].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[21].DI0
+
+fifo_colector_inst/data_buffer_3[21]
+   fifo_colector_inst/data_buffer_3_0[21].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[21].DI1
+
+fifo_colector_inst/data_buffer_3[22]
+   fifo_colector_inst/data_buffer_3_0[23].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[23].DI0
+
+fifo_colector_inst/data_buffer_3[23]
+   fifo_colector_inst/data_buffer_3_0[23].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[23].DI1
+
+fifo_colector_inst/data_buffer_3[24]
+   fifo_colector_inst/data_buffer_3_0[25].F0
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+
+fifo_colector_inst/data_buffer_3[25]
+   fifo_colector_inst/data_buffer_3_0[25].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[25].DI1
+
+fifo_colector_inst/data_buffer_3[26]
+   fifo_colector_inst/data_buffer_3_0[27].F0
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+
+fifo_colector_inst/data_buffer_3[27]
+   fifo_colector_inst/data_buffer_3_0[27].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[27].DI1
+
+fifo_colector_inst/data_buffer_3[28]
+   fifo_colector_inst/data_buffer_3_0[29].F0
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+
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+   fifo_colector_inst/data_buffer_3_0[29].F1
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+
+fifo_colector_inst/data_buffer_3[2]
+   fifo_colector_inst/data_buffer_3[2].OFX0
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+
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+   fifo_colector_inst/data_buffer_3_0[31].F0
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+
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+   fifo_colector_inst/data_buffer_3_0[31].F1
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+
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+   fifo_colector_inst/data_buffer_3[3].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[4].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[5].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[6].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[7].OFX0
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+
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+   fifo_colector_inst/data_buffer_3_0[9].F0
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+
+fifo_colector_inst/data_buffer_3[9]
+   fifo_colector_inst/data_buffer_3_0[9].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[9].DI1
+
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+         0.9  fifo_colector_inst/data_buffer_3_0[15].C1
+         1.2  fifo_colector_inst/data_buffer_3_0[17].B0
+         1.2  fifo_colector_inst/data_buffer_3_0[17].B1
+         0.8  fifo_colector_inst/data_buffer_3_0[19].A0
+         0.6  fifo_colector_inst/data_buffer_3_0[19].D1
+         0.7  fifo_colector_inst/data_buffer_3_0[21].C0
+         0.9  fifo_colector_inst/data_buffer_3_0[21].B1
+         0.9  fifo_colector_inst/data_buffer_3_0[23].C0
+         0.9  fifo_colector_inst/data_buffer_3_0[23].C1
+         1.0  fifo_colector_inst/data_buffer_3_0[25].C0
+         1.0  fifo_colector_inst/data_buffer_3_0[25].C1
+         1.0  fifo_colector_inst/data_buffer_3_0[27].C0
+         1.0  fifo_colector_inst/data_buffer_3_0[27].C1
+         0.5  fifo_colector_inst/data_buffer_3_0[29].D0
+         0.5  fifo_colector_inst/data_buffer_3_0[29].C1
+         0.5  fifo_colector_inst/data_buffer_3_0[31].D0
+         0.5  fifo_colector_inst/data_buffer_3_0[31].D1
+         0.8  fifo_colector_inst/data_buffer[33].M0
+         0.3  fifo_colector_inst/un5_in_read_enable.C0
+         0.4  fifo_colector_inst/un5_in_read_enable.M1
+         0.9  fifo_colector_inst/in_read_enable_1_.fb.A0
+         1.0  fifo_colector_inst/in_read_enable_1_.fb.B1
+         0.7  fifo_colector_inst/in_empty_pmux_0.D1
+
+fifo_colector_inst/iterator[1]
+   fifo_colector_inst/un5_in_read_enable.Q1
+         0.9  fifo_colector_inst/in_empty_pmux_0_RNIDRET.M0
+         0.7  fifo_colector_inst/data_buffer_3[0].A0
+         0.7  fifo_colector_inst/data_buffer_3[0].A1
+         0.8  fifo_colector_inst/data_buffer_3[1].A0
+         0.8  fifo_colector_inst/data_buffer_3[1].A1
+         0.8  fifo_colector_inst/data_buffer_3[2].A0
+         0.8  fifo_colector_inst/data_buffer_3[2].A1
+         0.9  fifo_colector_inst/data_buffer_3[3].C0
+         1.0  fifo_colector_inst/data_buffer_3[3].A1
+         0.6  fifo_colector_inst/data_buffer_3[4].A0
+         0.6  fifo_colector_inst/data_buffer_3[4].A1
+         0.8  fifo_colector_inst/data_buffer_3[5].C0
+         0.8  fifo_colector_inst/data_buffer_3[5].C1
+         0.7  fifo_colector_inst/data_buffer_3[6].A0
+         0.7  fifo_colector_inst/data_buffer_3[6].A1
+         0.6  fifo_colector_inst/data_buffer_3[7].A0
+         0.6  fifo_colector_inst/data_buffer_3[7].A1
+         0.9  fifo_colector_inst/data_buffer[33].M1
+         0.3  fifo_colector_inst/un5_in_read_enable.D0
+         1.1  fifo_colector_inst/in_read_enable_1_.fb.D0
+         1.0  fifo_colector_inst/in_read_enable_2_.fb.A0
+         1.2  fifo_colector_inst/in_empty_pmux_0.A0
+         0.8  fifo_colector_inst/iterator_RNI7U5I[1].A0
+
+fifo_colector_inst/iterator_RNI7U5I[1]
+   fifo_colector_inst/iterator_RNI7U5I[1].F0
+         1.0  fifo_colector_inst/data_buffer_3_0[9].LSR
+         0.8  fifo_colector_inst/data_buffer_3_0[11].LSR
+         0.7  fifo_colector_inst/data_buffer_3_0[13].LSR
+         0.5  fifo_colector_inst/data_buffer_3_0[15].LSR
+         0.4  fifo_colector_inst/data_buffer_3_0[17].LSR
+         0.7  fifo_colector_inst/data_buffer_3_0[19].LSR
+         0.7  fifo_colector_inst/data_buffer_3_0[21].LSR
+         0.4  fifo_colector_inst/data_buffer_3_0[23].LSR
+         0.4  fifo_colector_inst/data_buffer_3_0[25].LSR
+         0.4  fifo_colector_inst/data_buffer_3_0[27].LSR
+         0.7  fifo_colector_inst/data_buffer_3_0[29].LSR
+         1.0  fifo_colector_inst/data_buffer_3_0[31].LSR
+
+fifo_colector_inst/un5_in_read_enable
+   fifo_colector_inst/un5_in_read_enable.F0
+         0.0  fifo_colector_inst/un5_in_read_enable.DI0
+
+fifo_empty[0]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0
+         0.8  fifo_colector_inst/in_empty_pmux_0_RNIDRET.A0
+         0.8  fifo_colector_inst/in_empty_pmux_0.A1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.C0
+
+fifo_empty[1]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0
+         0.6  fifo_colector_inst/in_empty_pmux_0_RNIDRET.C0
+         0.6  fifo_colector_inst/in_empty_pmux_0.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.C0
+
+fifo_empty[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0
+         1.3  fifo_colector_inst/in_empty_pmux_0_RNIDRET.C1
+         1.3  fifo_colector_inst/in_empty_pmux_0.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0
+         1.1  fifo_colector_inst/iterator_RNI7U5I[1].C0
+
+fifo_rden_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.Q0
+         0.1  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D0
+         0.9  trb_adapter_inst/buf_rden_prev.M0
+         2.8  fifo_colector_inst/fifo40_inst/AND2_t19.A0
+         0.7  trb_adapter_inst/release_out.LSR
+         1.3  trb_adapter_inst_FEE_DATA_WRITE_OUTio.TXDATA0
+         0.8  fifo_rden_pad.PADDO
+
+fifo_read[0]
+   fifo_colector_inst/in_read_enable_1_.fb.Q0
+         0.3  fifo_colector_inst/in_read_enable_1_.fb.C0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0
+
+fifo_read[1]
+   fifo_colector_inst/in_read_enable_1_.fb.Q1
+         0.4  fifo_colector_inst/in_read_enable_1_.fb.A1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0
+
+fifo_read[2]
+   fifo_colector_inst/in_read_enable_2_.fb.Q0
+         0.1  fifo_colector_inst/in_read_enable_2_.fb.D0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.B0
+
+finished_c
+   trb_adapter_inst/release_out.Q0
+         0.5  trb_adapter_inst/finished_prev.M0
+         0.3  trb_adapter_inst/release_out.C0
+         0.8  finished_pad.PADDO
+         0.7  trb_adapter_inst_FEE_DATAFINISHED_OUTio.TXDATA0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready
+   genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.B0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3
+   genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[0]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].Q0
+         1.3  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[10]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[10].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].Q1
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[2]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[4]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[6]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[8]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9]
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.F0
+         0.2  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].CE
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].CE
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].CE
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[10].CE
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.A0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.C0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3
+   genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_41
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_42
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI51LH[7].B0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI51LH[7].F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.A1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.D1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.B1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.M0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI51LH[7].C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/m11_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/m11_i_1
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/m11_i_1_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/m15_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/m15_i_3
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.F0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/N_178_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced7_rising_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.LSR
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q1
+         0.2  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.Q0
+         1.2  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_out[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1].Q0
+         2.0  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_out[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1].Q1
+         1.8  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_out[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2].Q0
+         2.5  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         2.2  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.D0
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_valid_neg
+   genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid.Q0
+         1.4  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0_f5a
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1_f5b
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXB
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0_f5a
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1_f5b
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXB
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0_f5a
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1_f5b
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXB
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0_f5a
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1_f5b
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.OFX0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXB
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
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+
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
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+
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+
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+
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+
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+
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+
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+
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+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[0]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10].Q0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA10
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].Q1
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[2]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA2
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA3
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[4]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA4
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA5
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[6]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA6
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].Q1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA7
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[8]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA8
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.F0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].CE
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].CE
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].CE
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10].CE
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out_neg[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.5  fifo_colector_inst/data_buffer_3[0].D0
+         0.5  fifo_colector_inst/data_buffer_3[0].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.8  fifo_colector_inst/data_buffer_3_0[11].A0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.7  fifo_colector_inst/data_buffer_3_0[11].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.8  fifo_colector_inst/data_buffer_3_0[13].A0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3_0[13].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         1.0  fifo_colector_inst/data_buffer_3_0[15].A0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         1.0  fifo_colector_inst/data_buffer_3_0[15].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.6  fifo_colector_inst/data_buffer_3_0[17].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         0.7  fifo_colector_inst/data_buffer_3_0[17].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.6  fifo_colector_inst/data_buffer_3_0[19].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.7  fifo_colector_inst/data_buffer_3_0[19].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         0.7  fifo_colector_inst/data_buffer_3[1].D0
+         0.7  fifo_colector_inst/data_buffer_3[1].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.5  fifo_colector_inst/data_buffer_3_0[21].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.7  fifo_colector_inst/data_buffer_3_0[21].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.8  fifo_colector_inst/data_buffer_3_0[23].B0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.6  fifo_colector_inst/data_buffer_3_0[23].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.8  fifo_colector_inst/data_buffer_3[2].B0
+         0.8  fifo_colector_inst/data_buffer_3[2].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.7  fifo_colector_inst/data_buffer_3[3].D0
+         0.7  fifo_colector_inst/data_buffer_3[3].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.7  fifo_colector_inst/data_buffer_3[4].D0
+         0.7  fifo_colector_inst/data_buffer_3[4].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.7  fifo_colector_inst/data_buffer_3[5].B0
+         0.7  fifo_colector_inst/data_buffer_3[5].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.5  fifo_colector_inst/data_buffer_3[6].D0
+         0.5  fifo_colector_inst/data_buffer_3[6].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.7  fifo_colector_inst/data_buffer_3[7].D0
+         0.7  fifo_colector_inst/data_buffer_3[7].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         0.8  fifo_colector_inst/data_buffer_3_0[9].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.8  fifo_colector_inst/data_buffer_3_0[9].D1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready
+   genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.Q0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3
+   genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[0]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[10]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[10].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[2]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[4]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[6]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[8]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9]
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[10].CE
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3
+   genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_41
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_42
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7].B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7].F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.M0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7].D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/m11_i_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/m11_i_1
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/m11_i_1_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/m15_i_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/m15_i_3
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/N_180_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced7_rising_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.F0
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.LSR
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.D0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.OFX0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.Q0
+         1.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_out[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1].Q0
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_out[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1].Q1
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_out[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[2].Q0
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         1.9  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.D0
+         1.5  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_valid_neg
+   genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid.Q0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0_f5a
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1_f5b
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0_f5a
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1_f5b
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0_f5a
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1_f5b
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0_f5a
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1_f5b
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.OFX0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.F0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.M0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.M0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.A0
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+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
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+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.M0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
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+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.B0
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+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
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+
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+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
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+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.M1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.OFX1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.OFX1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.F0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.M0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.M0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.M0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.M0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.C1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.D0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.D1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[0]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[2]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA2
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA3
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[4]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA4
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[6]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[8]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.F0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10].CE
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out_neg[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.6  fifo_colector_inst/data_buffer_3_0[25].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.4  fifo_colector_inst/data_buffer_3[2].D0
+         0.4  fifo_colector_inst/data_buffer_3[2].D1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.8  fifo_colector_inst/data_buffer_3[3].B0
+         0.8  fifo_colector_inst/data_buffer_3[3].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.5  fifo_colector_inst/data_buffer_3[4].C0
+         0.5  fifo_colector_inst/data_buffer_3[4].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3[5].A0
+         0.8  fifo_colector_inst/data_buffer_3[5].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.6  fifo_colector_inst/data_buffer_3[6].C0
+         0.6  fifo_colector_inst/data_buffer_3[6].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.6  fifo_colector_inst/data_buffer_3[7].B0
+         0.6  fifo_colector_inst/data_buffer_3[7].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.9  fifo_colector_inst/data_buffer_3_0[9].B0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         0.8  fifo_colector_inst/data_buffer_3_0[9].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.5  fifo_colector_inst/data_buffer_3_0[11].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.8  fifo_colector_inst/data_buffer_3_0[11].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         0.8  fifo_colector_inst/data_buffer_3_0[25].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.6  fifo_colector_inst/data_buffer_3_0[13].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.6  fifo_colector_inst/data_buffer_3_0[13].D1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.8  fifo_colector_inst/data_buffer_3_0[15].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.8  fifo_colector_inst/data_buffer_3_0[15].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.6  fifo_colector_inst/data_buffer_3_0[27].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.8  fifo_colector_inst/data_buffer_3_0[27].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.6  fifo_colector_inst/data_buffer_3_0[29].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.7  fifo_colector_inst/data_buffer_3_0[29].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.8  fifo_colector_inst/data_buffer_3_0[31].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.7  fifo_colector_inst/data_buffer_3_0[31].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         0.6  fifo_colector_inst/data_buffer_3[0].C0
+         0.6  fifo_colector_inst/data_buffer_3[0].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.8  fifo_colector_inst/data_buffer_3[1].B0
+         0.8  fifo_colector_inst/data_buffer_3[1].B1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready
+   genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.C0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3
+   genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[0]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[10]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[10].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[2]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[4]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[6]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[8]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9]
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].CE
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].CE
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].CE
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[10].CE
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.A0
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_41
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_42
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7].A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7].F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.C1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.B1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.M0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7].D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/m11_i_1
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/m11_i_1_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/m11_i_1_0_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/m15_i_1
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/m15_i_3
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0_1
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/N_182_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced7_rising_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.LSR
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].Q1
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO_0.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_out[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1].Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_out[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1].Q1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_out[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[2].Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_valid_neg
+   genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0_f5a
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1_f5b
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.FXB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0_f5a
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1_f5b
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.FXB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0_f5a
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1_f5b
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.FXB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0_f5a
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1_f5b
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.OFX0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.FXB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
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+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.M0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.M0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.M0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.M0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
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+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.C1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.C1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.A1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
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+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_0.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.D1
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+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_0.C1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.C0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.C1
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+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
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+
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+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
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+
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+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
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+
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+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
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+
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+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
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+
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+
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.A0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.A0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.B0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5_1.OFX1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_7.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8_1.OFX1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_10.F0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         1.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.A1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.C0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.C1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.C1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.A1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_0.C1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_0.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.M1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         1.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15_1.OFX1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_17.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18_1.OFX1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_20.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[0]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA2
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA3
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[4]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA4
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[6]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[8]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.F0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10].CE
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/in_clk_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/out_buffered1[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out_neg[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].M1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         1.0  fifo_colector_inst/data_buffer_3_0[17].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.8  fifo_colector_inst/data_buffer_3_0[27].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.9  fifo_colector_inst/data_buffer_3_0[27].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.9  fifo_colector_inst/data_buffer_3_0[29].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.9  fifo_colector_inst/data_buffer_3_0[29].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.9  fifo_colector_inst/data_buffer_3_0[31].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.9  fifo_colector_inst/data_buffer_3_0[31].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.8  fifo_colector_inst/data_buffer_3[0].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         0.9  fifo_colector_inst/data_buffer_3[1].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.9  fifo_colector_inst/data_buffer_3[2].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.9  fifo_colector_inst/data_buffer_3[3].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         0.7  fifo_colector_inst/data_buffer_3_0[17].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.7  fifo_colector_inst/data_buffer_3[4].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.9  fifo_colector_inst/data_buffer_3[5].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.8  fifo_colector_inst/data_buffer_3[6].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.8  fifo_colector_inst/data_buffer_3[7].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.8  fifo_colector_inst/data_buffer_3_0[19].D0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.8  fifo_colector_inst/data_buffer_3_0[19].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.9  fifo_colector_inst/data_buffer_3_0[21].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.8  fifo_colector_inst/data_buffer_3_0[21].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.8  fifo_colector_inst/data_buffer_3_0[23].D0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         1.0  fifo_colector_inst/data_buffer_3_0[23].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         0.8  fifo_colector_inst/data_buffer_3_0[25].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3_0[25].D1
+
+hades_raw_out_c[0]
+   hades_tdc_channel_raw_out_inst_raw_outio[0].IOLDO
+         0.0  hades_raw_out_pad[0].IOLDO
+
+hades_raw_out_c[10]
+   hades_tdc_channel_raw_out_inst_raw_outio[10].IOLDO
+         0.0  hades_raw_out_pad[10].IOLDO
+
+hades_raw_out_c[11]
+   hades_tdc_channel_raw_out_inst_raw_outio[11].IOLDO
+         0.0  hades_raw_out_pad[11].IOLDO
+
+hades_raw_out_c[12]
+   hades_tdc_channel_raw_out_inst_raw_outio[12].IOLDO
+         0.0  hades_raw_out_pad[12].IOLDO
+
+hades_raw_out_c[13]
+   hades_tdc_channel_raw_out_inst_raw_outio[13].IOLDO
+         0.0  hades_raw_out_pad[13].IOLDO
+
+hades_raw_out_c[14]
+   hades_tdc_channel_raw_out_inst_raw_outio[14].IOLDO
+         0.0  hades_raw_out_pad[14].IOLDO
+
+hades_raw_out_c[15]
+   hades_tdc_channel_raw_out_inst_raw_outio[15].IOLDO
+         0.0  hades_raw_out_pad[15].IOLDO
+
+hades_raw_out_c[16]
+   hades_tdc_channel_raw_out_inst_raw_outio[16].IOLDO
+         0.0  hades_raw_out_pad[16].IOLDO
+
+hades_raw_out_c[17]
+   hades_tdc_channel_raw_out_inst_raw_outio[17].IOLDO
+         0.0  hades_raw_out_pad[17].IOLDO
+
+hades_raw_out_c[18]
+   hades_tdc_channel_raw_out_inst_raw_outio[18].IOLDO
+         0.0  hades_raw_out_pad[18].IOLDO
+
+hades_raw_out_c[19]
+   hades_tdc_channel_raw_out_inst_raw_outio[19].IOLDO
+         0.0  hades_raw_out_pad[19].IOLDO
+
+hades_raw_out_c[1]
+   hades_tdc_channel_raw_out_inst_raw_outio[1].IOLDO
+         0.0  hades_raw_out_pad[1].IOLDO
+
+hades_raw_out_c[20]
+   hades_tdc_channel_raw_out_inst_raw_outio[20].IOLDO
+         0.0  hades_raw_out_pad[20].IOLDO
+
+hades_raw_out_c[21]
+   hades_tdc_channel_raw_out_inst_raw_outio[21].IOLDO
+         0.0  hades_raw_out_pad[21].IOLDO
+
+hades_raw_out_c[22]
+   hades_tdc_channel_raw_out_inst_raw_outio[22].IOLDO
+         0.0  hades_raw_out_pad[22].IOLDO
+
+hades_raw_out_c[23]
+   hades_tdc_channel_raw_out_inst_raw_outio[23].IOLDO
+         0.0  hades_raw_out_pad[23].IOLDO
+
+hades_raw_out_c[2]
+   hades_tdc_channel_raw_out_inst_raw_outio[2].IOLDO
+         0.0  hades_raw_out_pad[2].IOLDO
+
+hades_raw_out_c[3]
+   hades_tdc_channel_raw_out_inst_raw_outio[3].IOLDO
+         0.0  hades_raw_out_pad[3].IOLDO
+
+hades_raw_out_c[4]
+   hades_tdc_channel_raw_out_inst_raw_outio[4].IOLDO
+         0.0  hades_raw_out_pad[4].IOLDO
+
+hades_raw_out_c[5]
+   hades_tdc_channel_raw_out_inst_raw_outio[5].IOLDO
+         0.0  hades_raw_out_pad[5].IOLDO
+
+hades_raw_out_c[6]
+   hades_tdc_channel_raw_out_inst_raw_outio[6].IOLDO
+         0.0  hades_raw_out_pad[6].IOLDO
+
+hades_raw_out_c[7]
+   hades_tdc_channel_raw_out_inst_raw_outio[7].IOLDO
+         0.0  hades_raw_out_pad[7].IOLDO
+
+hades_raw_out_c[8]
+   hades_tdc_channel_raw_out_inst_raw_outio[8].IOLDO
+         0.0  hades_raw_out_pad[8].IOLDO
+
+hades_raw_out_c[9]
+   hades_tdc_channel_raw_out_inst_raw_outio[9].IOLDO
+         0.0  hades_raw_out_pad[9].IOLDO
+
+hades_tdc_channel_raw_out_inst.buf_negative[0]
+   hades_tdc_channel_raw_out_inst/buf_negative[1].Q0
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[12].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[10]
+   hades_tdc_channel_raw_out_inst/buf_negative[11].Q0
+         0.8  hades_tdc_channel_raw_out_inst_raw_outio[22].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[11]
+   hades_tdc_channel_raw_out_inst/buf_negative[11].Q1
+         0.8  hades_tdc_channel_raw_out_inst_raw_outio[23].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[1]
+   hades_tdc_channel_raw_out_inst/buf_negative[1].Q1
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[13].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[2]
+   hades_tdc_channel_raw_out_inst/buf_negative[3].Q0
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[14].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[3]
+   hades_tdc_channel_raw_out_inst/buf_negative[3].Q1
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[15].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[4]
+   hades_tdc_channel_raw_out_inst/buf_negative[5].Q0
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[16].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[5]
+   hades_tdc_channel_raw_out_inst/buf_negative[5].Q1
+         0.8  hades_tdc_channel_raw_out_inst_raw_outio[17].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[6]
+   hades_tdc_channel_raw_out_inst/buf_negative[7].Q0
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[18].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[7]
+   hades_tdc_channel_raw_out_inst/buf_negative[7].Q1
+         0.3  hades_tdc_channel_raw_out_inst_raw_outio[19].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[8]
+   hades_tdc_channel_raw_out_inst/buf_negative[9].Q0
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[20].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative[9]
+   hades_tdc_channel_raw_out_inst/buf_negative[9].Q1
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[21].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_negative_ready10
+   hades_tdc_channel_raw_out_inst/buf_negative_ready10.F0
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[23].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[22].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[21].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[20].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[19].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[18].CE
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[17].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[16].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[15].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[14].CE
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[13].CE
+         0.8  hades_tdc_channel_raw_out_inst_raw_outio[12].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[11].CE
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[10].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[9].CE
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[8].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[7].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[6].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[5].CE
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[4].CE
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[3].CE
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[2].CE
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[1].CE
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[0].CE
+
+hades_tdc_channel_raw_out_inst.buf_positive[0]
+   hades_tdc_channel_raw_out_inst/buf_positive[1].Q0
+         0.8  hades_tdc_channel_raw_out_inst_raw_outio[0].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[10]
+   hades_tdc_channel_raw_out_inst/buf_positive[11].Q0
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[10].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[11]
+   hades_tdc_channel_raw_out_inst/buf_positive[11].Q1
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[11].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[1]
+   hades_tdc_channel_raw_out_inst/buf_positive[1].Q1
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[1].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[2]
+   hades_tdc_channel_raw_out_inst/buf_positive[3].Q0
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[2].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[3]
+   hades_tdc_channel_raw_out_inst/buf_positive[3].Q1
+         0.3  hades_tdc_channel_raw_out_inst_raw_outio[3].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[4]
+   hades_tdc_channel_raw_out_inst/buf_positive[5].Q0
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[4].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[5]
+   hades_tdc_channel_raw_out_inst/buf_positive[5].Q1
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[5].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[6]
+   hades_tdc_channel_raw_out_inst/buf_positive[7].Q0
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[6].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[7]
+   hades_tdc_channel_raw_out_inst/buf_positive[7].Q1
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[7].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[8]
+   hades_tdc_channel_raw_out_inst/buf_positive[9].Q0
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[8].TXDATA0
+
+hades_tdc_channel_raw_out_inst.buf_positive[9]
+   hades_tdc_channel_raw_out_inst/buf_positive[9].Q1
+         0.5  hades_tdc_channel_raw_out_inst_raw_outio[9].TXDATA0
+
+hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1[0].in_clk_synced[4]
+   hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1[0].in_clk_syncedio[4].INFF
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4].M1
+
+hades_tdc_channel_raw_out_inst/N_10_i
+   hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.F0
+         0.0  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.DI0
+
+hades_tdc_channel_raw_out_inst/N_12_i_0
+   hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.F0
+         0.0  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.DI0
+
+hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa
+   hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa_0_a2.F0
+         0.6  hades_tdc_channel_raw_out_inst/buf_negative[1].CE
+         0.6  hades_tdc_channel_raw_out_inst/buf_negative[3].CE
+         1.3  hades_tdc_channel_raw_out_inst/buf_negative[5].CE
+         1.1  hades_tdc_channel_raw_out_inst/buf_negative[7].CE
+         1.0  hades_tdc_channel_raw_out_inst/buf_negative[9].CE
+         1.3  hades_tdc_channel_raw_out_inst/buf_negative[11].CE
+
+hades_tdc_channel_raw_out_inst/buf_negative_ready
+   hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.Q0
+         0.3  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.C0
+         0.6  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.A0
+         0.7  hades_tdc_channel_raw_out_inst/buf_negative_ready10.A0
+
+hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa
+   hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa_0_a2.F0
+         0.9  hades_tdc_channel_raw_out_inst/buf_positive[1].CE
+         0.8  hades_tdc_channel_raw_out_inst/buf_positive[3].CE
+         1.2  hades_tdc_channel_raw_out_inst/buf_positive[5].CE
+         1.6  hades_tdc_channel_raw_out_inst/buf_positive[7].CE
+         1.2  hades_tdc_channel_raw_out_inst/buf_positive[9].CE
+         1.3  hades_tdc_channel_raw_out_inst/buf_positive[11].CE
+
+hades_tdc_channel_raw_out_inst/buf_positive_ready
+   hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.Q0
+         0.6  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.B0
+         0.1  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.D0
+         0.7  hades_tdc_channel_raw_out_inst/buf_negative_ready10.B0
+
+hades_tdc_channel_raw_out_inst/dec_inst/N_161
+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.C1
+
+hades_tdc_channel_raw_out_inst/dec_inst/N_162
+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.B0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q1
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q1
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q0
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+
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+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7]
+   hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q1
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNI5EBK[7].B0
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_rising_i
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNI5EBK[7].F0
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+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.LSR
+
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+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.C0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.A0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1
+
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+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q0
+         0.9  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0
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+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q1
+         0.7  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.B1
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0
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+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.D1
+         0.7  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0
+         0.7  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1
+         0.7  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0
+         0.8  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.A1
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+         0.7  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q0
+         0.8  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0
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+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+
+hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+   hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q1
+         0.2  hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNI5EBK[7].D0
+
+hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1
+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0
+
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+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0
+
+hades_tdc_channel_raw_out_inst/dec_inst/m11_i_2
+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0
+         0.0  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0
+
+hades_tdc_channel_raw_out_inst/dec_inst/m15_i_2
+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0
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+
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+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0
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+
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+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0
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+
+hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1]
+   hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/out[1].M1
+
+hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2]
+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/out[2].M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0_2
+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0
+         0.0  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0
+
+hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0
+   hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.F0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.M0
+
+hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_i
+   hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.OFX0
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+
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+
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+
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/N_9
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2]
+   hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].Q0
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4]
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+
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+
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+
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced7_rising_i
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+
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+
+hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1]
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+hades_tdc_channel_raw_out_inst/decoder_out[1]
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+         0.6  hades_tdc_channel_raw_out_inst/buf_positive[1].M1
+
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+   hades_tdc_channel_raw_out_inst/dec_inst/out[2].Q0
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+
+hades_tdc_channel_raw_out_inst/decoder_out_neg[0]
+   hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q0
+         0.3  hades_tdc_channel_raw_out_inst/buf_negative[1].M0
+
+hades_tdc_channel_raw_out_inst/decoder_out_neg[1]
+   hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q1
+         0.4  hades_tdc_channel_raw_out_inst/buf_negative[1].M1
+
+hades_tdc_channel_raw_out_inst/decoder_out_neg[2]
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+         0.3  hades_tdc_channel_raw_out_inst/buf_negative[3].M0
+
+hades_tdc_channel_raw_out_inst/decoder_valid
+   hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa_0_a2.Q0
+         0.5  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.B0
+         0.3  hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa_0_a2.C0
+
+hades_tdc_channel_raw_out_inst/decoder_valid_neg
+   hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa_0_a2.Q0
+         0.4  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.D0
+         0.3  hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa_0_a2.C0
+
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+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[3]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[4]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[5]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[6]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[7]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[3]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[7]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[3]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[5]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[6]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[7]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[0]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[2]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[3]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4].Q1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.4  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[7]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out[0]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.5  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out[1]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out[2]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out[3]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out[4]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out[5]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out[6]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out[7]
+   hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.3  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[0]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[1]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[2]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[3]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[4]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[5]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.4  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M1
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[6]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.6  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M0
+
+hades_tdc_channel_raw_out_inst/tdc_out_neg[7]
+   hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.3  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M1
+
+hades_trig_c
+   hades_trig_pad.PADDI
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         0.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         0.9  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         0.9  hades_trig_pad_RNIE1B4.A0
+         0.0  hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1[0].in_clk_syncedio[4].DI
+
+hades_trig_c_i
+   hades_trig_pad_RNIE1B4.F0
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.4  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.6  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.3  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.5  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+last_buf_empty_c
+   fifo_colector_inst/fifo40_inst/FF_1.Q0
+         2.4  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.C0
+         0.4  fifo_colector_inst/fifo40_inst/AND2_t19.C0
+         2.7  last_buf_empty_pad.PADDO
+
+pll0inst/GND
+   pll0inst/GND.F0
+         0.5  pll0inst/PLLInst_0.STDBY
+
+pll_clks[0]
+   pll0inst/PLLInst_0.CLKOP
+         1.7  coarse[8].CLK
+         1.7  coarse[2].CLK
+         1.7  coarse[4].CLK
+         1.7  coarse[6].CLK
+         1.7  coarse_RNO[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4].CLK
+         1.7  hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1[0].in_clk_syncedio[4].CLK
+         1.7  pll0inst/PLLInst_0.CLKFB
+
+pll_clks[1]
+   pll0inst/PLLInst_0.CLKOS
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+
+pll_clks[2]
+   pll0inst/PLLInst_0.CLKOS2
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+
+pll_clks[3]
+   pll0inst/PLLInst_0.CLKOS3
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_100.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_98.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_96.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_94.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_92.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_0.CLK
+         1.7  fifo_colector_inst/in_empty_pmux_0_RNIDRET.CLK
+         1.7  fifo_colector_inst/data_buffer_3[0].CLK
+         1.7  fifo_colector_inst/data_buffer_3[1].CLK
+         1.7  fifo_colector_inst/data_buffer_3[2].CLK
+         1.7  fifo_colector_inst/data_buffer_3[3].CLK
+         1.7  fifo_colector_inst/data_buffer_3[4].CLK
+         1.7  fifo_colector_inst/data_buffer_3[5].CLK
+         1.7  fifo_colector_inst/data_buffer_3[6].CLK
+         1.7  fifo_colector_inst/data_buffer_3[7].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[9].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[11].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[13].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[15].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[17].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[19].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[21].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[23].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[25].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[27].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[29].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[31].CLK
+         1.7  fifo_colector_inst/data_buffer[33].CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_30.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_28.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_26.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_24.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_22.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_8.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_6.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_4.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_2.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t12.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t9.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_80.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_78.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_76.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_74.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_72.CLK
+         1.7  fifo_colector_inst/un5_in_read_enable.CLK
+         1.7  fifo_colector_inst/in_read_enable_1_.fb.CLK
+         1.7  fifo_colector_inst/in_read_enable_2_.fb.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[9].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive[10].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_neg_inst/valid.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[9].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive[10].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_neg_inst/valid.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[9].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive[10].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_neg_inst/valid.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[9].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative[11].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[9].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive[11].CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/out[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_inst/out[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.CLK
+         1.7  fifo_colector_inst/N_16_i.CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa_0_a2.CLK
+         1.7  hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa_0_a2.CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[23].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[22].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[21].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[20].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[19].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[18].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[17].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[16].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[15].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[14].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[13].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[12].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[11].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[10].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[9].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[8].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[7].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[6].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[5].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[4].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[3].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[2].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[1].CLK
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[0].CLK
+         1.7  reset_dl_0io[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKA
+
+rd_clk_c
+   rd_clk_pad.PADDI
+         1.7  fifo_colector_inst/fifo40_inst/FF_70.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_68.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_66.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_64.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_62.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_1.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t7.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t5.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t3.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t1.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_50.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_48.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_46.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_44.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_42.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_40.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_38.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_36.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_34.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_32.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_20.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_18.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_12.CLK
+         1.7  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.CLK
+         1.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].CLK
+         1.7  trb_adapter_inst/buf_rden_prev.CLK
+         1.7  trb_adapter_inst/finished_prev.CLK
+         1.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].CLK
+         1.7  trb_adapter_inst/release_out.CLK
+         1.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATA_WRITE_OUTio.CLK
+         1.8  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].CLK
+         1.8  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].CLK
+         1.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKB
+
+release_out_c
+   trb_adapter_inst/release_out.F0
+         0.5  release_out_pad.PADDO
+         0.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.TXDATA0
+
+reset_dc_c
+   reset_dc_pad.PADDI
+         0.0  reset_dl_0io[1].DI
+
+reset_dl[1]
+   reset_dl_0io[1].INFF
+         0.4  fifo_colector_inst/N_16_i.M0
+
+reset_dl[2]
+   fifo_colector_inst/N_16_i.Q0
+         2.2  coarse[8].LSR
+         2.0  coarse[2].LSR
+         2.0  coarse[4].LSR
+         2.0  coarse[6].LSR
+         1.7  coarse_RNO[0].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/buf_negative_ready_3.CE
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_ready_3.CE
+         2.9  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[1].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[3].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[5].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[7].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9].LSR
+         2.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[10].LSR
+         2.8  genblk1[0].tdc_channel_fifo_out_inst/fifo_wrenc.LSR
+         3.2  genblk1[1].tdc_channel_fifo_out_inst/buf_negative_ready_3.CE
+         3.2  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_ready_3.CE
+         2.6  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[1].LSR
+         3.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[3].LSR
+         2.5  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[5].LSR
+         3.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[7].LSR
+         2.5  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9].LSR
+         3.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[10].LSR
+         3.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_wrenc.LSR
+         2.4  genblk1[2].tdc_channel_fifo_out_inst/buf_negative_ready_3.CE
+         2.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_ready_3.CE
+         2.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[1].LSR
+         2.6  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[3].LSR
+         2.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[5].LSR
+         2.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[7].LSR
+         2.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9].LSR
+         2.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[10].LSR
+         2.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_wrenc.LSR
+         1.0  hades_tdc_channel_raw_out_inst/buf_negative_ready_RNO.CE
+         1.0  hades_tdc_channel_raw_out_inst/buf_positive_ready_RNO.CE
+         2.4  genblk1[2].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.A0
+         2.7  genblk1[1].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.A0
+         3.3  genblk1[0].tdc_channel_fifo_out_inst/buf_positive_0_sqmuxa.C0
+         0.2  fifo_colector_inst/N_16_i.D0
+         1.0  hades_tdc_channel_raw_out_inst/buf_negative_0_sqmuxa_0_a2.A0
+         1.3  hades_tdc_channel_raw_out_inst/buf_positive_0_sqmuxa_0_a2.B0
+         1.5  hades_tdc_channel_raw_out_inst_raw_outio[23].LSR
+         1.5  hades_tdc_channel_raw_out_inst_raw_outio[22].LSR
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[21].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[20].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[19].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[18].LSR
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[17].LSR
+         1.5  hades_tdc_channel_raw_out_inst_raw_outio[16].LSR
+         0.9  hades_tdc_channel_raw_out_inst_raw_outio[15].LSR
+         0.9  hades_tdc_channel_raw_out_inst_raw_outio[14].LSR
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[13].LSR
+         0.7  hades_tdc_channel_raw_out_inst_raw_outio[12].LSR
+         1.2  hades_tdc_channel_raw_out_inst_raw_outio[11].LSR
+         1.7  hades_tdc_channel_raw_out_inst_raw_outio[10].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[9].LSR
+         1.1  hades_tdc_channel_raw_out_inst_raw_outio[8].LSR
+         1.5  hades_tdc_channel_raw_out_inst_raw_outio[7].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[6].LSR
+         1.3  hades_tdc_channel_raw_out_inst_raw_outio[5].LSR
+         1.2  hades_tdc_channel_raw_out_inst_raw_outio[4].LSR
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[3].LSR
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[2].LSR
+         0.6  hades_tdc_channel_raw_out_inst_raw_outio[1].LSR
+         1.0  hades_tdc_channel_raw_out_inst_raw_outio[0].LSR
+         0.9  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.LSR
+         0.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.LSR
+         0.7  trb_adapter_inst_FEE_DATA_WRITE_OUTio.LSR
+
+trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0]
+   trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].INFF
+         0.9  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].M0
+
+trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]
+   trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].INFF
+         0.6  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q0
+         0.5  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M1
+         0.5  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].B0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl_RNIRTQN[2].D0
+
+trb_adapter_inst/N_7_i
+   trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F0
+         0.0  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.DI0
+
+trb_adapter_inst/buf_rden_prev
+   trb_adapter_inst/buf_rden_prev.Q0
+         0.3  trb_adapter_inst/release_out.M0
+
+trb_adapter_inst/finished_prev
+   trb_adapter_inst/finished_prev.Q0
+         0.5  trb_adapter_inst/release_out.A0
+
+trig_c[0]
+   trig_pad[0].PADDI
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0
+         1.1  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         0.6  trig_pad_RNII4FF[0].D0
+
+trig_c[1]
+   trig_pad[1].PADDI
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         2.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         1.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         2.2  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1
+         2.1  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         1.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         1.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         1.5  trig_pad_RNIJ5FF[1].D0
+
+trig_c[2]
+   trig_pad[2].PADDI
+         2.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         2.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         2.1  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         2.2  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         2.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1
+         2.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         2.2  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         2.2  genblk1[2].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         1.8  trig_pad_RNIK6FF[2].D0
+
+trig_c_i[0]
+   trig_pad_RNII4FF[0].F0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[1]
+   trig_pad_RNIJ5FF[1].F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
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+         0.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[2]
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+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
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diff --git a/impl1/._Real_._Math_.vhd b/impl1/._Real_._Math_.vhd
new file mode 100644
index 0000000..ad185b2
--- /dev/null
+++ b/impl1/._Real_._Math_.vhd
@@ -0,0 +1,2574 @@
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, 
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package defines a standard for designers to use in
+--              describing VHDL models that make use of common REAL constants
+--              and common REAL elementary mathematical functions.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076-
+--              1993.
+--
+-- Notes:
+--              No declarations or definitions shall be included in, or
+--              excluded from, this package.
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to provide a guideline for implementations to
+--              verify their implementation of MATH_REAL.  Tool developers may
+--              choose to implement the package body in the most efficient
+--              manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package MATH_REAL is
+    constant CopyRightNotice: STRING
+      := "Copyright 1996 IEEE. All rights reserved.";
+
+    --
+    -- Constant Definitions
+    --
+    constant  MATH_E : REAL := 2.71828_18284_59045_23536;
+                                                      -- Value of e
+    constant  MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
+                                                      -- Value of 1/e
+    constant  MATH_PI : REAL := 3.14159_26535_89793_23846;
+                                                      -- Value of pi
+    constant  MATH_2_PI : REAL := 6.28318_53071_79586_47693;
+                                                      -- Value of 2*pi
+    constant  MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
+                                                      -- Value of 1/pi
+    constant  MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
+                                                      -- Value of pi/2
+    constant  MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
+                                                      -- Value of pi/3
+    constant  MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
+                                                      -- Value of pi/4
+    constant  MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
+                                                      -- Value 3*pi/2
+    constant  MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
+                                                      -- Natural log of 2
+    constant  MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
+                                                      -- Natural log of 10
+    constant  MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
+                                                      -- Log base 2 of e
+    constant  MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
+                                                      -- Log base 10 of e
+    constant  MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
+                                                      -- square root of 2
+    constant  MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
+                                                      -- square root of 1/2
+    constant  MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
+                                                      -- square root of pi
+    constant  MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
+                                     -- Conversion factor from degree to radian
+    constant  MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
+                                     -- Conversion factor from radian to degree
+
+    --
+    -- Function Declarations
+    --
+    function SIGN (X: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIGN(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function CEIL (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns smallest INTEGER value (as REAL) not less than X
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CEIL(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function FLOOR (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns largest INTEGER value (as REAL) not greater than X
+        -- Special values:
+        --         FLOOR(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         FLOOR(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function ROUND (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Rounds X to the nearest integer value (as real). If X is
+        --         halfway between two integers, rounding is away from 0.0
+        -- Special values:
+        --         ROUND(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ROUND(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function TRUNC (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Truncates X towards 0.0 and returns truncated value
+        -- Special values:
+        --         TRUNC(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         TRUNC(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function "MOD" (X, Y: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns floating point modulus of X/Y, with the same sign as
+        --         Y, and absolute value less than the absolute value of Y, and
+        --         for some INTEGER value N the result satisfies the relation
+        --         X = Y*N + MOD(X,Y)
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL; Y in REAL and Y /= 0.0
+        -- Error conditions:
+        --         Error if Y = 0.0
+        -- Range:
+        --         ABS(MOD(X,Y)) < ABS(Y)
+        -- Notes:
+        --         None
+
+    function REALMAX (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically larger of X and Y
+        -- Special values:
+        --         REALMAX(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMAX(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    function REALMIN (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically smaller of X and Y
+        -- Special values:
+        --         REALMIN(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMIN(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
+        -- Purpose:
+        --         Returns, in X, a pseudo-random number with uniform
+        --         distribution in the open interval (0.0, 1.0).
+        -- Special values:
+        --         None
+        -- Domain:
+        --         1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
+        -- Error conditions:
+        --         Error if SEED1 or SEED2 outside of valid domain
+        -- Range:
+        --         0.0 < X < 1.0
+        -- Notes:
+        --         a) The semantics for this function are described by the
+        --            algorithm published by Pierre L'Ecuyer in "Communications
+        --            of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
+        --            The algorithm is based on the combination of two
+        --            multiplicative linear congruential generators for 32-bit
+        --            platforms.
+        --
+        --         b) Before the first call to UNIFORM, the seed values
+        --            (SEED1, SEED2) have to be initialized to values in the range
+        --            [1, 2147483562] and [1, 2147483398] respectively.  The
+        --            seed values are modified after each call to UNIFORM.
+        --
+        --         c) This random number generator is portable for 32-bit
+        --            computers, and it has a period of ~2.30584*(10**18) for each
+        --            set of seed values.
+        --
+        --         d) For information on spectral tests for the algorithm, refer
+        --            to the L'Ecuyer article.
+
+    function SQRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns square root of X
+        -- Special values:
+        --         SQRT(0.0) = 0.0
+        --         SQRT(1.0) = 1.0
+        -- Domain:
+        --         X >= 0.0
+        -- Error conditions:
+        --         Error if X < 0.0
+        -- Range:
+        --         SQRT(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of SQRT is
+        --            approximately given by:
+        --                SQRT(X) <= SQRT(REAL'HIGH)
+
+    function CBRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cube root of X
+        -- Special values:
+        --         CBRT(0.0) = 0.0
+        --         CBRT(1.0) = 1.0
+        --         CBRT(-1.0) = -1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CBRT(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of CBRT is approximately given by:
+        --                ABS(CBRT(X)) <= CBRT(REAL'HIGH)
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0
+        --         0**Y = 0.0; Y > 0.0
+        --         X**1.0 = REAL(X); X >= 0
+        --         1**Y = 1.0
+        -- Domain:
+        --         X > 0
+        --         X = 0 for Y > 0.0
+        --         X < 0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0 and Y /= 0.0
+        --         Error if X = 0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function "**" (X : in REAL; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0.0
+        --         0.0**Y = 0.0; Y > 0.0
+        --         X**1.0 = X; X >= 0.0
+        --         1.0**Y = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         X = 0.0 for Y > 0.0
+        --         X < 0.0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0.0 and Y /= 0.0
+        --         Error if X = 0.0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function EXP (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns e**X; where e = MATH_E
+        -- Special values:
+        --         EXP(0.0) = 1.0
+        --         EXP(1.0) = MATH_E
+        --         EXP(-1.0) = MATH_1_OVER_E
+        --         EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
+        -- Domain:
+        --         X in REAL such that EXP(X) <= REAL'HIGH
+        -- Error conditions:
+        --         Error if X > LOG(REAL'HIGH)
+        -- Range:
+        --         EXP(X) >= 0.0
+        -- Notes:
+        --         a) The usable domain of EXP is approximately given by:
+        --                X <= LOG(REAL'HIGH)
+
+    function LOG (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns natural logarithm of X
+        -- Special values:
+        --         LOG(1.0) = 0.0
+        --         LOG(MATH_E) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG is approximately given by:
+        --                LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
+
+    function LOG2 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 2 of X
+        -- Special values:
+        --         LOG2(1.0) = 0.0
+        --         LOG2(2.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG2(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG2 is approximately given by:
+        --                LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
+
+    function LOG10 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 10 of X
+        -- Special values:
+        --         LOG10(1.0) = 0.0
+        --         LOG10(10.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG10(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG10 is approximately given by:
+        --                LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL;
+        -- Purpose:
+        --         Returns logarithm base BASE of X
+        -- Special values:
+        --         LOG(1.0, BASE) = 0.0
+        --         LOG(BASE, BASE) = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         BASE > 0.0
+        --         BASE /= 1.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        --         Error if BASE <= 0.0
+        --         Error if BASE = 1.0
+        -- Range:
+        --         LOG(X, BASE) is mathematically unbounded
+        -- Notes:
+        --         a) When BASE > 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
+        --         b) When 0.0 < BASE < 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
+
+    function  SIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns sine of X; X in radians
+        -- Special values:
+        --         SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        --         SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        --         SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIN(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  COS ( X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cosine of X; X in radians
+        -- Special values:
+        --         COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                            INTEGER
+        --         COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
+        --         COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(COS(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  TAN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns tangent of X; X in radians
+        -- Special values:
+        --         TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL and
+        --         X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
+        -- Error conditions:
+        --         Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
+        --                                                           INTEGER
+        -- Range:
+        --         TAN(X) is mathematically unbounded
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  ARCSIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse sine of X
+        -- Special values:
+        --         ARCSIN(0.0) = 0.0
+        --         ARCSIN(1.0) = MATH_PI_OVER_2
+        --         ARCSIN(-1.0) = -MATH_PI_OVER_2
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         ABS(ARCSIN(X) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCCOS (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse cosine of X
+        -- Special values:
+        --         ARCCOS(1.0) = 0.0
+        --         ARCCOS(0.0) = MATH_PI_OVER_2
+        --         ARCCOS(-1.0) = MATH_PI
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         0.0 <= ARCCOS(X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the value of the angle in radians of the point
+        --        (1.0, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0) = 0.0
+        -- Domain:
+        --         Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL; X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the principal value of the angle in radians of
+        --         the point (X, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0, X) = 0.0 if X > 0.0
+        --         ARCTAN(0.0, X) = MATH_PI if X < 0.0
+        --         ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
+        --         ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
+        -- Domain:
+        --         Y in REAL
+        --         X in REAL, X /= 0.0 when Y = 0.0
+        -- Error conditions:
+        --         Error if X = 0.0 and Y = 0.0
+        -- Range:
+        --         -MATH_PI < ARCTAN(Y,X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function SINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic sine of X
+        -- Special values:
+        --         SINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         SINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The usable domain of SINH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+
+    function COSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic cosine of X
+        -- Special values:
+        --         COSH(0.0) = 1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         COSH(X) >= 1.0
+        -- Notes:
+        --         a) The usable domain of COSH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+    function TANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic tangent of X
+        -- Special values:
+        --         TANH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(TANH(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function ARCSINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic sine of X
+        -- Special values:
+        --         ARCSINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ARCSINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCSINH is approximately given by:
+        --                ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
+
+    function ARCCOSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic cosine of X
+        -- Special values:
+        --         ARCCOSH(1.0) = 0.0
+        -- Domain:
+        --         X >= 1.0
+        -- Error conditions:
+        --         Error if X < 1.0
+        -- Range:
+        --         ARCCOSH(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of ARCCOSH is
+        --            approximately given by:   ARCCOSH(X) <= LOG(REAL'HIGH)
+
+    function ARCTANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic tangent of X
+        -- Special values:
+        --         ARCTANH(0.0) = 0.0
+        -- Domain:
+        --         ABS(X) < 1.0
+        -- Error conditions:
+        --         Error if ABS(X) >= 1.0
+        -- Range:
+        --         ARCTANH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCTANH is approximately given by:
+        --                ABS(ARCTANH(X)) < LOG(REAL'HIGH)
+
+end  MATH_REAL;
+
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+
+-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package body is a nonnormative implementation of the 
+--              functionality defined in the MATH_REAL package declaration.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076
+--              -1993.
+--
+-- Notes:
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to clarify such semantics and provide a
+--              guideline for implementations to verify their implementation
+--              of MATH_REAL.  Tool developers may choose to implement
+--              the package body in the most efficient manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package body MATH_REAL is
+
+    --
+    -- Local Constants for Use in the Package Body Only
+    --
+    constant  MATH_E_P2 :  REAL := 7.38905_60989_30650;   -- e**2
+    constant  MATH_E_P10 :  REAL := 22026.46579_48067_17; -- e**10
+    constant  MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
+    constant  MAX_ITER:  INTEGER := 27;  -- Maximum precision factor for cordic
+    constant  MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
+    constant  BASE_EPS: REAL := 0.00001;  -- Factor for convergence criteria
+    constant  KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
+
+    --
+    -- Local Type Declarations for Cordic Operations
+    --
+    type REAL_VECTOR is array (NATURAL range <>) of REAL;
+    type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
+    subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
+    subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
+    subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
+    subtype QUADRANT is INTEGER range 0 to 3;
+    type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
+
+    --
+    -- Auxiliary Functions for Cordic Algorithms
+    --
+    function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
+                NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
+        -- Description:
+        --        Returns power of two for a vector of values
+        -- Notes:
+        --        None
+        --
+        variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
+        variable TEMP : REAL := INITIAL_VALUE;
+        variable FLAG : BOOLEAN := TRUE;
+    begin
+              for I in 0 to NUMBER_OF_VALUES loop
+                 V(I) := TEMP;
+                 for P in D'RANGE loop
+                            if I = D(P) then
+                                FLAG := FALSE;
+                                exit;
+                            end if;
+                 end loop;
+                 if FLAG then
+                            TEMP := TEMP/2.0;
+                 end if;
+                 FLAG := TRUE;
+              end loop;
+              return V;
+    end POWER_OF_2_SERIES;
+
+
+    constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
+                                               NATURAL_VECTOR'(100, 90),1.0,
+                                                                  MAX_ITER);
+
+    constant EPSILON : REAL_VECTOR_N := (
+                                        7.8539816339744827e-01,
+                                        4.6364760900080606e-01,
+                                        2.4497866312686413e-01,
+                                        1.2435499454676144e-01,
+                                        6.2418809995957351e-02,
+                                        3.1239833430268277e-02,
+                                        1.5623728620476830e-02,
+                                        7.8123410601011116e-03,
+                                        3.9062301319669717e-03,
+                                        1.9531225164788189e-03,
+                                        9.7656218955931937e-04,
+                                        4.8828121119489829e-04,
+                                        2.4414062014936175e-04,
+                                        1.2207031189367021e-04,
+                                        6.1035156174208768e-05,
+                                        3.0517578115526093e-05,
+                                        1.5258789061315760e-05,
+                                        7.6293945311019699e-06,
+                                        3.8146972656064960e-06,
+                                        1.9073486328101870e-06,
+                                        9.5367431640596080e-07,
+                                        4.7683715820308876e-07,
+                                        2.3841857910155801e-07,
+                                        1.1920928955078067e-07,
+                                        5.9604644775390553e-08,
+                                        2.9802322387695303e-08,
+                                        1.4901161193847654e-08,
+                                        7.4505805969238281e-09
+                                       );
+
+    function CORDIC ( X0 : in REAL;
+                      Y0 : in REAL;
+                      Z0 : in REAL;
+                      N : in NATURAL;                 --  Precision factor
+            CORDIC_MODE : in CORDIC_MODE_TYPE         --  Rotation (Z -> 0)
+                                                      --  or vectoring (Y -> 0)
+                    ) return REAL_ARR_3 is
+        -- Description:
+        --        Compute cordic values
+        -- Notes:
+        --         None
+             variable X : REAL := X0;
+             variable Y : REAL := Y0;
+             variable Z : REAL := Z0;
+             variable X_TEMP : REAL;
+    begin
+       if CORDIC_MODE = ROTATION then
+           for K in 0 to N loop
+                      X_TEMP := X;
+                      if ( Z >= 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                      else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                      end if;
+            end loop;
+        else
+            for K in 0 to N loop
+                    X_TEMP := X;
+                    if ( Y < 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                    else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                    end if;
+            end loop;
+        end if;
+        return REAL_ARR_3'(X, Y, Z);
+    end CORDIC;
+
+    --
+    -- Bodies for Global Mathematical Functions Start Here
+    --
+    function SIGN (X: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        None
+    begin
+           if  ( X > 0.0 )  then
+                return 1.0;
+           elsif ( X < 0.0 )  then
+                return -1.0;
+           else
+                return 0.0;
+           end if;
+    end SIGN;
+
+    function CEIL (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is X <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+         if ABS(X) >= LARGE then
+               return X;
+         end if;
+
+         RD := REAL ( INTEGER(X));
+         if RD = X then
+            return X;
+         end if;
+
+            if X > 0.0 then
+                       if RD >= X then
+                                  return RD;
+                       else
+                                  return RD + 1.0;
+                       end if;
+            elsif  X = 0.0  then
+                return 0.0;
+            else
+                       if RD <= X then
+                                  return RD + 1.0;
+                       else
+                                  return RD;
+                       end if;
+            end if;
+    end CEIL;
+
+    function FLOOR (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is ABS(X) <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+        if ABS( X ) >= LARGE then
+                    return X;
+        end if;
+
+        RD := REAL ( INTEGER(X));
+        if RD = X then
+                return X;
+        end if;
+
+        if X > 0.0 then
+                      if RD <= X then
+                                  return RD;
+                       else
+                                  return RD - 1.0;
+                       end if;
+        elsif  X = 0.0  then
+                return 0.0;
+        else
+                   if RD >= X then
+                                  return RD - 1.0;
+                   else
+                                  return RD;
+                   end if;
+        end if;
+    end FLOOR;
+
+    function ROUND (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X + 0.5) if X > 0
+        --         c) Returns CEIL(X - 0.5) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X + 0.5);
+           elsif  X < 0.0  then
+                return CEIL( X - 0.5);
+           else
+                return 0.0;
+           end if;
+    end ROUND;
+
+    function TRUNC (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X) if X > 0
+        --         c) Returns CEIL(X) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X);
+           elsif  X < 0.0  then
+                return CEIL( X);
+           else
+                return 0.0;
+           end if;
+    end TRUNC;
+
+
+
+
+    function "MOD" (X, Y: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+
+        variable XNEGATIVE : BOOLEAN := X < 0.0;
+        variable YNEGATIVE : BOOLEAN := Y < 0.0;
+        variable VALUE : REAL;
+    begin
+        -- Check validity of input arguments
+            if (Y = 0.0) then
+                 assert FALSE
+                        report "MOD(X, 0.0) is undefined"
+                        severity ERROR;
+                 return 0.0;
+              end if;
+
+        -- Compute value
+        if ( XNEGATIVE ) then
+                if ( YNEGATIVE ) then
+                        VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        else
+                if ( YNEGATIVE ) then
+                        VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        end if;
+
+        return VALUE;
+    end "MOD";
+
+
+    function REALMAX (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMAX(X,Y) = X when X = Y
+        --
+    begin
+        if X >= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMAX;
+
+    function REALMIN (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMIN(X,Y) = X when X = Y
+        --
+    begin
+        if X <= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMIN;
+
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
+                                                                         is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+        --
+        variable Z, K: INTEGER;
+        variable TSEED1 : INTEGER := INTEGER'(SEED1);
+        variable TSEED2 : INTEGER := INTEGER'(SEED2);
+    begin
+        -- Check validity of arguments
+        if SEED1 > 2147483562 then
+                assert FALSE
+                        report "SEED1 > 2147483562 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        if SEED2 > 2147483398 then
+                assert FALSE
+                        report "SEED2 > 2147483398 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        -- Compute new seed values and pseudo-random number
+        K := TSEED1/53668;
+        TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
+
+        if TSEED1 < 0  then
+                TSEED1 := TSEED1 + 2147483563;
+        end if;
+
+        K := TSEED2/52774;
+        TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
+
+        if TSEED2 < 0  then
+                TSEED2 := TSEED2 + 2147483399;
+        end if;
+
+        Z := TSEED1 - TSEED2;
+        if Z < 1 then
+                Z := Z + 2147483562;
+        end if;
+
+        -- Get output values
+        SEED1 := POSITIVE'(TSEED1);
+        SEED2 := POSITIVE'(TSEED2);
+        X :=  REAL(Z)*4.656613e-10;
+    end UNIFORM;
+
+
+
+    function SQRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = 0.5*[F(n) + x/F(n)]
+        --        b) Returns 0.0 on error
+        --
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
+
+        variable INIVAL: REAL;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+        -- Check validity of argument
+        if ( X < 0.0 ) then
+                assert FALSE
+                        report "X < 0.0 in SQRT(X)"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get the square root for special cases
+        if X = 0.0 then
+                  return 0.0;
+        else
+                if ( X = 1.0 ) then
+                        return 1.0;
+                end if;
+        end if;
+
+        -- Get the square root for general cases
+        INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+
+        -- Check for  relative and absolute error and max count
+        while  ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                   (COUNT < MAX_COUNT) )  loop
+                OLDVAL := NEWVAL;
+                NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+                COUNT := COUNT + 1;
+        end loop;
+        return NEWVAL;
+    end SQRT;
+
+    function CBRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+        variable INIVAL: REAL;
+        variable XLOCAL : REAL := X;
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+
+        -- Compute root for special cases
+        if X = 0.0 then
+                return 0.0;
+        elsif ( X = 1.0 ) then
+                return 1.0;
+        else
+                if X = -1.0 then
+                        return -1.0;
+                end if;
+        end if;
+
+        -- Compute root for general cases
+        if NEGATIVE then
+                XLOCAL := -X;
+        end if;
+
+        INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
+                                          -- imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+
+        -- Check for relative and absolute errors and max count
+        while ( (  (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS ) )  AND
+                   ( COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+                COUNT := COUNT + 1;
+        end loop;
+
+        if NEGATIVE then
+                NEWVAL := -NEWVAL;
+        end if;
+
+        return NEWVAL;
+    end CBRT;
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (REAL(X));
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (REAL(X)));
+    end "**";
+
+    function "**" (X : in REAL; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0.0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0.0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0.0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0.0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0.0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (X);
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (X));
+    end "**";
+
+    function EXP  (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) This function computes the exponential using the following
+        --           series:
+        --                exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
+        --           and reduces argument X to take advantage of exp(x+y) =
+        --           exp(x)*exp(y)
+        --
+        --        b) This implementation limits X to be less than LOG(REAL'HIGH)
+        --           to avoid overflow.  Returns REAL'HIGH when X reaches that
+        --           limit
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
+
+            variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
+            variable XLOCAL : REAL := ABS(X);       -- Use positive value
+            variable OLDVAL: REAL ;
+            variable COUNT: INTEGER ;
+            variable NEWVAL: REAL ;
+            variable LAST_TERM: REAL ;
+        variable FACTOR : REAL := 1.0;
+
+     begin
+            -- Compute value for special cases
+        if X = 0.0 then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = 1.0  then
+                if RECIPROCAL then
+                        return MATH_1_OVER_E;
+                else
+                        return MATH_E;
+                end if;
+        end if;
+
+        if  XLOCAL = 2.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P2;
+                else
+                        return MATH_E_P2;
+                end if;
+        end if;
+
+        if  XLOCAL = 10.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P10;
+                else
+                        return MATH_E_P10;
+                end if;
+        end if;
+
+        if XLOCAL > LOG(REAL'HIGH) then
+                if RECIPROCAL then
+                        return 0.0;
+                else
+                        assert FALSE
+                                report "X > LOG(REAL'HIGH) in EXP(X)"
+                                severity NOTE;
+                        return REAL'HIGH;
+                end if;
+        end if;
+
+        -- Reduce argument to ABS(X) < 1.0
+        while XLOCAL > 10.0 loop
+                XLOCAL := XLOCAL - 10.0;
+                FACTOR := FACTOR*MATH_E_P10;
+        end loop;
+
+        while XLOCAL > 1.0 loop
+                XLOCAL := XLOCAL - 1.0;
+                FACTOR := FACTOR*MATH_E;
+        end loop;
+
+        -- Compute value for case 0 < XLOCAL < 1
+        OLDVAL := 1.0;
+        LAST_TERM := XLOCAL;
+        NEWVAL:= OLDVAL + LAST_TERM;
+        COUNT := 2;
+
+        -- Check for relative and absolute errors and max count
+        while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
+                  (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                  (COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
+                NEWVAL := OLDVAL + LAST_TERM;
+                COUNT := COUNT + 1;
+        end loop;
+
+        -- Compute final value using exp(x+y) = exp(x)*exp(y)
+        NEWVAL := NEWVAL*FACTOR;
+
+        if RECIPROCAL then
+                NEWVAL := 1.0/NEWVAL;
+        end if;
+
+        return NEWVAL;
+     end EXP;
+
+
+    --
+    -- Auxiliary Functions to Compute LOG
+    --
+    function ILOGB(X: in REAL) return INTEGER IS
+        -- Description:
+        --        Returns n such that -1 <= ABS(X)/2^n < 2
+        -- Notes:
+        --        None
+
+        variable N: INTEGER := 0;
+        variable Y: REAL := ABS(X);
+
+    begin
+        if(Y = 1.0 or Y = 0.0) then
+                return 0;
+        end if;
+
+        if( Y > 1.0) then
+                while Y >= 2.0 loop
+                        Y := Y/2.0;
+                        N := N+1;
+                end loop;
+                return N;
+        end if;
+
+        -- O < Y < 1
+        while Y < 1.0 loop
+                Y := Y*2.0;
+                N := N -1;
+        end loop;
+        return N;
+    end ILOGB;
+
+    function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
+        -- Description:
+        --        Returns X*2^n
+        -- Notes:
+        --         None
+    begin
+        return X*(2.0 ** N);
+    end LDEXP;
+
+    function LOG (X : in REAL ) return REAL IS
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        --
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+        --
+        -- Copyright (c) 1992 Regents of the University of California.
+        -- All rights reserved.
+        --
+        -- Redistribution and use in source and binary forms, with or without
+        -- modification, are permitted provided that the following conditions
+        -- are met:
+        -- 1. Redistributions of source code must retain the above copyright
+        -- notice, this list of conditions and the following disclaimer.
+        -- 2. Redistributions in binary form must reproduce the above copyright
+        -- notice, this list of conditions and the following disclaimer in the
+        -- documentation and/or other materials provided with the distribution.
+        -- 3. All advertising materials mentioning features or use of this
+        -- software must display the following acknowledgement:
+        -- This product includes software developed by the University of
+        -- California, Berkeley and its contributors.
+        -- 4. Neither the name of the University nor the names of its
+        -- contributors may be used to endorse or promote products derived
+        -- from this software without specific prior written permission.
+        --
+        -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+        -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+        -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+        -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
+        -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+        -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+        -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+        -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+        -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+        -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+        -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+        -- DAMAGE.
+        --
+        -- NOTE: This VHDL version was generated using the C version of the
+        --         original function by the IEEE VHDL Mathematical Package
+        --         Working Group (CS/JT)
+
+        constant N: INTEGER := 128;
+
+        -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
+        -- Used for generation of extend precision logarithms.
+        -- The constant 35184372088832 is 2^45, so the divide is exact.
+        -- It ensures correct reading of logF_head, even for inaccurate
+        -- decimal-to-binary conversion routines. (Everybody gets the
+        -- right answer for INTEGERs less than 2^53.)
+        -- Values for LOG(F) were generated using error < 10^-57 absolute
+        -- with the bc -l package.
+
+        type REAL_VECTOR is array (NATURAL range <>) of REAL;
+
+        constant A1:REAL := 0.08333333333333178827;
+        constant A2:REAL := 0.01250000000377174923;
+        constant A3:REAL := 0.002232139987919447809;
+        constant A4:REAL := 0.0004348877777076145742;
+
+        constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
+                0.0,
+                0.007782140442060381246,
+                0.015504186535963526694,
+                0.023167059281547608406,
+                0.030771658666765233647,
+                0.038318864302141264488,
+                0.045809536031242714670,
+                0.053244514518837604555,
+                0.060624621816486978786,
+                0.067950661908525944454,
+                0.075223421237524235039,
+                0.082443669210988446138,
+                0.089612158689760690322,
+                0.096729626458454731618,
+                0.103796793681567578460,
+                0.110814366340264314203,
+                0.117783035656430001836,
+                0.124703478501032805070,
+                0.131576357788617315236,
+                0.138402322859292326029,
+                0.145182009844575077295,
+                0.151916042025732167530,
+                0.158605030176659056451,
+                0.165249572895390883786,
+                0.171850256926518341060,
+                0.178407657472689606947,
+                0.184922338493834104156,
+                0.191394852999565046047,
+                0.197825743329758552135,
+                0.204215541428766300668,
+                0.210564769107350002741,
+                0.216873938300523150246,
+                0.223143551314024080056,
+                0.229374101064877322642,
+                0.235566071312860003672,
+                0.241719936886966024758,
+                0.247836163904594286577,
+                0.253915209980732470285,
+                0.259957524436686071567,
+                0.265963548496984003577,
+                0.271933715484010463114,
+                0.277868451003087102435,
+                0.283768173130738432519,
+                0.289633292582948342896,
+                0.295464212893421063199,
+                0.301261330578199704177,
+                0.307025035294827830512,
+                0.312755710004239517729,
+                0.318453731118097493890,
+                0.324119468654316733591,
+                0.329753286372579168528,
+                0.335355541920762334484,
+                0.340926586970454081892,
+                0.346466767346100823488,
+                0.351976423156884266063,
+                0.357455888922231679316,
+                0.362905493689140712376,
+                0.368325561158599157352,
+                0.373716409793814818840,
+                0.379078352934811846353,
+                0.384411698910298582632,
+                0.389716751140440464951,
+                0.394993808240542421117,
+                0.400243164127459749579,
+                0.405465108107819105498,
+                0.410659924985338875558,
+                0.415827895143593195825,
+                0.420969294644237379543,
+                0.426084395310681429691,
+                0.431173464818130014464,
+                0.436236766774527495726,
+                0.441274560805140936281,
+                0.446287102628048160113,
+                0.451274644139630254358,
+                0.456237433481874177232,
+                0.461175715122408291790,
+                0.466089729924533457960,
+                0.470979715219073113985,
+                0.475845904869856894947,
+                0.480688529345570714212,
+                0.485507815781602403149,
+                0.490303988045525329653,
+                0.495077266798034543171,
+                0.499827869556611403822,
+                0.504556010751912253908,
+                0.509261901790523552335,
+                0.513945751101346104405,
+                0.518607764208354637958,
+                0.523248143765158602036,
+                0.527867089620485785417,
+                0.532464798869114019908,
+                0.537041465897345915436,
+                0.541597282432121573947,
+                0.546132437597407260909,
+                0.550647117952394182793,
+                0.555141507540611200965,
+                0.559615787935399566777,
+                0.564070138285387656651,
+                0.568504735352689749561,
+                0.572919753562018740922,
+                0.577315365035246941260,
+                0.581691739635061821900,
+                0.586049045003164792433,
+                0.590387446602107957005,
+                0.594707107746216934174,
+                0.599008189645246602594,
+                0.603290851438941899687,
+                0.607555250224322662688,
+                0.611801541106615331955,
+                0.616029877215623855590,
+                0.620240409751204424537,
+                0.624433288012369303032,
+                0.628608659422752680256,
+                0.632766669570628437213,
+                0.636907462236194987781,
+                0.641031179420679109171,
+                0.645137961373620782978,
+                0.649227946625615004450,
+                0.653301272011958644725,
+                0.657358072709030238911,
+                0.661398482245203922502,
+                0.665422632544505177065,
+                0.669430653942981734871,
+                0.673422675212350441142,
+                0.677398823590920073911,
+                0.681359224807238206267,
+                0.685304003098281100392,
+                0.689233281238557538017,
+                0.693147180560117703862);
+
+        constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
+                0.0,
+                -0.00000000000000543229938420049,
+                0.00000000000000172745674997061,
+                -0.00000000000001323017818229233,
+                -0.00000000000001154527628289872,
+                -0.00000000000000466529469958300,
+                0.00000000000005148849572685810,
+                -0.00000000000002532168943117445,
+                -0.00000000000005213620639136504,
+                -0.00000000000001819506003016881,
+                0.00000000000006329065958724544,
+                0.00000000000008614512936087814,
+                -0.00000000000007355770219435028,
+                0.00000000000009638067658552277,
+                0.00000000000007598636597194141,
+                0.00000000000002579999128306990,
+                -0.00000000000004654729747598444,
+                -0.00000000000007556920687451336,
+                0.00000000000010195735223708472,
+                -0.00000000000017319034406422306,
+                -0.00000000000007718001336828098,
+                0.00000000000010980754099855238,
+                -0.00000000000002047235780046195,
+                -0.00000000000008372091099235912,
+                0.00000000000014088127937111135,
+                0.00000000000012869017157588257,
+                0.00000000000017788850778198106,
+                0.00000000000006440856150696891,
+                0.00000000000016132822667240822,
+                -0.00000000000007540916511956188,
+                -0.00000000000000036507188831790,
+                0.00000000000009120937249914984,
+                0.00000000000018567570959796010,
+                -0.00000000000003149265065191483,
+                -0.00000000000009309459495196889,
+                0.00000000000017914338601329117,
+                -0.00000000000001302979717330866,
+                0.00000000000023097385217586939,
+                0.00000000000023999540484211737,
+                0.00000000000015393776174455408,
+                -0.00000000000036870428315837678,
+                0.00000000000036920375082080089,
+                -0.00000000000009383417223663699,
+                0.00000000000009433398189512690,
+                0.00000000000041481318704258568,
+                -0.00000000000003792316480209314,
+                0.00000000000008403156304792424,
+                -0.00000000000034262934348285429,
+                0.00000000000043712191957429145,
+                -0.00000000000010475750058776541,
+                -0.00000000000011118671389559323,
+                0.00000000000037549577257259853,
+                0.00000000000013912841212197565,
+                0.00000000000010775743037572640,
+                0.00000000000029391859187648000,
+                -0.00000000000042790509060060774,
+                0.00000000000022774076114039555,
+                0.00000000000010849569622967912,
+                -0.00000000000023073801945705758,
+                0.00000000000015761203773969435,
+                0.00000000000003345710269544082,
+                -0.00000000000041525158063436123,
+                0.00000000000032655698896907146,
+                -0.00000000000044704265010452446,
+                0.00000000000034527647952039772,
+                -0.00000000000007048962392109746,
+                0.00000000000011776978751369214,
+                -0.00000000000010774341461609578,
+                0.00000000000021863343293215910,
+                0.00000000000024132639491333131,
+                0.00000000000039057462209830700,
+                -0.00000000000026570679203560751,
+                0.00000000000037135141919592021,
+                -0.00000000000017166921336082431,
+                -0.00000000000028658285157914353,
+                -0.00000000000023812542263446809,
+                0.00000000000006576659768580062,
+                -0.00000000000028210143846181267,
+                0.00000000000010701931762114254,
+                0.00000000000018119346366441110,
+                0.00000000000009840465278232627,
+                -0.00000000000033149150282752542,
+                -0.00000000000018302857356041668,
+                -0.00000000000016207400156744949,
+                0.00000000000048303314949553201,
+                -0.00000000000071560553172382115,
+                0.00000000000088821239518571855,
+                -0.00000000000030900580513238244,
+                -0.00000000000061076551972851496,
+                0.00000000000035659969663347830,
+                0.00000000000035782396591276383,
+                -0.00000000000046226087001544578,
+                0.00000000000062279762917225156,
+                0.00000000000072838947272065741,
+                0.00000000000026809646615211673,
+                -0.00000000000010960825046059278,
+                0.00000000000002311949383800537,
+                -0.00000000000058469058005299247,
+                -0.00000000000002103748251144494,
+                -0.00000000000023323182945587408,
+                -0.00000000000042333694288141916,
+                -0.00000000000043933937969737844,
+                0.00000000000041341647073835565,
+                0.00000000000006841763641591466,
+                0.00000000000047585534004430641,
+                0.00000000000083679678674757695,
+                -0.00000000000085763734646658640,
+                0.00000000000021913281229340092,
+                -0.00000000000062242842536431148,
+                -0.00000000000010983594325438430,
+                0.00000000000065310431377633651,
+                -0.00000000000047580199021710769,
+                -0.00000000000037854251265457040,
+                0.00000000000040939233218678664,
+                0.00000000000087424383914858291,
+                0.00000000000025218188456842882,
+                -0.00000000000003608131360422557,
+                -0.00000000000050518555924280902,
+                0.00000000000078699403323355317,
+                -0.00000000000067020876961949060,
+                0.00000000000016108575753932458,
+                0.00000000000058527188436251509,
+                -0.00000000000035246757297904791,
+                -0.00000000000018372084495629058,
+                0.00000000000088606689813494916,
+                0.00000000000066486268071468700,
+                0.00000000000063831615170646519,
+                0.00000000000025144230728376072,
+                -0.00000000000017239444525614834);
+
+        variable M, J:INTEGER;
+        variable F1, F2, G, Q, U, U2, V: REAL;
+        variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
+        variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
+
+        -- double logb(), ldexp();
+
+        variable U1:REAL;
+
+     begin
+
+        -- Check validity of argument
+        if ( X <= 0.0 ) then
+                assert FALSE
+                        report "X <= 0.0 in LOG(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = MATH_E ) then
+                return 1.0;
+        end if;
+
+        -- Argument reduction: 1 <= g < 2; x/2^m = g;
+        -- y = F*(1 + f/F) for |f| <= 2^-8
+
+        M := ILOGB(X);
+        G := LDEXP(X, -M);
+        J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
+        F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
+        F2 := G - F1;
+
+        -- Approximate expansion for log(1+f2/F1) ~= u + q
+        G := 1.0/(2.0*F1+F2);
+        U := 2.0*F2*G;
+        V := U*U;
+        Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
+
+        -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
+        --       u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
+        --       It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
+        --
+        if ( J /= 0 or M /= 0) then
+                U1 := U + 513.0;
+                U1 := U1 - 513.0;
+
+                -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
+                --        u1 = u to 24 bits.
+                --
+        else
+                U1 := U;
+                --TRUNC(U1); --In c this is u1 = (double) (float) (u1)
+        end if;
+
+        U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
+        -- u1 + u2 = 2f/(2F+f) to extra precision.
+
+        -- log(x) = log(2^m*F1*(1+f2/F1)) =
+        -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
+        -- (exact) + (tiny)
+
+        U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J);        -- Exact
+        U2 := (U2 + LOGF_TAIL(J)) + Q;        -- Tiny
+        U2 := U2 + LOGF_TAIL(N)*REAL(M);
+        return (U1 + U2);
+    end LOG;
+
+
+    function LOG2 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                assert FALSE
+                        report "X <= 0.0 in LOG2(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 2.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG2_OF_E*LOG(X) );
+    end LOG2;
+
+
+    function LOG10 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                   assert FALSE
+                        report "X <= 0.0 in LOG10(X)"
+                        severity ERROR;
+                   return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 10.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG10_OF_E*LOG(X) );
+    end LOG10;
+
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                 assert FALSE
+                        report "X <= 0.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        if ( BASE <= 0.0 or BASE = 1.0 )  then
+                 assert FALSE
+                        report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = BASE ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( LOG(X)/LOG(BASE));
+    end LOG;
+
+
+    function  SIN (X : in REAL ) return REAL is
+        -- Description:
+        --         See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) SIN(-X) = -SIN(X)
+        --         b) SIN(X) = X if ABS(X) < EPS
+        --         c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
+        --         d) SIN(MATH_PI_OVER_2 - X) = COS(X)
+        --         e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
+        --         f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                         EPS< ABS(X) <BASE_EPS
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
+
+        variable N : INTEGER;
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X) ;
+        variable VALUE: REAL;
+        variable TEMP : REAL;
+
+    begin
+        -- Make XLOCAL < MATH_2_PI
+        if XLOCAL > MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in SIN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI  then
+                return 0.0;
+        end if;
+
+        if  XLOCAL = MATH_PI_OVER_2 then
+                if NEGATIVE then
+                        return -1.0;
+                else
+                        return 1.0;
+                end if;
+        end if;
+
+        if  XLOCAL = MATH_3_PI_OVER_2 then
+                if NEGATIVE then
+                        return 1.0;
+                else
+                        return -1.0;
+                end if;
+        end if;
+
+        if XLOCAL < EPS then
+                if NEGATIVE then
+                        return -XLOCAL;
+                else
+                        return XLOCAL;
+                end if;
+        else
+                if XLOCAL < BASE_EPS then
+                        TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_2_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
+                 VALUE:=  CORDIC( KC, 0.0, x, 27, ROTATION)(1);
+        end if;
+
+        N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
+        case QUADRANT( N mod 4) is
+           when 0 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
+           when 1 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+           when 2 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
+           when 3 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+        end case;
+
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+    end SIN;
+
+
+   function COS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) COS(-X) = COS(X)
+        --        b) COS(X) = SIN(MATH_PI_OVER_2 - X)
+        --        c) COS(MATH_PI + X)  = -COS(X)
+        --        d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
+        --        e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                           EPS< ABS(X) <BASE_EPS
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE: REAL;
+        variable TEMP : REAL;
+
+    begin
+        -- Make XLOCAL < MATH_2_PI
+        if XLOCAL > MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in COS(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = MATH_PI then
+                return -1.0;
+        end if;
+
+        if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
+                return 0.0;
+        end if;
+
+        TEMP := ABS(XLOCAL);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS(XLOCAL -MATH_2_PI);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS (XLOCAL - MATH_PI);
+        if TEMP < EPS then
+                return (-1.0 + 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        return SIN(MATH_PI_OVER_2 - XLOCAL);
+   end COS;
+
+   function TAN (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) TAN(0.0) = 0.0
+        --        b) TAN(-X) = -TAN(X)
+        --        c) Returns REAL'LOW on error if X < 0.0
+        --        d) Returns REAL'HIGH on error if X > 0.0
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X) ;
+        variable VALUE: REAL;
+        variable TEMP : REAL;
+
+    begin
+        -- Make 0.0 <= XLOCAL <= MATH_2_PI
+        if XLOCAL > MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in TAN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Check validity of argument
+        if XLOCAL = MATH_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'LOW);
+                else
+                        return(REAL'HIGH);
+                end if;
+        end if;
+
+        if XLOCAL = MATH_3_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'HIGH);
+                else
+                        return(REAL'LOW);
+                end if;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0 or XLOCAL = MATH_PI then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        VALUE := SIN(XLOCAL)/COS(XLOCAL);
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+   end TAN;
+
+   function ARCSIN (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCSIN(-X) = -ARCSIN(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of arguments
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCSIN(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if XLOCAL = 0.0 then
+         return 0.0;
+      elsif XLOCAL = 1.0 then
+         if NEGATIVE then
+                return -MATH_PI_OVER_2;
+         else
+                return MATH_PI_OVER_2;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL < 0.9 then
+         VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      end if;
+
+      if NEGATIVE then
+         VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCSIN;
+
+   function ARCCOS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of argument
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCCOS(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if X = 1.0 then
+         return 0.0;
+      elsif X = 0.0 then
+         return MATH_PI_OVER_2;
+      elsif X = -1.0 then
+         return MATH_PI;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL > 0.9 then
+         VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
+      end if;
+
+
+      if NEGATIVE then
+         VALUE := MATH_PI - VALUE;
+      end if;
+
+      return VALUE;
+   end ARCCOS;
+
+
+   function ARCTAN (Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCTAN(-Y) = -ARCTAN(Y)
+        --        b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
+        --        c) ARCTAN(Y) = Y for |Y| < EPS
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
+
+        variable NEGATIVE : BOOLEAN := Y < 0.0;
+        variable RECIPROCAL : BOOLEAN;
+        variable YLOCAL : REAL := ABS(Y);
+        variable VALUE : REAL;
+
+   begin
+      -- Make argument |Y| <=1.0
+      if YLOCAL > 1.0 then
+                YLOCAL := 1.0/YLOCAL;
+                RECIPROCAL := TRUE;
+      else
+                RECIPROCAL := FALSE;
+      end if;
+
+      -- Compute value for special cases
+      if YLOCAL = 0.0 then
+         if RECIPROCAL then
+                if NEGATIVE then
+                        return (-MATH_PI_OVER_2);
+                else
+                        return (MATH_PI_OVER_2);
+                end if;
+         else
+                return 0.0;
+         end if;
+      end if;
+
+      if YLOCAL < EPS then
+         if NEGATIVE then
+                if RECIPROCAL then
+                        return (-MATH_PI_OVER_2 + YLOCAL);
+                else
+                        return -YLOCAL;
+                end if;
+         else
+                if RECIPROCAL then
+                        return (MATH_PI_OVER_2 - YLOCAL);
+                else
+                        return YLOCAL;
+                end if;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      VALUE :=  CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
+
+      if RECIPROCAL then
+         VALUE := MATH_PI_OVER_2 - VALUE;
+      end if;
+
+      if NEGATIVE then
+        VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCTAN;
+
+
+   function ARCTAN (Y : in REAL; X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 on error
+
+        variable YLOCAL : REAL;
+        variable VALUE : REAL;
+   begin
+
+     -- Check validity of arguments
+     if (Y = 0.0 and X = 0.0 ) then
+           assert FALSE report
+                "ARCTAN(0.0, 0.0) is undetermined"
+                severity ERROR;
+           return 0.0;
+     end if;
+
+     -- Compute value for special cases
+     if Y = 0.0 then
+        if X > 0.0 then
+           return 0.0;
+        else
+           return MATH_PI;
+        end if;
+     end if;
+
+     if X = 0.0 then
+        if Y > 0.0 then
+           return MATH_PI_OVER_2;
+        else
+           return -MATH_PI_OVER_2;
+        end if;
+     end if;
+
+
+     -- Compute value for general cases
+     YLOCAL := ABS(Y/X);
+
+     VALUE := ARCTAN(YLOCAL);
+
+     if X < 0.0 then
+         VALUE := MATH_PI - VALUE;
+     end if;
+
+     if Y < 0.0 then
+         VALUE := -VALUE;
+     end if;
+
+     return VALUE;
+   end ARCTAN;
+
+
+    function SINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/2.0
+        --        b) SINH(-X) = SINH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)*0.5;
+
+         if NEGATIVE then
+                VALUE := -VALUE;
+        end if;
+
+        return VALUE;
+    end SINH;
+
+    function  COSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) + EXP(-X))/2.0
+        --        b) COSH(-X) = COSH(X)
+
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 1.0;
+        end if;
+
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP + 1.0/TEMP)*0.5;
+
+        return VALUE;
+    end COSH;
+
+    function  TANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
+        --        b) TANH(-X) = -TANH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
+
+        if NEGATIVE then
+            return -VALUE;
+        else
+            return VALUE;
+        end if;
+    end TANH;
+
+    function ARCSINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X + 1.0))
+
+    begin
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X + 1.0)) );
+    end ARCSINH;
+
+
+
+   function ARCCOSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X - 1.0));   X >= 1.0
+        --        b) Returns X on error
+
+    begin
+        -- Check validity of arguments
+        if X < 1.0 then
+                 assert FALSE
+                        report "X < 1.0 in ARCCOSH(X)"
+                        severity ERROR;
+                 return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 1.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X - 1.0)));
+    end ARCCOSH;
+
+    function ARCTANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
+        --        b) Returns X on error
+    begin
+        -- Check validity of arguments
+        if ABS(X) >= 1.0 then
+                assert FALSE
+                        report "ABS(X) >= 1.0 in ARCTANH(X)"
+                        severity ERROR;
+                return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
+    end ARCTANH;
+
+end  MATH_REAL;
diff --git a/impl1/.recordref b/impl1/.recordref
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/.recordref_modgen b/impl1/.recordref_modgen
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/.vdbs/dbStat.txt b/impl1/.vdbs/dbStat.txt
new file mode 100644
index 0000000..e8652b9
--- /dev/null
+++ b/impl1/.vdbs/dbStat.txt
@@ -0,0 +1 @@
+top_rtl.vdb
diff --git a/impl1/.vdbs/s1_impl1_map.vdb b/impl1/.vdbs/s1_impl1_map.vdb
new file mode 100644
index 0000000..31c9145
Binary files /dev/null and b/impl1/.vdbs/s1_impl1_map.vdb differ
diff --git a/impl1/.vdbs/top_rtl.vdb b/impl1/.vdbs/top_rtl.vdb
new file mode 100644
index 0000000..6f05da9
Binary files /dev/null and b/impl1/.vdbs/top_rtl.vdb differ
diff --git a/impl1/.vdbs/top_tech.vdb b/impl1/.vdbs/top_tech.vdb
new file mode 100644
index 0000000..ec31f78
Binary files /dev/null and b/impl1/.vdbs/top_tech.vdb differ
diff --git a/impl1/_CMD_COMPILER.CML b/impl1/_CMD_COMPILER.CML
new file mode 100644
index 0000000..645d8fa
--- /dev/null
+++ b/impl1/_CMD_COMPILER.CML
@@ -0,0 +1 @@
+ -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs  -top  top_tf  -hdllog  /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_compiler.srr  -encrypt  -mp  4  -prodtype  synplify_premier  -distcompmode 1 -verification_mode 0  -vhdl  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd  -verilog  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/hadaq/mmichalek/lattice/simplified  -I /home/hadaq/mmichalek/lattice/simplified/impl1/  -I /opt/synplicity/O-2018.09-SP1/lib   -v2001  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v  -encrypt  -pro    -DSBP_SYNTHESIS    -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -jobname  "compiler" 
\ No newline at end of file
diff --git a/impl1/_CMD_HDL_INFO_GEN.CML b/impl1/_CMD_HDL_INFO_GEN.CML
new file mode 100644
index 0000000..6b4413b
--- /dev/null
+++ b/impl1/_CMD_HDL_INFO_GEN.CML
@@ -0,0 +1 @@
+ -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_hdl_.srs  -top  top_tf  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd  -log  /home/hadaq/mmichalek/lattice/simplified/impl1/syntax.log  -fileorder  /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/hdlorder.tcl  -jobname  "hdl_info_gen" 
\ No newline at end of file
diff --git a/impl1/_cmd._cml b/impl1/_cmd._cml
new file mode 100644
index 0000000..bb1545e
--- /dev/null
+++ b/impl1/_cmd._cml
@@ -0,0 +1 @@
+-distcompmode -link    -encrypt       -top work.top_tf -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs    
\ No newline at end of file
diff --git a/impl1/automake.err b/impl1/automake.err
new file mode 100644
index 0000000..d7d1216
--- /dev/null
+++ b/impl1/automake.err
@@ -0,0 +1 @@
+error waiting for process to exit: 
diff --git a/impl1/automake.log b/impl1/automake.log
new file mode 100644
index 0000000..fdbe3b4
--- /dev/null
+++ b/impl1/automake.log
@@ -0,0 +1,2671 @@
+
+synpwrap -msg -prj "s1_impl1_synplify.tcl" -log "s1_impl1.srf"
+Copyright (C) 1992-2019 Lattice Semiconductor Corporation. All rights reserved.
+Lattice Diamond Version 3.11.2.446
+    <postMsg mid="2011000" type="Info"    dynamic="0" navigation="0"  />
+###########################################################[
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Wed Jun 16 09:19:12 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Wed Jun 16 09:19:12 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Wed Jun 16 09:19:17 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Wed Jun 16 09:19:17 2021
+
+multi_srs_gen completed
+# Wed Jun 16 09:19:17 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Wed Jun 16 09:19:17 2021
+
+premap completed with warnings
+# Wed Jun 16 09:19:18 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Wed Jun 16 09:19:18 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Wed Jun 16 09:19:18 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Wed Jun 16 09:19:25 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
+Child process exit with 0.
+
+==contents of s1_impl1.srf
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Jun 16 09:19:13 2021
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
+Premap Report
+
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Jun 16 09:19:25 2021
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS2_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS3_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: top_tf|rd_clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
+
+
+Synthesis exit by 0.
+
+edif2ngd  -l "ECP5UM5G" -d LFE5UM5G-45F -path "/home/hadaq/mmichalek/lattice/simplified/impl1" -path "/home/hadaq/mmichalek/lattice/simplified"   "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi" "s1_impl1.ngo"   
+edif2ngd:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+    <postMsg mid="1121027" type="Warning" dynamic="1" navigation="0" arg0="MEM_INIT_FILE"  />
+    <postMsg mid="1121027" type="Warning" dynamic="1" navigation="0" arg0="MEM_INIT_FILE"  />
+    <postMsg mid="1121027" type="Warning" dynamic="1" navigation="0" arg0="MEM_INIT_FILE"  />
+    <postMsg mid="1121027" type="Warning" dynamic="1" navigation="0" arg0="MEM_INIT_FILE"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="TDC_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="COARSE_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="WINDOW_LENGTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="TDC_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="COARSE_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="ADDRESS_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="COARSE_WIDTH_INTERNAL"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="HITBUFFER_DEPTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="TDC_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="COARSE_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="TRIG_WIDTH"  />
+    <postMsg mid="1121028" type="Warning" dynamic="1" navigation="0" arg0="ADDRESS_WIDTH"  />
+Writing the design to s1_impl1.ngo...
+
+Total CPU Time: 0 secs  
+Total REAL Time: 0 secs  
+Peak Memory Usage: 45 MB
+
+
+ngdbuild  -a "ECP5UM5G" -d LFE5UM5G-45F  -p "/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data"  -p "/home/hadaq/mmichalek/lattice/simplified/impl1" -p "/home/hadaq/mmichalek/lattice/simplified"  "s1_impl1.ngo" "s1_impl1.ngd"  	
+ngdbuild:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Reading 's1_impl1.ngo' ...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+   1658 blocks expanded
+Complete the first expansion.
+Writing 's1_impl1.ngd' ...
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 86 MB
+
+
+map -a "ECP5UM5G" -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial   "s1_impl1.ngd" -o "s1_impl1_map.ncd" -pr "s1_impl1.prf" -mp "s1_impl1.mrp" -lpf "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf" -lpf "/home/hadaq/mmichalek/lattice/simplified/s1.lpf"   -xref_sym -xref_sig   -tdm     
+map:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+   Process the file: s1_impl1.ngd
+   Picdevice="LFE5UM5G-45F"
+
+   Pictype="CABGA381"
+
+   Picspeed=8
+
+   Remove unused logic
+
+   Do not produce over sized NCDs.
+
+Part used: LFE5UM5G-45FCABGA381, Performance used: 8.
+
+Your license expires in 13 days.
+
+A new map free license can be generated from the Lattice website. A map subscription license can be purchased from your local Lattice sales representative or from the Lattice website. For more information on map software refer to http://www.latticesemi.com/latticediamond .
+Loading device for application GENERIC from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+    <postMsg mid="1100086" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic error in &quot;BLOCK NET &quot;tdc_out*&quot; ;&quot;: " arg1="tdc_out*" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="10"  />
+    <postMsg mid="1100679" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic error in &quot;LOCATE COMP &quot;reset&quot; SITE &quot;D11&quot; ;&quot;: " arg1="reset" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="48"  />
+    <postMsg mid="1101611" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic error in &quot;UGROUP &quot;trig_gate0&quot; BBOX 1 1 &#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO&#xA;&#x9;BLKNAME trig_pad_RNII4FF[0];&quot;: " arg1="Block &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO&quot; of UGROUP &quot;trig_gate0&quot; not found in design" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="59"  />
+    <postMsg mid="1100675" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic error in &quot;LOCATE UGROUP &quot;trig_gate0&quot; SITE &quot;R68C13D&quot; ;&quot;: " arg1="trig_gate0" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="60"  />
+    <postMsg mid="1101611" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic error in &quot;UGROUP &quot;tdc_ch0&quot; BBOX 1 6 &#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de   ....   _inst/dec_inst/out_internal[2]&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;&quot;: " arg1="Block &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_cha   ....   out_internal[1]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]&quot; of UGROUP &quot;tdc_ch0&quot; not found in design" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="95"  />
+    <postMsg mid="1100675" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic error in &quot;LOCATE UGROUP &quot;tdc_ch0&quot; SITE &quot;R67C14D&quot; ;&quot;: " arg1="tdc_ch0" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="96"  />
+    <postMsg mid="1101611" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic error in &quot;UGROUP &quot;tdc2&quot; BBOX 1 6 &#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst&#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC&#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]&#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_   ....   st/dec_inst/valid&#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal&#xA;&#x9;BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;&quot;: " arg1="Block &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].td   ....   ternal[2]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0&quot; of UGROUP &quot;tdc2&quot; not found in design" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="141"  />
+    <postMsg mid="1100675" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic error in &quot;LOCATE UGROUP &quot;tdc2&quot; SITE &quot;R65C41D&quot; ;&quot;: " arg1="tdc2" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="142"  />
+    <postMsg mid="1101611" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic error in &quot;UGROUP &quot;dec3&quot; BBOX 1 6 &#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst&#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC&#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]&#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_   ....   st/dec_inst/valid&#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal&#xA;&#x9;BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;&quot;: " arg1="Block &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].td   ....   ternal[2]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0&quot; of UGROUP &quot;dec3&quot; not found in design" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="264"  />
+    <postMsg mid="1100675" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic error in &quot;LOCATE UGROUP &quot;dec3&quot; SITE &quot;R65C49D&quot; ;&quot;: " arg1="dec3" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="265"  />
+    <postMsg mid="1101611" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic error in &quot;UGROUP &quot;tdc0_neg&quot; BBOX 1 4 &#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_   ....   enblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]&#xA;&#x9;BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7];&quot;: " arg1="Block &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]&quot; of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]&quot; of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b   ....   of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]&quot; of UGROUP &quot;tdc0_neg&quot; not found in design" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="289"  />
+    <postMsg mid="1100675" type="Warning" dynamic="2" navigation="2" arg0="/home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic error in &quot;LOCATE UGROUP &quot;tdc0_neg&quot; SITE &quot;R69C14D&quot; ;&quot;: " arg1="tdc0_neg" arg2="/home/hadaq/mmichalek/lattice/simplified/s1.lpf" arg3="290"  />
+Package Status:                     Final          Version 1.38.
+
+Running general design DRC...
+
+Removing unused logic...
+
+Optimizing...
+
+144 CCU2 constant inputs absorbed.
+
+
+
+
+
+
+Design Summary:
+   Number of registers:    934 out of 44457 (2%)
+      PFU registers:          899 out of 43848 (2%)
+      PIO registers:           35 out of   609 (6%)
+   Number of SLICEs:       692 out of 21924 (3%)
+      SLICEs as Logic/ROM:    692 out of 21924 (3%)
+      SLICEs as RAM:            0 out of 16443 (0%)
+      SLICEs as Carry:        121 out of 21924 (1%)
+   Number of LUT4s:        630 out of 43848 (1%)
+      Number used as logic LUTs:        388
+      Number used as distributed RAM:     0
+      Number used as ripple logic:      242
+      Number used as shift registers:     0
+   Number of PIO sites used: 187 out of 203 (92%)
+      Number of PIO sites used for single ended IOs: 185
+      Number of PIO sites used for differential IOs: 2 (represented by 1 PIO comps in NCD)
+   Number of block RAMs:  4 out of 108 (4%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   DTR used :   No
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
+   Number of DCC:  0 out of 60 (0%)
+   Number of DCS:  0 out of 2 (0%)
+   Number of PLLs:  1 out of 4 (25%)
+   Number of DDRDLLs:  0 out of 4 (0%)
+   Number of CLKDIV:  0 out of 4 (0%)
+   Number of ECLKSYNC:  0 out of 10 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Number of DCUs:  0 out of 2 (0%)
+   Number of DCU Channels:  0 out of 4 (0%)
+   Number of EXTREFs:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
+
+   Number Of Mapped DSP Components:
+   --------------------------------
+   MULT18X18D          0
+   MULT9X9D            0
+   ALU54B              0
+   ALU24B              0
+   PRADD18A            0
+   PRADD9A             0
+   --------------------------------
+   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
+   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
+   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
+   Number of clocks:  6
+     Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk )
+     Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver: pll0inst/PLLInst_0 )
+     Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver: pll0inst/PLLInst_0 )
+     Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver: pll0inst/PLLInst_0 )
+     Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver: pll0inst/PLLInst_0 )
+     Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk )
+   Number of Clock Enables:  18
+     Net reset_dl[2]: 7 loads, 7 LSLICEs
+     Net N_248_i: 1 loads, 0 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs
+     Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs
+     Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs
+     Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads, 6 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads, 13 LSLICEs
+     Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10 loads, 1 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1 LSLICEs
+   Number of LSRs:  13
+     Net reset_dl[2]: 37 loads, 33 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs
+     Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs
+     Net fifo_rden_c: 1 loads, 1 LSLICEs
+     Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced7_rising_i: 3 loads, 3 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_rising_i: 4 loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4 loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1 LSLICEs
+     Net valid_fast_RNI999V: 9 loads, 0 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i: 4 loads, 4 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net reset_dl[2]: 59 loads
+     Net fifo_colector_inst/iterator[0]: 47 loads
+     Net fifo_colector_inst/iterator[1]: 23 loads
+     Net fifo_colector_inst/in_empty_pmux_i: 22 loads
+     Net un1_hit_i_2_0_a2: 20 loads
+     Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads
+    <postMsg mid="1104614" type="Warning" dynamic="2" navigation="0" arg0="Semantic error in &quot;PGROUP &quot;lvl1_dec&quot; BBOX 1 6  DEVSIZE&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464&quot;&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465&quot;&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474&quot;&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_ins   ....   inst/SLICE_734&quot;&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735&quot;&#xA;&#x9;COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736&quot;;&quot;: " arg1="lvl1_dec"  />
+ 
+
+   Number of warnings:  13
+   Number of errors:    0
+
+
+
+Total CPU Time: 4 secs  
+Total REAL Time: 5 secs  
+Peak Memory Usage: 361 MB
+
+Dumping design to file s1_impl1_map.ncd.
+
+trce -f "s1_impl1.mt" -o "s1_impl1.tw1" "s1_impl1_map.ncd" "s1_impl1.prf"
+trce:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 78  Score: 41485
+Cumulative negative slack: 24538
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 78 (setup), 0 (hold)
+Score: 41485 (setup), 0 (hold)
+Cumulative negative slack: 24538 (24538+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
+Peak Memory Usage: 369 MB
+
+
+mpartrce -p "s1_impl1.p2t" -f "s1_impl1.p3t" -tf "s1_impl1.pt" "s1_impl1_map.ncd" "s1_impl1.ncd"
+
+---- MParTrce Tool ----
+Removing old design directory at request of -rem command line option to this program.
+Running par. Please wait . . .
+
+Lattice Place and Route Report for Design "s1_impl1_map.ncd"
+Wed Jun 16 09:19:35 2021
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf
+Preference file: s1_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Your license expires in 13 days.
+
+A new par free license can be generated from the Lattice website. A par subscription license can be purchased from your local Lattice sales representative or from the Lattice website. For more information on par software refer to http://www.latticesemi.com/latticediamond .
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)     187/245          76% used
+                    187/203          92% bonded
+   IOLOGIC           35/245          14% used
+
+   SLICE            692/21924         3% used
+
+   EBR                4/108           3% used
+   PLL                1/4            25% used
+
+
+Number of Signals: 1594
+Number of Connections: 3725
+
+Pin Constraint Summary:
+   7 out of 186 pins locked (3% locked).
+
+The following 5 signals are selected to use the primary clock routing resources:
+    pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
+    pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+    pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0)
+    rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0)
+    pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+
+
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 8 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 788909.
+Finished Placer Phase 1.  REAL time: 24 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  774601
+Finished Placer Phase 2.  REAL time: 25 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 12 (8%)
+  GR_PCLK    : 0 out of 12 (0%)
+  PLL        : 1 out of 4 (25%)
+  DCS        : 0 out of 2 (0%)
+  DCC        : 0 out of 60 (0%)
+  CLKDIV     : 0 out of 4 (0%)
+
+Quadrant TL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant TR Clocks:
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8
+
+  PRIMARY  : 2 out of 16 (12%)
+
+Quadrant BL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant BR Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Edge Clocks:
+
+  No edge clock selected.
+
+
+--------------- End of Clock Report ---------------
+
+
++
+I/O Usage Summary (final):
+   187 out of 245 (76.3%) PIO sites used.
+   187 out of 203 (92.1%) bonded PIO sites used.
+   Number of PIO comps: 186; differential: 1.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 27 / 27 (100%) | 2.5V       | -          | -          |
+| 1        | 29 / 33 ( 87%) | 2.5V       | -          | -          |
+| 2        | 31 / 32 ( 96%) | 2.5V       | -          | -          |
+| 3        | 27 / 33 ( 81%) | 2.5V       | -          | -          |
+| 6        | 28 / 33 ( 84%) | 2.5V       | -          | -          |
+| 7        | 32 / 32 (100%) | 2.5V       | -          | -          |
+| 8        | 13 / 13 (100%) | 2.5V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 24 secs 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+0 connections routed; 3725 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 39 secs 
+
+Start NBR router at Wed Jun 16 09:20:14 CEST 2021
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021
+
+Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021
+Level 1, iteration 1
+21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.876ns/-158.654ns; real time: 41 secs 
+Level 2, iteration 1
+46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-159.217ns; real time: 41 secs 
+Level 3, iteration 1
+167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.962ns/-163.305ns; real time: 42 secs 
+Level 4, iteration 1
+81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-177.384ns; real time: 42 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021
+Level 1, iteration 1
+53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-171.398ns; real time: 43 secs 
+Level 4, iteration 1
+54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 2
+35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 3
+24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 4
+12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 5
+8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 43 secs 
+Level 4, iteration 6
+5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 44 secs 
+Level 4, iteration 7
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 8
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 9
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.896ns; real time: 44 secs 
+
+Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 156 (4.19%)
+  Estimated worst slack<setup> : -2.994ns
+  Timing score<setup> : 209210
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 46 secs 
+Total REAL time: 47 secs 
+Completely routed.
+End of route.  3725 routed (100.00%); 0 unrouted.
+
+Generating "par" statistics.
+
+Hold time timing score: 9, hold timing errors: 18
+
+Timing score: 209210 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -2.994
+PAR_SUMMARY::Timing score<setup/<ns>> = 209.210
+PAR_SUMMARY::Worst  slack<hold /<ns>> = -1.015
+PAR_SUMMARY::Timing score<hold /<ns>> = 9.647
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 48 secs 
+Total REAL time to completion: 48 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Exiting par with exit code 0
+Exiting mpartrce with exit code 0
+
+trce -f "s1_impl1.pt" -o "s1_impl1.twr" "s1_impl1.ncd" "s1_impl1.prf"
+trce:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 280  Score: 209210
+Cumulative negative slack: 139580
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 18  Score: 9647
+Cumulative negative slack: 9647
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 280 (setup), 18 (hold)
+Score: 209210 (setup), 9647 (hold)
+Cumulative negative slack: 149227 (139580+9647)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
+Peak Memory Usage: 370 MB
+
+
+iotiming  "s1_impl1.ncd" "s1_impl1.prf"
+I/O Timing Report:
+:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application iotiming from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Running Performance Grade: 8
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 9
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Running Performance Grade: 9
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: M
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Running Performance Grade: M
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+Done.
+
+ldbanno "s1_impl1.ncd" -n VHDL -o "s1_impl1_vho.vho"       -noslice -w -neg 
+ldbanno: version Diamond (64-bit) 3.11.2.446
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Writing a VHDL netlist using the orca library type based on the s1_impl1 design file.
+
+
+Loading design for application ldbanno from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application ldbanno from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Converting design s1_impl1.ncd into .ldb format.
+Loading preferences from s1_impl1.prf.
+Writing VHDL netlist to file s1_impl1_vho.vho
+Writing SDF timing to file s1_impl1_vho.sdf
+    <postMsg mid="35400250" type="Info"    dynamic="1" navigation="0" arg0="0"  />
+Total CPU Time: 5 secs 
+Total REAL Time: 6 secs 
+Peak Memory Usage: 271 MB
diff --git a/impl1/backup/s1_impl1.srr b/impl1/backup/s1_impl1.srr
new file mode 100644
index 0000000..bdc5717
--- /dev/null
+++ b/impl1/backup/s1_impl1.srr
@@ -0,0 +1,637 @@
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon Jul 27 07:12:33 2020
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top.v" (library work)
+Verilog syntax check successful!
+Selecting top level module top
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top.v":1:7:1:9|Synthesizing module top in library work.
+Running optimization stage 1 on top .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Jul 27 07:12:33 2020
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 66MB peak: 67MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Jul 27 07:12:33 2020
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+@W:: Distributed compilation : All files are passed to distribution points
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top.verilog "
+Compiling work_top_verilog as a separate process
+Compilation of node work.top finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name              Status      Start time     End Time       Total Real Time     Log File                                                                                
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+===========================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 67MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Jul 27 07:12:35 2020
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Jul 27 07:12:35 2020
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 67MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Jul 27 07:12:37 2020
+
+###########################################################]
+Premap Report
+
+# Mon Jul 27 07:12:37 2020
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+
+Clock Summary
+******************
+
+          Start       Requested     Requested     Clock        Clock                   Clock
+Level     Clock       Frequency     Period        Type         Group                   Load 
+--------------------------------------------------------------------------------------------
+0 -       top|clk     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     2    
+============================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+            Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
+Clock       Load      Pin           Seq Example     Seq Example       Comb Example 
+-----------------------------------------------------------------------------------
+top|clk     2         clk(port)     cnt[1:0].C      -                 -            
+===================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top.v":25:0:25:5|Found inferred clock top|clk which controls 2 sequential elements including cnt[1:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 2 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       clk                 Unconstrained_port     2          cnt[1:0]       
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 54MB peak: 141MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon Jul 27 07:12:37 2020
+
+###########################################################]
+Map & Optimize Report
+
+# Mon Jul 27 07:12:37 2020
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031430
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:00s		     3.78ns		   2 /         2
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 141MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+@W: MT420 |Found inferred clock top|clk with period 5.00ns. Please declare a user-defined clock on port clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon Jul 27 07:12:39 2020
+#
+
+
+Top view:               top
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 3.596
+
+                   Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
+---------------------------------------------------------------------------------------------------------------------
+top|clk            200.0 MHz     712.3 MHz     5.000         1.404         3.596     inferred     Inferred_clkgroup_0
+=====================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks             |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending   |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+top|clk   top|clk  |  5.000       3.596  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: top|clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                       Arrival          
+Instance     Reference     Type        Pin     Net          Time        Slack
+             Clock                                                           
+-----------------------------------------------------------------------------
+cnt[0]       top|clk       FD1S3IX     Q       CO0          0.838       3.596
+cnt[1]       top|clk       FD1S3IX     Q       cnt_c[1]     0.798       3.648
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                         Required          
+Instance     Reference     Type        Pin     Net            Time         Slack
+             Clock                                                              
+--------------------------------------------------------------------------------
+cnt[0]       top|clk       FD1S3IX     D       CO0_i          4.789        3.596
+cnt[1]       top|clk       FD1S3IX     D       cnt_RNO[1]     4.789        3.608
+================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.193
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     3.596
+
+    Number of logic level(s):                1
+    Starting point:                          cnt[0] / Q
+    Ending point:                            cnt[0] / D
+    The start point is clocked by            top|clk [rising] on pin CK
+    The end   point is clocked by            top|clk [rising] on pin CK
+
+Instance / Net                 Pin      Pin               Arrival     No. of    
+Name               Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------
+cnt[0]             FD1S3IX     Q        Out     0.838     0.838       -         
+CO0                Net         -        -       -         -           3         
+cnt_RNO[0]         INV         A        In      0.000     0.838       -         
+cnt_RNO[0]         INV         Z        Out     0.355     1.193       -         
+CO0_i              Net         -        -       -         -           1         
+cnt[0]             FD1S3IX     D        In      0.000     1.193       -         
+================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.181
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 3.608
+
+    Number of logic level(s):                1
+    Starting point:                          cnt[0] / Q
+    Ending point:                            cnt[1] / D
+    The start point is clocked by            top|clk [rising] on pin CK
+    The end   point is clocked by            top|clk [rising] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+cnt[0]             FD1S3IX      Q        Out     0.838     0.838       -         
+CO0                Net          -        -       -         -           3         
+cnt_RNO[1]         ORCALUT4     A        In      0.000     0.838       -         
+cnt_RNO[1]         ORCALUT4     Z        Out     0.343     1.181       -         
+cnt_RNO[1]         Net          -        -       -         -           1         
+cnt[1]             FD1S3IX      D        In      0.000     1.181       -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.141
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 3.648
+
+    Number of logic level(s):                1
+    Starting point:                          cnt[1] / Q
+    Ending point:                            cnt[1] / D
+    The start point is clocked by            top|clk [rising] on pin CK
+    The end   point is clocked by            top|clk [rising] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+cnt[1]             FD1S3IX      Q        Out     0.798     0.798       -         
+cnt_c[1]           Net          -        -       -         -           2         
+cnt_RNO[1]         ORCALUT4     B        In      0.000     0.798       -         
+cnt_RNO[1]         ORCALUT4     Z        Out     0.343     1.141       -         
+cnt_RNO[1]         Net          -        -       -         -           1         
+cnt[1]             FD1S3IX      D        In      0.000     1.141       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 2 of 43848 (0%)
+PIC Latch:       0
+I/O cells:       4
+
+
+Details:
+FD1S3IX:        2
+GSR:            1
+IB:             2
+INV:            1
+OB:             2
+ORCALUT4:       1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon Jul 27 07:12:39 2020
+
+###########################################################]
diff --git a/impl1/containment_cfg_verif.txt b/impl1/containment_cfg_verif.txt
new file mode 100644
index 0000000..ba51e5d
--- /dev/null
+++ b/impl1/containment_cfg_verif.txt
@@ -0,0 +1,41 @@
+top_tf.fifo_colector_inst.fifo40_inst work fifo40_dc 0 1
+top_tf.fifo_colector_inst work fifo_colector 0 1
+top_tf.trb_adapter_inst work trb_adapter 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_neg_inst work output_decoder8 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_inst work output_decoder8 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst work tdc4ddr_short 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst work tdc4ddr_short 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.trig_inv_inst1 work trig_inv 0 1
+top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst work hades_tdc_channel_raw_out 0 1
+top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst work output_decoder8 0 1
+top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst work tdc4ddr_short 0 1
+top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst work hades_LVL1_raw_out 0 1
+top_tf.hades_tdc_bundle_inst work hades_tdc_bundle 0 1
+top_tf.pll0inst work pll0 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1
+top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1
+top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1
+top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1
diff --git a/impl1/containment_xmr_verif.txt b/impl1/containment_xmr_verif.txt
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/dm/layer0.xdm b/impl1/dm/layer0.xdm
new file mode 100644
index 0000000..85ff6d9
--- /dev/null
+++ b/impl1/dm/layer0.xdm
@@ -0,0 +1,2437 @@
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+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_attr.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc
+INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real
+INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/synattr.vhd
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes
+(VERI-1482) Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/modules2.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top2.v
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(181,22-181,35) (VERI-1116) fifo_data_out is already declared
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(64,46-64,59) (VERI-1967) previous declaration of fifo_data_out is from here
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(181,22-181,35) (VERI-1329) second declaration of fifo_data_out ignored
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(64,46-64,59) (VERI-1310) fifo_data_out is declared here
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_modules.v
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(170,13-170,24) (VERI-1362) decoder_out is already implicitly declared on line 156
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(171,13-171,28) (VERI-1362) decoder_out_neg is already implicitly declared on line 163
+(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_colector.v
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(1,24-1,30) (VERI-1128) wr_clk is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(2,9-2,15) (VERI-1128) rd_clk is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(3,9-3,14) (VERI-1128) reset is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(4,9-4,16) (VERI-1128) in_data is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(5,9-5,17) (VERI-1128) in_empty is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(6,9-6,23) (VERI-1128) in_read_enable is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(7,9-7,17) (VERI-1128) out_data is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(8,9-8,18) (VERI-1128) out_empty is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(9,9-9,24) (VERI-1128) out_read_enable is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(10,9-10,16) (VERI-1128) discard is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(12,9-12,19) (VERI-1128) raw_enable is not declared
+ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(1,1-21,10) (VERI-1072) module hades_colector ignored due to previous errors
+(VERI-1483) Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_colector.v ignored due to errors
+(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.vhd
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(235,8-235,15) (VHDL-1012) analyzing entity intface
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(278,14-278,23) (VHDL-1010) analyzing architecture intface_a
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(50,8-50,13) (VHDL-1012) analyzing entity modem
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(70,14-70,21) (VHDL-1010) analyzing architecture modem_a
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(50,8-50,14) (VHDL-1012) analyzing entity rxcver
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(76,14-76,22) (VHDL-1010) analyzing architecture rxcver_a
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(50,8-50,14) (VHDL-1012) analyzing entity txmitt
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(74,14-74,22) (VHDL-1010) analyzing architecture txmitt_a
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(50,8-50,16) (VHDL-1012) analyzing entity uart_top
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(85,14-85,24) (VHDL-1010) analyzing architecture uart_top_a
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd
+INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(8,8-8,15) (VHDL-1012) analyzing entity trb5_tb
+INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(12,14-12,24) (VHDL-1010) analyzing architecture behavioral
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(9,8-9,18) (VHDL-1012) analyzing entity endp_dummy
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(28,14-28,24) (VHDL-1010) analyzing architecture behavioral
+(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(11,8-11,20) (VHDL-1012) analyzing entity endp_handler
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(30,14-30,24) (VHDL-1010) analyzing architecture behavioral
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v(8,8-8,12) (VERI-1018) compiling module pll1
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v(8,1-75,10) (VERI-9000) elaborating module 'pll1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(47,8-47,31) (VERI-1018) compiling module UART_VerilogWrapper_TOP
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(47,1-127,10) (VERI-9000) elaborating module 'UART_VerilogWrapper_TOP'
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(103,6-125,8) (VERI-1231) going to vhdl side to elaborate module uart_top
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(50,8-50,16) (VHDL-1067) elaborating Uart_top_uniq_0(Uart_top_a)
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(235,8-235,15) (VHDL-1067) elaborating Intface_uniq_0(Intface_a)
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(50,8-50,13) (VHDL-1067) elaborating Modem_uniq_0(Modem_a)
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(50,8-50,14) (VHDL-1067) elaborating Rxcver_uniq_0(Rxcver_a)
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(50,8-50,14) (VHDL-1067) elaborating Txmitt_uniq_0(Txmitt_a)
+INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(103,6-125,8) (VERI-1232) back to verilog to continue elaboration
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v(8,8-8,12) (VERI-1018) compiling module pll8
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v(8,1-80,10) (VERI-9000) elaborating module 'pll8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v(8,8-8,18) (VERI-1018) compiling module pll_random
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v(8,1-85,10) (VERI-9000) elaborating module 'pll_random'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(191,8-191,15) (VERI-1018) compiling module tdc4ddr
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(191,1-234,10) (VERI-9000) elaborating module 'tdc4ddr'
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,8-1,14) (VERI-1018) compiling module top_tf
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,1-228,10) (VERI-9000) elaborating module 'top_tf'
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v(8,1-90,10) (VERI-9000) elaborating module 'pll0_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(2,1-194,10) (VERI-9000) elaborating module 'hades_tdc_bundle_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(230,1-319,11) (VERI-9000) elaborating module 'trb_adapter_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(3,1-95,10) (VERI-9000) elaborating module 'fifo_colector_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_4'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(2,1-106,10) (VERI-9000) elaborating module 'hades_LVL1_raw_out_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(110,1-216,10) (VERI-9000) elaborating module 'hades_tdc_channel_raw_out_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v(8,1-1114,10) (VERI-9000) elaborating module 'fifo40_dc_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_5'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_26'
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,1-228,10) (VERI-9000) elaborating module 'top_tf'
+INFO - /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v(8,1-90,10) (VERI-9000) elaborating module 'pll0_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(2,1-194,10) (VERI-9000) elaborating module 'hades_tdc_bundle_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(230,1-319,11) (VERI-9000) elaborating module 'trb_adapter_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(3,1-95,10) (VERI-9000) elaborating module 'fifo_colector_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_4'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_5'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_6'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_7'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_8'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_9'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_4'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_5'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_6'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_7'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_8'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_9'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_4'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_5'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_6'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_7'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_8'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_9'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_4'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(2,1-106,10) (VERI-9000) elaborating module 'hades_LVL1_raw_out_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(110,1-216,10) (VERI-9000) elaborating module 'hades_tdc_channel_raw_out_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v(8,1-1114,10) (VERI-9000) elaborating module 'fifo40_dc_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_59'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_60'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_61'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_62'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_63'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_64'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_65'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_66'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_67'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_68'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_69'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_70'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_71'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_72'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_59'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_60'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_61'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_62'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_63'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_64'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_65'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_66'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_67'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_68'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_69'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_70'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_71'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_72'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_73'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_74'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_75'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_76'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_77'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_78'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_79'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_80'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_81'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_82'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_83'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_84'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_85'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_86'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_87'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_88'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_89'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_90'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_91'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_92'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_93'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_94'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_95'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_96'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_59'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_60'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_61'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_62'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_63'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_64'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_65'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_66'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_67'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_68'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_69'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_70'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_71'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_72'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_73'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_74'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_75'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_76'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_77'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_78'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_79'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_80'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_81'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_82'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_83'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_84'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_85'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_86'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_87'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_88'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_89'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_90'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_91'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_92'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_93'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_94'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_95'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_96'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_97'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_98'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_99'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_100'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_101'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_102'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_103'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_104'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_105'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_106'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_107'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_108'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_109'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_110'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_111'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_112'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_113'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_114'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_115'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_116'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_117'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_118'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_119'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_120'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_121'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_122'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_123'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_124'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_125'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_126'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_127'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_128'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_129'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_130'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_131'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_132'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_133'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_134'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_135'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_136'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_137'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_138'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_139'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_140'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_141'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_142'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_143'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_144'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_145'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_146'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_147'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_148'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_149'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_150'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_151'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_152'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_153'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_154'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_155'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_156'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_157'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_158'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_159'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_160'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_161'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_162'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_163'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_164'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_165'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_166'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_167'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_168'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_169'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_170'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_171'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_172'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_173'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_174'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_175'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_176'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_177'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_178'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_179'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_180'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_181'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_182'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_183'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_184'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_185'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_186'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_187'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_188'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_189'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_190'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_191'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_192'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_193'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_194'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_195'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_196'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_197'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_198'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_199'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_200'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_201'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_202'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_203'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_204'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_205'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_206'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_207'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_208'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_209'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_210'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_211'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_212'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_213'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_214'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_215'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_216'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_217'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_218'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_219'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_220'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_221'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_222'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_223'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_224'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_225'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_226'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_227'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_228'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_229'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_230'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_231'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_232'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_59'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_60'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_61'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_62'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_63'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_64'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_65'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_66'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_67'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_68'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_69'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_70'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_71'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_72'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_73'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_74'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_75'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_76'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_77'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_78'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_79'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_80'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_81'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_82'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_83'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_84'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_85'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_86'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_87'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_88'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_89'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_90'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_91'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_92'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_93'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_94'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_95'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_96'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_97'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_98'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_99'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_100'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_101'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_102'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_103'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_104'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_105'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_106'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_107'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_108'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_109'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_110'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_111'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_112'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_113'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_114'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_115'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_116'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_117'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_118'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_119'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_120'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_121'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_122'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_123'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_124'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_125'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_126'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_127'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_128'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_129'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_130'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_131'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_132'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_133'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_134'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_135'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_136'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_137'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_138'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_139'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_140'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_141'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_142'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_143'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_144'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_145'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_146'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_147'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_148'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_149'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_150'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_151'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_152'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_153'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_154'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_155'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_156'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_157'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_158'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_159'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_160'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_161'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_162'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_163'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_164'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_59'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_60'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_61'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_62'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_63'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_64'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_65'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_66'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_67'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_68'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_69'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_70'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_71'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_72'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_73'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_74'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_75'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_76'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_77'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_78'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_79'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_80'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_81'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_82'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_83'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_84'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_85'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_86'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_87'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_88'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_89'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_90'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_91'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_92'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_93'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_94'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_95'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_96'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_97'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_98'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_99'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_100'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_101'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_102'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_103'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_104'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_5'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_1'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_2'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_3'
+INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_45'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_46'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_47'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_48'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_49'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_50'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_51'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_52'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_53'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_54'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_55'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_56'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_57'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_58'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_26'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_27'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_28'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_29'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_30'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_31'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_32'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_33'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_34'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_35'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_36'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_37'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_38'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_39'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_40'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_41'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_1'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_2'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_3'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_4'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_5'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_6'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_7'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_8'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_9'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_10'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_11'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_12'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_13'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_14'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_15'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_16'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_17'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_18'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_19'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_20'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_21'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_22'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_23'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_24'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_25'
+INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_26'
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(137,11-137,37) (VERI-1330) actual bit length 9 differs from formal bit length 12 for port LVL1_offset
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(51,2-56,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(153,2-158,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(160,2-165,40) (VERI-1927) port in_synced_lb remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(187,22-187,59) (VERI-1330) actual bit length 1 differs from formal bit length 2 for port raw_valid_vect
+WARNING - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(40,1-51,9) (VERI-1927) port RPReset remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(194,9-194,33) (VERI-1330) actual bit length 32 differs from formal bit length 40 for port out_data
+WARNING - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(47,7-47,17) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port Reset
+WARNING - /home/hadaq/mmichalek/lattice/simplified/modules2.v(83,2-88,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/modules2.v(90,2-95,40) (VERI-1927) port in_synced_lb remains unconnected for this instance
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(209,11-209,26) (VERI-1330) actual bit length 20 differs from formal bit length 28 for port coarse
+WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(211,11-211,64) (VERI-1330) actual bit length 24 differs from formal bit length 32 for port fifo_data_out
+INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(8,8-8,15) (VHDL-1067) elaborating trb5_tb(Behavioral)
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(11,8-11,20) (VHDL-1067) elaborating endp_handler_uniq_0(Behavioral)
+INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(9,8-9,18) (VHDL-1067) elaborating endp_dummy_uniq_0(Behavioral)
+Done: design load finished with (12) errors, and (16) warnings
+
+</PRE></BODY></HTML>
\ No newline at end of file
diff --git a/impl1/impl1_syn.prj b/impl1/impl1_syn.prj
new file mode 100644
index 0000000..9ef85f1
--- /dev/null
+++ b/impl1/impl1_syn.prj
@@ -0,0 +1,87 @@
+#--  Synopsys, Inc.
+#--  Version O-2018.09-SP1
+#--  Project file /home/hadaq/mmichalek/lattice/simplified/impl1/impl1_syn.prj
+#--  Written on Sun Jan 24 23:19:27 2021
+
+
+#project files
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top.v"
+add_file -verilog "../pll0/pll0.v"
+add_file -verilog "../pll1/pll1.v"
+add_file -verilog "../fifo32dc/fifo32dc.v"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd"
+add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"
+add_file -verilog "../pll8/pll8.v"
+add_file -verilog "../pll_random/pll_random.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules.v"
+
+
+
+#implementation: "impl1"
+impl -add impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std sysv
+set_option -project_relative_includes 1
+set_option -hdl_define -set SBP_SYNTHESIS
+set_option -include_path {/home/hadaq/mmichalek/lattice/simplified}
+
+#device options
+set_option -technology ECP5UM5G
+set_option -part LFE5UM5G_45F
+set_option -package BG381C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "top"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency auto
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr no
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./impl1.edi"
+impl -active "impl1"
diff --git a/impl1/launch_synplify.tcl b/impl1/launch_synplify.tcl
new file mode 100644
index 0000000..9b2387b
--- /dev/null
+++ b/impl1/launch_synplify.tcl
@@ -0,0 +1,66 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/hadaq/mmichalek/lattice/simplified/impl1/launch_synplify.tcl
+#-- Written on Sun Jan 24 23:19:20 2021
+
+project -close
+set filename "/home/hadaq/mmichalek/lattice/simplified/impl1/impl1_syn.prj"
+if ([file exists "$filename"]) {
+	project -load "$filename"
+	project_file -remove *
+} else {
+	project -new "$filename"
+}
+set create_new 0
+
+#device options
+set_option -technology ECP5UM5G
+set_option -part LFE5UM5G_45F
+set_option -package BG381C
+set_option -speed_grade -8
+
+if {$create_new == 1} {
+#-- add synthesis options
+	set_option -symbolic_fsm_compiler true
+	set_option -resource_sharing false
+	set_option -vlog_std v2001
+	set_option -frequency 200
+	set_option -maxfan 1000
+	set_option -auto_constrain_io 0
+	set_option -disable_io_insertion false
+	set_option -retiming false; set_option -pipe true
+	set_option -force_gsr auto
+	set_option -compiler_compatible 0
+	set_option -dup false
+	
+	set_option -default_enum_encoding default
+	
+	set_option -num_critical_paths 3
+	
+	set_option -write_apr_constraint 1
+	set_option -fix_gated_and_generated_clocks 1
+	set_option -update_models_cp 0
+	set_option -resolve_multiple_driver 0
+	
+	
+	
+}
+#-- add_file options
+set_option -hdl_define -set SBP_SYNTHESIS
+set_option -include_path "/home/hadaq/mmichalek/lattice/simplified"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v"
+add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd"
+add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd"
+add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd"
+add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd"
+add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd"
+add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules.v"
+#-- top module name
+set_option -top_module {top}
+project -result_file {/home/hadaq/mmichalek/lattice/simplified/impl1/impl1.edi}
+project -save "$filename"
diff --git a/impl1/message.xml b/impl1/message.xml
new file mode 100644
index 0000000..c5b5771
--- /dev/null
+++ b/impl1/message.xml
@@ -0,0 +1,599 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliMessageLog>
+    <Task name="Map">
+        <Message>
+            <ID>1100086</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic error in &quot;BLOCK NET &quot;tdc_out*&quot; ;&quot;: </Dynamic>
+            <Dynamic>tdc_out*</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>10</Navigation>
+        </Message>
+        <Message>
+            <ID>1100679</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic error in &quot;LOCATE COMP &quot;reset&quot; SITE &quot;D11&quot; ;&quot;: </Dynamic>
+            <Dynamic>reset</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>48</Navigation>
+        </Message>
+        <Message>
+            <ID>1101611</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic error in &quot;UGROUP &quot;trig_gate0&quot; BBOX 1 1 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO
+	BLKNAME trig_pad_RNII4FF[0];&quot;: </Dynamic>
+            <Dynamic>Block &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2&quot; of UGROUP &quot;trig_gate0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO&quot; of UGROUP &quot;trig_gate0&quot; not found in design</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>59</Navigation>
+        </Message>
+        <Message>
+            <ID>1100675</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic error in &quot;LOCATE UGROUP &quot;trig_gate0&quot; SITE &quot;R68C13D&quot; ;&quot;: </Dynamic>
+            <Dynamic>trig_gate0</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>60</Navigation>
+        </Message>
+        <Message>
+            <ID>1101611</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic error in &quot;UGROUP &quot;tdc_ch0&quot; BBOX 1 6 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de   ....   _inst/dec_inst/out_internal[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;&quot;: </Dynamic>
+            <Dynamic>Block &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_cha   ....   out_internal[1]&quot; of UGROUP &quot;tdc_ch0&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]&quot; of UGROUP &quot;tdc_ch0&quot; not found in design</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>95</Navigation>
+        </Message>
+        <Message>
+            <ID>1100675</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic error in &quot;LOCATE UGROUP &quot;tdc_ch0&quot; SITE &quot;R67C14D&quot; ;&quot;: </Dynamic>
+            <Dynamic>tdc_ch0</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>96</Navigation>
+        </Message>
+        <Message>
+            <ID>1101611</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic error in &quot;UGROUP &quot;tdc2&quot; BBOX 1 6 
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_   ....   st/dec_inst/valid
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;&quot;: </Dynamic>
+            <Dynamic>Block &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].td   ....   ternal[2]&quot; of UGROUP &quot;tdc2&quot; not found in designBlock &quot;genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0&quot; of UGROUP &quot;tdc2&quot; not found in design</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>141</Navigation>
+        </Message>
+        <Message>
+            <ID>1100675</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic error in &quot;LOCATE UGROUP &quot;tdc2&quot; SITE &quot;R65C41D&quot; ;&quot;: </Dynamic>
+            <Dynamic>tdc2</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>142</Navigation>
+        </Message>
+        <Message>
+            <ID>1101611</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic error in &quot;UGROUP &quot;dec3&quot; BBOX 1 6 
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_   ....   st/dec_inst/valid
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;&quot;: </Dynamic>
+            <Dynamic>Block &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].td   ....   ternal[2]&quot; of UGROUP &quot;dec3&quot; not found in designBlock &quot;genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0&quot; of UGROUP &quot;dec3&quot; not found in design</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>264</Navigation>
+        </Message>
+        <Message>
+            <ID>1100675</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic error in &quot;LOCATE UGROUP &quot;dec3&quot; SITE &quot;R65C49D&quot; ;&quot;: </Dynamic>
+            <Dynamic>dec3</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>265</Navigation>
+        </Message>
+        <Message>
+            <ID>1101611</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic error in &quot;UGROUP &quot;tdc0_neg&quot; BBOX 1 4 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_   ....   enblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7];&quot;: </Dynamic>
+            <Dynamic>Block &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]&quot; of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]&quot; of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b   ....   of UGROUP &quot;tdc0_neg&quot; not found in designBlock &quot;genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]&quot; of UGROUP &quot;tdc0_neg&quot; not found in design</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>289</Navigation>
+        </Message>
+        <Message>
+            <ID>1100675</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic error in &quot;LOCATE UGROUP &quot;tdc0_neg&quot; SITE &quot;R69C14D&quot; ;&quot;: </Dynamic>
+            <Dynamic>tdc0_neg</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/s1.lpf</Navigation>
+            <Navigation>290</Navigation>
+        </Message>
+        <Message>
+            <ID>1104614</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>Semantic error in &quot;PGROUP &quot;lvl1_dec&quot; BBOX 1 6  DEVSIZE
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464&quot;
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465&quot;
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474&quot;
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_ins   ....   inst/SLICE_734&quot;
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735&quot;
+	COMP &quot;hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736&quot;;&quot;: </Dynamic>
+            <Dynamic>lvl1_dec</Dynamic>
+        </Message>
+    </Task>
+    <Task name="Lattice_Synthesis">
+        <Message>
+            <ID>35002000</ID>
+            <Severity>Info</Severity>
+        </Message>
+        <Message>
+            <ID>35001781</ID>
+            <Severity>Info</Severity>
+        </Message>
+        <Message>
+            <ID>35901018</ID>
+            <Severity>Info</Severity>
+            <Dynamic>/home/hadaq/mmichalek/lattice/simplified/top.v(1): </Dynamic>
+            <Dynamic>top</Dynamic>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top.v</Navigation>
+            <Navigation>1</Navigation>
+        </Message>
+        <Message>
+            <ID>35001611</ID>
+            <Severity>Warning</Severity>
+        </Message>
+        <Message>
+            <ID>1166052</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>logical</Dynamic>
+            <Dynamic>GND_net</Dynamic>
+            <Navigation>GND_net</Navigation>
+        </Message>
+        <Message>
+            <ID>1163101</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>1</Dynamic>
+        </Message>
+    </Task>
+    <Task name="TimingSimFileVHD">
+        <Message>
+            <ID>35400250</ID>
+            <Severity>Info</Severity>
+            <Dynamic>0</Dynamic>
+        </Message>
+    </Task>
+    <Task name="TimingSimFileVlg">
+        <Message>
+            <ID>35400250</ID>
+            <Severity>Info</Severity>
+            <Dynamic>0</Dynamic>
+        </Message>
+    </Task>
+    <Task name="Translate">
+        <Message>
+            <ID>1121027</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MEM_INIT_FILE</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121027</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MEM_INIT_FILE</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121027</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MEM_INIT_FILE</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121027</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MEM_INIT_FILE</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>TDC_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>COARSE_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>WINDOW_LENGTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>TDC_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>COARSE_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>ADDRESS_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>COARSE_WIDTH_INTERNAL</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>HITBUFFER_DEPTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>TDC_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>COARSE_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>TRIG_WIDTH</Dynamic>
+        </Message>
+        <Message>
+            <ID>1121028</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>ADDRESS_WIDTH</Dynamic>
+        </Message>
+    </Task>
+    <Task name="Synplify_Synthesis">
+        <Message>
+            <ID>2011000</ID>
+            <Severity>Info</Severity>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG921 :&quot;/home/hadaq/mmichalek/lattice/simplified/top2.v&quot;:181:21:181:33|fifo_data_out is already declared in this scope.</Dynamic>
+            <Navigation>CG921</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>21</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>33</Navigation>
+            <Navigation>fifo_data_out is already declared in this scope.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1337 :&quot;/home/hadaq/mmichalek/lattice/simplified/top2.v&quot;:270:9:270:24|Net buf_rden_falling is not declared.</Dynamic>
+            <Navigation>CG1337</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top2.v</Navigation>
+            <Navigation>270</Navigation>
+            <Navigation>9</Navigation>
+            <Navigation>270</Navigation>
+            <Navigation>24</Navigation>
+            <Navigation>Net buf_rden_falling is not declared.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1249 :&quot;/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v&quot;:170:12:170:22|Redeclaration of implicit signal decoder_out</Dynamic>
+            <Navigation>CG1249</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v</Navigation>
+            <Navigation>170</Navigation>
+            <Navigation>12</Navigation>
+            <Navigation>170</Navigation>
+            <Navigation>22</Navigation>
+            <Navigation>Redeclaration of implicit signal decoder_out</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1249 :&quot;/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v&quot;:171:12:171:26|Redeclaration of implicit signal decoder_out_neg</Dynamic>
+            <Navigation>CG1249</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v</Navigation>
+            <Navigation>171</Navigation>
+            <Navigation>12</Navigation>
+            <Navigation>171</Navigation>
+            <Navigation>26</Navigation>
+            <Navigation>Redeclaration of implicit signal decoder_out_neg</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG921 :&quot;/home/hadaq/mmichalek/lattice/simplified/top2.v&quot;:181:21:181:33|fifo_data_out is already declared in this scope.</Dynamic>
+            <Navigation>CG921</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>21</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>33</Navigation>
+            <Navigation>fifo_data_out is already declared in this scope.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1337 :&quot;/home/hadaq/mmichalek/lattice/simplified/top2.v&quot;:270:9:270:24|Net buf_rden_falling is not declared.</Dynamic>
+            <Navigation>CG1337</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top2.v</Navigation>
+            <Navigation>270</Navigation>
+            <Navigation>9</Navigation>
+            <Navigation>270</Navigation>
+            <Navigation>24</Navigation>
+            <Navigation>Net buf_rden_falling is not declared.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1249 :&quot;/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v&quot;:170:12:170:22|Redeclaration of implicit signal decoder_out</Dynamic>
+            <Navigation>CG1249</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v</Navigation>
+            <Navigation>170</Navigation>
+            <Navigation>12</Navigation>
+            <Navigation>170</Navigation>
+            <Navigation>22</Navigation>
+            <Navigation>Redeclaration of implicit signal decoder_out</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>CG1249 :&quot;/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v&quot;:171:12:171:26|Redeclaration of implicit signal decoder_out_neg</Dynamic>
+            <Navigation>CG1249</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v</Navigation>
+            <Navigation>171</Navigation>
+            <Navigation>12</Navigation>
+            <Navigation>171</Navigation>
+            <Navigation>26</Navigation>
+            <Navigation>Redeclaration of implicit signal decoder_out_neg</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN114 :&quot;/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v&quot;:407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.</Dynamic>
+            <Navigation>BN114</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v</Navigation>
+            <Navigation>407</Navigation>
+            <Navigation>13</Navigation>
+            <Navigation>407</Navigation>
+            <Navigation>25</Navigation>
+            <Navigation>Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT529 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
+            <Navigation>MT529</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>3</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>8</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT529 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
+            <Navigation>MT529</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>3</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>8</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT529 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
+            <Navigation>MT529</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>3</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>8</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT529 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
+            <Navigation>MT529</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>3</Navigation>
+            <Navigation>181</Navigation>
+            <Navigation>8</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT529 :&quot;/home/hadaq/mmichalek/lattice/simplified/top2.v&quot;:305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
+            <Navigation>MT529</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/top2.v</Navigation>
+            <Navigation>305</Navigation>
+            <Navigation>2</Navigation>
+            <Navigation>305</Navigation>
+            <Navigation>7</Navigation>
+            <Navigation>Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>BN132 :&quot;/home/hadaq/mmichalek/lattice/simplified/modules2.v&quot;:138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Dynamic>
+            <Navigation>BN132</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/modules2.v</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>1</Navigation>
+            <Navigation>138</Navigation>
+            <Navigation>6</Navigation>
+            <Navigation>Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</Navigation>
+        </Message>
+        <Message>
+            <ID>2019991</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT246 :&quot;/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v&quot;:60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)</Dynamic>
+            <Navigation>MT246</Navigation>
+            <Navigation>/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v</Navigation>
+            <Navigation>60</Navigation>
+            <Navigation>12</Navigation>
+            <Navigation>60</Navigation>
+            <Navigation>20</Navigation>
+            <Navigation>Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)</Navigation>
+        </Message>
+        <Message>
+            <ID>2019993</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].</Dynamic>
+            <Navigation>MT420</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].</Navigation>
+        </Message>
+        <Message>
+            <ID>2019993</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].</Dynamic>
+            <Navigation>MT420</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].</Navigation>
+        </Message>
+        <Message>
+            <ID>2019993</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].</Dynamic>
+            <Navigation>MT420</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].</Navigation>
+        </Message>
+        <Message>
+            <ID>2019993</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].</Dynamic>
+            <Navigation>MT420</Navigation>
+            <Navigation>Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].</Navigation>
+        </Message>
+        <Message>
+            <ID>2019993</ID>
+            <Severity>Warning</Severity>
+            <Dynamic>MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.</Dynamic>
+            <Navigation>MT420</Navigation>
+            <Navigation>Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.</Navigation>
+        </Message>
+    </Task>
+</BaliMessageLog>
\ No newline at end of file
diff --git a/impl1/run_options.txt b/impl1/run_options.txt
new file mode 100644
index 0000000..f585b1f
--- /dev/null
+++ b/impl1/run_options.txt
@@ -0,0 +1,100 @@
+#--  Synopsys, Inc.
+#--  Version O-2018.09-SP1
+#--  Project file /home/hadaq/mmichalek/lattice/simplified/impl1/run_options.txt
+#--  Written on Wed Jun 16 09:19:13 2021
+
+
+#project files
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules2.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top2.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd"
+
+
+
+#implementation: "impl1"
+impl -add impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -hdl_define -set SBP_SYNTHESIS
+set_option -include_path {/home/hadaq/mmichalek/lattice/simplified}
+
+#device options
+set_option -technology ECP5UM5G
+set_option -part LFE5UM5G_45F
+set_option -package BG381C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "top_tf"
+
+# hdl_compiler_options
+set_option -distributed_compile 1
+
+# mapper_without_write_options
+set_option -frequency 200
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 0
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./s1_impl1.edi"
+
+#set log file 
+set_option log_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf" 
+
+#design plan options
+impl -active "impl1"
diff --git a/impl1/s1_impl1.alt b/impl1/s1_impl1.alt
new file mode 100644
index 0000000..2d05fcf
--- /dev/null
+++ b/impl1/s1_impl1.alt
@@ -0,0 +1,90 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Wed May 26 19:57:02 2021 *
+NOTE DESIGN NAME: top_tf *
+NOTE DEVICE NAME: LFE5UM5G-45F-8CABGA381 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS fifo_data_out[0] : B8 : out *
+NOTE PINS clk : P3 : in *
+NOTE PINS release_out : F1 : out *
+NOTE PINS finished : J5 : out *
+NOTE PINS last_buf_empty : H5 : out *
+NOTE PINS discard : E2 : out *
+NOTE PINS burst : F2 : out *
+NOTE PINS LVL1_TRG_DATA_VALI_IN_rising : G3 : out *
+NOTE PINS FEE_TRG_RELEASE_OUT : H2 : out *
+NOTE PINS FEE_DATAFINISHED_OUT : G2 : out *
+NOTE PINS FEE_DATA_WRITE_OUT : G5 : out *
+NOTE PINS FEE_DATA_OUT[31] : C9 : out *
+NOTE PINS FEE_DATA_OUT[30] : C6 : out *
+NOTE PINS FEE_DATA_OUT[29] : C2 : out *
+NOTE PINS FEE_DATA_OUT[28] : C5 : out *
+NOTE PINS FEE_DATA_OUT[27] : A7 : out *
+NOTE PINS FEE_DATA_OUT[26] : A9 : out *
+NOTE PINS FEE_DATA_OUT[25] : F5 : out *
+NOTE PINS FEE_DATA_OUT[24] : D11 : out *
+NOTE PINS FEE_DATA_OUT[23] : E13 : out *
+NOTE PINS FEE_DATA_OUT[22] : H3 : out *
+NOTE PINS FEE_DATA_OUT[21] : B12 : out *
+NOTE PINS FEE_DATA_OUT[20] : A14 : out *
+NOTE PINS FEE_DATA_OUT[19] : A12 : out *
+NOTE PINS FEE_DATA_OUT[18] : C3 : out *
+NOTE PINS FEE_DATA_OUT[17] : E9 : out *
+NOTE PINS FEE_DATA_OUT[16] : C1 : out *
+NOTE PINS FEE_DATA_OUT[15] : C10 : out *
+NOTE PINS FEE_DATA_OUT[14] : E8 : out *
+NOTE PINS FEE_DATA_OUT[13] : A4 : out *
+NOTE PINS FEE_DATA_OUT[12] : A2 : out *
+NOTE PINS FEE_DATA_OUT[11] : C13 : out *
+NOTE PINS FEE_DATA_OUT[10] : D1 : out *
+NOTE PINS FEE_DATA_OUT[9] : B3 : out *
+NOTE PINS FEE_DATA_OUT[8] : C4 : out *
+NOTE PINS FEE_DATA_OUT[7] : D5 : out *
+NOTE PINS FEE_DATA_OUT[6] : A10 : out *
+NOTE PINS FEE_DATA_OUT[5] : A6 : out *
+NOTE PINS FEE_DATA_OUT[4] : D6 : out *
+NOTE PINS FEE_DATA_OUT[3] : D7 : out *
+NOTE PINS FEE_DATA_OUT[2] : D12 : out *
+NOTE PINS FEE_DATA_OUT[1] : D10 : out *
+NOTE PINS FEE_DATA_OUT[0] : C8 : out *
+NOTE PINS LVL1_INVALID_TRG_IN : G1 : in *
+NOTE PINS LVL1_TRG_DATA_VALID_IN : F3 : in *
+NOTE PINS fifo_rden : H4 : out *
+NOTE PINS fifo_data_out[31] : A11 : out *
+NOTE PINS fifo_data_out[30] : C7 : out *
+NOTE PINS fifo_data_out[29] : F4 : out *
+NOTE PINS fifo_data_out[28] : A5 : out *
+NOTE PINS fifo_data_out[27] : A8 : out *
+NOTE PINS fifo_data_out[26] : B10 : out *
+NOTE PINS fifo_data_out[25] : E5 : out *
+NOTE PINS fifo_data_out[24] : E11 : out *
+NOTE PINS fifo_data_out[23] : D13 : out *
+NOTE PINS fifo_data_out[22] : E1 : out *
+NOTE PINS fifo_data_out[21] : C12 : out *
+NOTE PINS fifo_data_out[20] : C14 : out *
+NOTE PINS fifo_data_out[19] : A13 : out *
+NOTE PINS fifo_data_out[18] : D3 : out *
+NOTE PINS fifo_data_out[17] : D9 : out *
+NOTE PINS fifo_data_out[16] : B1 : out *
+NOTE PINS fifo_data_out[15] : B9 : out *
+NOTE PINS fifo_data_out[14] : D8 : out *
+NOTE PINS fifo_data_out[13] : B5 : out *
+NOTE PINS fifo_data_out[12] : B2 : out *
+NOTE PINS fifo_data_out[11] : B13 : out *
+NOTE PINS fifo_data_out[10] : D2 : out *
+NOTE PINS fifo_data_out[9] : B4 : out *
+NOTE PINS fifo_data_out[8] : A3 : out *
+NOTE PINS fifo_data_out[7] : E4 : out *
+NOTE PINS fifo_data_out[6] : C11 : out *
+NOTE PINS fifo_data_out[5] : B6 : out *
+NOTE PINS fifo_data_out[4] : E6 : out *
+NOTE PINS fifo_data_out[3] : E7 : out *
+NOTE PINS fifo_data_out[2] : E12 : out *
+NOTE PINS fifo_data_out[1] : E10 : out *
+NOTE PINS trig[2] : T19 : in *
+NOTE PINS trig[1] : T3 : in *
+NOTE PINS trig[0] : R2 : in *
+NOTE PINS reset_dc : E3 : in *
+NOTE PINS rd_clk : B11 : in *
+NOTE CONFIGURATION MODE: JTAG *
+NOTE COMPRESSION: off *
diff --git a/impl1/s1_impl1.arearep b/impl1/s1_impl1.arearep
new file mode 100644
index 0000000..276b7e0
--- /dev/null
+++ b/impl1/s1_impl1.arearep
@@ -0,0 +1,12 @@
+----------------------------------------------------------------------
+Report for cell top.TECH
+Register bits:  2 of 44457 (0.004%)
+I/O cells:      4
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                            FD1S3IX         2          100.0
+                                GSR         1          100.0
+                                 IB         2          100.0
+                               LUT4         2          100.0
+                                 OB         2          100.0
+                              TOTAL         9
diff --git a/impl1/s1_impl1.areasrr b/impl1/s1_impl1.areasrr
new file mode 100644
index 0000000..422ad73
--- /dev/null
+++ b/impl1/s1_impl1.areasrr
@@ -0,0 +1,490 @@
+----------------------------------------------------------------------
+Report for cell top_tf.verilog
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        8       100.0
+                              CCU2C      121       100.0
+                            EHXPLLL        1       100.0
+                            FD1P3AX       69       100.0
+                            FD1P3BX        8       100.0
+                            FD1P3DX      232       100.0
+                            FD1P3IX       50       100.0
+                            FD1S3AX      321       100.0
+                            FD1S3BX        4       100.0
+                            FD1S3DX      164       100.0
+                            FD1S3IX       41       100.0
+                            FD1S3JX       10       100.0
+                                GSR        1       100.0
+                                 IB       11       100.0
+                           IFS1P3DX        5       100.0
+                                INV       20       100.0
+                                 OB      173       100.0
+                                OBZ        2       100.0
+                           OFS1P3DX       17       100.0
+                           OFS1P3IX       13       100.0
+                                OR2        4       100.0
+                           ORCALUT4      180       100.0
+                           PDPW16KD        4       100.0
+                                PUR        1       100.0
+                           ROM16X1A       96       100.0
+                                VHI       25       100.0
+                                VLO        6       100.0
+                               XOR2       72       100.0
+SUB MODULES 
+                           fifo32dc        1       100.0
+                         fifo32dc_0        1       100.0
+                         fifo32dc_1        1       100.0
+                          fifo40_dc        1       100.0
+                      fifo_colector        1       100.0
+                 hades_LVL1_raw_out        1       100.0
+                   hades_tdc_bundle        1       100.0
+          hades_tdc_channel_raw_out        1       100.0
+                  output_decoder8_0        1       100.0
+                output_decoder8_0_0        1       100.0
+                output_decoder8_0_1        1       100.0
+                  output_decoder8_2        1       100.0
+                output_decoder8_2_0        1       100.0
+                output_decoder8_2_1        1       100.0
+                               pll0        1       100.0
+                      tdc4ddr_short        1       100.0
+                    tdc4ddr_short_0        1       100.0
+                    tdc4ddr_short_1        1       100.0
+                    tdc4ddr_short_2        1       100.0
+                    tdc4ddr_short_3        1       100.0
+                    tdc4ddr_short_4        1       100.0
+               tdc_channel_fifo_out        1       100.0
+             tdc_channel_fifo_out_2        1       100.0
+             tdc_channel_fifo_out_3        1       100.0
+                        trb_adapter        1       100.0
+                           trig_inv        1       100.0
+                            
+                         TOTAL          1685           
+----------------------------------------------------------------------
+Report for cell tdc_channel_fifo_out_3.netlist
+  Original Cell name tdc_channel_fifo_out
+     Instance path:  genblk1[2].tdc_channel_fifo_out_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3AX       49        15.3
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                            FD1S3IX        3         7.3
+                                INV        2        10.0
+                                OR2        1        25.0
+                           ORCALUT4        5         2.8
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        4        16.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+SUB MODULES 
+                         fifo32dc_1        1       100.0
+                output_decoder8_2_1        1       100.0
+                    tdc4ddr_short_4        1       100.0
+                            
+                         TOTAL           241           
+----------------------------------------------------------------------
+Report for cell fifo32dc_1.netlist
+  Original Cell name fifo32dc
+     Instance path:  genblk1[2].tdc_channel_fifo_out_inst.fifo32dc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                                INV        2        10.0
+                                OR2        1        25.0
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        1         4.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+                            
+                         TOTAL           178           
+----------------------------------------------------------------------
+Report for cell output_decoder8_2_1.netlist
+  Original Cell name output_decoder8_2
+     Instance path:  genblk1[2].tdc_channel_fifo_out_inst.dec_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       25         7.8
+                            FD1S3IX        1         2.4
+                           ORCALUT4        4         2.2
+                                VHI        1         4.0
+                            
+                         TOTAL            31           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short_4.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  genblk1[2].tdc_channel_fifo_out_inst.tdc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                VHI        1         4.0
+                            
+                         TOTAL            25           
+----------------------------------------------------------------------
+Report for cell tdc_channel_fifo_out_2.netlist
+  Original Cell name tdc_channel_fifo_out
+     Instance path:  genblk1[1].tdc_channel_fifo_out_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3AX       49        15.3
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                            FD1S3IX        3         7.3
+                                INV        2        10.0
+                                OR2        1        25.0
+                           ORCALUT4        5         2.8
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        4        16.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+SUB MODULES 
+                         fifo32dc_0        1       100.0
+                output_decoder8_2_0        1       100.0
+                    tdc4ddr_short_3        1       100.0
+                            
+                         TOTAL           241           
+----------------------------------------------------------------------
+Report for cell fifo32dc_0.netlist
+  Original Cell name fifo32dc
+     Instance path:  genblk1[1].tdc_channel_fifo_out_inst.fifo32dc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                                INV        2        10.0
+                                OR2        1        25.0
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        1         4.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+                            
+                         TOTAL           178           
+----------------------------------------------------------------------
+Report for cell output_decoder8_2_0.netlist
+  Original Cell name output_decoder8_2
+     Instance path:  genblk1[1].tdc_channel_fifo_out_inst.dec_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       25         7.8
+                            FD1S3IX        1         2.4
+                           ORCALUT4        4         2.2
+                                VHI        1         4.0
+                            
+                         TOTAL            31           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short_3.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  genblk1[1].tdc_channel_fifo_out_inst.tdc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                VHI        1         4.0
+                            
+                         TOTAL            25           
+----------------------------------------------------------------------
+Report for cell tdc_channel_fifo_out.netlist
+  Original Cell name tdc_channel_fifo_out
+     Instance path:  genblk1[0].tdc_channel_fifo_out_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3AX       49        15.3
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                            FD1S3IX        3         7.3
+                                INV        2        10.0
+                                OR2        1        25.0
+                           ORCALUT4        5         2.8
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        4        16.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+SUB MODULES 
+                           fifo32dc        1       100.0
+                  output_decoder8_2        1       100.0
+                    tdc4ddr_short_2        1       100.0
+                            
+                         TOTAL           241           
+----------------------------------------------------------------------
+Report for cell fifo32dc.netlist
+  Original Cell name fifo32dc
+     Instance path:  genblk1[0].tdc_channel_fifo_out_inst.fifo32dc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                                INV        2        10.0
+                                OR2        1        25.0
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        1         4.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+                            
+                         TOTAL           178           
+----------------------------------------------------------------------
+Report for cell output_decoder8_2.netlist
+  Original Cell name output_decoder8
+     Instance path:  genblk1[0].tdc_channel_fifo_out_inst.dec_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       25         7.8
+                            FD1S3IX        1         2.4
+                           ORCALUT4        4         2.2
+                                VHI        1         4.0
+                            
+                         TOTAL            31           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short_2.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  genblk1[0].tdc_channel_fifo_out_inst.tdc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                VHI        1         4.0
+                            
+                         TOTAL            25           
+----------------------------------------------------------------------
+Report for cell fifo_colector.netlist
+     Instance path:  fifo_colector_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3AX       10        14.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1P3IX       24        48.0
+                            FD1S3AX        3         0.9
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                            FD1S3IX        3         7.3
+                                INV        2        10.0
+                                OR2        1        25.0
+                           ORCALUT4       48        26.7
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        2         8.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+SUB MODULES 
+                          fifo40_dc        1       100.0
+                            
+                         TOTAL           268           
+----------------------------------------------------------------------
+Report for cell fifo40_dc.netlist
+     Instance path:  fifo_colector_inst.fifo40_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                               AND2        2        25.0
+                              CCU2C       26        21.5
+                            FD1P3BX        2        25.0
+                            FD1P3DX       58        25.0
+                            FD1S3BX        1        25.0
+                            FD1S3DX       41        25.0
+                                INV        2        10.0
+                                OR2        1        25.0
+                           PDPW16KD        1        25.0
+                           ROM16X1A       24        25.0
+                                VHI        1         4.0
+                                VLO        1        16.7
+                               XOR2       18        25.0
+                            
+                         TOTAL           178           
+----------------------------------------------------------------------
+Report for cell trb_adapter.netlist
+     Instance path:  trb_adapter_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX        6         1.9
+                            FD1S3IX        1         2.4
+                           ORCALUT4        4         2.2
+                                VHI        1         4.0
+                            
+                         TOTAL            12           
+----------------------------------------------------------------------
+Report for cell hades_tdc_bundle.netlist
+     Instance path:  hades_tdc_bundle_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       17        14.0
+                            FD1P3AX       59        85.5
+                            FD1P3IX       26        52.0
+                            FD1S3AX      164        51.1
+                            FD1S3IX       28        68.3
+                            FD1S3JX       10       100.0
+                                INV        6        30.0
+                           ORCALUT4      113        62.8
+                                VHI        9        36.0
+SUB MODULES 
+                 hades_LVL1_raw_out        1       100.0
+          hades_tdc_channel_raw_out        1       100.0
+                  output_decoder8_0        1       100.0
+                output_decoder8_0_0        1       100.0
+                output_decoder8_0_1        1       100.0
+                      tdc4ddr_short        1       100.0
+                    tdc4ddr_short_0        1       100.0
+                    tdc4ddr_short_1        1       100.0
+                           trig_inv        1       100.0
+                            
+                         TOTAL           441           
+----------------------------------------------------------------------
+Report for cell hades_tdc_channel_raw_out.netlist
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C        8         6.6
+                            FD1P3AX       26        37.7
+                            FD1P3IX       24        48.0
+                            FD1S3AX      104        32.4
+                            FD1S3IX        3         7.3
+                            FD1S3JX        6        60.0
+                                INV        1         5.0
+                           ORCALUT4       34        18.9
+                                VHI        5        20.0
+SUB MODULES 
+                output_decoder8_0_0        1       100.0
+                output_decoder8_0_1        1       100.0
+                    tdc4ddr_short_0        1       100.0
+                    tdc4ddr_short_1        1       100.0
+                           trig_inv        1       100.0
+                            
+                         TOTAL           216           
+----------------------------------------------------------------------
+Report for cell output_decoder8_0_1.netlist
+  Original Cell name output_decoder8_0
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_neg_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       28         8.7
+                            FD1S3IX        1         2.4
+                            FD1S3JX        3        30.0
+                           ORCALUT4       13         7.2
+                                VHI        1         4.0
+                            
+                         TOTAL            46           
+----------------------------------------------------------------------
+Report for cell output_decoder8_0_0.netlist
+  Original Cell name output_decoder8_0
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       28         8.7
+                            FD1S3IX        1         2.4
+                            FD1S3JX        3        30.0
+                           ORCALUT4       14         7.8
+                                VHI        1         4.0
+                            
+                         TOTAL            47           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short_1.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                VHI        1         4.0
+                            
+                         TOTAL            25           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short_0.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                VHI        1         4.0
+                            
+                         TOTAL            25           
+----------------------------------------------------------------------
+Report for cell trig_inv.netlist
+     Instance path:  hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.trig_inv_inst1
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                INV        1         5.0
+                            
+                         TOTAL             1           
+----------------------------------------------------------------------
+Report for cell hades_LVL1_raw_out.netlist
+     Instance path:  hades_tdc_bundle_inst.hades_LVL1_raw_out_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C        5         4.1
+                            FD1P3IX        2         4.0
+                            FD1S3AX       60        18.7
+                            FD1S3IX        8        19.5
+                            FD1S3JX        4        40.0
+                                INV        4        20.0
+                           ORCALUT4       44        24.4
+                                VHI        3        12.0
+SUB MODULES 
+                  output_decoder8_0        1       100.0
+                      tdc4ddr_short        1       100.0
+                            
+                         TOTAL           132           
+----------------------------------------------------------------------
+Report for cell output_decoder8_0.netlist
+  Original Cell name output_decoder8
+     Instance path:  hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       29         9.0
+                            FD1S3IX        1         2.4
+                            FD1S3JX        3        30.0
+                                INV        1         5.0
+                           ORCALUT4       15         8.3
+                                VHI        1         4.0
+                            
+                         TOTAL            50           
+----------------------------------------------------------------------
+Report for cell tdc4ddr_short.netlist
+  Original Cell name tdc4ddr_short
+     Instance path:  hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3AX       24         7.5
+                                INV        3        15.0
+                                VHI        1         4.0
+                            
+                         TOTAL            28           
+----------------------------------------------------------------------
+Report for cell pll0.netlist
+     Instance path:  pll0inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            EHXPLLL        1       100.0
+                                VLO        1        16.7
+                            
+                         TOTAL             2           
diff --git a/impl1/s1_impl1.bgn b/impl1/s1_impl1.bgn
new file mode 100644
index 0000000..e325a9a
--- /dev/null
+++ b/impl1/s1_impl1.bgn
@@ -0,0 +1,80 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.11.2.446
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed May 26 19:56:50 2021
+
+
+Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s /home/hadaq/mmichalek/lattice/simplified/s1.sec -k /home/hadaq/mmichalek/lattice/simplified/s1.bek -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+
+Loading design for application Bitgen from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application Bitgen from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from s1_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                        CfgMode  |                      Disable**  |
++---------------------------------+---------------------------------+
+|                        DONE_EX  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                        DONE_OD  |                           ON**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                          2.4**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                    CONFIG_MODE  |                         JTAG**  |
++---------------------------------+---------------------------------+
+|                        WAKE_UP  |                           21**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                     DisableUES  |                        FALSE**  |
++---------------------------------+---------------------------------+
+|            SLAVE_PARALLEL_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                      DONE_PULL  |                           ON**  |
++---------------------------------+---------------------------------+
+|               CONFIG_IOVOLTAGE  |                          2.5**  |
++---------------------------------+---------------------------------+
+|                        TRANSFR  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 10.27.
+ 
+Saving bit stream in "s1_impl1.bit".
+Total CPU Time: 11 secs 
+Total REAL Time: 12 secs 
+Peak Memory Usage: 576 MB
diff --git a/impl1/s1_impl1.bit b/impl1/s1_impl1.bit
new file mode 100644
index 0000000..7ef1eed
Binary files /dev/null and b/impl1/s1_impl1.bit differ
diff --git a/impl1/s1_impl1.dir/5_1.dly b/impl1/s1_impl1.dir/5_1.dly
new file mode 100644
index 0000000..cd0d94a
--- /dev/null
+++ b/impl1/s1_impl1.dir/5_1.dly
@@ -0,0 +1,8546 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:19:35 2021
+
+File: s1_impl1.dir/5_1.dly
+
+ The 20 worst nets by delay are:
+---------------------------------
+| Max Delay         | Netname   |
+---------------------------------
+   4.3                 fifo_rden_c
+   3.7                 trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]
+   3.4                 reset_dl[2]
+   3.3                 FEE_DATA_OUT_c[16]
+   3.3                 hades_dbg2_coarse_c[7]
+   3.2                 FEE_DATA_OUT_c[18]
+   3.2                 FEE_DATA_OUT_c[5]
+   3.1                 FEE_DATA_OUT_c[7]
+   3.1                 FEE_DATA_OUT_c[6]
+   3.0                 FEE_DATA_OUT_c[20]
+   3.0                 hades_dbg2_coarse_c[4]
+   2.9                 FEE_DATA_OUT_c[17]
+   2.9                 FEE_DATA_OUT_c[28]
+   2.9                 FEE_DATA_OUT_c[1]
+   2.9                 hades_dbg2_coarse_c[5]
+   2.9                 FEE_DATA_OUT_c[4]
+   2.9                 FEE_DATA_OUT_c[2]
+   2.8                 FEE_DATA_OUT_c[13]
+   2.8                 FEE_DATA_OUT_c[22]
+   2.8                 FEE_DATA_OUT_c[25]
+---------------------------------
+
+-------------------------------------------------------------------------------
+                               Net Delays
+-------------------------------------------------------------------------------
+
+ANB0
+   hades_tdc_bundle_inst/hit_out_i_RNO[0].Q0
+         0.2  hades_tdc_bundle_inst/hit_out_i_RNO[0].D0
+         0.5  hades_tdc_bundle_inst/hit_out_i_RNO[0].B1
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C1
+         0.9  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].M0
+         0.3  hades_tdc_bundle_inst/buf_finished5_0_a2_0.D0
+         1.4  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.C0
+         0.3  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D0
+         1.5  hades_hit_out_i_pad[0].PADDO
+
+ANB1
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q0
+         0.6  hades_tdc_bundle_inst/hit_out_i_RNO[0].D1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.D1
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].C0
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A1
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.C0
+         0.3  hades_tdc_bundle_inst/buf_finished5_0_a2_0.D1
+         1.3  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.A0
+         0.5  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C1
+         0.5  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.C1
+         1.3  hades_hit_out_i_pad[1].PADDO
+
+ANB2
+   hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].Q0
+         0.9  hades_tdc_bundle_inst/hit_out_i_RNO[0].C1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B1
+         0.6  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B0
+         0.6  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B1
+         1.2  hades_tdc_bundle_inst/buf_finished5_0_a2_0.A0
+         0.9  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.B0
+         1.2  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B0
+         1.2  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B1
+         1.5  hades_hit_out_i_pad[2].PADDO
+
+ANB3
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q1
+         0.7  hades_tdc_bundle_inst/hit_out_i_RNO[0].A1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.A1
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A0
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.B0
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.B1
+         0.8  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.D0
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A1
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A1
+         1.7  hades_hit_out_i_pad[3].PADDO
+
+FEE_DATAFINISHED_OUT_c
+   trb_adapter_inst_FEE_DATAFINISHED_OUTio.IOLDO
+         0.0  FEE_DATAFINISHED_OUT_pad.IOLDO
+
+FEE_DATA_OUT_c[0]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA0
+         2.5  fifo_data_out_pad[0].PADDO
+         2.8  FEE_DATA_OUT_pad[0].PADDO
+
+FEE_DATA_OUT_c[10]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA10
+         2.1  FEE_DATA_OUT_pad[10].PADDO
+         2.1  fifo_data_out_pad[10].PADDO
+
+FEE_DATA_OUT_c[11]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA11
+         2.5  FEE_DATA_OUT_pad[11].PADDO
+         2.5  fifo_data_out_pad[11].PADDO
+
+FEE_DATA_OUT_c[12]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA12
+         2.4  FEE_DATA_OUT_pad[12].PADDO
+         2.6  fifo_data_out_pad[12].PADDO
+
+FEE_DATA_OUT_c[13]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA13
+         2.8  FEE_DATA_OUT_pad[13].PADDO
+         2.8  fifo_data_out_pad[13].PADDO
+
+FEE_DATA_OUT_c[14]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA14
+         2.6  FEE_DATA_OUT_pad[14].PADDO
+         2.8  fifo_data_out_pad[14].PADDO
+
+FEE_DATA_OUT_c[15]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA15
+         2.5  FEE_DATA_OUT_pad[15].PADDO
+         2.1  fifo_data_out_pad[15].PADDO
+
+FEE_DATA_OUT_c[16]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA16
+         3.2  FEE_DATA_OUT_pad[16].PADDO
+         3.3  fifo_data_out_pad[16].PADDO
+
+FEE_DATA_OUT_c[17]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA17
+         2.8  FEE_DATA_OUT_pad[17].PADDO
+         2.9  fifo_data_out_pad[17].PADDO
+
+FEE_DATA_OUT_c[18]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB0
+         2.8  FEE_DATA_OUT_pad[18].PADDO
+         3.2  fifo_data_out_pad[18].PADDO
+
+FEE_DATA_OUT_c[19]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB1
+         2.2  FEE_DATA_OUT_pad[19].PADDO
+         2.2  fifo_data_out_pad[19].PADDO
+
+FEE_DATA_OUT_c[1]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA1
+         2.9  FEE_DATA_OUT_pad[1].PADDO
+         2.9  fifo_data_out_pad[1].PADDO
+
+FEE_DATA_OUT_c[20]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB2
+         2.8  FEE_DATA_OUT_pad[20].PADDO
+         3.0  fifo_data_out_pad[20].PADDO
+
+FEE_DATA_OUT_c[21]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB3
+         2.4  FEE_DATA_OUT_pad[21].PADDO
+         2.3  fifo_data_out_pad[21].PADDO
+
+FEE_DATA_OUT_c[22]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB4
+         2.7  FEE_DATA_OUT_pad[22].PADDO
+         2.8  fifo_data_out_pad[22].PADDO
+
+FEE_DATA_OUT_c[23]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB5
+         2.4  FEE_DATA_OUT_pad[23].PADDO
+         2.4  fifo_data_out_pad[23].PADDO
+
+FEE_DATA_OUT_c[24]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB6
+         2.4  FEE_DATA_OUT_pad[24].PADDO
+         2.7  fifo_data_out_pad[24].PADDO
+
+FEE_DATA_OUT_c[25]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB7
+         2.8  FEE_DATA_OUT_pad[25].PADDO
+         2.8  fifo_data_out_pad[25].PADDO
+
+FEE_DATA_OUT_c[26]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB8
+         2.7  FEE_DATA_OUT_pad[26].PADDO
+         2.8  fifo_data_out_pad[26].PADDO
+
+FEE_DATA_OUT_c[27]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB9
+         2.8  FEE_DATA_OUT_pad[27].PADDO
+         2.8  fifo_data_out_pad[27].PADDO
+
+FEE_DATA_OUT_c[28]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB10
+         2.8  FEE_DATA_OUT_pad[28].PADDO
+         2.9  fifo_data_out_pad[28].PADDO
+
+FEE_DATA_OUT_c[29]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB11
+         2.7  FEE_DATA_OUT_pad[29].PADDO
+         2.7  fifo_data_out_pad[29].PADDO
+
+FEE_DATA_OUT_c[2]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA2
+         2.9  FEE_DATA_OUT_pad[2].PADDO
+         2.9  fifo_data_out_pad[2].PADDO
+
+FEE_DATA_OUT_c[30]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB12
+         2.6  FEE_DATA_OUT_pad[30].PADDO
+         2.6  fifo_data_out_pad[30].PADDO
+
+FEE_DATA_OUT_c[31]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB13
+         2.6  FEE_DATA_OUT_pad[31].PADDO
+         2.8  fifo_data_out_pad[31].PADDO
+
+FEE_DATA_OUT_c[3]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA3
+         2.5  FEE_DATA_OUT_pad[3].PADDO
+         2.5  fifo_data_out_pad[3].PADDO
+
+FEE_DATA_OUT_c[4]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA4
+         2.9  FEE_DATA_OUT_pad[4].PADDO
+         2.9  fifo_data_out_pad[4].PADDO
+
+FEE_DATA_OUT_c[5]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA5
+         3.0  FEE_DATA_OUT_pad[5].PADDO
+         3.2  fifo_data_out_pad[5].PADDO
+
+FEE_DATA_OUT_c[6]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA6
+         2.9  FEE_DATA_OUT_pad[6].PADDO
+         3.1  fifo_data_out_pad[6].PADDO
+
+FEE_DATA_OUT_c[7]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA7
+         2.9  FEE_DATA_OUT_pad[7].PADDO
+         3.1  fifo_data_out_pad[7].PADDO
+
+FEE_DATA_OUT_c[8]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA8
+         2.5  FEE_DATA_OUT_pad[8].PADDO
+         2.5  fifo_data_out_pad[8].PADDO
+
+FEE_DATA_OUT_c[9]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA9
+         2.4  FEE_DATA_OUT_pad[9].PADDO
+         2.6  fifo_data_out_pad[9].PADDO
+
+FEE_DATA_WRITE_OUT_c
+   trb_adapter_inst_FEE_DATA_WRITE_OUTio.IOLDO
+         0.0  FEE_DATA_WRITE_OUT_pad.IOLDO
+
+FEE_TRG_RELEASE_OUT_c
+   trb_adapter_inst_FEE_TRG_RELEASE_OUTio.IOLDO
+         0.0  FEE_TRG_RELEASE_OUT_pad.IOLDO
+
+LVL1_INVALID_TRG_IN_c
+   LVL1_INVALID_TRG_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALID_IN_c
+   LVL1_TRG_DATA_VALID_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALI_IN_rising_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F0
+         0.6  LVL1_TRG_DATA_VALI_IN_rising_pad.PADDO
+
+N_248_i
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.OFX0
+         0.4  hades_tdc_bundle_inst_buf_out_validio.CE
+
+burst_c
+   trb_adapter_inst/burst.F1
+         0.4  trb_adapter_inst/burst.B0
+         0.4  burst_pad.PADDO
+
+clk_c
+   clk_pad.PADDI
+         0.1  pll0inst/PLLInst_0.CLKI
+
+discard_c
+   trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].Q0
+         0.8  trb_adapter_inst/burst.C1
+         0.4  discard_pad.PADDO
+
+fifo_colector_inst/buffer_wr_enable
+   fifo_colector_inst/in_empty_pmux_0_RNIDRET.Q0
+         0.9  fifo_colector_inst/fifo40_inst/AND2_t20.B0
+
+fifo_colector_inst/data_buffer[0]
+   fifo_colector_inst/data_buffer_3[0].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA0
+
+fifo_colector_inst/data_buffer[10]
+   fifo_colector_inst/data_buffer_3_0[11].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA10
+
+fifo_colector_inst/data_buffer[11]
+   fifo_colector_inst/data_buffer_3_0[11].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA11
+
+fifo_colector_inst/data_buffer[12]
+   fifo_colector_inst/data_buffer_3_0[13].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA12
+
+fifo_colector_inst/data_buffer[13]
+   fifo_colector_inst/data_buffer_3_0[13].Q1
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA13
+
+fifo_colector_inst/data_buffer[14]
+   fifo_colector_inst/data_buffer_3_0[15].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA14
+
+fifo_colector_inst/data_buffer[15]
+   fifo_colector_inst/data_buffer_3_0[15].Q1
+         0.5  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA15
+
+fifo_colector_inst/data_buffer[16]
+   fifo_colector_inst/data_buffer_3_0[17].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA16
+
+fifo_colector_inst/data_buffer[17]
+   fifo_colector_inst/data_buffer_3_0[17].Q1
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA17
+
+fifo_colector_inst/data_buffer[18]
+   fifo_colector_inst/data_buffer_3_0[19].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB0
+
+fifo_colector_inst/data_buffer[19]
+   fifo_colector_inst/data_buffer_3_0[19].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB1
+
+fifo_colector_inst/data_buffer[1]
+   fifo_colector_inst/data_buffer_3[1].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA1
+
+fifo_colector_inst/data_buffer[20]
+   fifo_colector_inst/data_buffer_3_0[21].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB2
+
+fifo_colector_inst/data_buffer[21]
+   fifo_colector_inst/data_buffer_3_0[21].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB3
+
+fifo_colector_inst/data_buffer[22]
+   fifo_colector_inst/data_buffer_3_0[23].Q0
+         0.5  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB4
+
+fifo_colector_inst/data_buffer[23]
+   fifo_colector_inst/data_buffer_3_0[23].Q1
+         0.4  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB5
+
+fifo_colector_inst/data_buffer[24]
+   fifo_colector_inst/data_buffer_3_0[25].Q0
+         0.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB6
+
+fifo_colector_inst/data_buffer[25]
+   fifo_colector_inst/data_buffer_3_0[25].Q1
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB7
+
+fifo_colector_inst/data_buffer[26]
+   fifo_colector_inst/data_buffer_3_0[27].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB8
+
+fifo_colector_inst/data_buffer[27]
+   fifo_colector_inst/data_buffer_3_0[27].Q1
+         1.0  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB9
+
+fifo_colector_inst/data_buffer[28]
+   fifo_colector_inst/data_buffer_3_0[29].Q0
+         0.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB10
+
+fifo_colector_inst/data_buffer[29]
+   fifo_colector_inst/data_buffer_3_0[29].Q1
+         0.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB11
+
+fifo_colector_inst/data_buffer[2]
+   fifo_colector_inst/data_buffer_3[2].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA2
+
+fifo_colector_inst/data_buffer[30]
+   fifo_colector_inst/data_buffer_3_0[31].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB12
+
+fifo_colector_inst/data_buffer[31]
+   fifo_colector_inst/data_buffer_3_0[31].Q1
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB13
+
+fifo_colector_inst/data_buffer[32]
+   fifo_colector_inst/data_buffer[33].Q0
+         0.5  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB14
+
+fifo_colector_inst/data_buffer[33]
+   fifo_colector_inst/data_buffer[33].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB15
+
+fifo_colector_inst/data_buffer[3]
+   fifo_colector_inst/data_buffer_3[3].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA3
+
+fifo_colector_inst/data_buffer[4]
+   fifo_colector_inst/data_buffer_3[4].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA4
+
+fifo_colector_inst/data_buffer[5]
+   fifo_colector_inst/data_buffer_3[5].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA5
+
+fifo_colector_inst/data_buffer[6]
+   fifo_colector_inst/data_buffer_3[6].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA6
+
+fifo_colector_inst/data_buffer[7]
+   fifo_colector_inst/data_buffer_3[7].Q0
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA7
+
+fifo_colector_inst/data_buffer[8]
+   fifo_colector_inst/data_buffer_3_0[9].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA8
+
+fifo_colector_inst/data_buffer[9]
+   fifo_colector_inst/data_buffer_3_0[9].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA9
+
+fifo_colector_inst/data_buffer_3[0]
+   fifo_colector_inst/data_buffer_3[0].OFX0
+         0.0  fifo_colector_inst/data_buffer_3[0].DI0
+
+fifo_colector_inst/data_buffer_3[10]
+   fifo_colector_inst/data_buffer_3_0[11].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[11].DI0
+
+fifo_colector_inst/data_buffer_3[11]
+   fifo_colector_inst/data_buffer_3_0[11].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[11].DI1
+
+fifo_colector_inst/data_buffer_3[12]
+   fifo_colector_inst/data_buffer_3_0[13].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[13].DI0
+
+fifo_colector_inst/data_buffer_3[13]
+   fifo_colector_inst/data_buffer_3_0[13].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[13].DI1
+
+fifo_colector_inst/data_buffer_3[14]
+   fifo_colector_inst/data_buffer_3_0[15].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[15].DI0
+
+fifo_colector_inst/data_buffer_3[15]
+   fifo_colector_inst/data_buffer_3_0[15].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[15].DI1
+
+fifo_colector_inst/data_buffer_3[16]
+   fifo_colector_inst/data_buffer_3_0[17].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[17].DI0
+
+fifo_colector_inst/data_buffer_3[17]
+   fifo_colector_inst/data_buffer_3_0[17].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[17].DI1
+
+fifo_colector_inst/data_buffer_3[18]
+   fifo_colector_inst/data_buffer_3_0[19].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[19].DI0
+
+fifo_colector_inst/data_buffer_3[19]
+   fifo_colector_inst/data_buffer_3_0[19].F1
+         0.0  fifo_colector_inst/data_buffer_3_0[19].DI1
+
+fifo_colector_inst/data_buffer_3[1]
+   fifo_colector_inst/data_buffer_3[1].OFX0
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+
+fifo_colector_inst/data_buffer_3[20]
+   fifo_colector_inst/data_buffer_3_0[21].F0
+         0.0  fifo_colector_inst/data_buffer_3_0[21].DI0
+
+fifo_colector_inst/data_buffer_3[21]
+   fifo_colector_inst/data_buffer_3_0[21].F1
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+
+fifo_colector_inst/data_buffer_3[22]
+   fifo_colector_inst/data_buffer_3_0[23].F0
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+
+fifo_colector_inst/data_buffer_3[23]
+   fifo_colector_inst/data_buffer_3_0[23].F1
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+
+fifo_colector_inst/data_buffer_3[24]
+   fifo_colector_inst/data_buffer_3_0[25].F0
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+
+fifo_colector_inst/data_buffer_3[25]
+   fifo_colector_inst/data_buffer_3_0[25].F1
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+
+fifo_colector_inst/data_buffer_3[26]
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+
+fifo_colector_inst/data_buffer_3[27]
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+
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+
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+
+fifo_colector_inst/data_buffer_3[2]
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+fifo_colector_inst/fb_0
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+
+fifo_colector_inst/fb_0_0
+   fifo_colector_inst/in_read_enable_2_.fb.F0
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+
+fifo_colector_inst/fb_0_1
+   fifo_colector_inst/in_read_enable_1_.fb.F1
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+
+fifo_colector_inst/fifo40_inst/Full
+   fifo_colector_inst/fifo40_inst/FF_0.Q0
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+
+fifo_colector_inst/fifo40_inst/cmp_ci
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+
+fifo_colector_inst/fifo40_inst/cmp_ci_1
+   fifo_colector_inst/fifo40_inst/full_cmp_ci_a.FCO
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+
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+   fifo_colector_inst/fifo40_inst/FF_100.FCO
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+
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+
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+   fifo_colector_inst/fifo40_inst/empty_cmp_0.FCO
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+fifo_empty[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0
+         1.3  fifo_colector_inst/in_empty_pmux_0_RNIDRET.B1
+         1.4  fifo_colector_inst/in_empty_pmux_0.D0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0
+         1.3  fifo_colector_inst/iterator_RNI7U5I[1].A0
+
+fifo_rden_c
+   trb_adapter_inst/burst.Q0
+         0.1  trb_adapter_inst/burst.D0
+         3.3  trb_adapter_inst/buf_rden_prev.M0
+         2.6  fifo_colector_inst/fifo40_inst/AND2_t19.C0
+         3.3  trb_adapter_inst/release_out.LSR
+         3.4  trb_adapter_inst_FEE_DATA_WRITE_OUTio.TXDATA0
+         4.3  fifo_rden_pad.PADDO
+
+fifo_read[0]
+   fifo_colector_inst/in_read_enable_1_.fb.Q0
+         0.1  fifo_colector_inst/in_read_enable_1_.fb.D0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.B0
+
+fifo_read[1]
+   fifo_colector_inst/in_read_enable_1_.fb.Q1
+         0.4  fifo_colector_inst/in_read_enable_1_.fb.B1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0
+
+fifo_read[2]
+   fifo_colector_inst/in_read_enable_2_.fb.Q0
+         0.1  fifo_colector_inst/in_read_enable_2_.fb.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0
+
+finished_c
+   trb_adapter_inst/release_out.Q0
+         0.5  trb_adapter_inst/finished_prev.M0
+         0.6  trb_adapter_inst/release_out.A0
+         1.0  finished_pad.PADDO
+         0.5  trb_adapter_inst_FEE_DATAFINISHED_OUTio.TXDATA0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         1.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         1.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0
+         1.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fb_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
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+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
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+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
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+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
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+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
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+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
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+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
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+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
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+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
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+
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+
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+
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+
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+
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+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         1.1  fifo_colector_inst/data_buffer_3[0].B0
+         1.1  fifo_colector_inst/data_buffer_3[0].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.9  fifo_colector_inst/data_buffer_3_0[11].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         1.2  fifo_colector_inst/data_buffer_3_0[11].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.7  fifo_colector_inst/data_buffer_3_0[13].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3_0[13].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.9  fifo_colector_inst/data_buffer_3_0[15].A0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.7  fifo_colector_inst/data_buffer_3_0[15].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.6  fifo_colector_inst/data_buffer_3_0[17].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         0.8  fifo_colector_inst/data_buffer_3_0[17].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.7  fifo_colector_inst/data_buffer_3_0[19].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         1.1  fifo_colector_inst/data_buffer_3_0[19].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.0  fifo_colector_inst/data_buffer_3[1].B0
+         1.0  fifo_colector_inst/data_buffer_3[1].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.9  fifo_colector_inst/data_buffer_3_0[21].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         1.0  fifo_colector_inst/data_buffer_3_0[21].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.8  fifo_colector_inst/data_buffer_3_0[23].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.9  fifo_colector_inst/data_buffer_3_0[23].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         1.0  fifo_colector_inst/data_buffer_3[2].C0
+         1.0  fifo_colector_inst/data_buffer_3[2].C1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.8  fifo_colector_inst/data_buffer_3[3].C0
+         0.8  fifo_colector_inst/data_buffer_3[3].C1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.9  fifo_colector_inst/data_buffer_3[4].D0
+         0.9  fifo_colector_inst/data_buffer_3[4].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         1.1  fifo_colector_inst/data_buffer_3[5].B0
+         1.1  fifo_colector_inst/data_buffer_3[5].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.9  fifo_colector_inst/data_buffer_3[6].B0
+         0.9  fifo_colector_inst/data_buffer_3[6].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.8  fifo_colector_inst/data_buffer_3[7].D0
+         0.8  fifo_colector_inst/data_buffer_3[7].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         1.0  fifo_colector_inst/data_buffer_3_0[9].B0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3_0[9].C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.A0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fb_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.A0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.9  fifo_colector_inst/data_buffer_3_0[25].A0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.9  fifo_colector_inst/data_buffer_3[2].B0
+         0.9  fifo_colector_inst/data_buffer_3[2].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.7  fifo_colector_inst/data_buffer_3[3].B0
+         0.7  fifo_colector_inst/data_buffer_3[3].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.6  fifo_colector_inst/data_buffer_3[4].B0
+         0.6  fifo_colector_inst/data_buffer_3[4].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.5  fifo_colector_inst/data_buffer_3[5].C0
+         0.5  fifo_colector_inst/data_buffer_3[5].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.4  fifo_colector_inst/data_buffer_3[6].D0
+         0.4  fifo_colector_inst/data_buffer_3[6].D1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.9  fifo_colector_inst/data_buffer_3[7].C0
+         0.9  fifo_colector_inst/data_buffer_3[7].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.7  fifo_colector_inst/data_buffer_3_0[9].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         1.1  fifo_colector_inst/data_buffer_3_0[9].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.8  fifo_colector_inst/data_buffer_3_0[11].B0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.9  fifo_colector_inst/data_buffer_3_0[11].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.0  fifo_colector_inst/data_buffer_3_0[25].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.8  fifo_colector_inst/data_buffer_3_0[13].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.8  fifo_colector_inst/data_buffer_3_0[13].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.6  fifo_colector_inst/data_buffer_3_0[15].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.8  fifo_colector_inst/data_buffer_3_0[15].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.5  fifo_colector_inst/data_buffer_3_0[27].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.7  fifo_colector_inst/data_buffer_3_0[27].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.7  fifo_colector_inst/data_buffer_3_0[29].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.8  fifo_colector_inst/data_buffer_3_0[29].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.6  fifo_colector_inst/data_buffer_3_0[31].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.7  fifo_colector_inst/data_buffer_3_0[31].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         0.9  fifo_colector_inst/data_buffer_3[0].C0
+         0.9  fifo_colector_inst/data_buffer_3[0].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3[1].C0
+         0.9  fifo_colector_inst/data_buffer_3[1].C1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fb_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0
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+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
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+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         1.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
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+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.9  fifo_colector_inst/data_buffer_3_0[17].C0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.8  fifo_colector_inst/data_buffer_3_0[27].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.7  fifo_colector_inst/data_buffer_3_0[27].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         1.0  fifo_colector_inst/data_buffer_3_0[29].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3_0[29].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         1.1  fifo_colector_inst/data_buffer_3_0[31].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.8  fifo_colector_inst/data_buffer_3_0[31].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         1.0  fifo_colector_inst/data_buffer_3[0].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         1.0  fifo_colector_inst/data_buffer_3[1].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.8  fifo_colector_inst/data_buffer_3[2].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.8  fifo_colector_inst/data_buffer_3[3].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.1  fifo_colector_inst/data_buffer_3_0[17].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.8  fifo_colector_inst/data_buffer_3[4].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.9  fifo_colector_inst/data_buffer_3[5].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.9  fifo_colector_inst/data_buffer_3[6].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.9  fifo_colector_inst/data_buffer_3[7].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         1.0  fifo_colector_inst/data_buffer_3_0[19].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         1.0  fifo_colector_inst/data_buffer_3_0[19].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.9  fifo_colector_inst/data_buffer_3_0[21].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         1.1  fifo_colector_inst/data_buffer_3_0[21].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         1.0  fifo_colector_inst/data_buffer_3_0[23].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         1.0  fifo_colector_inst/data_buffer_3_0[23].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         1.0  fifo_colector_inst/data_buffer_3_0[25].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3_0[25].C1
+
+hades_buf_drop_c[1]
+   hades_tdc_bundle_inst_buf_drop_1io[1].IOLDO
+         0.0  hades_buf_drop_pad[1].IOLDO
+
+hades_buf_finished_c
+   hades_tdc_bundle_inst/buf_finished5_0_a2_0.Q0
+         0.9  hades_tdc_bundle_inst/buf_release.M0
+         1.2  hades_buf_finished_pad.PADDO
+
+hades_buf_out_valid_c
+   hades_tdc_bundle_inst_buf_out_validio.IOLDO
+         0.0  hades_buf_out_valid_pad.IOLDO
+
+hades_buf_release_c
+   hades_tdc_bundle_inst/buf_release.Q0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[0].D0
+         1.2  hades_tdc_bundle_inst/hit_valid_1_RNO[0].B1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].D0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].D1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].C1
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[3].C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[3].B1
+         1.3  hades_buf_release_pad.PADDO
+
+hades_dbg2_coarse_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q0
+         1.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.C1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.C1
+         0.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.C1
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].A0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].A1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B1
+         1.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M1
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D1
+         1.8  hades_dbg2_coarse_pad[0].PADDO
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].TXDATA0
+
+hades_dbg2_coarse_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.D1
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.D1
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.B1
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].D0
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M0
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B1
+         1.8  hades_dbg2_coarse_pad[1].PADDO
+         1.5  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].TXDATA0
+
+hades_dbg2_coarse_c[2]
+   hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q0
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].C0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].B1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A1
+         1.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A0
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C1
+         2.7  hades_dbg2_coarse_pad[2].PADDO
+         2.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].TXDATA0
+
+hades_dbg2_coarse_c[3]
+   hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].C1
+         0.9  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A0
+         0.9  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C1
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.A0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.C0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A1
+         2.0  hades_dbg2_coarse_pad[3].PADDO
+         1.8  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].TXDATA0
+
+hades_dbg2_coarse_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q0
+         0.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.C1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.D1
+         1.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M1
+         1.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M1
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.D1
+         3.0  hades_dbg2_coarse_pad[4].PADDO
+         1.9  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].TXDATA0
+
+hades_dbg2_coarse_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.A1
+         2.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M0
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M0
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.B1
+         2.9  hades_dbg2_coarse_pad[5].PADDO
+         2.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].TXDATA0
+
+hades_dbg2_coarse_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q0
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C1
+         2.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M1
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M1
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.C0
+         2.5  hades_dbg2_coarse_pad[6].PADDO
+
+hades_dbg2_coarse_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D0
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C0
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D1
+         1.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M0
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.A0
+         3.3  hades_dbg2_coarse_pad[7].PADDO
+
+hades_dbg2_coarse_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.Q0
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.C1
+         1.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M1
+         1.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M1
+         2.4  hades_dbg2_coarse_pad[8].PADDO
+
+hades_dbg2_out_c[0]
+   hades_tdc_bundle_inst_hitbuffer_1_io[0].IOLDO
+         0.0  hades_dbg2_out_pad[0].IOLDO
+
+hades_dbg2_out_c[10]
+   hades_tdc_bundle_inst/hitbuffer_1_[10].Q0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[7].M0
+         1.7  hades_dbg2_out_pad[10].PADDO
+
+hades_dbg2_out_c[11]
+   hades_tdc_bundle_inst/hitbuffer_1_[10].Q1
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[7].M1
+         1.9  hades_dbg2_out_pad[11].PADDO
+
+hades_dbg2_out_c[12]
+   hades_tdc_bundle_inst/hitbuffer_1_[11].Q0
+         1.0  hades_tdc_bundle_inst/drop_cmp_buf_1[8].M0
+         1.7  hades_dbg2_out_pad[12].PADDO
+
+hades_dbg2_out_c[16]
+   hades_tdc_bundle_inst_hitbuffer_1_io[12].IOLDO
+         0.0  hades_dbg2_out_pad[16].IOLDO
+
+hades_dbg2_out_c[17]
+   hades_tdc_bundle_inst_hitbuffer_1_io[13].IOLDO
+         0.0  hades_dbg2_out_pad[17].IOLDO
+
+hades_dbg2_out_c[18]
+   hades_tdc_bundle_inst_hitbuffer_1_io[14].IOLDO
+         0.0  hades_dbg2_out_pad[18].IOLDO
+
+hades_dbg2_out_c[1]
+   hades_tdc_bundle_inst_hitbuffer_1_io[1].IOLDO
+         0.0  hades_dbg2_out_pad[1].IOLDO
+
+hades_dbg2_out_c[20]
+   hades_tdc_bundle_inst_hitbuffer_1_io[15].IOLDO
+         0.0  hades_dbg2_out_pad[20].IOLDO
+
+hades_dbg2_out_c[21]
+   hades_tdc_bundle_inst_hitbuffer_1_io[16].IOLDO
+         0.0  hades_dbg2_out_pad[21].IOLDO
+
+hades_dbg2_out_c[22]
+   hades_tdc_bundle_inst_hitbuffer_1_io[17].IOLDO
+         0.0  hades_dbg2_out_pad[22].IOLDO
+
+hades_dbg2_out_c[23]
+   hades_tdc_bundle_inst_hitbuffer_1_io[18].IOLDO
+         0.0  hades_dbg2_out_pad[23].IOLDO
+
+hades_dbg2_out_c[24]
+   hades_tdc_bundle_inst_hitbuffer_1_io[19].IOLDO
+         0.0  hades_dbg2_out_pad[24].IOLDO
+
+hades_dbg2_out_c[25]
+   hades_tdc_bundle_inst_hitbuffer_1_io[20].IOLDO
+         0.0  hades_dbg2_out_pad[25].IOLDO
+
+hades_dbg2_out_c[26]
+   hades_tdc_bundle_inst_hitbuffer_1_io[21].IOLDO
+         0.0  hades_dbg2_out_pad[26].IOLDO
+
+hades_dbg2_out_c[27]
+   hades_tdc_bundle_inst_hitbuffer_1_io[22].IOLDO
+         0.0  hades_dbg2_out_pad[27].IOLDO
+
+hades_dbg2_out_c[28]
+   hades_tdc_bundle_inst_hitbuffer_1_io[23].IOLDO
+         0.0  hades_dbg2_out_pad[28].IOLDO
+
+hades_dbg2_out_c[2]
+   hades_tdc_bundle_inst_hitbuffer_1_io[2].IOLDO
+         0.0  hades_dbg2_out_pad[2].IOLDO
+
+hades_dbg2_out_c[4]
+   hades_tdc_bundle_inst/hitbuffer_1_[4].Q0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[1].M0
+         1.8  hades_dbg2_out_pad[4].PADDO
+
+hades_dbg2_out_c[5]
+   hades_tdc_bundle_inst/hitbuffer_1_[4].Q1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[1].M1
+         1.4  hades_dbg2_out_pad[5].PADDO
+
+hades_dbg2_out_c[6]
+   hades_tdc_bundle_inst/hitbuffer_1_[6].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[3].M0
+         1.5  hades_dbg2_out_pad[6].PADDO
+
+hades_dbg2_out_c[7]
+   hades_tdc_bundle_inst/hitbuffer_1_[6].Q1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_1[3].M1
+         1.4  hades_dbg2_out_pad[7].PADDO
+
+hades_dbg2_out_c[8]
+   hades_tdc_bundle_inst/hitbuffer_1_[8].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[5].M0
+         1.5  hades_dbg2_out_pad[8].PADDO
+
+hades_dbg2_out_c[9]
+   hades_tdc_bundle_inst/hitbuffer_1_[8].Q1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[5].M1
+         1.5  hades_dbg2_out_pad[9].PADDO
+
+hades_discard_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.Q0
+         1.5  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].D0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.A0
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].M0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A0
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A1
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B1
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.A0
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.A0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.A0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.B0
+         0.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].B0
+         1.3  hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].A0
+         2.1  hades_discard_pad.PADDO
+
+hades_drop_cmp_buf_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.D1
+         1.1  hades_drop_cmp_buf_pad[0].PADDO
+
+hades_drop_cmp_buf_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q1
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.A1
+         1.3  hades_drop_cmp_buf_pad[1].PADDO
+
+hades_drop_cmp_buf_c[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C0
+         1.5  hades_drop_cmp_buf_pad[2].PADDO
+
+hades_drop_cmp_buf_c[3]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q1
+         1.0  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A0
+         1.5  hades_drop_cmp_buf_pad[3].PADDO
+
+hades_drop_cmp_buf_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q0
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A1
+         1.4  hades_drop_cmp_buf_pad[4].PADDO
+
+hades_drop_cmp_buf_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q1
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C1
+         1.4  hades_drop_cmp_buf_pad[5].PADDO
+
+hades_drop_cmp_buf_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B0
+         1.2  hades_drop_cmp_buf_pad[6].PADDO
+
+hades_drop_cmp_buf_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q1
+         0.8  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.A0
+         1.6  hades_drop_cmp_buf_pad[7].PADDO
+
+hades_drop_cmp_buf_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[8].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D1
+         1.4  hades_drop_cmp_buf_pad[8].PADDO
+
+hades_drop_cmp_buf_coarse_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.C1
+         1.5  hades_drop_cmp_buf_coarse_pad[0].PADDO
+
+hades_drop_cmp_buf_coarse_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.B1
+         1.9  hades_drop_cmp_buf_coarse_pad[1].PADDO
+
+hades_drop_cmp_buf_coarse_c[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B0
+         1.5  hades_drop_cmp_buf_coarse_pad[2].PADDO
+
+hades_drop_cmp_buf_coarse_c[3]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D0
+         2.0  hades_drop_cmp_buf_coarse_pad[3].PADDO
+
+hades_drop_cmp_buf_coarse_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B1
+         1.8  hades_drop_cmp_buf_coarse_pad[4].PADDO
+
+hades_drop_cmp_buf_coarse_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D1
+         1.9  hades_drop_cmp_buf_coarse_pad[5].PADDO
+
+hades_drop_cmp_buf_coarse_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C0
+         1.7  hades_drop_cmp_buf_coarse_pad[6].PADDO
+
+hades_drop_cmp_buf_coarse_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q1
+         0.4  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D0
+         1.6  hades_drop_cmp_buf_coarse_pad[7].PADDO
+
+hades_drop_cmp_buf_coarse_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B1
+         1.9  hades_drop_cmp_buf_coarse_pad[8].PADDO
+
+hades_drop_cmp_buf_coarse_c[9]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C1
+         2.0  hades_drop_cmp_buf_coarse_pad[9].PADDO
+
+hades_drop_cmp_buf_valid_c
+   hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.Q0
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].B0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].B1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D1
+         1.3  hades_drop_cmp_buf_valid_pad.PADDO
+
+hades_hit_valid_c[0]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[0].Q0
+         0.3  hades_tdc_bundle_inst/hit_valid_1_RNO[0].C0
+         0.3  hades_tdc_bundle_inst/hit_valid_1_RNO[0].D1
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C0
+         1.2  hades_hit_valid_pad[0].PADDO
+
+hades_hit_valid_c[1]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[1].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.D0
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[1].M0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.C0
+         1.1  hades_hit_valid_pad[1].PADDO
+
+hades_hit_valid_c[2]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[2].Q0
+         0.2  hades_tdc_bundle_inst/hit_valid_1_RNO[2].D0
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[2].A1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.B0
+         1.2  hades_hit_valid_pad[2].PADDO
+
+hades_hit_valid_c[3]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[3].Q0
+         0.2  hades_tdc_bundle_inst/hit_valid_1_RNO[3].D0
+         0.4  hades_tdc_bundle_inst/hit_valid_1_RNO[3].C1
+         0.9  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A0
+         0.9  hades_hit_valid_pad[3].PADDO
+
+hades_invalid_dl_c[0]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].INFF
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M0
+         0.6  hades_invalid_dl_pad[0].PADDO
+
+hades_invalid_dl_c[1]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M1
+         1.2  hades_invalid_dl_pad[1].PADDO
+
+hades_invalid_dl_c[2]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q1
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C0
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].M0
+         1.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.D0
+         0.9  hades_invalid_dl_pad[2].PADDO
+
+hades_invalid_dl_c[3]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].Q0
+         1.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D0
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.B0
+         1.2  hades_invalid_dl_pad[3].PADDO
+
+hades_lvl1_c
+   hades_lvl1_pad.PADDI
+         0.9  hades_lvl1_pad_RNINMH5.D0
+         0.0  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].DI
+
+hades_lvl1_c_i
+   hades_lvl1_pad_RNINMH5.F0
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+hades_lvl1_invalid_c
+   hades_lvl1_invalid_pad.PADDI
+         0.1  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].DI
+
+hades_offset_c[0]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].IOLDO
+         0.0  hades_offset_pad[0].IOLDO
+
+hades_offset_c[1]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].IOLDO
+         0.0  hades_offset_pad[1].IOLDO
+
+hades_offset_c[2]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].IOLDO
+         0.0  hades_offset_pad[2].IOLDO
+
+hades_offset_c[3]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].IOLDO
+         0.0  hades_offset_pad[3].IOLDO
+
+hades_offset_c[4]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].IOLDO
+         0.0  hades_offset_pad[4].IOLDO
+
+hades_offset_c[5]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].IOLDO
+         0.0  hades_offset_pad[5].IOLDO
+
+hades_offset_c[6]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].IOLDO
+         0.0  hades_offset_pad[6].IOLDO
+
+hades_offset_c[7]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].IOLDO
+         0.0  hades_offset_pad[7].IOLDO
+
+hades_offset_c[8]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].IOLDO
+         0.0  hades_offset_pad[8].IOLDO
+
+hades_offset_valid_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.Q0
+         2.7  hades_offset_valid_pad.PADDO
+         2.5  hades_tdc_bundle_inst_referenced_out_validio.TXDATA0
+
+hades_raw_out_valid_c
+   hades_tdc_bundle_inst_referenced_out_validio.IOLDO
+         0.0  hades_raw_out_valid_pad.IOLDO
+
+hades_tdc_bundle_inst.buf_out12
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F0
+         0.8  hades_tdc_bundle_inst_buf_out_validio.TXDATA0
+
+hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa
+   hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F1
+         1.0  hades_tdc_bundle_inst_buf_drop_1io[1].TXDATA0
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.OFX0
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CE
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.D0
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CE
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CE
+         1.5  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CE
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q0
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
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+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
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+
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+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
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+
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+
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+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q1
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].Q0
+         0.4  hades_tdc_bundle_inst/hitbuffer_1_[11].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q0
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q1
+         0.8  hades_tdc_bundle_inst/hitbuffer_1_[4].M1
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q0
+         0.6  hades_tdc_bundle_inst/hitbuffer_1_[6].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q1
+         0.6  hades_tdc_bundle_inst/hitbuffer_1_[6].M1
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q0
+         0.8  hades_tdc_bundle_inst/hitbuffer_1_[8].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q1
+         0.8  hades_tdc_bundle_inst/hitbuffer_1_[8].M1
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q0
+         0.6  hades_tdc_bundle_inst/hitbuffer_1_[10].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.Q0
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+         1.2  hades_tdc_bundle_inst/hit_valid_1_RNO[2].D1
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[3].D1
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C0
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C1
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D1
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.F0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CE
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CE
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CE
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CE
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CE
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CE
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.F0
+         1.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CE
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CE
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CE
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CE
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CE
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CE
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CE
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CE
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.DI0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.F0
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+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CE
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CE
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CE
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CE
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.F0
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.DI0
+
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+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].M1
+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].Q1
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].M1
+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].Q1
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1
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+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_cry
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_14
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_19
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.F0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.C0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_cry
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.F0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.B0
+
+hades_tdc_bundle_inst/hit_i[0]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q0
+         0.9  hades_tdc_bundle_inst/hit_valid_1_RNO[0].A0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[2].B1
+         0.7  hades_tdc_bundle_inst/hit_valid_1_RNO[3].A1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.D1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B0
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B1
+
+hades_tdc_bundle_inst/hit_i[1]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[0].M0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].M0
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[3].M0
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C0
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C1
+
+hades_tdc_bundle_inst/hit_out_i_6[2]
+   hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].OFX0
+         0.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].DI0
+
+hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0]
+   hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].F0
+         0.4  hades_tdc_bundle_inst/hit_out_i_RNO[0].M0
+
+hades_tdc_bundle_inst/hit_valid25
+   hades_tdc_bundle_inst/hit_valid25_0_I_27_0.F0
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.B0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[1].C0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[1].C1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C1
+
+hades_tdc_bundle_inst/hit_valid25_0_I_27_cry
+   hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0]
+   hades_tdc_bundle_inst/hit_valid25_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2]
+   hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F0
+         0.1  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D0
+
+hades_trig_c
+   hades_trig_pad.PADDI
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         1.1  hades_trig_pad_RNIE1B4.A0
+
+hades_trig_c_i
+   hades_trig_pad_RNIE1B4.F0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+hades_window_end_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.Q0
+         1.2  hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].C0
+         2.5  hades_window_end_pad.PADDO
+
+last_buf_empty_c
+   fifo_colector_inst/fifo40_inst/FF_1.Q0
+         2.6  trb_adapter_inst/burst.C0
+         1.0  fifo_colector_inst/fifo40_inst/AND2_t19.D0
+         2.7  last_buf_empty_pad.PADDO
+
+pll0inst/GND
+   pll0inst/GND.F0
+         0.5  pll0inst/PLLInst_0.STDBY
+
+pll_clks[0]
+   pll0inst/PLLInst_0.CLKOP
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK
+         1.7  pll0inst/PLLInst_0.CLKFB
+
+pll_clks[1]
+   pll0inst/PLLInst_0.CLKOS
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+
+pll_clks[2]
+   pll0inst/PLLInst_0.CLKOS2
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+
+pll_clks[3]
+   pll0inst/PLLInst_0.CLKOS3
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_100.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_98.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_96.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_94.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_92.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_0.CLK
+         1.7  hades_tdc_bundle_inst/hit_out_i_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.CLK
+         1.7  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].CLK
+         1.7  fifo_colector_inst/in_empty_pmux_0_RNIDRET.CLK
+         1.7  fifo_colector_inst/data_buffer_3[0].CLK
+         1.7  fifo_colector_inst/data_buffer_3[1].CLK
+         1.7  fifo_colector_inst/data_buffer_3[2].CLK
+         1.7  fifo_colector_inst/data_buffer_3[3].CLK
+         1.7  fifo_colector_inst/data_buffer_3[4].CLK
+         1.7  fifo_colector_inst/data_buffer_3[5].CLK
+         1.7  fifo_colector_inst/data_buffer_3[6].CLK
+         1.7  fifo_colector_inst/data_buffer_3[7].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[9].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[11].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[13].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[15].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[17].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[19].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[21].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[23].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[25].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[27].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[29].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[31].CLK
+         1.7  fifo_colector_inst/data_buffer[33].CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_30.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_28.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_26.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_24.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_22.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_8.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_6.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_4.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_2.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t12.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t9.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_80.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_78.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_76.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_74.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_72.CLK
+         1.7  fifo_colector_inst/un5_in_read_enable.CLK
+         1.7  fifo_colector_inst/in_read_enable_1_.fb.CLK
+         1.7  fifo_colector_inst/in_read_enable_2_.fb.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/buf_finished5_0_a2_0.CLK
+         1.7  hades_tdc_bundle_inst/buf_release.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.CLK
+         1.7  hades_tdc_bundle_inst/coarse_RNI6RPP[2].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[4].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[6].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[8].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[10].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[1].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[3].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[5].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[7].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[8].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[1].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[2].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[23].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[22].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[21].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[20].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[19].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[18].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[17].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[16].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[15].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[14].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[13].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[12].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[2].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[1].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[0].CLK
+         1.7  hades_tdc_bundle_inst_buf_drop_1io[1].CLK
+         1.7  hades_tdc_bundle_inst_buf_out_validio.CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].CLK
+         1.7  hades_tdc_bundle_inst_referenced_out_validio.CLK
+         1.7  reset_dl_0io[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKA
+
+rd_clk_c
+   rd_clk_pad.PADDI
+         1.7  fifo_colector_inst/fifo40_inst/FF_70.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_68.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_66.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_64.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_62.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_1.CLK
+         1.7  trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t7.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t5.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t3.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t1.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_50.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_48.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_46.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_44.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_42.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_40.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_38.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_36.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_34.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_32.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_20.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_18.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_12.CLK
+         1.7  trb_adapter_inst/burst.CLK
+         1.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].CLK
+         1.7  trb_adapter_inst/buf_rden_prev.CLK
+         1.7  trb_adapter_inst/finished_prev.CLK
+         1.7  trb_adapter_inst/release_out.CLK
+         1.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATA_WRITE_OUTio.CLK
+         1.8  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].CLK
+         1.8  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].CLK
+         1.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKB
+
+release_out_c
+   trb_adapter_inst/release_out.F0
+         0.7  release_out_pad.PADDO
+         0.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.TXDATA0
+
+reset_dc_c
+   reset_dc_pad.PADDI
+         0.0  reset_dl_0io[1].DI
+
+reset_dl[1]
+   reset_dl_0io[1].INFF
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.M0
+
+reset_dl[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.Q0
+         0.8  hades_tdc_bundle_inst/hit_out_i_RNO[0].LSR
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.LSR
+         1.4  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].LSR
+         2.1  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         2.4  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         3.4  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         0.5  hades_tdc_bundle_inst/buf_finished5_0_a2_0.LSR
+         0.9  hades_tdc_bundle_inst/buf_release.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.LSR
+         2.0  hades_tdc_bundle_inst/coarse_RNI6RPP[2].LSR
+         2.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.LSR
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.LSR
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CE
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[0].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[1].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[2].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[3].CE
+         1.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.LSR
+         1.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].LSR
+         2.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].LSR
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].LSR
+         2.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A0
+         2.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A1
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.M0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C1
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C0
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].LSR
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].LSR
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].LSR
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].LSR
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].LSR
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.LSR
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CE
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CE
+         0.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.LSR
+         1.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.M0
+         1.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.A0
+         3.2  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.2  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.A0
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.C0
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.B0
+         2.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.A0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].C0
+         0.2  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.D0
+         1.4  hades_tdc_bundle_inst_buf_drop_1io[1].LSR
+         1.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.LSR
+         1.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.LSR
+         1.9  trb_adapter_inst_FEE_DATA_WRITE_OUTio.LSR
+
+trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0]
+   trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].INFF
+         0.6  trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].M0
+
+trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]
+   trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].INFF
+         3.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q0
+         0.5  trb_adapter_inst/burst.B1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M1
+         0.5  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q1
+         0.5  trb_adapter_inst/burst.A1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D0
+
+trb_adapter_inst/buf_rden4
+   trb_adapter_inst/burst.F0
+         0.0  trb_adapter_inst/burst.DI0
+
+trb_adapter_inst/buf_rden_prev
+   trb_adapter_inst/buf_rden_prev.Q0
+         0.3  trb_adapter_inst/release_out.M0
+
+trb_adapter_inst/finished_prev
+   trb_adapter_inst/finished_prev.Q0
+         0.5  trb_adapter_inst/release_out.B0
+
+trig_c[0]
+   trig_pad[0].PADDI
+         0.4  trig_pad_RNII4FF[0].D0
+
+trig_c[1]
+   trig_pad[1].PADDI
+         1.5  trig_pad_RNIJ5FF[1].D0
+
+trig_c[2]
+   trig_pad[2].PADDI
+         1.7  trig_pad_RNIK6FF[2].D0
+
+trig_c_i[0]
+   trig_pad_RNII4FF[0].F0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[1]
+   trig_pad_RNIJ5FF[1].F0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[2]
+   trig_pad_RNIK6FF[2].F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+un1_hit_i_2_0_a2
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F0
+         0.4  hades_tdc_bundle_inst/hitbuffer_1_[4].CE
+         0.4  hades_tdc_bundle_inst/hitbuffer_1_[6].CE
+         0.6  hades_tdc_bundle_inst/hitbuffer_1_[8].CE
+         1.3  hades_tdc_bundle_inst/hitbuffer_1_[10].CE
+         1.0  hades_tdc_bundle_inst/hitbuffer_1_[11].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[23].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[22].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[21].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[20].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[19].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[18].CE
+         1.4  hades_tdc_bundle_inst_hitbuffer_1_io[17].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[16].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[15].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[14].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[13].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[12].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[2].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[1].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[0].CE
+
+valid_fast_RNI999V
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.F0
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].LSR
diff --git a/impl1/s1_impl1.dir/5_1.ncd b/impl1/s1_impl1.dir/5_1.ncd
new file mode 100644
index 0000000..eb6d8aa
Binary files /dev/null and b/impl1/s1_impl1.dir/5_1.ncd differ
diff --git a/impl1/s1_impl1.dir/5_1.pad b/impl1/s1_impl1.dir/5_1.pad
new file mode 100644
index 0000000..9c4860c
--- /dev/null
+++ b/impl1/s1_impl1.dir/5_1.pad
@@ -0,0 +1,702 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LFE5UM5G-45F
+Performance Grade:      8
+PACKAGE:          CABGA381
+Package Status:                     Final          Version 1.38
+
+Wed Jun 16 09:20:00 2021
+
+Pinout by Port Name:
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| Port Name                     | Pin/Bank | Buffer Type  | Site  | BC Enable | Properties                        |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| FEE_DATAFINISHED_OUT          | D13/1    | LVCMOS25_OUT | PT53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[0]               | R17/3    | LVCMOS25_OUT | PR44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[10]              | J19/2    | LVCMOS25_OUT | PR32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[11]              | R3/8     | LVCMOS25_OUT | PB15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[12]              | N5/6     | LVCMOS25_OUT | PL59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[13]              | G16/2    | LVCMOS25_OUT | PR17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[14]              | P5/6     | LVCMOS25_OUT | PL59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[15]              | M19/3    | LVCMOS25_OUT | PR35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[16]              | N19/3    | LVCMOS25_OUT | PR59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[17]              | B15/1    | LVCMOS25_OUT | PT69A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[18]              | A15/1    | LVCMOS25_OUT | PT67A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[19]              | K5/6     | LVCMOS25_OUT | PL44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[1]               | N3/6     | LVCMOS25_OUT | PL62A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[20]              | V1/8     | LVCMOS25_OUT | PB6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[21]              | G19/2    | LVCMOS25_OUT | PR29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[22]              | T2/8     | LVCMOS25_OUT | PB13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[23]              | H20/2    | LVCMOS25_OUT | PR29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[24]              | K19/2    | LVCMOS25_OUT | PR32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[25]              | H17/2    | LVCMOS25_OUT | PR20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[26]              | L19/3    | LVCMOS25_OUT | PR35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[27]              | C20/2    | LVCMOS25_OUT | PR23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[28]              | F19/2    | LVCMOS25_OUT | PR26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[29]              | U1/8     | LVCMOS25_OUT | PB6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[2]               | G18/2    | LVCMOS25_OUT | PR17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[30]              | D20/2    | LVCMOS25_OUT | PR23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[31]              | H18/2    | LVCMOS25_OUT | PR20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[3]               | M17/3    | LVCMOS25_OUT | PR41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[4]               | E18/2    | LVCMOS25_OUT | PR14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[5]               | F16/2    | LVCMOS25_OUT | PR11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[6]               | A16/1    | LVCMOS25_OUT | PT74A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[7]               | L3/6     | LVCMOS25_OUT | PL62C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[8]               | L16/3    | LVCMOS25_OUT | PR38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[9]               | F20/2    | LVCMOS25_OUT | PR26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_WRITE_OUT            | C13/1    | LVCMOS25_OUT | PT51B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_TRG_RELEASE_OUT           | E13/1    | LVCMOS25_OUT | PT53B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| LVL1_INVALID_TRG_IN           | R16/3    | LVCMOS25_IN  | PR44C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALID_IN        | A9/0     | LVCMOS25_IN  | PT33A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALI_IN_rising  | N18/3    | LVCMOS25_OUT | PR41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| burst                         | N16/3    | LVCMOS25_OUT | PR41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| clk                           | P3/6     | LVDS_IN      | PL68C |           | CLAMP:ON                          |
+| discard                       | P16/3    | LVCMOS25_OUT | PR44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[0]              | P17/3    | LVCMOS25_OUT | PR41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[10]             | K20/2    | LVCMOS25_OUT | PR32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[11]             | U2/8     | LVCMOS25_OUT | PB13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[12]             | N4/6     | LVCMOS25_OUT | PL59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[13]             | J16/2    | LVCMOS25_OUT | PR20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[14]             | M4/6     | LVCMOS25_OUT | PL59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[15]             | J20/2    | LVCMOS25_OUT | PR32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[16]             | P18/3    | LVCMOS25_OUT | PR59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[17]             | C15/1    | LVCMOS25_OUT | PT69B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[18]             | E14/1    | LVCMOS25_OUT | PT58B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[19]             | L4/6     | LVCMOS25_OUT | PL44C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[1]              | M3/6     | LVCMOS25_OUT | PL62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[20]             | Y2/8     | LVCMOS25_OUT | PB9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[21]             | K18/2    | LVCMOS25_OUT | PR29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[22]             | W1/8     | LVCMOS25_OUT | PB9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[23]             | J18/2    | LVCMOS25_OUT | PR29C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[24]             | M20/3    | LVCMOS25_OUT | PR35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[25]             | J17/2    | LVCMOS25_OUT | PR20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[26]             | L20/3    | LVCMOS25_OUT | PR35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[27]             | D19/2    | LVCMOS25_OUT | PR23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[28]             | G20/2    | LVCMOS25_OUT | PR26D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[29]             | T1/8     | LVCMOS25_OUT | PB4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[2]              | F17/2    | LVCMOS25_OUT | PR17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[30]             | E19/2    | LVCMOS25_OUT | PR23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[31]             | H16/2    | LVCMOS25_OUT | PR17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[3]              | L17/3    | LVCMOS25_OUT | PR38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[4]              | F18/2    | LVCMOS25_OUT | PR14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[5]              | D17/2    | LVCMOS25_OUT | PR11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[6]              | B16/1    | LVCMOS25_OUT | PT74B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[7]              | N1/6     | LVCMOS25_OUT | PL65D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[8]              | M18/3    | LVCMOS25_OUT | PR38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[9]              | E20/2    | LVCMOS25_OUT | PR26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_empty1                   | N17/3    | LVCMOS25_OUT | PR44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_rden                     | A19/1    | LVCMOS25_OUT | PT85A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| finished                      | D14/1    | LVCMOS25_OUT | PT58A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[0]             | N20/3    | LVCMOS25_OUT | PR59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[1]             | A10/0    | LVCMOS25_OUT | PT36A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[2]             | R20/3    | LVCMOS25_OUT | PR62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[3]             | U16/3    | LVCMOS25_OUT | PR68C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_finished            | A4/7     | LVCMOS25_OUT | PL11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_out_valid           | C9/0     | LVCMOS25_OUT | PT27A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_release             | E7/0     | LVCMOS25_OUT | PT9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[0]          | G5/7     | LVCMOS25_OUT | PL29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[1]          | H3/7     | LVCMOS25_OUT | PL29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[2]          | E3/7     | LVCMOS25_OUT | PL20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[3]          | C2/7     | LVCMOS25_OUT | PL23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[4]          | B6/0     | LVCMOS25_OUT | PT4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[5]          | B1/7     | LVCMOS25_OUT | PL23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[6]          | E5/7     | LVCMOS25_OUT | PL20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[7]          | M5/6     | LVCMOS25_OUT | PL53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[8]          | F1/6     | LVCMOS25_OUT | PL35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[0]             | J3/6     | LVCMOS25_OUT | PL38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[10]            | A8/0     | LVCMOS25_OUT | PT18B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[11]            | D6/0     | LVCMOS25_OUT | PT6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[12]            | B8/0     | LVCMOS25_OUT | PT15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[13]            | P19/3    | LVCMOS25_OUT | PR59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[14]            | P1/6     | LVCMOS25_OUT | PL68A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[15]            | C17/1    | LVCMOS25_OUT | PT78B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[16]            | G3/7     | LVCMOS25_OUT | PL32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[17]            | G1/6     | LVCMOS25_OUT | PL35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[18]            | J5/6     | LVCMOS25_OUT | PL38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[19]            | R1/8     | LVCMOS25_OUT | PB4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[1]             | E2/7     | LVCMOS25_OUT | PL32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[20]            | K3/6     | LVCMOS25_OUT | PL38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[21]            | G2/6     | LVCMOS25_OUT | PL35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[22]            | H4/7     | LVCMOS25_OUT | PL29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[23]            | J4/6     | LVCMOS25_OUT | PL38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[24]            | H1/6     | LVCMOS25_OUT | PL41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[25]            | J1/6     | LVCMOS25_OUT | PL41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[26]            | K1/6     | LVCMOS25_OUT | PL41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[27]            | F2/7     | LVCMOS25_OUT | PL32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[28]            | H2/6     | LVCMOS25_OUT | PL35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[29]            | A17/1    | LVCMOS25_OUT | PT80A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[2]             | F3/7     | LVCMOS25_OUT | PL32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[30]            | E16/2    | LVCMOS25_OUT | PR11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[31]            | R18/3    | LVCMOS25_OUT | PR65B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[3]             | C16/1    | LVCMOS25_OUT | PT76A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[4]             | E4/7     | LVCMOS25_OUT | PL17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[5]             | C3/7     | LVCMOS25_OUT | PL17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[6]             | F4/7     | LVCMOS25_OUT | PL20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[7]             | B3/7     | LVCMOS25_OUT | PL14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[8]             | E8/0     | LVCMOS25_OUT | PT13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[9]             | C7/0     | LVCMOS25_OUT | PT11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_discard                 | B11/0    | LVCMOS25_OUT | PT38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[0]         | D3/7     | LVCMOS25_OUT | PL17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[10]        | B17/1    | LVCMOS25_OUT | PT78A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[11]        | U17/3    | LVCMOS25_OUT | PR68B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[1]         | D9/0     | LVCMOS25_OUT | PT20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[2]         | A6/0     | LVCMOS25_OUT | PT4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[3]         | C6/0     | LVCMOS25_OUT | PT11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[4]         | F5/7     | LVCMOS25_OUT | PL20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[5]         | C4/7     | LVCMOS25_OUT | PL14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[6]         | D8/0     | LVCMOS25_OUT | PT13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[7]         | D5/7     | LVCMOS25_OUT | PL17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[8]         | B4/7     | LVCMOS25_OUT | PL14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[9]         | B20/1    | LVCMOS25_OUT | PT85B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[0]  | A11/0    | LVCMOS25_OUT | PT36B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[10] | T17/3    | LVCMOS25_OUT | PR68D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[11] | D18/2    | LVCMOS25_OUT | PR14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[1]  | A13/1    | LVCMOS25_OUT | PT49B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[2]  | B10/0    | LVCMOS25_OUT | PT33B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[3]  | C12/1    | LVCMOS25_OUT | PT44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[4]  | E12/1    | LVCMOS25_OUT | PT47B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[5]  | D12/1    | LVCMOS25_OUT | PT47A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[6]  | E11/1    | LVCMOS25_OUT | PT42B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[7]  | D11/1    | LVCMOS25_OUT | PT42A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[8]  | B13/1    | LVCMOS25_OUT | PT51A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[9]  | A12/1    | LVCMOS25_OUT | PT49A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_valid      | A7/0     | LVCMOS25_OUT | PT18A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[0]            | E9/0     | LVCMOS25_OUT | PT20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[1]            | C11/0    | LVCMOS25_OUT | PT38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[2]            | E6/0     | LVCMOS25_OUT | PT6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[3]            | D7/0     | LVCMOS25_OUT | PT9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[0]            | A3/7     | LVCMOS25_OUT | PL14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[1]            | B5/7     | LVCMOS25_OUT | PL11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[2]            | A5/7     | LVCMOS25_OUT | PL11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[3]            | C5/7     | LVCMOS25_OUT | PL11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[0]           | V2/8     | LVCMOS25_OUT | PB11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[1]           | L5/6     | LVCMOS25_OUT | PL44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[2]           | K2/6     | LVCMOS25_OUT | PL41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[3]           | K4/6     | LVCMOS25_OUT | PL44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_lvl1                    | E1/7     | LVCMOS25_IN  | PL26D |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_lvl1_invalid            | W2/8     | LVCMOS25_IN  | PB11B |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_offset[0]               | D10/0    | LVCMOS25_OUT | PT29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[1]               | C10/0    | LVCMOS25_OUT | PT31B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[2]               | E10/0    | LVCMOS25_OUT | PT29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[3]               | D1/7     | LVCMOS25_OUT | PL26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[4]               | C1/7     | LVCMOS25_OUT | PL26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[5]               | D2/7     | LVCMOS25_OUT | PL26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[6]               | A2/7     | LVCMOS25_OUT | PL23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[7]               | B9/0     | LVCMOS25_OUT | PT31A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[8]               | B2/7     | LVCMOS25_OUT | PL23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset_valid            | D15/1    | LVCMOS25_OUT | PT71A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_out_valid           | E15/1    | LVCMOS25_OUT | PT71B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[0]       | U20/3    | LVCMOS25_OUT | PR62D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[1]       | E17/2    | LVCMOS25_OUT | PR14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_trig                    | H5/7     | LVCMOS25_IN  | PL29C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_window_end              | C14/1    | LVCMOS25_OUT | PT56B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| last_buf_empty                | L18/3    | LVCMOS25_OUT | PR38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| rd_clk                        | B12/1    | LVCMOS25_IN  | PT44A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| release_out                   | A14/1    | LVCMOS25_OUT | PT56A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| reset_dc                      | C8/0     | LVCMOS25_IN  | PT15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[0]                       | R2/8     | LVCMOS25_IN  | PB15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[1]                       | T3/8     | LVCMOS25_IN  | PB18A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[2]                       | T19/3    | LVCMOS25_IN  | PR65A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
+| 6    | 2.5V  |
+| 7    | 2.5V  |
+| 8    | 2.5V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| Pin/Bank | Pin Info                      | Preference | Buffer Type  | Site         | Dual Function            | BC Enable |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| A2/7     | hades_offset[6]               |            | LVCMOS25_OUT | PL23A        | LDQ29                    |           |
+| A3/7     | hades_hit_valid[0]            |            | LVCMOS25_OUT | PL14C        | LDQ17                    |           |
+| A4/7     | hades_buf_finished            |            | LVCMOS25_OUT | PL11A        | ULC_GPLL0T_IN/LDQ17      |           |
+| A5/7     | hades_hit_valid[2]            |            | LVCMOS25_OUT | PL11B        | ULC_GPLL0C_IN/LDQ17      |           |
+| A6/0     | hades_drop_cmp_buf[2]         |            | LVCMOS25_OUT | PT4A         | ULC_GPLL1T_IN            |           |
+| A7/0     | hades_drop_cmp_buf_valid      |            | LVCMOS25_OUT | PT18A        |                          |           |
+| A8/0     | hades_dbg2_out[10]            |            | LVCMOS25_OUT | PT18B        |                          |           |
+| A9/0     | LVL1_TRG_DATA_VALID_IN        | LOCATED    | LVCMOS25_IN  | PT33A        | GR_PCLK0_1               |           |
+| A10/0    | hades_buf_drop[1]             |            | LVCMOS25_OUT | PT36A        | PCLKT0_1                 |           |
+| A11/0    | hades_drop_cmp_buf_coarse[0]  |            | LVCMOS25_OUT | PT36B        |                          |           |
+| A12/1    | hades_drop_cmp_buf_coarse[9]  |            | LVCMOS25_OUT | PT49A        |                          |           |
+| A13/1    | hades_drop_cmp_buf_coarse[1]  |            | LVCMOS25_OUT | PT49B        |                          |           |
+| A14/1    | release_out                   |            | LVCMOS25_OUT | PT56A        |                          |           |
+| A15/1    | FEE_DATA_OUT[18]              |            | LVCMOS25_OUT | PT67A        |                          |           |
+| A16/1    | FEE_DATA_OUT[6]               |            | LVCMOS25_OUT | PT74A        |                          |           |
+| A17/1    | hades_dbg2_out[29]            |            | LVCMOS25_OUT | PT80A        |                          |           |
+| A18/1    |     unused, PULL:DOWN         |            |              | PT83A        |                          |           |
+| A19/1    | fifo_rden                     |            | LVCMOS25_OUT | PT85A        | URC_GPLL1T_IN            |           |
+| B1/7     | hades_dbg2_coarse[5]          |            | LVCMOS25_OUT | PL23B        | LDQ29                    |           |
+| B2/7     | hades_offset[8]               |            | LVCMOS25_OUT | PL23C        | VREF1_7/LDQ29            |           |
+| B3/7     | hades_dbg2_out[7]             |            | LVCMOS25_OUT | PL14D        | LDQ17                    |           |
+| B4/7     | hades_drop_cmp_buf[8]         |            | LVCMOS25_OUT | PL14B        | LDQ17                    |           |
+| B5/7     | hades_hit_valid[1]            |            | LVCMOS25_OUT | PL11C        | LDQ17                    |           |
+| B6/0     | hades_dbg2_coarse[4]          |            | LVCMOS25_OUT | PT4B         | ULC_GPLL1C_IN            |           |
+| B8/0     | hades_dbg2_out[12]            |            | LVCMOS25_OUT | PT15B        |                          |           |
+| B9/0     | hades_offset[7]               |            | LVCMOS25_OUT | PT31A        |                          |           |
+| B10/0    | hades_drop_cmp_buf_coarse[2]  |            | LVCMOS25_OUT | PT33B        | GR_PCLK0_0               |           |
+| B11/0    | hades_discard                 |            | LVCMOS25_OUT | PT38A        | PCLKT0_0                 |           |
+| B12/1    | rd_clk                        |            | LVCMOS25_IN  | PT44A        | PCLKT1_0                 |           |
+| B13/1    | hades_drop_cmp_buf_coarse[8]  |            | LVCMOS25_OUT | PT51A        |                          |           |
+| B15/1    | FEE_DATA_OUT[17]              |            | LVCMOS25_OUT | PT69A        |                          |           |
+| B16/1    | fifo_data_out[6]              |            | LVCMOS25_OUT | PT74B        |                          |           |
+| B17/1    | hades_drop_cmp_buf[10]        |            | LVCMOS25_OUT | PT78A        |                          |           |
+| B18/1    |     unused, PULL:DOWN         |            |              | PT80B        |                          |           |
+| B19/1    |     unused, PULL:DOWN         |            |              | PT83B        |                          |           |
+| B20/1    | hades_drop_cmp_buf[9]         |            | LVCMOS25_OUT | PT85B        | URC_GPLL1C_IN            |           |
+| C1/7     | hades_offset[4]               |            | LVCMOS25_OUT | PL26A        | LDQ29                    |           |
+| C2/7     | hades_dbg2_coarse[3]          |            | LVCMOS25_OUT | PL23D        | LDQ29                    |           |
+| C3/7     | hades_dbg2_out[5]             |            | LVCMOS25_OUT | PL17C        | LDQ17                    |           |
+| C4/7     | hades_drop_cmp_buf[5]         |            | LVCMOS25_OUT | PL14A        | LDQ17                    |           |
+| C5/7     | hades_hit_valid[3]            |            | LVCMOS25_OUT | PL11D        | LDQ17                    |           |
+| C6/0     | hades_drop_cmp_buf[3]         |            | LVCMOS25_OUT | PT11A        |                          |           |
+| C7/0     | hades_dbg2_out[9]             |            | LVCMOS25_OUT | PT11B        |                          |           |
+| C8/0     | reset_dc                      |            | LVCMOS25_IN  | PT15A        |                          |           |
+| C9/0     | hades_buf_out_valid           |            | LVCMOS25_OUT | PT27A        |                          |           |
+| C10/0    | hades_offset[1]               |            | LVCMOS25_OUT | PT31B        |                          |           |
+| C11/0    | hades_hit_out_i[1]            |            | LVCMOS25_OUT | PT38B        |                          |           |
+| C12/1    | hades_drop_cmp_buf_coarse[3]  |            | LVCMOS25_OUT | PT44B        |                          |           |
+| C13/1    | FEE_DATA_WRITE_OUT            |            | LVCMOS25_OUT | PT51B        |                          |           |
+| C14/1    | hades_window_end              |            | LVCMOS25_OUT | PT56B        |                          |           |
+| C15/1    | fifo_data_out[17]             |            | LVCMOS25_OUT | PT69B        |                          |           |
+| C16/1    | hades_dbg2_out[3]             |            | LVCMOS25_OUT | PT76A        |                          |           |
+| C17/1    | hades_dbg2_out[15]            |            | LVCMOS25_OUT | PT78B        |                          |           |
+| C18/2    |     unused, PULL:DOWN         |            |              | PR11A        | URC_GPLL0T_IN/RDQ17      |           |
+| C20/2    | FEE_DATA_OUT[27]              |            | LVCMOS25_OUT | PR23A        | RDQ29                    |           |
+| CCLK/8   |                               |            |              | CCLK         | MCLK/SCK                 |           |
+| D1/7     | hades_offset[3]               |            | LVCMOS25_OUT | PL26B        | LDQ29                    |           |
+| D2/7     | hades_offset[5]               |            | LVCMOS25_OUT | PL26C        | LDQ29                    |           |
+| D3/7     | hades_drop_cmp_buf[0]         |            | LVCMOS25_OUT | PL17D        | LDQ17                    |           |
+| D5/7     | hades_drop_cmp_buf[7]         |            | LVCMOS25_OUT | PL17B        | LDQSN17                  |           |
+| D6/0     | hades_dbg2_out[11]            |            | LVCMOS25_OUT | PT6B         |                          |           |
+| D7/0     | hades_hit_out_i[3]            |            | LVCMOS25_OUT | PT9B         |                          |           |
+| D8/0     | hades_drop_cmp_buf[6]         |            | LVCMOS25_OUT | PT13B        |                          |           |
+| D9/0     | hades_drop_cmp_buf[1]         |            | LVCMOS25_OUT | PT20A        |                          |           |
+| D10/0    | hades_offset[0]               |            | LVCMOS25_OUT | PT29A        |                          |           |
+| D11/1    | hades_drop_cmp_buf_coarse[7]  |            | LVCMOS25_OUT | PT42A        | PCLKT1_1                 |           |
+| D12/1    | hades_drop_cmp_buf_coarse[5]  |            | LVCMOS25_OUT | PT47A        | GR_PCLK1_0               |           |
+| D13/1    | FEE_DATAFINISHED_OUT          |            | LVCMOS25_OUT | PT53A        |                          |           |
+| D14/1    | finished                      |            | LVCMOS25_OUT | PT58A        |                          |           |
+| D15/1    | hades_offset_valid            |            | LVCMOS25_OUT | PT71A        |                          |           |
+| D16/1    |     unused, PULL:DOWN         |            |              | PT76B        |                          |           |
+| D17/2    | fifo_data_out[5]              |            | LVCMOS25_OUT | PR11B        | URC_GPLL0C_IN/RDQ17      |           |
+| D18/2    | hades_drop_cmp_buf_coarse[11] |            | LVCMOS25_OUT | PR14A        | RDQ17                    |           |
+| D19/2    | fifo_data_out[27]             |            | LVCMOS25_OUT | PR23B        | RDQ29                    |           |
+| D20/2    | FEE_DATA_OUT[30]              |            | LVCMOS25_OUT | PR23C        | VREF1_2/RDQ29            |           |
+| E1/7     | hades_lvl1                    | LOCATED    | LVCMOS25_IN  | PL26D        | LDQ29                    |           |
+| E2/7     | hades_dbg2_out[1]             |            | LVCMOS25_OUT | PL32D        | PCLKC7_0/LDQ29           |           |
+| E3/7     | hades_dbg2_coarse[2]          |            | LVCMOS25_OUT | PL20B        | LDQ17                    |           |
+| E4/7     | hades_dbg2_out[4]             |            | LVCMOS25_OUT | PL17A        | LDQS17                   |           |
+| E5/7     | hades_dbg2_coarse[6]          |            | LVCMOS25_OUT | PL20C        | LDQ17                    |           |
+| E6/0     | hades_hit_out_i[2]            |            | LVCMOS25_OUT | PT6A         |                          |           |
+| E7/0     | hades_buf_release             |            | LVCMOS25_OUT | PT9A         |                          |           |
+| E8/0     | hades_dbg2_out[8]             |            | LVCMOS25_OUT | PT13A        |                          |           |
+| E9/0     | hades_hit_out_i[0]            |            | LVCMOS25_OUT | PT20B        |                          |           |
+| E10/0    | hades_offset[2]               |            | LVCMOS25_OUT | PT29B        |                          |           |
+| E11/1    | hades_drop_cmp_buf_coarse[6]  |            | LVCMOS25_OUT | PT42B        |                          |           |
+| E12/1    | hades_drop_cmp_buf_coarse[4]  |            | LVCMOS25_OUT | PT47B        | GR_PCLK1_1               |           |
+| E13/1    | FEE_TRG_RELEASE_OUT           |            | LVCMOS25_OUT | PT53B        |                          |           |
+| E14/1    | fifo_data_out[18]             |            | LVCMOS25_OUT | PT58B        |                          |           |
+| E15/1    | hades_raw_out_valid           |            | LVCMOS25_OUT | PT71B        |                          |           |
+| E16/2    | hades_dbg2_out[30]            |            | LVCMOS25_OUT | PR11C        | RDQ17                    |           |
+| E17/2    | hades_raw_valid_vect[1]       |            | LVCMOS25_OUT | PR14B        | RDQ17                    |           |
+| E18/2    | FEE_DATA_OUT[4]               |            | LVCMOS25_OUT | PR14C        | RDQ17                    |           |
+| E19/2    | fifo_data_out[30]             |            | LVCMOS25_OUT | PR23D        | RDQ29                    |           |
+| E20/2    | fifo_data_out[9]              |            | LVCMOS25_OUT | PR26A        | RDQ29                    |           |
+| F1/6     | hades_dbg2_coarse[8]          |            | LVCMOS25_OUT | PL35B        | PCLKC6_1/LDQ41           |           |
+| F2/7     | hades_dbg2_out[27]            |            | LVCMOS25_OUT | PL32C        | PCLKT7_0/LDQ29           |           |
+| F3/7     | hades_dbg2_out[2]             |            | LVCMOS25_OUT | PL32B        | PCLKC7_1/LDQ29           |           |
+| F4/7     | hades_dbg2_out[6]             |            | LVCMOS25_OUT | PL20A        | LDQ17                    |           |
+| F5/7     | hades_drop_cmp_buf[4]         |            | LVCMOS25_OUT | PL20D        | LDQ17                    |           |
+| F16/2    | FEE_DATA_OUT[5]               |            | LVCMOS25_OUT | PR11D        | RDQ17                    |           |
+| F17/2    | fifo_data_out[2]              |            | LVCMOS25_OUT | PR17A        | RDQS17                   |           |
+| F18/2    | fifo_data_out[4]              |            | LVCMOS25_OUT | PR14D        | RDQ17                    |           |
+| F19/2    | FEE_DATA_OUT[28]              |            | LVCMOS25_OUT | PR26B        | RDQ29                    |           |
+| F20/2    | FEE_DATA_OUT[9]               |            | LVCMOS25_OUT | PR26C        | RDQ29                    |           |
+| G1/6     | hades_dbg2_out[17]            |            | LVCMOS25_OUT | PL35D        | PCLKC6_0/LDQ41           |           |
+| G2/6     | hades_dbg2_out[21]            |            | LVCMOS25_OUT | PL35A        | PCLKT6_1/LDQ41           |           |
+| G3/7     | hades_dbg2_out[16]            |            | LVCMOS25_OUT | PL32A        | PCLKT7_1/LDQ29           |           |
+| G5/7     | hades_dbg2_coarse[0]          |            | LVCMOS25_OUT | PL29B        | LDQSN29                  |           |
+| G16/2    | FEE_DATA_OUT[13]              |            | LVCMOS25_OUT | PR17C        | RDQ17                    |           |
+| G18/2    | FEE_DATA_OUT[2]               |            | LVCMOS25_OUT | PR17B        | RDQSN17                  |           |
+| G19/2    | FEE_DATA_OUT[21]              |            | LVCMOS25_OUT | PR29A        | GR_PCLK2_1/RDQS29        |           |
+| G20/2    | fifo_data_out[28]             |            | LVCMOS25_OUT | PR26D        | RDQ29                    |           |
+| H1/6     | hades_dbg2_out[24]            |            | LVCMOS25_OUT | PL41C        | LDQ41                    |           |
+| H2/6     | hades_dbg2_out[28]            |            | LVCMOS25_OUT | PL35C        | PCLKT6_0/LDQ41           |           |
+| H3/7     | hades_dbg2_coarse[1]          |            | LVCMOS25_OUT | PL29D        | LDQ29                    |           |
+| H4/7     | hades_dbg2_out[22]            |            | LVCMOS25_OUT | PL29A        | GR_PCLK7_1/LDQS29        |           |
+| H5/7     | hades_trig                    | LOCATED    | LVCMOS25_IN  | PL29C        | GR_PCLK7_0/LDQ29         |           |
+| H16/2    | fifo_data_out[31]             |            | LVCMOS25_OUT | PR17D        | RDQ17                    |           |
+| H17/2    | FEE_DATA_OUT[25]              |            | LVCMOS25_OUT | PR20B        | RDQ17                    |           |
+| H18/2    | FEE_DATA_OUT[31]              |            | LVCMOS25_OUT | PR20A        | RDQ17                    |           |
+| H20/2    | FEE_DATA_OUT[23]              |            | LVCMOS25_OUT | PR29B        | RDQSN29                  |           |
+| J1/6     | hades_dbg2_out[25]            |            | LVCMOS25_OUT | PL41B        | LDQSN41                  |           |
+| J3/6     | hades_dbg2_out[0]             |            | LVCMOS25_OUT | PL38C        | GR_PCLK6_1/LDQ41         |           |
+| J4/6     | hades_dbg2_out[23]            |            | LVCMOS25_OUT | PL38A        | GR_PCLK6_0/LDQ41         |           |
+| J5/6     | hades_dbg2_out[18]            |            | LVCMOS25_OUT | PL38B        | LDQ41                    |           |
+| J16/2    | fifo_data_out[13]             |            | LVCMOS25_OUT | PR20D        | RDQ17                    |           |
+| J17/2    | fifo_data_out[25]             |            | LVCMOS25_OUT | PR20C        | RDQ17                    |           |
+| J18/2    | fifo_data_out[23]             |            | LVCMOS25_OUT | PR29C        | GR_PCLK2_0/RDQ29         |           |
+| J19/2    | FEE_DATA_OUT[10]              |            | LVCMOS25_OUT | PR32A        | PCLKT2_1/RDQ29           |           |
+| J20/2    | fifo_data_out[15]             |            | LVCMOS25_OUT | PR32C        | PCLKT2_0/RDQ29           |           |
+| K1/6     | hades_dbg2_out[26]            |            | LVCMOS25_OUT | PL41D        | LDQ41                    |           |
+| K2/6     | hades_invalid_dl[2]           |            | LVCMOS25_OUT | PL41A        | LDQS41                   |           |
+| K3/6     | hades_dbg2_out[20]            |            | LVCMOS25_OUT | PL38D        | LDQ41                    |           |
+| K4/6     | hades_invalid_dl[3]           |            | LVCMOS25_OUT | PL44A        | LDQ41                    |           |
+| K5/6     | FEE_DATA_OUT[19]              |            | LVCMOS25_OUT | PL44B        | VREF1_6/LDQ41            |           |
+| K18/2    | fifo_data_out[21]             |            | LVCMOS25_OUT | PR29D        | RDQ29                    |           |
+| K19/2    | FEE_DATA_OUT[24]              |            | LVCMOS25_OUT | PR32B        | PCLKC2_1/RDQ29           |           |
+| K20/2    | fifo_data_out[10]             |            | LVCMOS25_OUT | PR32D        | PCLKC2_0/RDQ29           |           |
+| L1/6     |     unused, PULL:DOWN         |            |              | PL65C        | LDQ65                    |           |
+| L2/6     |     unused, PULL:DOWN         |            |              | PL62D        | LDQ65                    |           |
+| L3/6     | FEE_DATA_OUT[7]               |            | LVCMOS25_OUT | PL62C        | LDQ65                    |           |
+| L4/6     | fifo_data_out[19]             |            | LVCMOS25_OUT | PL44C        | LDQ41                    |           |
+| L5/6     | hades_invalid_dl[1]           |            | LVCMOS25_OUT | PL44D        | LDQ41                    |           |
+| L16/3    | FEE_DATA_OUT[8]               |            | LVCMOS25_OUT | PR38A        | GR_PCLK3_0/RDQ41         |           |
+| L17/3    | fifo_data_out[3]              |            | LVCMOS25_OUT | PR38B        | RDQ41                    |           |
+| L18/3    | last_buf_empty                |            | LVCMOS25_OUT | PR38C        | GR_PCLK3_1/RDQ41         |           |
+| L19/3    | FEE_DATA_OUT[26]              |            | LVCMOS25_OUT | PR35C        | PCLKT3_0/RDQ41           |           |
+| L20/3    | fifo_data_out[26]             |            | LVCMOS25_OUT | PR35A        | PCLKT3_1/RDQ41           |           |
+| M1/6     |     unused, PULL:DOWN         |            |              | PL65B        | LDQSN65                  |           |
+| M3/6     | fifo_data_out[1]              |            | LVCMOS25_OUT | PL62B        | LDQ65                    |           |
+| M4/6     | fifo_data_out[14]             |            | LVCMOS25_OUT | PL59A        | LDQ65                    |           |
+| M5/6     | hades_dbg2_coarse[7]          |            | LVCMOS25_OUT | PL53A        | LDQS53                   |           |
+| M17/3    | FEE_DATA_OUT[3]               |            | LVCMOS25_OUT | PR41B        | RDQSN41                  |           |
+| M18/3    | fifo_data_out[8]              |            | LVCMOS25_OUT | PR38D        | RDQ41                    |           |
+| M19/3    | FEE_DATA_OUT[15]              |            | LVCMOS25_OUT | PR35D        | PCLKC3_0/RDQ41           |           |
+| M20/3    | fifo_data_out[24]             |            | LVCMOS25_OUT | PR35B        | PCLKC3_1/RDQ41           |           |
+| N1/6     | fifo_data_out[7]              |            | LVCMOS25_OUT | PL65D        | LDQ65                    |           |
+| N2/6     |     unused, PULL:DOWN         |            |              | PL65A        | LDQS65                   |           |
+| N3/6     | FEE_DATA_OUT[1]               |            | LVCMOS25_OUT | PL62A        | LDQ65                    |           |
+| N4/6     | fifo_data_out[12]             |            | LVCMOS25_OUT | PL59C        | LDQ65                    |           |
+| N5/6     | FEE_DATA_OUT[12]              |            | LVCMOS25_OUT | PL59B        | LDQ65                    |           |
+| N16/3    | burst                         |            | LVCMOS25_OUT | PR41A        | RDQS41                   |           |
+| N17/3    | fifo_empty1                   |            | LVCMOS25_OUT | PR44A        | RDQ41                    |           |
+| N18/3    | LVL1_TRG_DATA_VALI_IN_rising  |            | LVCMOS25_OUT | PR41C        | RDQ41                    |           |
+| N19/3    | FEE_DATA_OUT[16]              |            | LVCMOS25_OUT | PR59A        | RDQ65                    |           |
+| N20/3    | hades_buf_drop[0]             |            | LVCMOS25_OUT | PR59B        | RDQ65                    |           |
+| P1/6     | hades_dbg2_out[14]            |            | LVCMOS25_OUT | PL68A        | LDQ65                    |           |
+| P2/6     |     unused, PULL:DOWN         |            |              | PL68B        | LDQ65                    |           |
+| P3/6     | clk+                          | LOCATED    | LVDS_IN      | PL68C        | LLC_GPLL0T_IN/LDQ65      |           |
+| P4/6     | clk-                          |            | LVDS_IN      | PL68D        | LLC_GPLL0C_IN/LDQ65      |           |
+| P5/6     | FEE_DATA_OUT[14]              |            | LVCMOS25_OUT | PL59D        | LDQ65                    |           |
+| P16/3    | discard                       |            | LVCMOS25_OUT | PR44B        | VREF1_3/RDQ41            |           |
+| P17/3    | fifo_data_out[0]              |            | LVCMOS25_OUT | PR41D        | RDQ41                    |           |
+| P18/3    | fifo_data_out[16]             |            | LVCMOS25_OUT | PR59D        | RDQ65                    |           |
+| P19/3    | hades_dbg2_out[13]            |            | LVCMOS25_OUT | PR59C        | RDQ65                    |           |
+| P20/3    |     unused, PULL:DOWN         |            |              | PR62A        | RDQ65                    |           |
+| PL47A/6  |     unused, PULL:DOWN         |            |              | PL47A        | LDQ53                    |           |
+| PL47B/6  |     unused, PULL:DOWN         |            |              | PL47B        | LDQ53                    |           |
+| PL47C/6  |     unused, PULL:DOWN         |            |              | PL47C        | LDQ53                    |           |
+| PL47D/6  |     unused, PULL:DOWN         |            |              | PL47D        | LDQ53                    |           |
+| PL50A/6  |     unused, PULL:DOWN         |            |              | PL50A        | LDQ53                    |           |
+| PL50B/6  |     unused, PULL:DOWN         |            |              | PL50B        | LDQ53                    |           |
+| PL50C/6  |     unused, PULL:DOWN         |            |              | PL50C        | LDQ53                    |           |
+| PL50D/6  |     unused, PULL:DOWN         |            |              | PL50D        | LDQ53                    |           |
+| PL53B/6  |     unused, PULL:DOWN         |            |              | PL53B        | LDQSN53                  |           |
+| PL53C/6  |     unused, PULL:DOWN         |            |              | PL53C        | LDQ53                    |           |
+| PL53D/6  |     unused, PULL:DOWN         |            |              | PL53D        | LDQ53                    |           |
+| PL56A/6  |     unused, PULL:DOWN         |            |              | PL56A        | LDQ53                    |           |
+| PL56B/6  |     unused, PULL:DOWN         |            |              | PL56B        | LDQ53                    |           |
+| PL56C/6  |     unused, PULL:DOWN         |            |              | PL56C        | LDQ53                    |           |
+| PL56D/6  |     unused, PULL:DOWN         |            |              | PL56D        | LDQ53                    |           |
+| PR47A/3  |     unused, PULL:DOWN         |            |              | PR47A        | RDQ53                    |           |
+| PR47B/3  |     unused, PULL:DOWN         |            |              | PR47B        | RDQ53                    |           |
+| PR47C/3  |     unused, PULL:DOWN         |            |              | PR47C        | RDQ53                    |           |
+| PR47D/3  |     unused, PULL:DOWN         |            |              | PR47D        | RDQ53                    |           |
+| PR50A/3  |     unused, PULL:DOWN         |            |              | PR50A        | RDQ53                    |           |
+| PR50B/3  |     unused, PULL:DOWN         |            |              | PR50B        | RDQ53                    |           |
+| PR50C/3  |     unused, PULL:DOWN         |            |              | PR50C        | RDQ53                    |           |
+| PR50D/3  |     unused, PULL:DOWN         |            |              | PR50D        | RDQ53                    |           |
+| PR53B/3  |     unused, PULL:DOWN         |            |              | PR53B        | RDQSN53                  |           |
+| PR53C/3  |     unused, PULL:DOWN         |            |              | PR53C        | RDQ53                    |           |
+| PR53D/3  |     unused, PULL:DOWN         |            |              | PR53D        | RDQ53                    |           |
+| PR56A/3  |     unused, PULL:DOWN         |            |              | PR56A        | RDQ53                    |           |
+| PR56B/3  |     unused, PULL:DOWN         |            |              | PR56B        | RDQ53                    |           |
+| PR56C/3  |     unused, PULL:DOWN         |            |              | PR56C        | RDQ53                    |           |
+| PR56D/3  |     unused, PULL:DOWN         |            |              | PR56D        | RDQ53                    |           |
+| PT22A/0  |     unused, PULL:DOWN         |            |              | PT22A        |                          |           |
+| PT22B/0  |     unused, PULL:DOWN         |            |              | PT22B        |                          |           |
+| PT24A/0  |     unused, PULL:DOWN         |            |              | PT24A        |                          |           |
+| PT24B/0  |     unused, PULL:DOWN         |            |              | PT24B        |                          |           |
+| PT27B/0  |     unused, PULL:DOWN         |            |              | PT27B        |                          |           |
+| PT60A/1  |     unused, PULL:DOWN         |            |              | PT60A        |                          |           |
+| PT60B/1  |     unused, PULL:DOWN         |            |              | PT60B        |                          |           |
+| PT62A/1  |     unused, PULL:DOWN         |            |              | PT62A        |                          |           |
+| PT62B/1  |     unused, PULL:DOWN         |            |              | PT62B        |                          |           |
+| PT65A/1  |     unused, PULL:DOWN         |            |              | PT65A        |                          |           |
+| PT65B/1  |     unused, PULL:DOWN         |            |              | PT65B        |                          |           |
+| PT67B/1  |     unused, PULL:DOWN         |            |              | PT67B        |                          |           |
+| R1/8     | hades_dbg2_out[19]            |            | LVCMOS25_OUT | PB4A         | D7/IO7                   |           |
+| R2/8     | trig[0]                       | LOCATED    | LVCMOS25_IN  | PB15A        | HOLDN/DI/BUSY/CSSPIN/CEN |           |
+| R3/8     | FEE_DATA_OUT[11]              |            | LVCMOS25_OUT | PB15B        | DOUT/CSON                |           |
+| R16/3    | LVL1_INVALID_TRG_IN           |            | LVCMOS25_IN  | PR44C        | RDQ41                    |           |
+| R17/3    | FEE_DATA_OUT[0]               |            | LVCMOS25_OUT | PR44D        | RDQ41                    |           |
+| R18/3    | hades_dbg2_out[31]            |            | LVCMOS25_OUT | PR65B        | RDQSN65                  |           |
+| R20/3    | hades_buf_drop[2]             |            | LVCMOS25_OUT | PR62B        | RDQ65                    |           |
+| T1/8     | fifo_data_out[29]             |            | LVCMOS25_OUT | PB4B         | D6/IO6                   |           |
+| T2/8     | FEE_DATA_OUT[22]              |            | LVCMOS25_OUT | PB13A        | SN/CSN                   |           |
+| T3/8     | trig[1]                       | LOCATED    | LVCMOS25_IN  | PB18A        | WRITEN                   |           |
+| T16/3    |     unused, PULL:DOWN         |            |              | PR53A        | RDQS53                   |           |
+| T17/3    | hades_drop_cmp_buf_coarse[10] |            | LVCMOS25_OUT | PR68D        | LRC_GPLL0C_IN/RDQ65      |           |
+| T18/3    |     unused, PULL:DOWN         |            |              | PR65D        | RDQ65                    |           |
+| T19/3    | trig[2]                       | LOCATED    | LVCMOS25_IN  | PR65A        | RDQS65                   |           |
+| T20/3    |     unused, PULL:DOWN         |            |              | PR62C        | RDQ65                    |           |
+| TCK/40   |                               |            |              | TCK          |                          |           |
+| TDI/40   |                               |            |              | TDI          |                          |           |
+| TDO/40   |                               |            |              | TDO          |                          |           |
+| TMS/40   |                               |            |              | TMS          |                          |           |
+| U1/8     | FEE_DATA_OUT[29]              |            | LVCMOS25_OUT | PB6A         | D5/MISO2/IO5             |           |
+| U2/8     | fifo_data_out[11]             |            | LVCMOS25_OUT | PB13B        | CS1N                     |           |
+| U16/3    | hades_buf_drop[3]             |            | LVCMOS25_OUT | PR68C        | LRC_GPLL0T_IN/RDQ65      |           |
+| U17/3    | hades_drop_cmp_buf[11]        |            | LVCMOS25_OUT | PR68B        | RDQ65                    |           |
+| U18/3    |     unused, PULL:DOWN         |            |              | PR68A        | RDQ65                    |           |
+| U19/3    |     unused, PULL:DOWN         |            |              | PR65C        | RDQ65                    |           |
+| U20/3    | hades_raw_valid_vect[0]       |            | LVCMOS25_OUT | PR62D        | RDQ65                    |           |
+| V1/8     | FEE_DATA_OUT[20]              |            | LVCMOS25_OUT | PB6B         | D4/MOSI2/IO4             |           |
+| V2/8     | hades_invalid_dl[0]           |            | LVCMOS25_OUT | PB11A        | D1/MISO/IO1              |           |
+| W1/8     | fifo_data_out[22]             |            | LVCMOS25_OUT | PB9A         | D3/IO3                   |           |
+| W2/8     | hades_lvl1_invalid            |            | LVCMOS25_IN  | PB11B        | D0/MOSI/IO0              |           |
+| W4/50    |                               |            |              | HDTXP0_D0CH0 |                          |           |
+| W5/50    |                               |            |              | HDTXN0_D0CH0 |                          |           |
+| W8/50    |                               |            |              | HDTXP0_D0CH1 |                          |           |
+| W9/50    |                               |            |              | HDTXN0_D0CH1 |                          |           |
+| W13/51   |                               |            |              | HDTXP0_D1CH0 |                          |           |
+| W14/51   |                               |            |              | HDTXN0_D1CH0 |                          |           |
+| W17/51   |                               |            |              | HDTXP0_D1CH1 |                          |           |
+| W18/51   |                               |            |              | HDTXN0_D1CH1 |                          |           |
+| W20/51   |                               |            |              | REFCLKN_D1   |                          |           |
+| Y2/8     | fifo_data_out[20]             |            | LVCMOS25_OUT | PB9B         | D2/IO2                   |           |
+| Y5/50    |                               |            |              | HDRXP0_D0CH0 |                          |           |
+| Y6/50    |                               |            |              | HDRXN0_D0CH0 |                          |           |
+| Y7/50    |                               |            |              | HDRXP0_D0CH1 |                          |           |
+| Y8/50    |                               |            |              | HDRXN0_D0CH1 |                          |           |
+| Y11/50   |                               |            |              | REFCLKP_D0   |                          |           |
+| Y12/50   |                               |            |              | REFCLKN_D0   |                          |           |
+| Y14/51   |                               |            |              | HDRXP0_D1CH0 |                          |           |
+| Y15/51   |                               |            |              | HDRXN0_D1CH0 |                          |           |
+| Y16/51   |                               |            |              | HDRXP0_D1CH1 |                          |           |
+| Y17/51   |                               |            |              | HDRXN0_D1CH1 |                          |           |
+| Y19/51   |                               |            |              | REFCLKP_D1   |                          |           |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "FEE_DATAFINISHED_OUT"  SITE  "D13";
+LOCATE  COMP  "FEE_DATA_OUT[0]"  SITE  "R17";
+LOCATE  COMP  "FEE_DATA_OUT[10]"  SITE  "J19";
+LOCATE  COMP  "FEE_DATA_OUT[11]"  SITE  "R3";
+LOCATE  COMP  "FEE_DATA_OUT[12]"  SITE  "N5";
+LOCATE  COMP  "FEE_DATA_OUT[13]"  SITE  "G16";
+LOCATE  COMP  "FEE_DATA_OUT[14]"  SITE  "P5";
+LOCATE  COMP  "FEE_DATA_OUT[15]"  SITE  "M19";
+LOCATE  COMP  "FEE_DATA_OUT[16]"  SITE  "N19";
+LOCATE  COMP  "FEE_DATA_OUT[17]"  SITE  "B15";
+LOCATE  COMP  "FEE_DATA_OUT[18]"  SITE  "A15";
+LOCATE  COMP  "FEE_DATA_OUT[19]"  SITE  "K5";
+LOCATE  COMP  "FEE_DATA_OUT[1]"  SITE  "N3";
+LOCATE  COMP  "FEE_DATA_OUT[20]"  SITE  "V1";
+LOCATE  COMP  "FEE_DATA_OUT[21]"  SITE  "G19";
+LOCATE  COMP  "FEE_DATA_OUT[22]"  SITE  "T2";
+LOCATE  COMP  "FEE_DATA_OUT[23]"  SITE  "H20";
+LOCATE  COMP  "FEE_DATA_OUT[24]"  SITE  "K19";
+LOCATE  COMP  "FEE_DATA_OUT[25]"  SITE  "H17";
+LOCATE  COMP  "FEE_DATA_OUT[26]"  SITE  "L19";
+LOCATE  COMP  "FEE_DATA_OUT[27]"  SITE  "C20";
+LOCATE  COMP  "FEE_DATA_OUT[28]"  SITE  "F19";
+LOCATE  COMP  "FEE_DATA_OUT[29]"  SITE  "U1";
+LOCATE  COMP  "FEE_DATA_OUT[2]"  SITE  "G18";
+LOCATE  COMP  "FEE_DATA_OUT[30]"  SITE  "D20";
+LOCATE  COMP  "FEE_DATA_OUT[31]"  SITE  "H18";
+LOCATE  COMP  "FEE_DATA_OUT[3]"  SITE  "M17";
+LOCATE  COMP  "FEE_DATA_OUT[4]"  SITE  "E18";
+LOCATE  COMP  "FEE_DATA_OUT[5]"  SITE  "F16";
+LOCATE  COMP  "FEE_DATA_OUT[6]"  SITE  "A16";
+LOCATE  COMP  "FEE_DATA_OUT[7]"  SITE  "L3";
+LOCATE  COMP  "FEE_DATA_OUT[8]"  SITE  "L16";
+LOCATE  COMP  "FEE_DATA_OUT[9]"  SITE  "F20";
+LOCATE  COMP  "FEE_DATA_WRITE_OUT"  SITE  "C13";
+LOCATE  COMP  "FEE_TRG_RELEASE_OUT"  SITE  "E13";
+LOCATE  COMP  "LVL1_INVALID_TRG_IN"  SITE  "R16";
+LOCATE  COMP  "LVL1_TRG_DATA_VALID_IN"  SITE  "A9";
+LOCATE  COMP  "LVL1_TRG_DATA_VALI_IN_rising"  SITE  "N18";
+LOCATE  COMP  "burst"  SITE  "N16";
+LOCATE  COMP  "clk"  SITE  "P3";
+LOCATE  COMP  "discard"  SITE  "P16";
+LOCATE  COMP  "fifo_data_out[0]"  SITE  "P17";
+LOCATE  COMP  "fifo_data_out[10]"  SITE  "K20";
+LOCATE  COMP  "fifo_data_out[11]"  SITE  "U2";
+LOCATE  COMP  "fifo_data_out[12]"  SITE  "N4";
+LOCATE  COMP  "fifo_data_out[13]"  SITE  "J16";
+LOCATE  COMP  "fifo_data_out[14]"  SITE  "M4";
+LOCATE  COMP  "fifo_data_out[15]"  SITE  "J20";
+LOCATE  COMP  "fifo_data_out[16]"  SITE  "P18";
+LOCATE  COMP  "fifo_data_out[17]"  SITE  "C15";
+LOCATE  COMP  "fifo_data_out[18]"  SITE  "E14";
+LOCATE  COMP  "fifo_data_out[19]"  SITE  "L4";
+LOCATE  COMP  "fifo_data_out[1]"  SITE  "M3";
+LOCATE  COMP  "fifo_data_out[20]"  SITE  "Y2";
+LOCATE  COMP  "fifo_data_out[21]"  SITE  "K18";
+LOCATE  COMP  "fifo_data_out[22]"  SITE  "W1";
+LOCATE  COMP  "fifo_data_out[23]"  SITE  "J18";
+LOCATE  COMP  "fifo_data_out[24]"  SITE  "M20";
+LOCATE  COMP  "fifo_data_out[25]"  SITE  "J17";
+LOCATE  COMP  "fifo_data_out[26]"  SITE  "L20";
+LOCATE  COMP  "fifo_data_out[27]"  SITE  "D19";
+LOCATE  COMP  "fifo_data_out[28]"  SITE  "G20";
+LOCATE  COMP  "fifo_data_out[29]"  SITE  "T1";
+LOCATE  COMP  "fifo_data_out[2]"  SITE  "F17";
+LOCATE  COMP  "fifo_data_out[30]"  SITE  "E19";
+LOCATE  COMP  "fifo_data_out[31]"  SITE  "H16";
+LOCATE  COMP  "fifo_data_out[3]"  SITE  "L17";
+LOCATE  COMP  "fifo_data_out[4]"  SITE  "F18";
+LOCATE  COMP  "fifo_data_out[5]"  SITE  "D17";
+LOCATE  COMP  "fifo_data_out[6]"  SITE  "B16";
+LOCATE  COMP  "fifo_data_out[7]"  SITE  "N1";
+LOCATE  COMP  "fifo_data_out[8]"  SITE  "M18";
+LOCATE  COMP  "fifo_data_out[9]"  SITE  "E20";
+LOCATE  COMP  "fifo_empty1"  SITE  "N17";
+LOCATE  COMP  "fifo_rden"  SITE  "A19";
+LOCATE  COMP  "finished"  SITE  "D14";
+LOCATE  COMP  "hades_buf_drop[0]"  SITE  "N20";
+LOCATE  COMP  "hades_buf_drop[1]"  SITE  "A10";
+LOCATE  COMP  "hades_buf_drop[2]"  SITE  "R20";
+LOCATE  COMP  "hades_buf_drop[3]"  SITE  "U16";
+LOCATE  COMP  "hades_buf_finished"  SITE  "A4";
+LOCATE  COMP  "hades_buf_out_valid"  SITE  "C9";
+LOCATE  COMP  "hades_buf_release"  SITE  "E7";
+LOCATE  COMP  "hades_dbg2_coarse[0]"  SITE  "G5";
+LOCATE  COMP  "hades_dbg2_coarse[1]"  SITE  "H3";
+LOCATE  COMP  "hades_dbg2_coarse[2]"  SITE  "E3";
+LOCATE  COMP  "hades_dbg2_coarse[3]"  SITE  "C2";
+LOCATE  COMP  "hades_dbg2_coarse[4]"  SITE  "B6";
+LOCATE  COMP  "hades_dbg2_coarse[5]"  SITE  "B1";
+LOCATE  COMP  "hades_dbg2_coarse[6]"  SITE  "E5";
+LOCATE  COMP  "hades_dbg2_coarse[7]"  SITE  "M5";
+LOCATE  COMP  "hades_dbg2_coarse[8]"  SITE  "F1";
+LOCATE  COMP  "hades_dbg2_out[0]"  SITE  "J3";
+LOCATE  COMP  "hades_dbg2_out[10]"  SITE  "A8";
+LOCATE  COMP  "hades_dbg2_out[11]"  SITE  "D6";
+LOCATE  COMP  "hades_dbg2_out[12]"  SITE  "B8";
+LOCATE  COMP  "hades_dbg2_out[13]"  SITE  "P19";
+LOCATE  COMP  "hades_dbg2_out[14]"  SITE  "P1";
+LOCATE  COMP  "hades_dbg2_out[15]"  SITE  "C17";
+LOCATE  COMP  "hades_dbg2_out[16]"  SITE  "G3";
+LOCATE  COMP  "hades_dbg2_out[17]"  SITE  "G1";
+LOCATE  COMP  "hades_dbg2_out[18]"  SITE  "J5";
+LOCATE  COMP  "hades_dbg2_out[19]"  SITE  "R1";
+LOCATE  COMP  "hades_dbg2_out[1]"  SITE  "E2";
+LOCATE  COMP  "hades_dbg2_out[20]"  SITE  "K3";
+LOCATE  COMP  "hades_dbg2_out[21]"  SITE  "G2";
+LOCATE  COMP  "hades_dbg2_out[22]"  SITE  "H4";
+LOCATE  COMP  "hades_dbg2_out[23]"  SITE  "J4";
+LOCATE  COMP  "hades_dbg2_out[24]"  SITE  "H1";
+LOCATE  COMP  "hades_dbg2_out[25]"  SITE  "J1";
+LOCATE  COMP  "hades_dbg2_out[26]"  SITE  "K1";
+LOCATE  COMP  "hades_dbg2_out[27]"  SITE  "F2";
+LOCATE  COMP  "hades_dbg2_out[28]"  SITE  "H2";
+LOCATE  COMP  "hades_dbg2_out[29]"  SITE  "A17";
+LOCATE  COMP  "hades_dbg2_out[2]"  SITE  "F3";
+LOCATE  COMP  "hades_dbg2_out[30]"  SITE  "E16";
+LOCATE  COMP  "hades_dbg2_out[31]"  SITE  "R18";
+LOCATE  COMP  "hades_dbg2_out[3]"  SITE  "C16";
+LOCATE  COMP  "hades_dbg2_out[4]"  SITE  "E4";
+LOCATE  COMP  "hades_dbg2_out[5]"  SITE  "C3";
+LOCATE  COMP  "hades_dbg2_out[6]"  SITE  "F4";
+LOCATE  COMP  "hades_dbg2_out[7]"  SITE  "B3";
+LOCATE  COMP  "hades_dbg2_out[8]"  SITE  "E8";
+LOCATE  COMP  "hades_dbg2_out[9]"  SITE  "C7";
+LOCATE  COMP  "hades_discard"  SITE  "B11";
+LOCATE  COMP  "hades_drop_cmp_buf[0]"  SITE  "D3";
+LOCATE  COMP  "hades_drop_cmp_buf[10]"  SITE  "B17";
+LOCATE  COMP  "hades_drop_cmp_buf[11]"  SITE  "U17";
+LOCATE  COMP  "hades_drop_cmp_buf[1]"  SITE  "D9";
+LOCATE  COMP  "hades_drop_cmp_buf[2]"  SITE  "A6";
+LOCATE  COMP  "hades_drop_cmp_buf[3]"  SITE  "C6";
+LOCATE  COMP  "hades_drop_cmp_buf[4]"  SITE  "F5";
+LOCATE  COMP  "hades_drop_cmp_buf[5]"  SITE  "C4";
+LOCATE  COMP  "hades_drop_cmp_buf[6]"  SITE  "D8";
+LOCATE  COMP  "hades_drop_cmp_buf[7]"  SITE  "D5";
+LOCATE  COMP  "hades_drop_cmp_buf[8]"  SITE  "B4";
+LOCATE  COMP  "hades_drop_cmp_buf[9]"  SITE  "B20";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[0]"  SITE  "A11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[10]"  SITE  "T17";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[11]"  SITE  "D18";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[1]"  SITE  "A13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[2]"  SITE  "B10";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[3]"  SITE  "C12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[4]"  SITE  "E12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[5]"  SITE  "D12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[6]"  SITE  "E11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[7]"  SITE  "D11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[8]"  SITE  "B13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[9]"  SITE  "A12";
+LOCATE  COMP  "hades_drop_cmp_buf_valid"  SITE  "A7";
+LOCATE  COMP  "hades_hit_out_i[0]"  SITE  "E9";
+LOCATE  COMP  "hades_hit_out_i[1]"  SITE  "C11";
+LOCATE  COMP  "hades_hit_out_i[2]"  SITE  "E6";
+LOCATE  COMP  "hades_hit_out_i[3]"  SITE  "D7";
+LOCATE  COMP  "hades_hit_valid[0]"  SITE  "A3";
+LOCATE  COMP  "hades_hit_valid[1]"  SITE  "B5";
+LOCATE  COMP  "hades_hit_valid[2]"  SITE  "A5";
+LOCATE  COMP  "hades_hit_valid[3]"  SITE  "C5";
+LOCATE  COMP  "hades_invalid_dl[0]"  SITE  "V2";
+LOCATE  COMP  "hades_invalid_dl[1]"  SITE  "L5";
+LOCATE  COMP  "hades_invalid_dl[2]"  SITE  "K2";
+LOCATE  COMP  "hades_invalid_dl[3]"  SITE  "K4";
+LOCATE  COMP  "hades_lvl1"  SITE  "E1";
+LOCATE  COMP  "hades_lvl1_invalid"  SITE  "W2";
+LOCATE  COMP  "hades_offset[0]"  SITE  "D10";
+LOCATE  COMP  "hades_offset[1]"  SITE  "C10";
+LOCATE  COMP  "hades_offset[2]"  SITE  "E10";
+LOCATE  COMP  "hades_offset[3]"  SITE  "D1";
+LOCATE  COMP  "hades_offset[4]"  SITE  "C1";
+LOCATE  COMP  "hades_offset[5]"  SITE  "D2";
+LOCATE  COMP  "hades_offset[6]"  SITE  "A2";
+LOCATE  COMP  "hades_offset[7]"  SITE  "B9";
+LOCATE  COMP  "hades_offset[8]"  SITE  "B2";
+LOCATE  COMP  "hades_offset_valid"  SITE  "D15";
+LOCATE  COMP  "hades_raw_out_valid"  SITE  "E15";
+LOCATE  COMP  "hades_raw_valid_vect[0]"  SITE  "U20";
+LOCATE  COMP  "hades_raw_valid_vect[1]"  SITE  "E17";
+LOCATE  COMP  "hades_trig"  SITE  "H5";
+LOCATE  COMP  "hades_window_end"  SITE  "C14";
+LOCATE  COMP  "last_buf_empty"  SITE  "L18";
+LOCATE  COMP  "rd_clk"  SITE  "B12";
+LOCATE  COMP  "release_out"  SITE  "A14";
+LOCATE  COMP  "reset_dc"  SITE  "C8";
+LOCATE  COMP  "trig[0]"  SITE  "R2";
+LOCATE  COMP  "trig[1]"  SITE  "T3";
+LOCATE  COMP  "trig[2]"  SITE  "T19";
+
+#PLL
+LOCATE  COMP  "pll0inst/PLLInst_0"  SITE  "PLL_BL0" ;
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:20:03 2021
+
diff --git a/impl1/s1_impl1.dir/5_1.par b/impl1/s1_impl1.dir/5_1.par
new file mode 100644
index 0000000..da19d19
--- /dev/null
+++ b/impl1/s1_impl1.dir/5_1.par
@@ -0,0 +1,296 @@
+
+Lattice Place and Route Report for Design "s1_impl1_map.ncd"
+Wed Jun 16 09:19:35 2021
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf
+Preference file: s1_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)     187/245          76% used
+                    187/203          92% bonded
+   IOLOGIC           35/245          14% used
+
+   SLICE            692/21924         3% used
+
+   EBR                4/108           3% used
+   PLL                1/4            25% used
+
+
+Number of Signals: 1594
+Number of Connections: 3725
+
+Pin Constraint Summary:
+   7 out of 186 pins locked (3% locked).
+
+The following 5 signals are selected to use the primary clock routing resources:
+    pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
+    pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+    pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0)
+    rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0)
+    pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+
+
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 8 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 788909.
+Finished Placer Phase 1.  REAL time: 24 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  774601
+Finished Placer Phase 2.  REAL time: 25 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 12 (8%)
+  GR_PCLK    : 0 out of 12 (0%)
+  PLL        : 1 out of 4 (25%)
+  DCS        : 0 out of 2 (0%)
+  DCC        : 0 out of 60 (0%)
+  CLKDIV     : 0 out of 4 (0%)
+
+Quadrant TL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant TR Clocks:
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8
+
+  PRIMARY  : 2 out of 16 (12%)
+
+Quadrant BL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant BR Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Edge Clocks:
+
+  No edge clock selected.
+
+
+--------------- End of Clock Report ---------------
+
+
++
+I/O Usage Summary (final):
+   187 out of 245 (76.3%) PIO sites used.
+   187 out of 203 (92.1%) bonded PIO sites used.
+   Number of PIO comps: 186; differential: 1.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 27 / 27 (100%) | 2.5V       | -          | -          |
+| 1        | 29 / 33 ( 87%) | 2.5V       | -          | -          |
+| 2        | 31 / 32 ( 96%) | 2.5V       | -          | -          |
+| 3        | 27 / 33 ( 81%) | 2.5V       | -          | -          |
+| 6        | 28 / 33 ( 84%) | 2.5V       | -          | -          |
+| 7        | 32 / 32 (100%) | 2.5V       | -          | -          |
+| 8        | 13 / 13 (100%) | 2.5V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 24 secs 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+0 connections routed; 3725 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 39 secs 
+
+Start NBR router at Wed Jun 16 09:20:14 CEST 2021
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021
+
+Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021
+Level 1, iteration 1
+21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.876ns/-158.654ns; real time: 41 secs 
+Level 2, iteration 1
+46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-159.217ns; real time: 41 secs 
+Level 3, iteration 1
+167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.962ns/-163.305ns; real time: 42 secs 
+Level 4, iteration 1
+81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-177.384ns; real time: 42 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021
+Level 1, iteration 1
+53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-171.398ns; real time: 43 secs 
+Level 4, iteration 1
+54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 2
+35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 3
+24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 4
+12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 5
+8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 43 secs 
+Level 4, iteration 6
+5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 44 secs 
+Level 4, iteration 7
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 8
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 9
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.896ns; real time: 44 secs 
+
+Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 156 (4.19%)
+  Estimated worst slack<setup> : -2.994ns
+  Timing score<setup> : 209210
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 46 secs 
+Total REAL time: 47 secs 
+Completely routed.
+End of route.  3725 routed (100.00%); 0 unrouted.
+
+Generating "par" statistics.
+
+
+   The Delay Summary Report
+
+   The SCORE FOR THIS DESIGN is: 284326
+
+
+   The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
+
+   The AVERAGE CONNECTION DELAY for this design is:          0.79 (  0.79)
+   The AVERAGE CONNECTION DELAY on CRITICAL NETS is:         0.00 (  0.00)
+   The CLOCK SKEW AVERAGE for this design is:                0.03
+   The MAXIMUM PIN DELAY IS:                                 4.32 (  4.32)
+   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:     3.37 (  3.37)
+
+   Listing Pin Delays by value: (nsec)
+
+    d <= 10    < d <= 20   < d <= 30   < d <= 40   < d <= 50    d > 50
+   ---------   ---------   ---------   ---------   ---------   ---------
+        3725           0           0           0           0           0
+
+Hold time timing score: 9, hold timing errors: 18
+
+
+Timing score: 209210 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -2.994
+PAR_SUMMARY::Timing score<setup/<ns>> = 209.210
+PAR_SUMMARY::Worst  slack<hold /<ns>> = -1.015
+PAR_SUMMARY::Timing score<hold /<ns>> = 9.647
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 48 secs 
+Total REAL time to completion: 48 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/impl1/s1_impl1.dir/5_1_par.asd b/impl1/s1_impl1.dir/5_1_par.asd
new file mode 100644
index 0000000..a3e7dbd
--- /dev/null
+++ b/impl1/s1_impl1.dir/5_1_par.asd
@@ -0,0 +1,67 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 5;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = pll_clks[0];
+GLOBAL_PRIMARY_0_DRIVERTYPE = PLL;
+GLOBAL_PRIMARY_0_LOADNUM = 25;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = pll_clks[1];
+GLOBAL_PRIMARY_1_DRIVERTYPE = PLL;
+GLOBAL_PRIMARY_1_LOADNUM = 24;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = pll_clks[3];
+GLOBAL_PRIMARY_2_DRIVERTYPE = PLL;
+GLOBAL_PRIMARY_2_LOADNUM = 446;
+; Global primary clock #3
+GLOBAL_PRIMARY_3_SIGNALNAME = rd_clk_c;
+GLOBAL_PRIMARY_3_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_3_LOADNUM = 38;
+; Global primary clock #4
+GLOBAL_PRIMARY_4_SIGNALNAME = pll_clks[2];
+GLOBAL_PRIMARY_4_DRIVERTYPE = PLL;
+GLOBAL_PRIMARY_4_LOADNUM = 24;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 27;
+BANK_0_AVAIL = 27;
+BANK_0_VCCIO = 2.5V;
+BANK_0_VREF1 = NA;
+BANK_0_VREF2 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 29;
+BANK_1_AVAIL = 33;
+BANK_1_VCCIO = 2.5V;
+BANK_1_VREF1 = NA;
+BANK_1_VREF2 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 31;
+BANK_2_AVAIL = 32;
+BANK_2_VCCIO = 2.5V;
+BANK_2_VREF1 = NA;
+BANK_2_VREF2 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 27;
+BANK_3_AVAIL = 33;
+BANK_3_VCCIO = 2.5V;
+BANK_3_VREF1 = NA;
+BANK_3_VREF2 = NA;
+; I/O Bank 6 Usage
+BANK_6_USED = 28;
+BANK_6_AVAIL = 33;
+BANK_6_VCCIO = 2.5V;
+BANK_6_VREF1 = NA;
+BANK_6_VREF2 = NA;
+; I/O Bank 7 Usage
+BANK_7_USED = 32;
+BANK_7_AVAIL = 32;
+BANK_7_VCCIO = 2.5V;
+BANK_7_VREF1 = NA;
+BANK_7_VREF2 = NA;
+; I/O Bank 8 Usage
+BANK_8_USED = 13;
+BANK_8_AVAIL = 13;
+BANK_8_VCCIO = 2.5V;
+BANK_8_VREF1 = NA;
+BANK_8_VREF2 = NA;
diff --git a/impl1/s1_impl1.dir/s1_impl1.par b/impl1/s1_impl1.dir/s1_impl1.par
new file mode 100644
index 0000000..2e34b09
--- /dev/null
+++ b/impl1/s1_impl1.dir/s1_impl1.par
@@ -0,0 +1,27 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:19:35 2021
+
+/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t
+s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset
+/home/hadaq/mmichalek/lattice/simplified/promote.xml
+
+
+Preference file: s1_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -2.994       209210       -1.015       9647         48           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 48 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/impl1/s1_impl1.dly b/impl1/s1_impl1.dly
new file mode 100644
index 0000000..cd0d94a
--- /dev/null
+++ b/impl1/s1_impl1.dly
@@ -0,0 +1,8546 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:19:35 2021
+
+File: s1_impl1.dir/5_1.dly
+
+ The 20 worst nets by delay are:
+---------------------------------
+| Max Delay         | Netname   |
+---------------------------------
+   4.3                 fifo_rden_c
+   3.7                 trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]
+   3.4                 reset_dl[2]
+   3.3                 FEE_DATA_OUT_c[16]
+   3.3                 hades_dbg2_coarse_c[7]
+   3.2                 FEE_DATA_OUT_c[18]
+   3.2                 FEE_DATA_OUT_c[5]
+   3.1                 FEE_DATA_OUT_c[7]
+   3.1                 FEE_DATA_OUT_c[6]
+   3.0                 FEE_DATA_OUT_c[20]
+   3.0                 hades_dbg2_coarse_c[4]
+   2.9                 FEE_DATA_OUT_c[17]
+   2.9                 FEE_DATA_OUT_c[28]
+   2.9                 FEE_DATA_OUT_c[1]
+   2.9                 hades_dbg2_coarse_c[5]
+   2.9                 FEE_DATA_OUT_c[4]
+   2.9                 FEE_DATA_OUT_c[2]
+   2.8                 FEE_DATA_OUT_c[13]
+   2.8                 FEE_DATA_OUT_c[22]
+   2.8                 FEE_DATA_OUT_c[25]
+---------------------------------
+
+-------------------------------------------------------------------------------
+                               Net Delays
+-------------------------------------------------------------------------------
+
+ANB0
+   hades_tdc_bundle_inst/hit_out_i_RNO[0].Q0
+         0.2  hades_tdc_bundle_inst/hit_out_i_RNO[0].D0
+         0.5  hades_tdc_bundle_inst/hit_out_i_RNO[0].B1
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C1
+         0.9  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].M0
+         0.3  hades_tdc_bundle_inst/buf_finished5_0_a2_0.D0
+         1.4  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.C0
+         0.3  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D0
+         1.5  hades_hit_out_i_pad[0].PADDO
+
+ANB1
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q0
+         0.6  hades_tdc_bundle_inst/hit_out_i_RNO[0].D1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.D1
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].C0
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A1
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.C0
+         0.3  hades_tdc_bundle_inst/buf_finished5_0_a2_0.D1
+         1.3  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.A0
+         0.5  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C1
+         0.5  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.C1
+         1.3  hades_hit_out_i_pad[1].PADDO
+
+ANB2
+   hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].Q0
+         0.9  hades_tdc_bundle_inst/hit_out_i_RNO[0].C1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B1
+         0.6  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B0
+         0.6  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B1
+         1.2  hades_tdc_bundle_inst/buf_finished5_0_a2_0.A0
+         0.9  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.B0
+         1.2  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B0
+         1.2  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B1
+         1.5  hades_hit_out_i_pad[2].PADDO
+
+ANB3
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q1
+         0.7  hades_tdc_bundle_inst/hit_out_i_RNO[0].A1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.A1
+         1.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A0
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.B0
+         0.6  hades_tdc_bundle_inst/buf_finished5_0_a2_0.B1
+         0.8  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.D0
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A1
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A1
+         1.7  hades_hit_out_i_pad[3].PADDO
+
+FEE_DATAFINISHED_OUT_c
+   trb_adapter_inst_FEE_DATAFINISHED_OUTio.IOLDO
+         0.0  FEE_DATAFINISHED_OUT_pad.IOLDO
+
+FEE_DATA_OUT_c[0]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA0
+         2.5  fifo_data_out_pad[0].PADDO
+         2.8  FEE_DATA_OUT_pad[0].PADDO
+
+FEE_DATA_OUT_c[10]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA10
+         2.1  FEE_DATA_OUT_pad[10].PADDO
+         2.1  fifo_data_out_pad[10].PADDO
+
+FEE_DATA_OUT_c[11]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA11
+         2.5  FEE_DATA_OUT_pad[11].PADDO
+         2.5  fifo_data_out_pad[11].PADDO
+
+FEE_DATA_OUT_c[12]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA12
+         2.4  FEE_DATA_OUT_pad[12].PADDO
+         2.6  fifo_data_out_pad[12].PADDO
+
+FEE_DATA_OUT_c[13]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA13
+         2.8  FEE_DATA_OUT_pad[13].PADDO
+         2.8  fifo_data_out_pad[13].PADDO
+
+FEE_DATA_OUT_c[14]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA14
+         2.6  FEE_DATA_OUT_pad[14].PADDO
+         2.8  fifo_data_out_pad[14].PADDO
+
+FEE_DATA_OUT_c[15]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA15
+         2.5  FEE_DATA_OUT_pad[15].PADDO
+         2.1  fifo_data_out_pad[15].PADDO
+
+FEE_DATA_OUT_c[16]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA16
+         3.2  FEE_DATA_OUT_pad[16].PADDO
+         3.3  fifo_data_out_pad[16].PADDO
+
+FEE_DATA_OUT_c[17]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA17
+         2.8  FEE_DATA_OUT_pad[17].PADDO
+         2.9  fifo_data_out_pad[17].PADDO
+
+FEE_DATA_OUT_c[18]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB0
+         2.8  FEE_DATA_OUT_pad[18].PADDO
+         3.2  fifo_data_out_pad[18].PADDO
+
+FEE_DATA_OUT_c[19]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB1
+         2.2  FEE_DATA_OUT_pad[19].PADDO
+         2.2  fifo_data_out_pad[19].PADDO
+
+FEE_DATA_OUT_c[1]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA1
+         2.9  FEE_DATA_OUT_pad[1].PADDO
+         2.9  fifo_data_out_pad[1].PADDO
+
+FEE_DATA_OUT_c[20]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB2
+         2.8  FEE_DATA_OUT_pad[20].PADDO
+         3.0  fifo_data_out_pad[20].PADDO
+
+FEE_DATA_OUT_c[21]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB3
+         2.4  FEE_DATA_OUT_pad[21].PADDO
+         2.3  fifo_data_out_pad[21].PADDO
+
+FEE_DATA_OUT_c[22]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB4
+         2.7  FEE_DATA_OUT_pad[22].PADDO
+         2.8  fifo_data_out_pad[22].PADDO
+
+FEE_DATA_OUT_c[23]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB5
+         2.4  FEE_DATA_OUT_pad[23].PADDO
+         2.4  fifo_data_out_pad[23].PADDO
+
+FEE_DATA_OUT_c[24]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB6
+         2.4  FEE_DATA_OUT_pad[24].PADDO
+         2.7  fifo_data_out_pad[24].PADDO
+
+FEE_DATA_OUT_c[25]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB7
+         2.8  FEE_DATA_OUT_pad[25].PADDO
+         2.8  fifo_data_out_pad[25].PADDO
+
+FEE_DATA_OUT_c[26]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB8
+         2.7  FEE_DATA_OUT_pad[26].PADDO
+         2.8  fifo_data_out_pad[26].PADDO
+
+FEE_DATA_OUT_c[27]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB9
+         2.8  FEE_DATA_OUT_pad[27].PADDO
+         2.8  fifo_data_out_pad[27].PADDO
+
+FEE_DATA_OUT_c[28]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB10
+         2.8  FEE_DATA_OUT_pad[28].PADDO
+         2.9  fifo_data_out_pad[28].PADDO
+
+FEE_DATA_OUT_c[29]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB11
+         2.7  FEE_DATA_OUT_pad[29].PADDO
+         2.7  fifo_data_out_pad[29].PADDO
+
+FEE_DATA_OUT_c[2]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA2
+         2.9  FEE_DATA_OUT_pad[2].PADDO
+         2.9  fifo_data_out_pad[2].PADDO
+
+FEE_DATA_OUT_c[30]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB12
+         2.6  FEE_DATA_OUT_pad[30].PADDO
+         2.6  fifo_data_out_pad[30].PADDO
+
+FEE_DATA_OUT_c[31]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB13
+         2.6  FEE_DATA_OUT_pad[31].PADDO
+         2.8  fifo_data_out_pad[31].PADDO
+
+FEE_DATA_OUT_c[3]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA3
+         2.5  FEE_DATA_OUT_pad[3].PADDO
+         2.5  fifo_data_out_pad[3].PADDO
+
+FEE_DATA_OUT_c[4]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA4
+         2.9  FEE_DATA_OUT_pad[4].PADDO
+         2.9  fifo_data_out_pad[4].PADDO
+
+FEE_DATA_OUT_c[5]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA5
+         3.0  FEE_DATA_OUT_pad[5].PADDO
+         3.2  fifo_data_out_pad[5].PADDO
+
+FEE_DATA_OUT_c[6]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA6
+         2.9  FEE_DATA_OUT_pad[6].PADDO
+         3.1  fifo_data_out_pad[6].PADDO
+
+FEE_DATA_OUT_c[7]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA7
+         2.9  FEE_DATA_OUT_pad[7].PADDO
+         3.1  fifo_data_out_pad[7].PADDO
+
+FEE_DATA_OUT_c[8]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA8
+         2.5  FEE_DATA_OUT_pad[8].PADDO
+         2.5  fifo_data_out_pad[8].PADDO
+
+FEE_DATA_OUT_c[9]
+   fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA9
+         2.4  FEE_DATA_OUT_pad[9].PADDO
+         2.6  fifo_data_out_pad[9].PADDO
+
+FEE_DATA_WRITE_OUT_c
+   trb_adapter_inst_FEE_DATA_WRITE_OUTio.IOLDO
+         0.0  FEE_DATA_WRITE_OUT_pad.IOLDO
+
+FEE_TRG_RELEASE_OUT_c
+   trb_adapter_inst_FEE_TRG_RELEASE_OUTio.IOLDO
+         0.0  FEE_TRG_RELEASE_OUT_pad.IOLDO
+
+LVL1_INVALID_TRG_IN_c
+   LVL1_INVALID_TRG_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALID_IN_c
+   LVL1_TRG_DATA_VALID_IN_pad.PADDI
+         0.0  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].DI
+
+LVL1_TRG_DATA_VALI_IN_rising_c
+   trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F0
+         0.6  LVL1_TRG_DATA_VALI_IN_rising_pad.PADDO
+
+N_248_i
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.OFX0
+         0.4  hades_tdc_bundle_inst_buf_out_validio.CE
+
+burst_c
+   trb_adapter_inst/burst.F1
+         0.4  trb_adapter_inst/burst.B0
+         0.4  burst_pad.PADDO
+
+clk_c
+   clk_pad.PADDI
+         0.1  pll0inst/PLLInst_0.CLKI
+
+discard_c
+   trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].Q0
+         0.8  trb_adapter_inst/burst.C1
+         0.4  discard_pad.PADDO
+
+fifo_colector_inst/buffer_wr_enable
+   fifo_colector_inst/in_empty_pmux_0_RNIDRET.Q0
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[11].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[11].Q1
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA11
+
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+   fifo_colector_inst/data_buffer_3_0[13].Q0
+         0.6  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA12
+
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+   fifo_colector_inst/data_buffer_3_0[13].Q1
+         0.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA13
+
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+   fifo_colector_inst/data_buffer_3_0[15].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[15].Q1
+         0.5  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA15
+
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+
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+   fifo_colector_inst/data_buffer_3_0[17].Q1
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+
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+   fifo_colector_inst/data_buffer_3_0[19].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[19].Q1
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+
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+   fifo_colector_inst/data_buffer_3[1].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA1
+
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+   fifo_colector_inst/data_buffer_3_0[21].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[21].Q1
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[23].Q1
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+
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+   fifo_colector_inst/data_buffer_3_0[25].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[25].Q1
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+
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+   fifo_colector_inst/data_buffer_3_0[27].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB8
+
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+   fifo_colector_inst/data_buffer_3_0[27].Q1
+         1.0  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB9
+
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+
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+   fifo_colector_inst/data_buffer_3_0[29].Q1
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[31].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[31].Q1
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+
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+         0.5  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB14
+
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+   fifo_colector_inst/data_buffer[33].Q1
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+
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+   fifo_colector_inst/data_buffer_3[3].Q0
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+
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+
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+
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+   fifo_colector_inst/data_buffer_3[6].Q0
+         0.9  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA6
+
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+   fifo_colector_inst/data_buffer_3[7].Q0
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+
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+   fifo_colector_inst/data_buffer_3_0[9].Q0
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[17].F1
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[19].F1
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+
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+   fifo_colector_inst/data_buffer_3[1].OFX0
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+
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+   fifo_colector_inst/data_buffer_3_0[21].F0
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+
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+
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+
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+
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+   fifo_colector_inst/data_buffer_3_0[25].F0
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   fifo_colector_inst/data_buffer_3[3].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[4].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[5].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[6].OFX0
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+
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+   fifo_colector_inst/data_buffer_3[7].OFX0
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+
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+
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+
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+
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+   fifo_colector_inst/in_read_enable_1_.fb.F1
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+
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+   fifo_colector_inst/fifo40_inst/FF_0.Q0
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+
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+
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+   fifo_colector_inst/fifo40_inst/full_cmp_ci_a.FCO
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+
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+   fifo_colector_inst/fifo40_inst/FF_100.FCO
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+
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+   fifo_colector_inst/fifo40_inst/FF_70.FCO
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+
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+
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+   fifo_colector_inst/fifo40_inst/full_cmp_0.FCO
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+
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+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         1.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         1.6  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0
+         1.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fb_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0
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+
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+
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+
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+
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
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+
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+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
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+
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+
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+
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+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         1.2  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         1.2  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         1.0  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         1.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.A0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.9  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.1  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.8  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         1.1  fifo_colector_inst/data_buffer_3[0].B0
+         1.1  fifo_colector_inst/data_buffer_3[0].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.9  fifo_colector_inst/data_buffer_3_0[11].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         1.2  fifo_colector_inst/data_buffer_3_0[11].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.7  fifo_colector_inst/data_buffer_3_0[13].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3_0[13].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.9  fifo_colector_inst/data_buffer_3_0[15].A0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.7  fifo_colector_inst/data_buffer_3_0[15].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.6  fifo_colector_inst/data_buffer_3_0[17].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         0.8  fifo_colector_inst/data_buffer_3_0[17].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.7  fifo_colector_inst/data_buffer_3_0[19].D0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         1.1  fifo_colector_inst/data_buffer_3_0[19].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.0  fifo_colector_inst/data_buffer_3[1].B0
+         1.0  fifo_colector_inst/data_buffer_3[1].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.9  fifo_colector_inst/data_buffer_3_0[21].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         1.0  fifo_colector_inst/data_buffer_3_0[21].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.8  fifo_colector_inst/data_buffer_3_0[23].C0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.9  fifo_colector_inst/data_buffer_3_0[23].A1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         1.0  fifo_colector_inst/data_buffer_3[2].C0
+         1.0  fifo_colector_inst/data_buffer_3[2].C1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.8  fifo_colector_inst/data_buffer_3[3].C0
+         0.8  fifo_colector_inst/data_buffer_3[3].C1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.9  fifo_colector_inst/data_buffer_3[4].D0
+         0.9  fifo_colector_inst/data_buffer_3[4].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         1.1  fifo_colector_inst/data_buffer_3[5].B0
+         1.1  fifo_colector_inst/data_buffer_3[5].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.9  fifo_colector_inst/data_buffer_3[6].B0
+         0.9  fifo_colector_inst/data_buffer_3[6].B1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.8  fifo_colector_inst/data_buffer_3[7].D0
+         0.8  fifo_colector_inst/data_buffer_3[7].D1
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         1.0  fifo_colector_inst/data_buffer_3_0[9].B0
+
+genblk1[0].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3_0[9].C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.A0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fb_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
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+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0
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+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
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+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.A0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         1.1  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         1.0  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.1  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.9  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.2  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.5  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.9  fifo_colector_inst/data_buffer_3_0[25].A0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.9  fifo_colector_inst/data_buffer_3[2].B0
+         0.9  fifo_colector_inst/data_buffer_3[2].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.7  fifo_colector_inst/data_buffer_3[3].B0
+         0.7  fifo_colector_inst/data_buffer_3[3].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         0.6  fifo_colector_inst/data_buffer_3[4].B0
+         0.6  fifo_colector_inst/data_buffer_3[4].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.5  fifo_colector_inst/data_buffer_3[5].C0
+         0.5  fifo_colector_inst/data_buffer_3[5].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         0.4  fifo_colector_inst/data_buffer_3[6].D0
+         0.4  fifo_colector_inst/data_buffer_3[6].D1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.9  fifo_colector_inst/data_buffer_3[7].C0
+         0.9  fifo_colector_inst/data_buffer_3[7].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         0.7  fifo_colector_inst/data_buffer_3_0[9].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         1.1  fifo_colector_inst/data_buffer_3_0[9].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.8  fifo_colector_inst/data_buffer_3_0[11].B0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.9  fifo_colector_inst/data_buffer_3_0[11].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.0  fifo_colector_inst/data_buffer_3_0[25].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.8  fifo_colector_inst/data_buffer_3_0[13].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.8  fifo_colector_inst/data_buffer_3_0[13].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.6  fifo_colector_inst/data_buffer_3_0[15].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.8  fifo_colector_inst/data_buffer_3_0[15].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.5  fifo_colector_inst/data_buffer_3_0[27].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.7  fifo_colector_inst/data_buffer_3_0[27].B1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.7  fifo_colector_inst/data_buffer_3_0[29].C0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.8  fifo_colector_inst/data_buffer_3_0[29].A1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.6  fifo_colector_inst/data_buffer_3_0[31].D0
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.7  fifo_colector_inst/data_buffer_3_0[31].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         0.9  fifo_colector_inst/data_buffer_3[0].C0
+         0.9  fifo_colector_inst/data_buffer_3[0].C1
+
+genblk1[1].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3[1].C0
+         0.9  fifo_colector_inst/data_buffer_3[1].C1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0
+         1.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/decoder_valid
+   genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.Q0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fb_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0
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+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0
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+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0
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+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0
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+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0
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+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1
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+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0
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+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0
+         1.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0
+         0.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1
+         0.1  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1
+         0.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1
+         0.9  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.C0
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15
+         1.0  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0
+         0.2  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.3  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0
+
+genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7]
+   genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[0]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.9  fifo_colector_inst/data_buffer_3_0[17].C0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[10]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10
+         0.8  fifo_colector_inst/data_buffer_3_0[27].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[11]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11
+         0.7  fifo_colector_inst/data_buffer_3_0[27].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[12]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12
+         1.0  fifo_colector_inst/data_buffer_3_0[29].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[13]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13
+         0.8  fifo_colector_inst/data_buffer_3_0[29].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[14]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14
+         1.1  fifo_colector_inst/data_buffer_3_0[31].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[15]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15
+         0.8  fifo_colector_inst/data_buffer_3_0[31].D1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[16]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16
+         1.0  fifo_colector_inst/data_buffer_3[0].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[17]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17
+         1.0  fifo_colector_inst/data_buffer_3[1].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[18]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0
+         0.8  fifo_colector_inst/data_buffer_3[2].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[19]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1
+         0.8  fifo_colector_inst/data_buffer_3[3].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[1]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         1.1  fifo_colector_inst/data_buffer_3_0[17].C1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[20]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2
+         0.8  fifo_colector_inst/data_buffer_3[4].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[21]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3
+         0.9  fifo_colector_inst/data_buffer_3[5].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[22]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4
+         0.9  fifo_colector_inst/data_buffer_3[6].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[23]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5
+         0.9  fifo_colector_inst/data_buffer_3[7].M0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[2]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         1.0  fifo_colector_inst/data_buffer_3_0[19].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[3]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         1.0  fifo_colector_inst/data_buffer_3_0[19].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[4]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.9  fifo_colector_inst/data_buffer_3_0[21].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[5]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         1.1  fifo_colector_inst/data_buffer_3_0[21].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[6]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         1.0  fifo_colector_inst/data_buffer_3_0[23].A0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[7]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         1.0  fifo_colector_inst/data_buffer_3_0[23].B1
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[8]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8
+         1.0  fifo_colector_inst/data_buffer_3_0[25].B0
+
+genblk1[2].un1_tdc_channel_fifo_out_inst[9]
+   genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9
+         0.9  fifo_colector_inst/data_buffer_3_0[25].C1
+
+hades_buf_drop_c[1]
+   hades_tdc_bundle_inst_buf_drop_1io[1].IOLDO
+         0.0  hades_buf_drop_pad[1].IOLDO
+
+hades_buf_finished_c
+   hades_tdc_bundle_inst/buf_finished5_0_a2_0.Q0
+         0.9  hades_tdc_bundle_inst/buf_release.M0
+         1.2  hades_buf_finished_pad.PADDO
+
+hades_buf_out_valid_c
+   hades_tdc_bundle_inst_buf_out_validio.IOLDO
+         0.0  hades_buf_out_valid_pad.IOLDO
+
+hades_buf_release_c
+   hades_tdc_bundle_inst/buf_release.Q0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[0].D0
+         1.2  hades_tdc_bundle_inst/hit_valid_1_RNO[0].B1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].D0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].D1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].C1
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[3].C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[3].B1
+         1.3  hades_buf_release_pad.PADDO
+
+hades_dbg2_coarse_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q0
+         1.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.C1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.C1
+         0.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.C1
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].A0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].A1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B1
+         1.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M1
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D1
+         1.8  hades_dbg2_coarse_pad[0].PADDO
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].TXDATA0
+
+hades_dbg2_coarse_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.D1
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.D1
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.B1
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].D0
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M0
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B1
+         1.8  hades_dbg2_coarse_pad[1].PADDO
+         1.5  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].TXDATA0
+
+hades_dbg2_coarse_c[2]
+   hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q0
+         0.3  hades_tdc_bundle_inst/coarse_RNI6RPP[2].C0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].B1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A1
+         1.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A0
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C1
+         2.7  hades_dbg2_coarse_pad[2].PADDO
+         2.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].TXDATA0
+
+hades_dbg2_coarse_c[3]
+   hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A0
+         0.5  hades_tdc_bundle_inst/coarse_RNI6RPP[2].C1
+         0.9  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A0
+         0.9  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C1
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.A0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.C0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A1
+         2.0  hades_dbg2_coarse_pad[3].PADDO
+         1.8  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].TXDATA0
+
+hades_dbg2_coarse_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q0
+         0.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.C1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.D1
+         1.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M1
+         1.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M1
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.D1
+         3.0  hades_dbg2_coarse_pad[4].PADDO
+         1.9  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].TXDATA0
+
+hades_dbg2_coarse_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.A1
+         2.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M0
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M0
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.B1
+         2.9  hades_dbg2_coarse_pad[5].PADDO
+         2.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].TXDATA0
+
+hades_dbg2_coarse_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q0
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C0
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C1
+         2.1  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M1
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M1
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.C0
+         2.5  hades_dbg2_coarse_pad[6].PADDO
+
+hades_dbg2_coarse_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D0
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C0
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D1
+         1.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M0
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.A0
+         3.3  hades_dbg2_coarse_pad[7].PADDO
+
+hades_dbg2_coarse_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.Q0
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D1
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C0
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.C1
+         1.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M1
+         1.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M1
+         2.4  hades_dbg2_coarse_pad[8].PADDO
+
+hades_dbg2_out_c[0]
+   hades_tdc_bundle_inst_hitbuffer_1_io[0].IOLDO
+         0.0  hades_dbg2_out_pad[0].IOLDO
+
+hades_dbg2_out_c[10]
+   hades_tdc_bundle_inst/hitbuffer_1_[10].Q0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[7].M0
+         1.7  hades_dbg2_out_pad[10].PADDO
+
+hades_dbg2_out_c[11]
+   hades_tdc_bundle_inst/hitbuffer_1_[10].Q1
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[7].M1
+         1.9  hades_dbg2_out_pad[11].PADDO
+
+hades_dbg2_out_c[12]
+   hades_tdc_bundle_inst/hitbuffer_1_[11].Q0
+         1.0  hades_tdc_bundle_inst/drop_cmp_buf_1[8].M0
+         1.7  hades_dbg2_out_pad[12].PADDO
+
+hades_dbg2_out_c[16]
+   hades_tdc_bundle_inst_hitbuffer_1_io[12].IOLDO
+         0.0  hades_dbg2_out_pad[16].IOLDO
+
+hades_dbg2_out_c[17]
+   hades_tdc_bundle_inst_hitbuffer_1_io[13].IOLDO
+         0.0  hades_dbg2_out_pad[17].IOLDO
+
+hades_dbg2_out_c[18]
+   hades_tdc_bundle_inst_hitbuffer_1_io[14].IOLDO
+         0.0  hades_dbg2_out_pad[18].IOLDO
+
+hades_dbg2_out_c[1]
+   hades_tdc_bundle_inst_hitbuffer_1_io[1].IOLDO
+         0.0  hades_dbg2_out_pad[1].IOLDO
+
+hades_dbg2_out_c[20]
+   hades_tdc_bundle_inst_hitbuffer_1_io[15].IOLDO
+         0.0  hades_dbg2_out_pad[20].IOLDO
+
+hades_dbg2_out_c[21]
+   hades_tdc_bundle_inst_hitbuffer_1_io[16].IOLDO
+         0.0  hades_dbg2_out_pad[21].IOLDO
+
+hades_dbg2_out_c[22]
+   hades_tdc_bundle_inst_hitbuffer_1_io[17].IOLDO
+         0.0  hades_dbg2_out_pad[22].IOLDO
+
+hades_dbg2_out_c[23]
+   hades_tdc_bundle_inst_hitbuffer_1_io[18].IOLDO
+         0.0  hades_dbg2_out_pad[23].IOLDO
+
+hades_dbg2_out_c[24]
+   hades_tdc_bundle_inst_hitbuffer_1_io[19].IOLDO
+         0.0  hades_dbg2_out_pad[24].IOLDO
+
+hades_dbg2_out_c[25]
+   hades_tdc_bundle_inst_hitbuffer_1_io[20].IOLDO
+         0.0  hades_dbg2_out_pad[25].IOLDO
+
+hades_dbg2_out_c[26]
+   hades_tdc_bundle_inst_hitbuffer_1_io[21].IOLDO
+         0.0  hades_dbg2_out_pad[26].IOLDO
+
+hades_dbg2_out_c[27]
+   hades_tdc_bundle_inst_hitbuffer_1_io[22].IOLDO
+         0.0  hades_dbg2_out_pad[27].IOLDO
+
+hades_dbg2_out_c[28]
+   hades_tdc_bundle_inst_hitbuffer_1_io[23].IOLDO
+         0.0  hades_dbg2_out_pad[28].IOLDO
+
+hades_dbg2_out_c[2]
+   hades_tdc_bundle_inst_hitbuffer_1_io[2].IOLDO
+         0.0  hades_dbg2_out_pad[2].IOLDO
+
+hades_dbg2_out_c[4]
+   hades_tdc_bundle_inst/hitbuffer_1_[4].Q0
+         0.8  hades_tdc_bundle_inst/drop_cmp_buf_1[1].M0
+         1.8  hades_dbg2_out_pad[4].PADDO
+
+hades_dbg2_out_c[5]
+   hades_tdc_bundle_inst/hitbuffer_1_[4].Q1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[1].M1
+         1.4  hades_dbg2_out_pad[5].PADDO
+
+hades_dbg2_out_c[6]
+   hades_tdc_bundle_inst/hitbuffer_1_[6].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[3].M0
+         1.5  hades_dbg2_out_pad[6].PADDO
+
+hades_dbg2_out_c[7]
+   hades_tdc_bundle_inst/hitbuffer_1_[6].Q1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_1[3].M1
+         1.4  hades_dbg2_out_pad[7].PADDO
+
+hades_dbg2_out_c[8]
+   hades_tdc_bundle_inst/hitbuffer_1_[8].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[5].M0
+         1.5  hades_dbg2_out_pad[8].PADDO
+
+hades_dbg2_out_c[9]
+   hades_tdc_bundle_inst/hitbuffer_1_[8].Q1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_1[5].M1
+         1.5  hades_dbg2_out_pad[9].PADDO
+
+hades_discard_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.Q0
+         1.5  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].D0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.A0
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].M0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A0
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A1
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B0
+         1.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B1
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.A0
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C1
+         1.0  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.A0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.A0
+         0.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.B0
+         0.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].B0
+         1.3  hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].A0
+         2.1  hades_discard_pad.PADDO
+
+hades_drop_cmp_buf_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.D1
+         1.1  hades_drop_cmp_buf_pad[0].PADDO
+
+hades_drop_cmp_buf_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q1
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.A1
+         1.3  hades_drop_cmp_buf_pad[1].PADDO
+
+hades_drop_cmp_buf_c[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C0
+         1.5  hades_drop_cmp_buf_pad[2].PADDO
+
+hades_drop_cmp_buf_c[3]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q1
+         1.0  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A0
+         1.5  hades_drop_cmp_buf_pad[3].PADDO
+
+hades_drop_cmp_buf_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q0
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A1
+         1.4  hades_drop_cmp_buf_pad[4].PADDO
+
+hades_drop_cmp_buf_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q1
+         0.9  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C1
+         1.4  hades_drop_cmp_buf_pad[5].PADDO
+
+hades_drop_cmp_buf_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B0
+         1.2  hades_drop_cmp_buf_pad[6].PADDO
+
+hades_drop_cmp_buf_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q1
+         0.8  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.A0
+         1.6  hades_drop_cmp_buf_pad[7].PADDO
+
+hades_drop_cmp_buf_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_1[8].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D1
+         1.4  hades_drop_cmp_buf_pad[8].PADDO
+
+hades_drop_cmp_buf_coarse_c[0]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.C1
+         1.5  hades_drop_cmp_buf_coarse_pad[0].PADDO
+
+hades_drop_cmp_buf_coarse_c[1]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_1_0.B1
+         1.9  hades_drop_cmp_buf_coarse_pad[1].PADDO
+
+hades_drop_cmp_buf_coarse_c[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B0
+         1.5  hades_drop_cmp_buf_coarse_pad[2].PADDO
+
+hades_drop_cmp_buf_coarse_c[3]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D0
+         2.0  hades_drop_cmp_buf_coarse_pad[3].PADDO
+
+hades_drop_cmp_buf_coarse_c[4]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B1
+         1.8  hades_drop_cmp_buf_coarse_pad[4].PADDO
+
+hades_drop_cmp_buf_coarse_c[5]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q1
+         0.5  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D1
+         1.9  hades_drop_cmp_buf_coarse_pad[5].PADDO
+
+hades_drop_cmp_buf_coarse_c[6]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q0
+         0.6  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C0
+         1.7  hades_drop_cmp_buf_coarse_pad[6].PADDO
+
+hades_drop_cmp_buf_coarse_c[7]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q1
+         0.4  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D0
+         1.6  hades_drop_cmp_buf_coarse_pad[7].PADDO
+
+hades_drop_cmp_buf_coarse_c[8]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B1
+         1.9  hades_drop_cmp_buf_coarse_pad[8].PADDO
+
+hades_drop_cmp_buf_coarse_c[9]
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.Q0
+         0.7  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C1
+         2.0  hades_drop_cmp_buf_coarse_pad[9].PADDO
+
+hades_drop_cmp_buf_valid_c
+   hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.Q0
+         0.3  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.C0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].B0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[1].B1
+         0.5  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D1
+         1.3  hades_drop_cmp_buf_valid_pad.PADDO
+
+hades_hit_valid_c[0]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[0].Q0
+         0.3  hades_tdc_bundle_inst/hit_valid_1_RNO[0].C0
+         0.3  hades_tdc_bundle_inst/hit_valid_1_RNO[0].D1
+         0.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C0
+         1.2  hades_hit_valid_pad[0].PADDO
+
+hades_hit_valid_c[1]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[1].Q0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.D0
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[1].M0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C0
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.C0
+         1.1  hades_hit_valid_pad[1].PADDO
+
+hades_hit_valid_c[2]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[2].Q0
+         0.2  hades_tdc_bundle_inst/hit_valid_1_RNO[2].D0
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[2].A1
+         0.7  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.B0
+         1.2  hades_hit_valid_pad[2].PADDO
+
+hades_hit_valid_c[3]
+   hades_tdc_bundle_inst/hit_valid_1_RNO[3].Q0
+         0.2  hades_tdc_bundle_inst/hit_valid_1_RNO[3].D0
+         0.4  hades_tdc_bundle_inst/hit_valid_1_RNO[3].C1
+         0.9  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A0
+         0.9  hades_hit_valid_pad[3].PADDO
+
+hades_invalid_dl_c[0]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].INFF
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M0
+         0.6  hades_invalid_dl_pad[0].PADDO
+
+hades_invalid_dl_c[1]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M1
+         1.2  hades_invalid_dl_pad[1].PADDO
+
+hades_invalid_dl_c[2]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q1
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C0
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].M0
+         1.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.D0
+         0.9  hades_invalid_dl_pad[2].PADDO
+
+hades_invalid_dl_c[3]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].Q0
+         1.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D0
+         1.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.B0
+         1.2  hades_invalid_dl_pad[3].PADDO
+
+hades_lvl1_c
+   hades_lvl1_pad.PADDI
+         0.9  hades_lvl1_pad_RNINMH5.D0
+         0.0  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].DI
+
+hades_lvl1_c_i
+   hades_lvl1_pad_RNINMH5.F0
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+hades_lvl1_invalid_c
+   hades_lvl1_invalid_pad.PADDI
+         0.1  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].DI
+
+hades_offset_c[0]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].IOLDO
+         0.0  hades_offset_pad[0].IOLDO
+
+hades_offset_c[1]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].IOLDO
+         0.0  hades_offset_pad[1].IOLDO
+
+hades_offset_c[2]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].IOLDO
+         0.0  hades_offset_pad[2].IOLDO
+
+hades_offset_c[3]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].IOLDO
+         0.0  hades_offset_pad[3].IOLDO
+
+hades_offset_c[4]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].IOLDO
+         0.0  hades_offset_pad[4].IOLDO
+
+hades_offset_c[5]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].IOLDO
+         0.0  hades_offset_pad[5].IOLDO
+
+hades_offset_c[6]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].IOLDO
+         0.0  hades_offset_pad[6].IOLDO
+
+hades_offset_c[7]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].IOLDO
+         0.0  hades_offset_pad[7].IOLDO
+
+hades_offset_c[8]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].IOLDO
+         0.0  hades_offset_pad[8].IOLDO
+
+hades_offset_valid_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.Q0
+         2.7  hades_offset_valid_pad.PADDO
+         2.5  hades_tdc_bundle_inst_referenced_out_validio.TXDATA0
+
+hades_raw_out_valid_c
+   hades_tdc_bundle_inst_referenced_out_validio.IOLDO
+         0.0  hades_raw_out_valid_pad.IOLDO
+
+hades_tdc_bundle_inst.buf_out12
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F0
+         0.8  hades_tdc_bundle_inst_buf_out_validio.TXDATA0
+
+hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa
+   hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F1
+         1.0  hades_tdc_bundle_inst_buf_drop_1io[1].TXDATA0
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.OFX0
+         0.6  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CE
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.D0
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CE
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CE
+         1.5  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CE
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CE
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CE
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q0
+         1.0  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].TXDATA0
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q1
+         1.1  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].TXDATA0
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].Q0
+         1.1  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].TXDATA0
+
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0]
+   hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].INFF
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].M0
+
+hades_tdc_bundle_inst.hades_raw_out[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q0
+         1.0  hades_tdc_bundle_inst_hitbuffer_1_io[0].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[12]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q1
+         0.5  hades_tdc_bundle_inst_hitbuffer_1_io[12].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[13]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q0
+         0.9  hades_tdc_bundle_inst_hitbuffer_1_io[13].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[14]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q1
+         0.9  hades_tdc_bundle_inst_hitbuffer_1_io[14].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[15]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q0
+         1.2  hades_tdc_bundle_inst_hitbuffer_1_io[15].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[16]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q1
+         1.1  hades_tdc_bundle_inst_hitbuffer_1_io[16].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[17]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q0
+         1.0  hades_tdc_bundle_inst_hitbuffer_1_io[17].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[18]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q1
+         1.1  hades_tdc_bundle_inst_hitbuffer_1_io[18].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[19]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q0
+         1.3  hades_tdc_bundle_inst_hitbuffer_1_io[19].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q1
+         0.8  hades_tdc_bundle_inst_hitbuffer_1_io[1].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[20]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q1
+         1.3  hades_tdc_bundle_inst_hitbuffer_1_io[20].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[21]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q0
+         1.3  hades_tdc_bundle_inst_hitbuffer_1_io[21].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[22]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q1
+         0.7  hades_tdc_bundle_inst_hitbuffer_1_io[22].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[23]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].Q0
+         0.8  hades_tdc_bundle_inst_hitbuffer_1_io[23].TXDATA0
+
+hades_tdc_bundle_inst.hades_raw_out[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q0
+         0.5  hades_tdc_bundle_inst_hitbuffer_1_io[2].TXDATA0
+
+hades_tdc_bundle_inst/N_243_i
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.OFX0
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1
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+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0
+
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+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_cry
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_14
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_19
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F1
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.F0
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.C0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_cry
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14
+   hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F0
+         0.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C1
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F0
+         0.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D0
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[0]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[2]
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i
+   hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.F0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.B0
+
+hades_tdc_bundle_inst/hit_i[0]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q0
+         0.9  hades_tdc_bundle_inst/hit_valid_1_RNO[0].A0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[2].B1
+         0.7  hades_tdc_bundle_inst/hit_valid_1_RNO[3].A1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A0
+         0.3  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.D1
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B0
+         0.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B1
+
+hades_tdc_bundle_inst/hit_i[1]
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q1
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[0].M0
+         0.8  hades_tdc_bundle_inst/hit_valid_1_RNO[2].M0
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[3].M0
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A1
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C0
+         0.4  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C1
+
+hades_tdc_bundle_inst/hit_out_i_6[2]
+   hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].OFX0
+         0.0  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].DI0
+
+hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0]
+   hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].F0
+         0.4  hades_tdc_bundle_inst/hit_out_i_RNO[0].M0
+
+hades_tdc_bundle_inst/hit_valid25
+   hades_tdc_bundle_inst/hit_valid25_0_I_27_0.F0
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.B0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[1].C0
+         1.0  hades_tdc_bundle_inst/hit_valid_1_RNO[1].C1
+         0.6  hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C1
+
+hades_tdc_bundle_inst/hit_valid25_0_I_27_cry
+   hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_27_0.FCI
+
+hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0]
+   hades_tdc_bundle_inst/hit_valid25_0_I_1_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCI
+
+hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2]
+   hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCO
+         0.0  hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCI
+
+hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0
+   hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F0
+         0.1  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D0
+
+hades_trig_c
+   hades_trig_pad.PADDI
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1
+         1.1  hades_trig_pad_RNIE1B4.A0
+
+hades_trig_c_i
+   hades_trig_pad_RNIE1B4.F0
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.5  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.8  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+hades_window_end_c
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.Q0
+         1.2  hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].C0
+         2.5  hades_window_end_pad.PADDO
+
+last_buf_empty_c
+   fifo_colector_inst/fifo40_inst/FF_1.Q0
+         2.6  trb_adapter_inst/burst.C0
+         1.0  fifo_colector_inst/fifo40_inst/AND2_t19.D0
+         2.7  last_buf_empty_pad.PADDO
+
+pll0inst/GND
+   pll0inst/GND.F0
+         0.5  pll0inst/PLLInst_0.STDBY
+
+pll_clks[0]
+   pll0inst/PLLInst_0.CLKOP
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK
+         1.7  pll0inst/PLLInst_0.CLKFB
+
+pll_clks[1]
+   pll0inst/PLLInst_0.CLKOS
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK
+
+pll_clks[2]
+   pll0inst/PLLInst_0.CLKOS2
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK
+
+pll_clks[3]
+   pll0inst/PLLInst_0.CLKOS3
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_100.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_98.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_96.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_94.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_92.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_0.CLK
+         1.7  hades_tdc_bundle_inst/hit_out_i_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.CLK
+         1.7  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].CLK
+         1.7  fifo_colector_inst/in_empty_pmux_0_RNIDRET.CLK
+         1.7  fifo_colector_inst/data_buffer_3[0].CLK
+         1.7  fifo_colector_inst/data_buffer_3[1].CLK
+         1.7  fifo_colector_inst/data_buffer_3[2].CLK
+         1.7  fifo_colector_inst/data_buffer_3[3].CLK
+         1.7  fifo_colector_inst/data_buffer_3[4].CLK
+         1.7  fifo_colector_inst/data_buffer_3[5].CLK
+         1.7  fifo_colector_inst/data_buffer_3[6].CLK
+         1.7  fifo_colector_inst/data_buffer_3[7].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[9].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[11].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[13].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[15].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[17].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[19].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[21].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[23].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[25].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[27].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[29].CLK
+         1.7  fifo_colector_inst/data_buffer_3_0[31].CLK
+         1.7  fifo_colector_inst/data_buffer[33].CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_30.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_28.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_26.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_24.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_22.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_8.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_6.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_4.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_2.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t12.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t10.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t9.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_80.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_78.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_76.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_74.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_72.CLK
+         1.7  fifo_colector_inst/un5_in_read_enable.CLK
+         1.7  fifo_colector_inst/in_read_enable_1_.fb.CLK
+         1.7  fifo_colector_inst/in_read_enable_2_.fb.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/buf_finished5_0_a2_0.CLK
+         1.7  hades_tdc_bundle_inst/buf_release.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.CLK
+         1.7  hades_tdc_bundle_inst/coarse_RNI6RPP[2].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[4].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[6].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[8].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[10].CLK
+         1.7  hades_tdc_bundle_inst/hitbuffer_1_[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[1].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[3].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[5].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[7].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_1[8].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[1].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[2].CLK
+         1.7  hades_tdc_bundle_inst/hit_valid_1_RNO[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.CLK
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.CLK
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.CLK
+         1.7  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[23].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[22].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[21].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[20].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[19].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[18].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[17].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[16].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[15].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[14].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[13].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[12].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[2].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[1].CLK
+         1.7  hades_tdc_bundle_inst_hitbuffer_1_io[0].CLK
+         1.7  hades_tdc_bundle_inst_buf_drop_1io[1].CLK
+         1.7  hades_tdc_bundle_inst_buf_out_validio.CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].CLK
+         1.7  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].CLK
+         1.7  hades_tdc_bundle_inst_referenced_out_validio.CLK
+         1.7  reset_dl_0io[1].CLK
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA
+         1.7  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB
+         1.7  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKA
+
+rd_clk_c
+   rd_clk_pad.PADDI
+         1.7  fifo_colector_inst/fifo40_inst/FF_70.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_68.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_66.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_64.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_62.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_1.CLK
+         1.7  trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t7.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t5.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t3.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t1.CLK
+         1.7  fifo_colector_inst/fifo40_inst/XOR2_t0.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_50.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_48.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_46.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_44.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_42.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_40.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_38.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_36.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_34.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_32.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_20.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_18.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_16.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_14.CLK
+         1.7  fifo_colector_inst/fifo40_inst/FF_12.CLK
+         1.7  trb_adapter_inst/burst.CLK
+         1.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].CLK
+         1.7  trb_adapter_inst/buf_rden_prev.CLK
+         1.7  trb_adapter_inst/finished_prev.CLK
+         1.7  trb_adapter_inst/release_out.CLK
+         1.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.CLK
+         1.8  trb_adapter_inst_FEE_DATA_WRITE_OUTio.CLK
+         1.8  trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].CLK
+         1.8  trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].CLK
+         1.8  fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKB
+
+release_out_c
+   trb_adapter_inst/release_out.F0
+         0.7  release_out_pad.PADDO
+         0.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.TXDATA0
+
+reset_dc_c
+   reset_dc_pad.PADDI
+         0.0  reset_dl_0io[1].DI
+
+reset_dl[1]
+   reset_dl_0io[1].INFF
+         1.1  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.M0
+
+reset_dl[2]
+   hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.Q0
+         0.8  hades_tdc_bundle_inst/hit_out_i_RNO[0].LSR
+         0.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.LSR
+         1.4  hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].LSR
+         2.1  genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         2.4  genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         3.4  genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR
+         0.5  hades_tdc_bundle_inst/buf_finished5_0_a2_0.LSR
+         0.9  hades_tdc_bundle_inst/buf_release.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.LSR
+         2.0  hades_tdc_bundle_inst/coarse_RNI6RPP[2].LSR
+         2.1  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.LSR
+         2.0  hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.LSR
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.LSR
+         0.4  hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CE
+         0.6  hades_tdc_bundle_inst/hit_valid_1_RNO[0].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[1].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[2].CE
+         0.5  hades_tdc_bundle_inst/hit_valid_1_RNO[3].CE
+         1.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.LSR
+         1.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].LSR
+         2.3  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].LSR
+         1.4  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].LSR
+         2.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].LSR
+         2.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A0
+         2.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A1
+         1.8  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.M0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C1
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C0
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C1
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].LSR
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].LSR
+         1.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].LSR
+         1.7  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].LSR
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].LSR
+         1.2  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.LSR
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CE
+         0.9  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CE
+         0.9  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.LSR
+         1.6  hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.M0
+         1.2  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.A0
+         3.2  genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.8  genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.2  genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR
+         2.0  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.A0
+         1.6  hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.C0
+         2.1  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.B0
+         2.5  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.A0
+         1.7  hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].C0
+         0.2  hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.D0
+         1.4  hades_tdc_bundle_inst_buf_drop_1io[1].LSR
+         1.8  trb_adapter_inst_FEE_TRG_RELEASE_OUTio.LSR
+         1.8  trb_adapter_inst_FEE_DATAFINISHED_OUTio.LSR
+         1.9  trb_adapter_inst_FEE_DATA_WRITE_OUTio.LSR
+
+trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0]
+   trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].INFF
+         0.6  trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].M0
+
+trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]
+   trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].INFF
+         3.7  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q0
+         0.5  trb_adapter_inst/burst.B1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M1
+         0.5  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B0
+
+trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
+   trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q1
+         0.5  trb_adapter_inst/burst.A1
+         0.3  trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D0
+
+trb_adapter_inst/buf_rden4
+   trb_adapter_inst/burst.F0
+         0.0  trb_adapter_inst/burst.DI0
+
+trb_adapter_inst/buf_rden_prev
+   trb_adapter_inst/buf_rden_prev.Q0
+         0.3  trb_adapter_inst/release_out.M0
+
+trb_adapter_inst/finished_prev
+   trb_adapter_inst/finished_prev.Q0
+         0.5  trb_adapter_inst/release_out.B0
+
+trig_c[0]
+   trig_pad[0].PADDI
+         0.4  trig_pad_RNII4FF[0].D0
+
+trig_c[1]
+   trig_pad[1].PADDI
+         1.5  trig_pad_RNIJ5FF[1].D0
+
+trig_c[2]
+   trig_pad[2].PADDI
+         1.7  trig_pad_RNIK6FF[2].D0
+
+trig_c_i[0]
+   trig_pad_RNII4FF[0].F0
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.4  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.5  genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[1]
+   trig_pad_RNIJ5FF[1].F0
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.7  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.4  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+trig_c_i[2]
+   trig_pad_RNIK6FF[2].F0
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1
+         0.4  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1
+         0.8  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1
+         0.5  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1
+         0.6  genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1
+
+un1_hit_i_2_0_a2
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F0
+         0.4  hades_tdc_bundle_inst/hitbuffer_1_[4].CE
+         0.4  hades_tdc_bundle_inst/hitbuffer_1_[6].CE
+         0.6  hades_tdc_bundle_inst/hitbuffer_1_[8].CE
+         1.3  hades_tdc_bundle_inst/hitbuffer_1_[10].CE
+         1.0  hades_tdc_bundle_inst/hitbuffer_1_[11].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[23].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[22].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[21].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[20].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[19].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[18].CE
+         1.4  hades_tdc_bundle_inst_hitbuffer_1_io[17].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[16].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[15].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[14].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[13].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[12].CE
+         1.5  hades_tdc_bundle_inst_hitbuffer_1_io[2].CE
+         1.6  hades_tdc_bundle_inst_hitbuffer_1_io[1].CE
+         1.8  hades_tdc_bundle_inst_hitbuffer_1_io[0].CE
+
+valid_fast_RNI999V
+   hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.F0
+         1.3  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].LSR
+         1.4  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].LSR
+         1.2  hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].LSR
diff --git a/impl1/s1_impl1.drc b/impl1/s1_impl1.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/impl1/s1_impl1.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/impl1/s1_impl1.edi b/impl1/s1_impl1.edi
new file mode 100644
index 0000000..eff80c7
--- /dev/null
+++ b/impl1/s1_impl1.edi
@@ -0,0 +1,20420 @@
+(edif top_tf
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timeStamp 2021 6 16 9 19 25)
+      (author "Synopsys, Inc.")
+      (program "Synplify Premier" (version "O-2018.09-SP1, mapper maprc, Build 4745R"))
+     )
+   )
+  (library LUCENT
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell PDPW16KD (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port DI0 (direction INPUT))
+           (port DI1 (direction INPUT))
+           (port DI2 (direction INPUT))
+           (port DI3 (direction INPUT))
+           (port DI4 (direction INPUT))
+           (port DI5 (direction INPUT))
+           (port DI6 (direction INPUT))
+           (port DI7 (direction INPUT))
+           (port DI8 (direction INPUT))
+           (port DI9 (direction INPUT))
+           (port DI10 (direction INPUT))
+           (port DI11 (direction INPUT))
+           (port DI12 (direction INPUT))
+           (port DI13 (direction INPUT))
+           (port DI14 (direction INPUT))
+           (port DI15 (direction INPUT))
+           (port DI16 (direction INPUT))
+           (port DI17 (direction INPUT))
+           (port DI18 (direction INPUT))
+           (port DI19 (direction INPUT))
+           (port DI20 (direction INPUT))
+           (port DI21 (direction INPUT))
+           (port DI22 (direction INPUT))
+           (port DI23 (direction INPUT))
+           (port DI24 (direction INPUT))
+           (port DI25 (direction INPUT))
+           (port DI26 (direction INPUT))
+           (port DI27 (direction INPUT))
+           (port DI28 (direction INPUT))
+           (port DI29 (direction INPUT))
+           (port DI30 (direction INPUT))
+           (port DI31 (direction INPUT))
+           (port DI32 (direction INPUT))
+           (port DI33 (direction INPUT))
+           (port DI34 (direction INPUT))
+           (port DI35 (direction INPUT))
+           (port ADW0 (direction INPUT))
+           (port ADW1 (direction INPUT))
+           (port ADW2 (direction INPUT))
+           (port ADW3 (direction INPUT))
+           (port ADW4 (direction INPUT))
+           (port ADW5 (direction INPUT))
+           (port ADW6 (direction INPUT))
+           (port ADW7 (direction INPUT))
+           (port ADW8 (direction INPUT))
+           (port BE0 (direction INPUT))
+           (port BE1 (direction INPUT))
+           (port BE2 (direction INPUT))
+           (port BE3 (direction INPUT))
+           (port CEW (direction INPUT))
+           (port CLKW (direction INPUT))
+           (port CSW0 (direction INPUT))
+           (port CSW1 (direction INPUT))
+           (port CSW2 (direction INPUT))
+           (port ADR0 (direction INPUT))
+           (port ADR1 (direction INPUT))
+           (port ADR2 (direction INPUT))
+           (port ADR3 (direction INPUT))
+           (port ADR4 (direction INPUT))
+           (port ADR5 (direction INPUT))
+           (port ADR6 (direction INPUT))
+           (port ADR7 (direction INPUT))
+           (port ADR8 (direction INPUT))
+           (port ADR9 (direction INPUT))
+           (port ADR10 (direction INPUT))
+           (port ADR11 (direction INPUT))
+           (port ADR12 (direction INPUT))
+           (port ADR13 (direction INPUT))
+           (port CER (direction INPUT))
+           (port CLKR (direction INPUT))
+           (port CSR0 (direction INPUT))
+           (port CSR1 (direction INPUT))
+           (port CSR2 (direction INPUT))
+           (port RST (direction INPUT))
+           (port OCER (direction INPUT))
+           (port DO0 (direction OUTPUT))
+           (port DO1 (direction OUTPUT))
+           (port DO2 (direction OUTPUT))
+           (port DO3 (direction OUTPUT))
+           (port DO4 (direction OUTPUT))
+           (port DO5 (direction OUTPUT))
+           (port DO6 (direction OUTPUT))
+           (port DO7 (direction OUTPUT))
+           (port DO8 (direction OUTPUT))
+           (port DO9 (direction OUTPUT))
+           (port DO10 (direction OUTPUT))
+           (port DO11 (direction OUTPUT))
+           (port DO12 (direction OUTPUT))
+           (port DO13 (direction OUTPUT))
+           (port DO14 (direction OUTPUT))
+           (port DO15 (direction OUTPUT))
+           (port DO16 (direction OUTPUT))
+           (port DO17 (direction OUTPUT))
+           (port DO18 (direction OUTPUT))
+           (port DO19 (direction OUTPUT))
+           (port DO20 (direction OUTPUT))
+           (port DO21 (direction OUTPUT))
+           (port DO22 (direction OUTPUT))
+           (port DO23 (direction OUTPUT))
+           (port DO24 (direction OUTPUT))
+           (port DO25 (direction OUTPUT))
+           (port DO26 (direction OUTPUT))
+           (port DO27 (direction OUTPUT))
+           (port DO28 (direction OUTPUT))
+           (port DO29 (direction OUTPUT))
+           (port DO30 (direction OUTPUT))
+           (port DO31 (direction OUTPUT))
+           (port DO32 (direction OUTPUT))
+           (port DO33 (direction OUTPUT))
+           (port DO34 (direction OUTPUT))
+           (port DO35 (direction OUTPUT))
+         )
+        (property INITVAL_3F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_3E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_3D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_3C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_3B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_3A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_39 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_38 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_37 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_36 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_35 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_34 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_33 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_32 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_31 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_30 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_2A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_29 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_28 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_27 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_26 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_25 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_24 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_23 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_22 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_21 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_20 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_1A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_19 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_18 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_17 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_16 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_15 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_14 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_13 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_12 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_11 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_10 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_0A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_09 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_08 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_07 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_06 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_05 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_04 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_03 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_02 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_01 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property INITVAL_00 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
+        (property GSR (string "DISABLED"))
+        (property REGMODE (string "NOREG"))
+        (property DATA_WIDTH_R (integer 36))
+        (property DATA_WIDTH_W (integer 36))
+       )
+    )
+    (cell ROM16X1A (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port AD0 (direction INPUT))
+           (port AD1 (direction INPUT))
+           (port AD2 (direction INPUT))
+           (port AD3 (direction INPUT))
+           (port DO0 (direction OUTPUT))
+         )
+       )
+    )
+    (cell CCU2C (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A0 (direction INPUT))
+           (port B0 (direction INPUT))
+           (port C0 (direction INPUT))
+           (port D0 (direction INPUT))
+           (port A1 (direction INPUT))
+           (port B1 (direction INPUT))
+           (port C1 (direction INPUT))
+           (port D1 (direction INPUT))
+           (port CIN (direction INPUT))
+           (port COUT (direction OUTPUT))
+           (port S0 (direction OUTPUT))
+           (port S1 (direction OUTPUT))
+         )
+        (property INJECT1_1 (string "NO"))
+        (property INJECT1_0 (string "NO"))
+        (property INIT1 (string "0000"))
+        (property INIT0 (string "0000"))
+       )
+    )
+    (cell OBZ (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port T (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell OB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell IB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3JX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port PD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3DX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3BX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port PD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell OFS1P3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port SCLK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3DX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell OFS1P3DX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port SCLK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell IFS1P3DX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port SCLK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3BX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port PD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell XOR2 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell OR2 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell AND2 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell ORCALUT4 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port C (direction INPUT))
+           (port D (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell GSR (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port GSR (direction INPUT))
+         )
+       )
+    )
+    (cell INV (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VHI (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VLO (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+  )
+  (library work
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell output_decoder8_0_1 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port reset_dl_0 (direction INPUT))
+           (port (array (rename tdc_out_neg "tdc_out_neg[7:0]") 8) (direction INPUT))
+           (port (array (rename decoder_out_neg "decoder_out_neg[2:0]") 3) (direction OUTPUT))
+           (port N_11_i (direction OUTPUT))
+           (port buf_positive_ready (direction INPUT))
+           (port decoder_valid_neg (direction OUTPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+A)))"))
+          )
+          (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D+(!C+(!B+A)))"))
+          )
+          (instance valid_RNI97O31 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance (rename in_synced_RNIT1GT_7 "in_synced_RNIT1GT[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance un1_out_internal35_1_0_o5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_0 "out_internal_2_1_0_.m11_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (!C+(B !A)))"))
+          )
+          (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_m3 "out_internal_2_1_0_.m11_i_m3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (!B+A))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i_1 "out_internal_2_1_0_.m15_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C !A))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+A))"))
+          )
+          (instance un1_out_internal31_1_i_0_o5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (!B+!A))+D (!C+(!B+!A)))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net un1_out_internal35_1_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef out_internal_2))
+           (portRef CK (instanceRef out_2))
+           (portRef CK (instanceRef out_internal_1))
+           (portRef CK (instanceRef out_1))
+           (portRef CK (instanceRef out_internal_0))
+           (portRef CK (instanceRef out_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef in_synced_RNIT1GT_7))
+           (portRef PD (instanceRef out_internal_2))
+           (portRef PD (instanceRef out_internal_1))
+           (portRef PD (instanceRef out_internal_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+          ))
+          (net decoder_valid_neg (joined
+           (portRef Q (instanceRef valid))
+           (portRef B (instanceRef valid_RNI97O31))
+           (portRef decoder_valid_neg)
+          ))
+          (net (rename out_internal_0 "out_internal[0]") (joined
+           (portRef Q (instanceRef out_internal_0))
+           (portRef D (instanceRef out_0))
+          ))
+          (net (rename decoder_out_neg_0 "decoder_out_neg[0]") (joined
+           (portRef Q (instanceRef out_0))
+           (portRef (member decoder_out_neg 2))
+          ))
+          (net m11_i_1 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i))
+           (portRef D (instanceRef out_internal_0))
+          ))
+          (net (rename out_internal_1 "out_internal[1]") (joined
+           (portRef Q (instanceRef out_internal_1))
+           (portRef D (instanceRef out_1))
+          ))
+          (net (rename decoder_out_neg_1 "decoder_out_neg[1]") (joined
+           (portRef Q (instanceRef out_1))
+           (portRef (member decoder_out_neg 1))
+          ))
+          (net m15_i_1 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i))
+           (portRef D (instanceRef out_internal_1))
+          ))
+          (net (rename out_internal_2 "out_internal[2]") (joined
+           (portRef Q (instanceRef out_internal_2))
+           (portRef D (instanceRef out_2))
+          ))
+          (net (rename decoder_out_neg_2 "decoder_out_neg[2]") (joined
+           (portRef Q (instanceRef out_2))
+           (portRef (member decoder_out_neg 0))
+          ))
+          (net N_5 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0))
+           (portRef D (instanceRef out_internal_2))
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef D (instanceRef un1_out_internal31_1_i_0_o5))
+           (portRef A (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_0))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef C (instanceRef un1_out_internal31_1_i_0_o5))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i_1))
+           (portRef B (instanceRef un1_out_internal35_1_0_m3))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_0))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef B (instanceRef un1_out_internal31_1_i_0_o5))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i_1))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_m3))
+           (portRef C (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef un1_out_internal35_1_0_o5))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i_1))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_m3))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_o5))
+           (portRef B (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef D (instanceRef out_internal_2_1_0__m15_i_1))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_o5))
+           (portRef C (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_m3))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef un1_out_internal35_1_0_o5))
+           (portRef D (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef A (instanceRef un1_out_internal31_1_i_0_o5))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef in_synced_RNIT1GT_7))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef in_synced_RNIT1GT_7))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined
+           (portRef (member tdc_out_neg 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined
+           (portRef (member tdc_out_neg 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined
+           (portRef (member tdc_out_neg 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined
+           (portRef (member tdc_out_neg 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined
+           (portRef (member tdc_out_neg 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined
+           (portRef (member tdc_out_neg 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined
+           (portRef (member tdc_out_neg 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined
+           (portRef (member tdc_out_neg 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net un1_out_internal35_1_0_m3 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net un1_out_internal35_1_0_o5 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_o5))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net m11_i_m3 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_m3))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net un1_out_internal31_1_i_0_o5 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0_o5))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i))
+           (portRef A (instanceRef un1_out_internal31_1_i_0))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net m11_i_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_0))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net buf_positive_ready (joined
+           (portRef buf_positive_ready)
+           (portRef A (instanceRef valid_RNI97O31))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef C (instanceRef valid_RNI97O31))
+          ))
+          (net N_11_i (joined
+           (portRef Z (instanceRef valid_RNI97O31))
+           (portRef N_11_i)
+          ))
+          (net m15_i_1_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i_1))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i))
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell output_decoder8_0_0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port reset_dl_0 (direction INPUT))
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT))
+           (port (array (rename decoder_out "decoder_out[2:0]") 3) (direction OUTPUT))
+           (port N_251_i (direction OUTPUT))
+           (port decoder_valid (direction OUTPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B A)))"))
+          )
+          (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i_3 "out_internal_2_1_0_.m15_i_3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B+!A)))"))
+          )
+          (instance (rename in_synced_RNIB4EQ_7 "in_synced_RNIB4EQ[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance valid_RNI8UMR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance un1_out_internal35_1_0_o7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_1 "out_internal_2_1_0_.m11_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (!C+(B !A)))"))
+          )
+          (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance un1_out_internal31_1_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i_0 "out_internal_2_1_0_.m15_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_1_0 "out_internal_2_1_0_.m11_i_1_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B A+B !A)))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+A)))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net un1_out_internal35_1_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef out_internal_2))
+           (portRef CK (instanceRef out_2))
+           (portRef CK (instanceRef out_internal_1))
+           (portRef CK (instanceRef out_1))
+           (portRef CK (instanceRef out_0))
+           (portRef CK (instanceRef out_internal_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef in_synced_RNIB4EQ_7))
+           (portRef PD (instanceRef out_internal_2))
+           (portRef PD (instanceRef out_internal_1))
+           (portRef PD (instanceRef out_internal_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+          ))
+          (net decoder_valid (joined
+           (portRef Q (instanceRef valid))
+           (portRef A (instanceRef valid_RNI8UMR))
+           (portRef decoder_valid)
+          ))
+          (net m11_i_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i))
+           (portRef D (instanceRef out_internal_0))
+          ))
+          (net (rename out_internal_0 "out_internal[0]") (joined
+           (portRef Q (instanceRef out_internal_0))
+           (portRef D (instanceRef out_0))
+          ))
+          (net (rename decoder_out_0 "decoder_out[0]") (joined
+           (portRef Q (instanceRef out_0))
+           (portRef (member decoder_out 2))
+          ))
+          (net (rename out_internal_1 "out_internal[1]") (joined
+           (portRef Q (instanceRef out_internal_1))
+           (portRef D (instanceRef out_1))
+          ))
+          (net (rename decoder_out_1 "decoder_out[1]") (joined
+           (portRef Q (instanceRef out_1))
+           (portRef (member decoder_out 1))
+          ))
+          (net m15_i_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i))
+           (portRef D (instanceRef out_internal_1))
+          ))
+          (net (rename out_internal_2 "out_internal[2]") (joined
+           (portRef Q (instanceRef out_internal_2))
+           (portRef D (instanceRef out_2))
+          ))
+          (net (rename decoder_out_2 "decoder_out[2]") (joined
+           (portRef Q (instanceRef out_2))
+           (portRef (member decoder_out 0))
+          ))
+          (net un1_out_internal31_1_i_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0))
+           (portRef D (instanceRef out_internal_2))
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef A (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i_3))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef A (instanceRef un1_out_internal35_1_0_o7))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef A (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_o7))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i_3))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_o7))
+           (portRef D (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef B (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef B (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef un1_out_internal35_1_0_o7))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef in_synced_RNIB4EQ_7))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef in_synced_RNIB4EQ_7))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net N_268 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef un1_out_internal31_1_i_0))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net N_269 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_o7))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net m15_i_0_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net m15_i_3 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef D (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net un1_out_internal31_1_i_0_1 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef D (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef B (instanceRef valid_RNI8UMR))
+          ))
+          (net N_251_i (joined
+           (portRef Z (instanceRef valid_RNI8UMR))
+           (portRef N_251_i)
+          ))
+          (net m11_i_1 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net m11_i_1_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i))
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell tdc4ddr_short_1 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out_neg "tdc_out_neg[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port trig_gate_neg (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out_neg 4))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out_neg 0))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net trig_gate_neg (joined
+           (portRef trig_gate_neg)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out_neg 5))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out_neg 1))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out_neg 6))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out_neg 2))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out_neg 7))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out_neg 3))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell tdc4ddr_short_0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port hades_trig_c_i (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out 4))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out 0))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net hades_trig_c_i (joined
+           (portRef hades_trig_c_i)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out 5))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out 1))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out 6))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out 2))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out 7))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out 3))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell trig_inv (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port hades_trig_c_i (direction INPUT))
+           (port trig_gate_neg (direction OUTPUT))
+         )
+         (contents
+          (instance out_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (net in_1 (joined
+           (portRef A (instanceRef out_RNO))
+           (portRef hades_trig_c_i)
+          ))
+          (net (rename out "trig_gate_neg") (joined
+           (portRef trig_gate_neg)
+           (portRef Z (instanceRef out_RNO))
+          ))
+         )
+        (property orig_inst_of (string "trig_inv"))
+       )
+    )
+    (cell output_decoder8_0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT))
+           (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port un1_reset_0_a2_2_0 (direction OUTPUT))
+           (port G_25_0_a3_5_0 (direction INPUT))
+           (port G_25_0_a3_4_0 (direction INPUT))
+           (port decoder_valid (direction OUTPUT))
+           (port CN (direction OUTPUT))
+           (port valid_fast_RNI999V_1z (direction OUTPUT))
+           (port hades_discard_c (direction INPUT))
+           (port valid_fast_1z (direction OUTPUT))
+           (port offset_1_sqmuxa_i_0 (direction INPUT))
+         )
+         (contents
+          (instance valid_fast_RNI999V (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B+A)+C A)+D (B+A))"))
+          )
+          (instance (rename in_synced_7__CN "in_synced_7_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B A)))"))
+          )
+          (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i_3 "out_internal_2_1_0_.m15_i_3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B+!A)))"))
+          )
+          (instance (rename in_synced_RNI3HPF_7 "in_synced_RNI3HPF[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance un1_out_internal35_1_0_o7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A))+D (!B A))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_1 "out_internal_2_1_0_.m11_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (!C+(B !A)))"))
+          )
+          (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance un1_out_internal31_1_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename out_internal_2_1_0__m15_i_0 "out_internal_2_1_0_.m15_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i_1_0 "out_internal_2_1_0_.m11_i_1_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B A+B !A)))"))
+          )
+          (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+A)))"))
+          )
+          (instance valid_fast_RNI5DQ71 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (B A)))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef D (instanceRef valid_fast_RNI5DQ71))
+           (portRef A (instanceRef valid_fast_RNI999V))
+          ))
+          (net offset_1_sqmuxa_i_0 (joined
+           (portRef offset_1_sqmuxa_i_0)
+           (portRef B (instanceRef valid_fast_RNI999V))
+          ))
+          (net (rename valid_fast_1z "valid_fast") (joined
+           (portRef Q (instanceRef valid_fast))
+           (portRef C (instanceRef valid_fast_RNI5DQ71))
+           (portRef C (instanceRef valid_fast_RNI999V))
+           (portRef valid_fast_1z)
+          ))
+          (net hades_discard_c (joined
+           (portRef hades_discard_c)
+           (portRef D (instanceRef valid_fast_RNI999V))
+          ))
+          (net (rename valid_fast_RNI999V_1z "valid_fast_RNI999V") (joined
+           (portRef Z (instanceRef valid_fast_RNI999V))
+           (portRef valid_fast_RNI999V_1z)
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef A (instanceRef in_synced_7__CN))
+          ))
+          (net CN (joined
+           (portRef Z (instanceRef in_synced_7__CN))
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef out_2))
+           (portRef CK (instanceRef out_internal_2))
+           (portRef CK (instanceRef out_internal_1))
+           (portRef CK (instanceRef out_1))
+           (portRef CK (instanceRef out_internal_0))
+           (portRef CK (instanceRef out_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_fast))
+           (portRef CK (instanceRef valid_internal))
+           (portRef CN)
+          ))
+          (net un1_out_internal35_1_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef in_synced_RNI3HPF_7))
+           (portRef PD (instanceRef out_internal_2))
+           (portRef PD (instanceRef out_internal_1))
+           (portRef PD (instanceRef out_internal_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+           (portRef D (instanceRef valid_fast))
+          ))
+          (net decoder_valid (joined
+           (portRef Q (instanceRef valid))
+           (portRef decoder_valid)
+          ))
+          (net (rename out_internal_0 "out_internal[0]") (joined
+           (portRef Q (instanceRef out_internal_0))
+           (portRef D (instanceRef out_0))
+          ))
+          (net (rename offset_5_0 "offset_5[0]") (joined
+           (portRef Q (instanceRef out_0))
+           (portRef (member offset_5 2))
+          ))
+          (net m11_i (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i))
+           (portRef D (instanceRef out_internal_0))
+          ))
+          (net (rename out_internal_1 "out_internal[1]") (joined
+           (portRef Q (instanceRef out_internal_1))
+           (portRef D (instanceRef out_1))
+          ))
+          (net (rename offset_5_1 "offset_5[1]") (joined
+           (portRef Q (instanceRef out_1))
+           (portRef (member offset_5 1))
+          ))
+          (net m15_i (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i))
+           (portRef D (instanceRef out_internal_1))
+          ))
+          (net un1_out_internal31_1_i_0 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0))
+           (portRef D (instanceRef out_internal_2))
+          ))
+          (net (rename out_internal_2 "out_internal[2]") (joined
+           (portRef Q (instanceRef out_internal_2))
+           (portRef D (instanceRef out_2))
+          ))
+          (net (rename offset_5_2 "offset_5[2]") (joined
+           (portRef Q (instanceRef out_2))
+           (portRef (member offset_5 0))
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef A (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i_3))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef A (instanceRef un1_out_internal35_1_0_o7))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef A (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_o7))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i_3))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef un1_out_internal35_1_0_o7))
+           (portRef D (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef B (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef A (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef B (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef un1_out_internal35_1_0_o7))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef B (instanceRef out_internal_2_1_0__m11_i))
+           (portRef B (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef in_synced_RNI3HPF_7))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef in_synced_RNI3HPF_7))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net N_290 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m3))
+           (portRef A (instanceRef un1_out_internal31_1_i_0))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net N_291 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_o7))
+           (portRef A (instanceRef out_internal_2_1_0__m11_i))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net m15_i_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i_0))
+           (portRef C (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net m15_i_3 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m15_i_3))
+           (portRef D (instanceRef out_internal_2_1_0__m15_i))
+          ))
+          (net un1_out_internal31_1_i_0_1 (joined
+           (portRef Z (instanceRef un1_out_internal31_1_i_0_1))
+           (portRef D (instanceRef un1_out_internal31_1_i_0))
+          ))
+          (net m11_i_1 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_1))
+           (portRef C (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net m11_i_1_0 (joined
+           (portRef Z (instanceRef out_internal_2_1_0__m11_i_1_0))
+           (portRef D (instanceRef out_internal_2_1_0__m11_i))
+          ))
+          (net G_25_0_a3_4_0 (joined
+           (portRef G_25_0_a3_4_0)
+           (portRef A (instanceRef valid_fast_RNI5DQ71))
+          ))
+          (net G_25_0_a3_5_0 (joined
+           (portRef G_25_0_a3_5_0)
+           (portRef B (instanceRef valid_fast_RNI5DQ71))
+          ))
+          (net un1_reset_0_a2_2_0 (joined
+           (portRef Z (instanceRef valid_fast_RNI5DQ71))
+           (portRef un1_reset_0_a2_2_0)
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell tdc4ddr_short (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port hades_lvl1_c_i (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction OUTPUT))
+           (port CN_0 (direction OUTPUT))
+           (port CN (direction OUTPUT))
+         )
+         (contents
+          (instance (rename genblk1_2__out_buffered1_6__CN "genblk1[2].out_buffered1_6_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename genblk1_1__out_buffered1_5__CN "genblk1[1].out_buffered1_5_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename genblk1_0__out_buffered1_4__CN "genblk1[0].out_buffered1_4_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+           (portRef A (instanceRef genblk1_2__out_buffered1_6__CN))
+          ))
+          (net CN (joined
+           (portRef Z (instanceRef genblk1_2__out_buffered1_6__CN))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+           (portRef CN)
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+           (portRef A (instanceRef genblk1_1__out_buffered1_5__CN))
+          ))
+          (net CN_0 (joined
+           (portRef Z (instanceRef genblk1_1__out_buffered1_5__CN))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+           (portRef CN_0)
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+           (portRef A (instanceRef genblk1_0__out_buffered1_4__CN))
+          ))
+          (net CN_1 (joined
+           (portRef Z (instanceRef genblk1_0__out_buffered1_4__CN))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+           (portRef CN_1)
+          ))
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out 4))
+          ))
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out 0))
+          ))
+          (net hades_lvl1_c_i (joined
+           (portRef hades_lvl1_c_i)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out 5))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out 1))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out 6))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out 2))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out 7))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out 3))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell fifo32dc_1 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port fifo_in_data_0 (direction INPUT))
+           (port fifo_empty_0 (direction OUTPUT))
+           (port fifo_read_0 (direction INPUT))
+           (port fifo_wren (direction INPUT))
+         )
+         (contents
+          (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0410"))
+          )
+          (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x1004"))
+          )
+          (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0140"))
+          )
+          (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x4001"))
+          )
+          (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT)))
+           (property MEM_LPC_FILE (string "fifo32dc.lpc"))
+           (property MEM_INIT_FILE (string ""))
+           (property DATA_WIDTH_W (integer 36))
+           (property DATA_WIDTH_R (integer 36))
+           (property REGMODE (string "NOREG"))
+           (property RESETMODE (string "SYNC"))
+           (property GSR (string "ENABLED"))
+           (property CSDECODE_W (string "0b001"))
+           (property CSDECODE_R (string "0b000"))
+           (property ASYNC_RESET_RELEASE (string "SYNC"))
+           (property INIT_DATA (string "STATIC"))
+          )
+          (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net fifo_wren (joined
+           (portRef fifo_wren)
+           (portRef A (instanceRef AND2_t20))
+          ))
+          (net invout_1 (joined
+           (portRef Z (instanceRef INV_1))
+           (portRef B (instanceRef AND2_t20))
+          ))
+          (net wren_i (joined
+           (portRef Z (instanceRef AND2_t20))
+           (portRef B1 (instanceRef full_cmp_ci_a))
+           (portRef A1 (instanceRef full_cmp_ci_a))
+           (portRef SP (instanceRef FF_72))
+           (portRef SP (instanceRef FF_73))
+           (portRef SP (instanceRef FF_74))
+           (portRef SP (instanceRef FF_75))
+           (portRef SP (instanceRef FF_76))
+           (portRef SP (instanceRef FF_77))
+           (portRef SP (instanceRef FF_78))
+           (portRef SP (instanceRef FF_79))
+           (portRef SP (instanceRef FF_80))
+           (portRef SP (instanceRef FF_81))
+           (portRef SP (instanceRef FF_82))
+           (portRef SP (instanceRef FF_83))
+           (portRef SP (instanceRef FF_84))
+           (portRef SP (instanceRef FF_85))
+           (portRef SP (instanceRef FF_86))
+           (portRef SP (instanceRef FF_87))
+           (portRef SP (instanceRef FF_88))
+           (portRef SP (instanceRef FF_89))
+           (portRef SP (instanceRef FF_90))
+           (portRef SP (instanceRef FF_91))
+           (portRef SP (instanceRef FF_92))
+           (portRef SP (instanceRef FF_93))
+           (portRef SP (instanceRef FF_94))
+           (portRef SP (instanceRef FF_95))
+           (portRef SP (instanceRef FF_96))
+           (portRef SP (instanceRef FF_97))
+           (portRef SP (instanceRef FF_98))
+           (portRef SP (instanceRef FF_99))
+           (portRef SP (instanceRef FF_100))
+           (portRef SP (instanceRef FF_101))
+           (portRef CEW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net Full (joined
+           (portRef Q (instanceRef FF_0))
+           (portRef A (instanceRef INV_1))
+          ))
+          (net (rename fifo_read_0 "fifo_read[2]") (joined
+           (portRef fifo_read_0)
+           (portRef A (instanceRef AND2_t19))
+          ))
+          (net invout_0 (joined
+           (portRef Z (instanceRef INV_0))
+           (portRef B (instanceRef AND2_t19))
+          ))
+          (net rden_i (joined
+           (portRef Z (instanceRef AND2_t19))
+           (portRef B1 (instanceRef empty_cmp_ci_a))
+           (portRef A1 (instanceRef empty_cmp_ci_a))
+           (portRef SP (instanceRef FF_42))
+           (portRef SP (instanceRef FF_43))
+           (portRef SP (instanceRef FF_44))
+           (portRef SP (instanceRef FF_45))
+           (portRef SP (instanceRef FF_46))
+           (portRef SP (instanceRef FF_47))
+           (portRef SP (instanceRef FF_48))
+           (portRef SP (instanceRef FF_49))
+           (portRef SP (instanceRef FF_50))
+           (portRef SP (instanceRef FF_51))
+           (portRef SP (instanceRef FF_52))
+           (portRef SP (instanceRef FF_53))
+           (portRef SP (instanceRef FF_54))
+           (portRef SP (instanceRef FF_55))
+           (portRef SP (instanceRef FF_56))
+           (portRef SP (instanceRef FF_57))
+           (portRef SP (instanceRef FF_58))
+           (portRef SP (instanceRef FF_59))
+           (portRef SP (instanceRef FF_60))
+           (portRef SP (instanceRef FF_61))
+           (portRef SP (instanceRef FF_62))
+           (portRef SP (instanceRef FF_63))
+           (portRef SP (instanceRef FF_64))
+           (portRef SP (instanceRef FF_65))
+           (portRef SP (instanceRef FF_66))
+           (portRef SP (instanceRef FF_67))
+           (portRef SP (instanceRef FF_68))
+           (portRef SP (instanceRef FF_69))
+           (portRef SP (instanceRef FF_70))
+           (portRef SP (instanceRef FF_71))
+           (portRef OCER (instanceRef pdp_ram_0_0_0))
+           (portRef CER (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename fifo_empty_0 "fifo_empty[2]") (joined
+           (portRef Q (instanceRef FF_1))
+           (portRef A (instanceRef INV_0))
+           (portRef fifo_empty_0)
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef B1 (instanceRef a1))
+           (portRef A1 (instanceRef a1))
+           (portRef B0 (instanceRef a1))
+           (portRef A0 (instanceRef a1))
+           (portRef B0 (instanceRef full_cmp_ci_a))
+           (portRef A0 (instanceRef full_cmp_ci_a))
+           (portRef B1 (instanceRef a0))
+           (portRef A1 (instanceRef a0))
+           (portRef B0 (instanceRef a0))
+           (portRef A0 (instanceRef a0))
+           (portRef B0 (instanceRef empty_cmp_ci_a))
+           (portRef A0 (instanceRef empty_cmp_ci_a))
+           (portRef B1 (instanceRef r_gctr_4))
+           (portRef B0 (instanceRef r_gctr_4))
+           (portRef B1 (instanceRef r_gctr_3))
+           (portRef B0 (instanceRef r_gctr_3))
+           (portRef B1 (instanceRef r_gctr_2))
+           (portRef B0 (instanceRef r_gctr_2))
+           (portRef B1 (instanceRef r_gctr_1))
+           (portRef B0 (instanceRef r_gctr_1))
+           (portRef B1 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_cia))
+           (portRef A0 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_4))
+           (portRef B0 (instanceRef w_gctr_4))
+           (portRef B1 (instanceRef w_gctr_3))
+           (portRef B0 (instanceRef w_gctr_3))
+           (portRef B1 (instanceRef w_gctr_2))
+           (portRef B0 (instanceRef w_gctr_2))
+           (portRef B1 (instanceRef w_gctr_1))
+           (portRef B0 (instanceRef w_gctr_1))
+           (portRef B1 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_cia))
+           (portRef A0 (instanceRef w_gctr_cia))
+           (portRef CD (instanceRef FF_0))
+           (portRef CD (instanceRef FF_12))
+           (portRef CD (instanceRef FF_13))
+           (portRef CD (instanceRef FF_14))
+           (portRef CD (instanceRef FF_15))
+           (portRef CD (instanceRef FF_16))
+           (portRef CD (instanceRef FF_17))
+           (portRef CD (instanceRef FF_18))
+           (portRef CD (instanceRef FF_19))
+           (portRef CD (instanceRef FF_20))
+           (portRef CD (instanceRef FF_21))
+           (portRef CD (instanceRef FF_32))
+           (portRef CD (instanceRef FF_33))
+           (portRef CD (instanceRef FF_34))
+           (portRef CD (instanceRef FF_35))
+           (portRef CD (instanceRef FF_36))
+           (portRef CD (instanceRef FF_37))
+           (portRef CD (instanceRef FF_38))
+           (portRef CD (instanceRef FF_39))
+           (portRef CD (instanceRef FF_40))
+           (portRef CD (instanceRef FF_41))
+           (portRef CD (instanceRef FF_72))
+           (portRef CD (instanceRef FF_73))
+           (portRef CD (instanceRef FF_74))
+           (portRef CD (instanceRef FF_75))
+           (portRef CD (instanceRef FF_76))
+           (portRef CD (instanceRef FF_77))
+           (portRef CD (instanceRef FF_78))
+           (portRef CD (instanceRef FF_79))
+           (portRef CD (instanceRef FF_80))
+           (portRef CD (instanceRef FF_81))
+           (portRef CD (instanceRef FF_82))
+           (portRef CD (instanceRef FF_83))
+           (portRef CD (instanceRef FF_84))
+           (portRef CD (instanceRef FF_85))
+           (portRef CD (instanceRef FF_86))
+           (portRef CD (instanceRef FF_87))
+           (portRef CD (instanceRef FF_88))
+           (portRef CD (instanceRef FF_89))
+           (portRef CD (instanceRef FF_90))
+           (portRef CD (instanceRef FF_91))
+           (portRef CD (instanceRef FF_92))
+           (portRef CD (instanceRef FF_93))
+           (portRef CD (instanceRef FF_94))
+           (portRef CD (instanceRef FF_95))
+           (portRef CD (instanceRef FF_96))
+           (portRef CD (instanceRef FF_97))
+           (portRef CD (instanceRef FF_98))
+           (portRef CD (instanceRef FF_99))
+           (portRef CD (instanceRef FF_100))
+           (portRef PD (instanceRef FF_101))
+           (portRef RST (instanceRef pdp_ram_0_0_0))
+           (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI35 (instanceRef pdp_ram_0_0_0))
+           (portRef DI34 (instanceRef pdp_ram_0_0_0))
+           (portRef DI33 (instanceRef pdp_ram_0_0_0))
+           (portRef DI32 (instanceRef pdp_ram_0_0_0))
+           (portRef DI31 (instanceRef pdp_ram_0_0_0))
+           (portRef DI30 (instanceRef pdp_ram_0_0_0))
+           (portRef DI29 (instanceRef pdp_ram_0_0_0))
+           (portRef DI28 (instanceRef pdp_ram_0_0_0))
+           (portRef DI25 (instanceRef pdp_ram_0_0_0))
+           (portRef DI23 (instanceRef pdp_ram_0_0_0))
+           (portRef DI22 (instanceRef pdp_ram_0_0_0))
+           (portRef DI21 (instanceRef pdp_ram_0_0_0))
+           (portRef DI20 (instanceRef pdp_ram_0_0_0))
+           (portRef DI19 (instanceRef pdp_ram_0_0_0))
+           (portRef DI18 (instanceRef pdp_ram_0_0_0))
+           (portRef DI17 (instanceRef pdp_ram_0_0_0))
+           (portRef DI16 (instanceRef pdp_ram_0_0_0))
+           (portRef DI14 (instanceRef pdp_ram_0_0_0))
+           (portRef DI10 (instanceRef pdp_ram_0_0_0))
+           (portRef DI8 (instanceRef pdp_ram_0_0_0))
+           (portRef DI7 (instanceRef pdp_ram_0_0_0))
+           (portRef DI6 (instanceRef pdp_ram_0_0_0))
+           (portRef DI5 (instanceRef pdp_ram_0_0_0))
+           (portRef DI4 (instanceRef pdp_ram_0_0_0))
+           (portRef DI3 (instanceRef pdp_ram_0_0_0))
+           (portRef DI2 (instanceRef pdp_ram_0_0_0))
+           (portRef DI1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI0 (instanceRef pdp_ram_0_0_0))
+           (portRef AD0 (instanceRef LUT4_0))
+           (portRef AD0 (instanceRef LUT4_1))
+           (portRef AD0 (instanceRef LUT4_2))
+           (portRef AD0 (instanceRef LUT4_3))
+           (portRef AD0 (instanceRef LUT4_5))
+           (portRef AD1 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_10))
+           (portRef AD1 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_15))
+           (portRef AD1 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_20))
+           (portRef AD1 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_21))
+           (portRef B (instanceRef OR2_t18))
+           (portRef A (instanceRef OR2_t18))
+          ))
+          (net rRst (joined
+           (portRef Z (instanceRef OR2_t18))
+           (portRef PD (instanceRef FF_1))
+           (portRef CD (instanceRef FF_2))
+           (portRef CD (instanceRef FF_3))
+           (portRef CD (instanceRef FF_4))
+           (portRef CD (instanceRef FF_5))
+           (portRef CD (instanceRef FF_6))
+           (portRef CD (instanceRef FF_7))
+           (portRef CD (instanceRef FF_8))
+           (portRef CD (instanceRef FF_9))
+           (portRef CD (instanceRef FF_10))
+           (portRef CD (instanceRef FF_11))
+           (portRef CD (instanceRef FF_22))
+           (portRef CD (instanceRef FF_23))
+           (portRef CD (instanceRef FF_24))
+           (portRef CD (instanceRef FF_25))
+           (portRef CD (instanceRef FF_26))
+           (portRef CD (instanceRef FF_27))
+           (portRef CD (instanceRef FF_28))
+           (portRef CD (instanceRef FF_29))
+           (portRef CD (instanceRef FF_30))
+           (portRef CD (instanceRef FF_31))
+           (portRef CD (instanceRef FF_42))
+           (portRef CD (instanceRef FF_43))
+           (portRef CD (instanceRef FF_44))
+           (portRef CD (instanceRef FF_45))
+           (portRef CD (instanceRef FF_46))
+           (portRef CD (instanceRef FF_47))
+           (portRef CD (instanceRef FF_48))
+           (portRef CD (instanceRef FF_49))
+           (portRef CD (instanceRef FF_50))
+           (portRef CD (instanceRef FF_51))
+           (portRef CD (instanceRef FF_52))
+           (portRef CD (instanceRef FF_53))
+           (portRef CD (instanceRef FF_54))
+           (portRef CD (instanceRef FF_55))
+           (portRef CD (instanceRef FF_56))
+           (portRef CD (instanceRef FF_57))
+           (portRef CD (instanceRef FF_58))
+           (portRef CD (instanceRef FF_59))
+           (portRef CD (instanceRef FF_60))
+           (portRef CD (instanceRef FF_61))
+           (portRef CD (instanceRef FF_62))
+           (portRef CD (instanceRef FF_63))
+           (portRef CD (instanceRef FF_64))
+           (portRef CD (instanceRef FF_65))
+           (portRef CD (instanceRef FF_66))
+           (portRef CD (instanceRef FF_67))
+           (portRef CD (instanceRef FF_68))
+           (portRef CD (instanceRef FF_69))
+           (portRef CD (instanceRef FF_70))
+           (portRef PD (instanceRef FF_71))
+          ))
+          (net wcount_0 (joined
+           (portRef Q (instanceRef FF_101))
+           (portRef A0 (instanceRef full_cmp_0))
+           (portRef A0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_81))
+           (portRef A (instanceRef XOR2_t17))
+          ))
+          (net wcount_1 (joined
+           (portRef Q (instanceRef FF_100))
+           (portRef A1 (instanceRef full_cmp_0))
+           (portRef A1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_80))
+           (portRef A (instanceRef XOR2_t16))
+           (portRef B (instanceRef XOR2_t17))
+          ))
+          (net w_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t17))
+           (portRef D (instanceRef FF_91))
+          ))
+          (net wcount_2 (joined
+           (portRef Q (instanceRef FF_99))
+           (portRef A0 (instanceRef full_cmp_1))
+           (portRef A0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_79))
+           (portRef A (instanceRef XOR2_t15))
+           (portRef B (instanceRef XOR2_t16))
+          ))
+          (net w_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t16))
+           (portRef D (instanceRef FF_90))
+          ))
+          (net wcount_3 (joined
+           (portRef Q (instanceRef FF_98))
+           (portRef A1 (instanceRef full_cmp_1))
+           (portRef A1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_78))
+           (portRef A (instanceRef XOR2_t14))
+           (portRef B (instanceRef XOR2_t15))
+          ))
+          (net w_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t15))
+           (portRef D (instanceRef FF_89))
+          ))
+          (net wcount_4 (joined
+           (portRef Q (instanceRef FF_97))
+           (portRef A0 (instanceRef full_cmp_2))
+           (portRef A0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_77))
+           (portRef A (instanceRef XOR2_t13))
+           (portRef B (instanceRef XOR2_t14))
+          ))
+          (net w_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t14))
+           (portRef D (instanceRef FF_88))
+          ))
+          (net wcount_5 (joined
+           (portRef Q (instanceRef FF_96))
+           (portRef A1 (instanceRef full_cmp_2))
+           (portRef A1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_76))
+           (portRef A (instanceRef XOR2_t12))
+           (portRef B (instanceRef XOR2_t13))
+          ))
+          (net w_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t13))
+           (portRef D (instanceRef FF_87))
+          ))
+          (net wcount_6 (joined
+           (portRef Q (instanceRef FF_95))
+           (portRef A0 (instanceRef full_cmp_3))
+           (portRef A0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_75))
+           (portRef A (instanceRef XOR2_t11))
+           (portRef B (instanceRef XOR2_t12))
+          ))
+          (net w_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t12))
+           (portRef D (instanceRef FF_86))
+          ))
+          (net wcount_7 (joined
+           (portRef Q (instanceRef FF_94))
+           (portRef A1 (instanceRef full_cmp_3))
+           (portRef A1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_74))
+           (portRef A (instanceRef XOR2_t10))
+           (portRef B (instanceRef XOR2_t11))
+          ))
+          (net w_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t11))
+           (portRef D (instanceRef FF_85))
+          ))
+          (net wcount_8 (joined
+           (portRef Q (instanceRef FF_93))
+           (portRef A0 (instanceRef full_cmp_4))
+           (portRef A0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_73))
+           (portRef A (instanceRef XOR2_t9))
+           (portRef B (instanceRef XOR2_t10))
+          ))
+          (net w_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t10))
+           (portRef D (instanceRef FF_84))
+          ))
+          (net wcount_9 (joined
+           (portRef Q (instanceRef FF_92))
+           (portRef A1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_72))
+           (portRef D (instanceRef FF_82))
+           (portRef AD2 (instanceRef LUT4_0))
+           (portRef AD2 (instanceRef LUT4_1))
+           (portRef B (instanceRef XOR2_t9))
+          ))
+          (net w_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t9))
+           (portRef D (instanceRef FF_83))
+          ))
+          (net rcount_0 (joined
+           (portRef Q (instanceRef FF_71))
+           (portRef A0 (instanceRef empty_cmp_0))
+           (portRef A0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_51))
+           (portRef A (instanceRef XOR2_t8))
+          ))
+          (net rcount_1 (joined
+           (portRef Q (instanceRef FF_70))
+           (portRef A1 (instanceRef empty_cmp_0))
+           (portRef A1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_50))
+           (portRef A (instanceRef XOR2_t7))
+           (portRef B (instanceRef XOR2_t8))
+          ))
+          (net r_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t8))
+           (portRef D (instanceRef FF_61))
+          ))
+          (net rcount_2 (joined
+           (portRef Q (instanceRef FF_69))
+           (portRef A0 (instanceRef empty_cmp_1))
+           (portRef A0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_49))
+           (portRef A (instanceRef XOR2_t6))
+           (portRef B (instanceRef XOR2_t7))
+          ))
+          (net r_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t7))
+           (portRef D (instanceRef FF_60))
+          ))
+          (net rcount_3 (joined
+           (portRef Q (instanceRef FF_68))
+           (portRef A1 (instanceRef empty_cmp_1))
+           (portRef A1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_48))
+           (portRef A (instanceRef XOR2_t5))
+           (portRef B (instanceRef XOR2_t6))
+          ))
+          (net r_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t6))
+           (portRef D (instanceRef FF_59))
+          ))
+          (net rcount_4 (joined
+           (portRef Q (instanceRef FF_67))
+           (portRef A0 (instanceRef empty_cmp_2))
+           (portRef A0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_47))
+           (portRef A (instanceRef XOR2_t4))
+           (portRef B (instanceRef XOR2_t5))
+          ))
+          (net r_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t5))
+           (portRef D (instanceRef FF_58))
+          ))
+          (net rcount_5 (joined
+           (portRef Q (instanceRef FF_66))
+           (portRef A1 (instanceRef empty_cmp_2))
+           (portRef A1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_46))
+           (portRef A (instanceRef XOR2_t3))
+           (portRef B (instanceRef XOR2_t4))
+          ))
+          (net r_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t4))
+           (portRef D (instanceRef FF_57))
+          ))
+          (net rcount_6 (joined
+           (portRef Q (instanceRef FF_65))
+           (portRef A0 (instanceRef empty_cmp_3))
+           (portRef A0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_45))
+           (portRef A (instanceRef XOR2_t2))
+           (portRef B (instanceRef XOR2_t3))
+          ))
+          (net r_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t3))
+           (portRef D (instanceRef FF_56))
+          ))
+          (net rcount_7 (joined
+           (portRef Q (instanceRef FF_64))
+           (portRef A1 (instanceRef empty_cmp_3))
+           (portRef A1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_44))
+           (portRef A (instanceRef XOR2_t1))
+           (portRef B (instanceRef XOR2_t2))
+          ))
+          (net r_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t2))
+           (portRef D (instanceRef FF_55))
+          ))
+          (net rcount_8 (joined
+           (portRef Q (instanceRef FF_63))
+           (portRef A0 (instanceRef empty_cmp_4))
+           (portRef A0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_43))
+           (portRef A (instanceRef XOR2_t0))
+           (portRef B (instanceRef XOR2_t1))
+          ))
+          (net r_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t1))
+           (portRef D (instanceRef FF_54))
+          ))
+          (net rcount_9 (joined
+           (portRef Q (instanceRef FF_62))
+           (portRef A1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_42))
+           (portRef D (instanceRef FF_52))
+           (portRef AD2 (instanceRef LUT4_2))
+           (portRef AD2 (instanceRef LUT4_3))
+           (portRef B (instanceRef XOR2_t0))
+          ))
+          (net r_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t0))
+           (portRef D (instanceRef FF_53))
+          ))
+          (net w_gcount_r29 (joined
+           (portRef Q (instanceRef FF_12))
+           (portRef AD1 (instanceRef LUT4_2))
+           (portRef AD1 (instanceRef LUT4_3))
+           (portRef AD1 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r28 (joined
+           (portRef Q (instanceRef FF_13))
+           (portRef AD2 (instanceRef LUT4_20))
+           (portRef AD3 (instanceRef LUT4_21))
+           (portRef AD1 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r27 (joined
+           (portRef Q (instanceRef FF_14))
+           (portRef AD1 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r26 (joined
+           (portRef Q (instanceRef FF_15))
+           (portRef AD1 (instanceRef LUT4_18))
+           (portRef AD2 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_23))
+          ))
+          (net w_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_23))
+           (portRef B0 (instanceRef empty_cmp_3))
+           (portRef AD3 (instanceRef LUT4_14))
+           (portRef AD3 (instanceRef LUT4_15))
+           (portRef AD3 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_17))
+          ))
+          (net w_gcount_r25 (joined
+           (portRef Q (instanceRef FF_16))
+           (portRef AD1 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_18))
+           (portRef AD3 (instanceRef LUT4_19))
+           (portRef AD0 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r24 (joined
+           (portRef Q (instanceRef FF_17))
+           (portRef AD2 (instanceRef LUT4_17))
+           (portRef AD3 (instanceRef LUT4_18))
+           (portRef AD1 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r23 (joined
+           (portRef Q (instanceRef FF_18))
+           (portRef AD3 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r22 (joined
+           (portRef Q (instanceRef FF_19))
+           (portRef AD3 (instanceRef LUT4_22))
+          ))
+          (net w_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_22))
+           (portRef AD2 (instanceRef LUT4_14))
+           (portRef AD2 (instanceRef LUT4_15))
+           (portRef AD2 (instanceRef LUT4_16))
+          ))
+          (net wcount_r8 (joined
+           (portRef DO0 (instanceRef LUT4_21))
+           (portRef B0 (instanceRef empty_cmp_4))
+           (portRef AD0 (instanceRef LUT4_19))
+          ))
+          (net wcount_r7 (joined
+           (portRef DO0 (instanceRef LUT4_20))
+           (portRef B1 (instanceRef empty_cmp_3))
+           (portRef AD0 (instanceRef LUT4_18))
+          ))
+          (net wcount_r5 (joined
+           (portRef DO0 (instanceRef LUT4_19))
+           (portRef B1 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r4 (joined
+           (portRef DO0 (instanceRef LUT4_18))
+           (portRef B0 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r3 (joined
+           (portRef DO0 (instanceRef LUT4_17))
+           (portRef B1 (instanceRef empty_cmp_1))
+          ))
+          (net wcount_r2 (joined
+           (portRef DO0 (instanceRef LUT4_16))
+           (portRef B0 (instanceRef empty_cmp_1))
+          ))
+          (net w_gcount_r21 (joined
+           (portRef Q (instanceRef FF_20))
+           (portRef AD0 (instanceRef LUT4_14))
+           (portRef AD1 (instanceRef LUT4_15))
+          ))
+          (net wcount_r1 (joined
+           (portRef DO0 (instanceRef LUT4_15))
+           (portRef B1 (instanceRef empty_cmp_0))
+          ))
+          (net w_gcount_r20 (joined
+           (portRef Q (instanceRef FF_21))
+           (portRef AD1 (instanceRef LUT4_14))
+          ))
+          (net wcount_r0 (joined
+           (portRef DO0 (instanceRef LUT4_14))
+           (portRef B0 (instanceRef empty_cmp_0))
+          ))
+          (net r_gcount_w29 (joined
+           (portRef Q (instanceRef FF_2))
+           (portRef AD1 (instanceRef LUT4_0))
+           (portRef AD1 (instanceRef LUT4_1))
+           (portRef AD1 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w28 (joined
+           (portRef Q (instanceRef FF_3))
+           (portRef AD2 (instanceRef LUT4_10))
+           (portRef AD3 (instanceRef LUT4_11))
+           (portRef AD1 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w27 (joined
+           (portRef Q (instanceRef FF_4))
+           (portRef AD1 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w26 (joined
+           (portRef Q (instanceRef FF_5))
+           (portRef AD1 (instanceRef LUT4_8))
+           (portRef AD2 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_13))
+          ))
+          (net r_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_13))
+           (portRef B0 (instanceRef full_cmp_3))
+           (portRef AD3 (instanceRef LUT4_4))
+           (portRef AD3 (instanceRef LUT4_5))
+           (portRef AD3 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_7))
+          ))
+          (net r_gcount_w25 (joined
+           (portRef Q (instanceRef FF_6))
+           (portRef AD1 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_8))
+           (portRef AD3 (instanceRef LUT4_9))
+           (portRef AD0 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w24 (joined
+           (portRef Q (instanceRef FF_7))
+           (portRef AD2 (instanceRef LUT4_7))
+           (portRef AD3 (instanceRef LUT4_8))
+           (portRef AD1 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w23 (joined
+           (portRef Q (instanceRef FF_8))
+           (portRef AD3 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w22 (joined
+           (portRef Q (instanceRef FF_9))
+           (portRef AD3 (instanceRef LUT4_12))
+          ))
+          (net r_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_12))
+           (portRef AD2 (instanceRef LUT4_4))
+           (portRef AD2 (instanceRef LUT4_5))
+           (portRef AD2 (instanceRef LUT4_6))
+          ))
+          (net rcount_w8 (joined
+           (portRef DO0 (instanceRef LUT4_11))
+           (portRef B0 (instanceRef full_cmp_4))
+           (portRef AD0 (instanceRef LUT4_9))
+          ))
+          (net rcount_w7 (joined
+           (portRef DO0 (instanceRef LUT4_10))
+           (portRef B1 (instanceRef full_cmp_3))
+           (portRef AD0 (instanceRef LUT4_8))
+          ))
+          (net rcount_w5 (joined
+           (portRef DO0 (instanceRef LUT4_9))
+           (portRef B1 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w4 (joined
+           (portRef DO0 (instanceRef LUT4_8))
+           (portRef B0 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w3 (joined
+           (portRef DO0 (instanceRef LUT4_7))
+           (portRef B1 (instanceRef full_cmp_1))
+          ))
+          (net rcount_w2 (joined
+           (portRef DO0 (instanceRef LUT4_6))
+           (portRef B0 (instanceRef full_cmp_1))
+          ))
+          (net r_gcount_w21 (joined
+           (portRef Q (instanceRef FF_10))
+           (portRef AD0 (instanceRef LUT4_4))
+           (portRef AD1 (instanceRef LUT4_5))
+          ))
+          (net rcount_w1 (joined
+           (portRef DO0 (instanceRef LUT4_5))
+           (portRef B1 (instanceRef full_cmp_0))
+          ))
+          (net r_gcount_w20 (joined
+           (portRef Q (instanceRef FF_11))
+           (portRef AD1 (instanceRef LUT4_4))
+          ))
+          (net rcount_w0 (joined
+           (portRef DO0 (instanceRef LUT4_4))
+           (portRef B0 (instanceRef full_cmp_0))
+          ))
+          (net rptr_9 (joined
+           (portRef Q (instanceRef FF_42))
+           (portRef AD3 (instanceRef LUT4_2))
+           (portRef AD3 (instanceRef LUT4_3))
+          ))
+          (net empty_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_3))
+           (portRef A1 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_2))
+           (portRef B1 (instanceRef empty_cmp_4))
+          ))
+          (net wptr_9 (joined
+           (portRef Q (instanceRef FF_72))
+           (portRef AD3 (instanceRef LUT4_0))
+           (portRef AD3 (instanceRef LUT4_1))
+          ))
+          (net full_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_1))
+           (portRef A1 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_0))
+           (portRef B1 (instanceRef full_cmp_4))
+          ))
+          (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined
+           (portRef fifo_in_data_0)
+           (portRef DI27 (instanceRef pdp_ram_0_0_0))
+           (portRef DI26 (instanceRef pdp_ram_0_0_0))
+           (portRef DI24 (instanceRef pdp_ram_0_0_0))
+           (portRef DI15 (instanceRef pdp_ram_0_0_0))
+           (portRef DI13 (instanceRef pdp_ram_0_0_0))
+           (portRef DI12 (instanceRef pdp_ram_0_0_0))
+           (portRef DI11 (instanceRef pdp_ram_0_0_0))
+           (portRef DI9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_0 (joined
+           (portRef Q (instanceRef FF_81))
+           (portRef ADW0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_1 (joined
+           (portRef Q (instanceRef FF_80))
+           (portRef ADW1 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_2 (joined
+           (portRef Q (instanceRef FF_79))
+           (portRef ADW2 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_3 (joined
+           (portRef Q (instanceRef FF_78))
+           (portRef ADW3 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_4 (joined
+           (portRef Q (instanceRef FF_77))
+           (portRef ADW4 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_5 (joined
+           (portRef Q (instanceRef FF_76))
+           (portRef ADW5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_6 (joined
+           (portRef Q (instanceRef FF_75))
+           (portRef ADW6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_7 (joined
+           (portRef Q (instanceRef FF_74))
+           (portRef ADW7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_8 (joined
+           (portRef Q (instanceRef FF_73))
+           (portRef ADW8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef a1))
+           (portRef C1 (instanceRef a1))
+           (portRef D0 (instanceRef a1))
+           (portRef C0 (instanceRef a1))
+           (portRef D1 (instanceRef full_cmp_4))
+           (portRef C1 (instanceRef full_cmp_4))
+           (portRef D0 (instanceRef full_cmp_4))
+           (portRef C0 (instanceRef full_cmp_4))
+           (portRef D1 (instanceRef full_cmp_3))
+           (portRef C1 (instanceRef full_cmp_3))
+           (portRef D0 (instanceRef full_cmp_3))
+           (portRef C0 (instanceRef full_cmp_3))
+           (portRef D1 (instanceRef full_cmp_2))
+           (portRef C1 (instanceRef full_cmp_2))
+           (portRef D0 (instanceRef full_cmp_2))
+           (portRef C0 (instanceRef full_cmp_2))
+           (portRef D1 (instanceRef full_cmp_1))
+           (portRef C1 (instanceRef full_cmp_1))
+           (portRef D0 (instanceRef full_cmp_1))
+           (portRef C0 (instanceRef full_cmp_1))
+           (portRef D1 (instanceRef full_cmp_0))
+           (portRef C1 (instanceRef full_cmp_0))
+           (portRef D0 (instanceRef full_cmp_0))
+           (portRef C0 (instanceRef full_cmp_0))
+           (portRef D1 (instanceRef full_cmp_ci_a))
+           (portRef C1 (instanceRef full_cmp_ci_a))
+           (portRef D0 (instanceRef full_cmp_ci_a))
+           (portRef C0 (instanceRef full_cmp_ci_a))
+           (portRef D1 (instanceRef a0))
+           (portRef C1 (instanceRef a0))
+           (portRef D0 (instanceRef a0))
+           (portRef C0 (instanceRef a0))
+           (portRef D1 (instanceRef empty_cmp_4))
+           (portRef C1 (instanceRef empty_cmp_4))
+           (portRef D0 (instanceRef empty_cmp_4))
+           (portRef C0 (instanceRef empty_cmp_4))
+           (portRef D1 (instanceRef empty_cmp_3))
+           (portRef C1 (instanceRef empty_cmp_3))
+           (portRef D0 (instanceRef empty_cmp_3))
+           (portRef C0 (instanceRef empty_cmp_3))
+           (portRef D1 (instanceRef empty_cmp_2))
+           (portRef C1 (instanceRef empty_cmp_2))
+           (portRef D0 (instanceRef empty_cmp_2))
+           (portRef C0 (instanceRef empty_cmp_2))
+           (portRef D1 (instanceRef empty_cmp_1))
+           (portRef C1 (instanceRef empty_cmp_1))
+           (portRef D0 (instanceRef empty_cmp_1))
+           (portRef C0 (instanceRef empty_cmp_1))
+           (portRef D1 (instanceRef empty_cmp_0))
+           (portRef C1 (instanceRef empty_cmp_0))
+           (portRef D0 (instanceRef empty_cmp_0))
+           (portRef C0 (instanceRef empty_cmp_0))
+           (portRef D1 (instanceRef empty_cmp_ci_a))
+           (portRef C1 (instanceRef empty_cmp_ci_a))
+           (portRef D0 (instanceRef empty_cmp_ci_a))
+           (portRef C0 (instanceRef empty_cmp_ci_a))
+           (portRef D1 (instanceRef r_gctr_4))
+           (portRef C1 (instanceRef r_gctr_4))
+           (portRef D0 (instanceRef r_gctr_4))
+           (portRef C0 (instanceRef r_gctr_4))
+           (portRef D1 (instanceRef r_gctr_3))
+           (portRef C1 (instanceRef r_gctr_3))
+           (portRef D0 (instanceRef r_gctr_3))
+           (portRef C0 (instanceRef r_gctr_3))
+           (portRef D1 (instanceRef r_gctr_2))
+           (portRef C1 (instanceRef r_gctr_2))
+           (portRef D0 (instanceRef r_gctr_2))
+           (portRef C0 (instanceRef r_gctr_2))
+           (portRef D1 (instanceRef r_gctr_1))
+           (portRef C1 (instanceRef r_gctr_1))
+           (portRef D0 (instanceRef r_gctr_1))
+           (portRef C0 (instanceRef r_gctr_1))
+           (portRef D1 (instanceRef r_gctr_0))
+           (portRef C1 (instanceRef r_gctr_0))
+           (portRef D0 (instanceRef r_gctr_0))
+           (portRef C0 (instanceRef r_gctr_0))
+           (portRef D1 (instanceRef r_gctr_cia))
+           (portRef C1 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef r_gctr_cia))
+           (portRef A1 (instanceRef r_gctr_cia))
+           (portRef D0 (instanceRef r_gctr_cia))
+           (portRef C0 (instanceRef r_gctr_cia))
+           (portRef D1 (instanceRef w_gctr_4))
+           (portRef C1 (instanceRef w_gctr_4))
+           (portRef D0 (instanceRef w_gctr_4))
+           (portRef C0 (instanceRef w_gctr_4))
+           (portRef D1 (instanceRef w_gctr_3))
+           (portRef C1 (instanceRef w_gctr_3))
+           (portRef D0 (instanceRef w_gctr_3))
+           (portRef C0 (instanceRef w_gctr_3))
+           (portRef D1 (instanceRef w_gctr_2))
+           (portRef C1 (instanceRef w_gctr_2))
+           (portRef D0 (instanceRef w_gctr_2))
+           (portRef C0 (instanceRef w_gctr_2))
+           (portRef D1 (instanceRef w_gctr_1))
+           (portRef C1 (instanceRef w_gctr_1))
+           (portRef D0 (instanceRef w_gctr_1))
+           (portRef C0 (instanceRef w_gctr_1))
+           (portRef D1 (instanceRef w_gctr_0))
+           (portRef C1 (instanceRef w_gctr_0))
+           (portRef D0 (instanceRef w_gctr_0))
+           (portRef C0 (instanceRef w_gctr_0))
+           (portRef D1 (instanceRef w_gctr_cia))
+           (portRef C1 (instanceRef w_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_cia))
+           (portRef A1 (instanceRef w_gctr_cia))
+           (portRef D0 (instanceRef w_gctr_cia))
+           (portRef C0 (instanceRef w_gctr_cia))
+           (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+           (portRef BE3 (instanceRef pdp_ram_0_0_0))
+           (portRef BE2 (instanceRef pdp_ram_0_0_0))
+           (portRef BE1 (instanceRef pdp_ram_0_0_0))
+           (portRef BE0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef CK (instanceRef FF_0))
+           (portRef CK (instanceRef FF_1))
+           (portRef CK (instanceRef FF_2))
+           (portRef CK (instanceRef FF_3))
+           (portRef CK (instanceRef FF_4))
+           (portRef CK (instanceRef FF_5))
+           (portRef CK (instanceRef FF_6))
+           (portRef CK (instanceRef FF_7))
+           (portRef CK (instanceRef FF_8))
+           (portRef CK (instanceRef FF_9))
+           (portRef CK (instanceRef FF_10))
+           (portRef CK (instanceRef FF_11))
+           (portRef CK (instanceRef FF_12))
+           (portRef CK (instanceRef FF_13))
+           (portRef CK (instanceRef FF_14))
+           (portRef CK (instanceRef FF_15))
+           (portRef CK (instanceRef FF_16))
+           (portRef CK (instanceRef FF_17))
+           (portRef CK (instanceRef FF_18))
+           (portRef CK (instanceRef FF_19))
+           (portRef CK (instanceRef FF_20))
+           (portRef CK (instanceRef FF_21))
+           (portRef CK (instanceRef FF_22))
+           (portRef CK (instanceRef FF_23))
+           (portRef CK (instanceRef FF_24))
+           (portRef CK (instanceRef FF_25))
+           (portRef CK (instanceRef FF_26))
+           (portRef CK (instanceRef FF_27))
+           (portRef CK (instanceRef FF_28))
+           (portRef CK (instanceRef FF_29))
+           (portRef CK (instanceRef FF_30))
+           (portRef CK (instanceRef FF_31))
+           (portRef CK (instanceRef FF_32))
+           (portRef CK (instanceRef FF_33))
+           (portRef CK (instanceRef FF_34))
+           (portRef CK (instanceRef FF_35))
+           (portRef CK (instanceRef FF_36))
+           (portRef CK (instanceRef FF_37))
+           (portRef CK (instanceRef FF_38))
+           (portRef CK (instanceRef FF_39))
+           (portRef CK (instanceRef FF_40))
+           (portRef CK (instanceRef FF_41))
+           (portRef CK (instanceRef FF_42))
+           (portRef CK (instanceRef FF_43))
+           (portRef CK (instanceRef FF_44))
+           (portRef CK (instanceRef FF_45))
+           (portRef CK (instanceRef FF_46))
+           (portRef CK (instanceRef FF_47))
+           (portRef CK (instanceRef FF_48))
+           (portRef CK (instanceRef FF_49))
+           (portRef CK (instanceRef FF_50))
+           (portRef CK (instanceRef FF_51))
+           (portRef CK (instanceRef FF_52))
+           (portRef CK (instanceRef FF_53))
+           (portRef CK (instanceRef FF_54))
+           (portRef CK (instanceRef FF_55))
+           (portRef CK (instanceRef FF_56))
+           (portRef CK (instanceRef FF_57))
+           (portRef CK (instanceRef FF_58))
+           (portRef CK (instanceRef FF_59))
+           (portRef CK (instanceRef FF_60))
+           (portRef CK (instanceRef FF_61))
+           (portRef CK (instanceRef FF_62))
+           (portRef CK (instanceRef FF_63))
+           (portRef CK (instanceRef FF_64))
+           (portRef CK (instanceRef FF_65))
+           (portRef CK (instanceRef FF_66))
+           (portRef CK (instanceRef FF_67))
+           (portRef CK (instanceRef FF_68))
+           (portRef CK (instanceRef FF_69))
+           (portRef CK (instanceRef FF_70))
+           (portRef CK (instanceRef FF_71))
+           (portRef CK (instanceRef FF_72))
+           (portRef CK (instanceRef FF_73))
+           (portRef CK (instanceRef FF_74))
+           (portRef CK (instanceRef FF_75))
+           (portRef CK (instanceRef FF_76))
+           (portRef CK (instanceRef FF_77))
+           (portRef CK (instanceRef FF_78))
+           (portRef CK (instanceRef FF_79))
+           (portRef CK (instanceRef FF_80))
+           (portRef CK (instanceRef FF_81))
+           (portRef CK (instanceRef FF_82))
+           (portRef CK (instanceRef FF_83))
+           (portRef CK (instanceRef FF_84))
+           (portRef CK (instanceRef FF_85))
+           (portRef CK (instanceRef FF_86))
+           (portRef CK (instanceRef FF_87))
+           (portRef CK (instanceRef FF_88))
+           (portRef CK (instanceRef FF_89))
+           (portRef CK (instanceRef FF_90))
+           (portRef CK (instanceRef FF_91))
+           (portRef CK (instanceRef FF_92))
+           (portRef CK (instanceRef FF_93))
+           (portRef CK (instanceRef FF_94))
+           (portRef CK (instanceRef FF_95))
+           (portRef CK (instanceRef FF_96))
+           (portRef CK (instanceRef FF_97))
+           (portRef CK (instanceRef FF_98))
+           (portRef CK (instanceRef FF_99))
+           (portRef CK (instanceRef FF_100))
+           (portRef CK (instanceRef FF_101))
+           (portRef CLKR (instanceRef pdp_ram_0_0_0))
+           (portRef CLKW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_0 (joined
+           (portRef Q (instanceRef FF_51))
+           (portRef ADR5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_1 (joined
+           (portRef Q (instanceRef FF_50))
+           (portRef ADR6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_2 (joined
+           (portRef Q (instanceRef FF_49))
+           (portRef ADR7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_3 (joined
+           (portRef Q (instanceRef FF_48))
+           (portRef ADR8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_4 (joined
+           (portRef Q (instanceRef FF_47))
+           (portRef ADR9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_5 (joined
+           (portRef Q (instanceRef FF_46))
+           (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_6 (joined
+           (portRef Q (instanceRef FF_45))
+           (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_7 (joined
+           (portRef Q (instanceRef FF_44))
+           (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_8 (joined
+           (portRef Q (instanceRef FF_43))
+           (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef DO0 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef DO1 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef DO2 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef DO3 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef DO4 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef DO5 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename Q_1_24 "Q_1[24]") (joined
+           (portRef DO6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_25 "Q_1[25]") (joined
+           (portRef DO7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_26 "Q_1[26]") (joined
+           (portRef DO8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_27 "Q_1[27]") (joined
+           (portRef DO9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_28 "Q_1[28]") (joined
+           (portRef DO10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_29 "Q_1[29]") (joined
+           (portRef DO11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_30 "Q_1[30]") (joined
+           (portRef DO12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_31 "Q_1[31]") (joined
+           (portRef DO13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO14_1 (joined
+           (portRef DO14 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO15_1 (joined
+           (portRef DO15 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO16_1 (joined
+           (portRef DO16 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO17_1 (joined
+           (portRef DO17 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef DO18 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef DO19 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef DO20 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef DO21 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef DO22 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef DO23 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef DO24 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef DO25 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef DO26 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef DO27 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef DO28 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef DO29 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef DO30 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef DO31 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef DO32 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef DO33 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef DO34 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef DO35 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net iwcount_0 (joined
+           (portRef S0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_101))
+          ))
+          (net iwcount_1 (joined
+           (portRef S1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_100))
+          ))
+          (net iwcount_2 (joined
+           (portRef S0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_99))
+          ))
+          (net iwcount_3 (joined
+           (portRef S1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_98))
+          ))
+          (net iwcount_4 (joined
+           (portRef S0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_97))
+          ))
+          (net iwcount_5 (joined
+           (portRef S1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_96))
+          ))
+          (net iwcount_6 (joined
+           (portRef S0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_95))
+          ))
+          (net iwcount_7 (joined
+           (portRef S1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_94))
+          ))
+          (net iwcount_8 (joined
+           (portRef S0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_93))
+          ))
+          (net iwcount_9 (joined
+           (portRef S1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_92))
+          ))
+          (net w_gcount_0 (joined
+           (portRef Q (instanceRef FF_91))
+           (portRef D (instanceRef FF_41))
+          ))
+          (net w_gcount_1 (joined
+           (portRef Q (instanceRef FF_90))
+           (portRef D (instanceRef FF_40))
+          ))
+          (net w_gcount_2 (joined
+           (portRef Q (instanceRef FF_89))
+           (portRef D (instanceRef FF_39))
+          ))
+          (net w_gcount_3 (joined
+           (portRef Q (instanceRef FF_88))
+           (portRef D (instanceRef FF_38))
+          ))
+          (net w_gcount_4 (joined
+           (portRef Q (instanceRef FF_87))
+           (portRef D (instanceRef FF_37))
+          ))
+          (net w_gcount_5 (joined
+           (portRef Q (instanceRef FF_86))
+           (portRef D (instanceRef FF_36))
+          ))
+          (net w_gcount_6 (joined
+           (portRef Q (instanceRef FF_85))
+           (portRef D (instanceRef FF_35))
+          ))
+          (net w_gcount_7 (joined
+           (portRef Q (instanceRef FF_84))
+           (portRef D (instanceRef FF_34))
+          ))
+          (net w_gcount_8 (joined
+           (portRef Q (instanceRef FF_83))
+           (portRef D (instanceRef FF_33))
+          ))
+          (net w_gcount_9 (joined
+           (portRef Q (instanceRef FF_82))
+           (portRef D (instanceRef FF_32))
+          ))
+          (net ircount_0 (joined
+           (portRef S0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_71))
+          ))
+          (net ircount_1 (joined
+           (portRef S1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_70))
+          ))
+          (net ircount_2 (joined
+           (portRef S0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_69))
+          ))
+          (net ircount_3 (joined
+           (portRef S1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_68))
+          ))
+          (net ircount_4 (joined
+           (portRef S0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_67))
+          ))
+          (net ircount_5 (joined
+           (portRef S1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_66))
+          ))
+          (net ircount_6 (joined
+           (portRef S0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_65))
+          ))
+          (net ircount_7 (joined
+           (portRef S1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_64))
+          ))
+          (net ircount_8 (joined
+           (portRef S0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_63))
+          ))
+          (net ircount_9 (joined
+           (portRef S1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_62))
+          ))
+          (net r_gcount_0 (joined
+           (portRef Q (instanceRef FF_61))
+           (portRef D (instanceRef FF_31))
+          ))
+          (net r_gcount_1 (joined
+           (portRef Q (instanceRef FF_60))
+           (portRef D (instanceRef FF_30))
+          ))
+          (net r_gcount_2 (joined
+           (portRef Q (instanceRef FF_59))
+           (portRef D (instanceRef FF_29))
+          ))
+          (net r_gcount_3 (joined
+           (portRef Q (instanceRef FF_58))
+           (portRef D (instanceRef FF_28))
+          ))
+          (net r_gcount_4 (joined
+           (portRef Q (instanceRef FF_57))
+           (portRef D (instanceRef FF_27))
+          ))
+          (net r_gcount_5 (joined
+           (portRef Q (instanceRef FF_56))
+           (portRef D (instanceRef FF_26))
+          ))
+          (net r_gcount_6 (joined
+           (portRef Q (instanceRef FF_55))
+           (portRef D (instanceRef FF_25))
+          ))
+          (net r_gcount_7 (joined
+           (portRef Q (instanceRef FF_54))
+           (portRef D (instanceRef FF_24))
+          ))
+          (net r_gcount_8 (joined
+           (portRef Q (instanceRef FF_53))
+           (portRef D (instanceRef FF_23))
+          ))
+          (net r_gcount_9 (joined
+           (portRef Q (instanceRef FF_52))
+           (portRef D (instanceRef FF_22))
+          ))
+          (net w_gcount_r0 (joined
+           (portRef Q (instanceRef FF_41))
+           (portRef D (instanceRef FF_21))
+          ))
+          (net w_gcount_r1 (joined
+           (portRef Q (instanceRef FF_40))
+           (portRef D (instanceRef FF_20))
+          ))
+          (net w_gcount_r2 (joined
+           (portRef Q (instanceRef FF_39))
+           (portRef D (instanceRef FF_19))
+          ))
+          (net w_gcount_r3 (joined
+           (portRef Q (instanceRef FF_38))
+           (portRef D (instanceRef FF_18))
+          ))
+          (net w_gcount_r4 (joined
+           (portRef Q (instanceRef FF_37))
+           (portRef D (instanceRef FF_17))
+          ))
+          (net w_gcount_r5 (joined
+           (portRef Q (instanceRef FF_36))
+           (portRef D (instanceRef FF_16))
+          ))
+          (net w_gcount_r6 (joined
+           (portRef Q (instanceRef FF_35))
+           (portRef D (instanceRef FF_15))
+          ))
+          (net w_gcount_r7 (joined
+           (portRef Q (instanceRef FF_34))
+           (portRef D (instanceRef FF_14))
+          ))
+          (net w_gcount_r8 (joined
+           (portRef Q (instanceRef FF_33))
+           (portRef D (instanceRef FF_13))
+          ))
+          (net w_gcount_r9 (joined
+           (portRef Q (instanceRef FF_32))
+           (portRef D (instanceRef FF_12))
+          ))
+          (net r_gcount_w0 (joined
+           (portRef Q (instanceRef FF_31))
+           (portRef D (instanceRef FF_11))
+          ))
+          (net r_gcount_w1 (joined
+           (portRef Q (instanceRef FF_30))
+           (portRef D (instanceRef FF_10))
+          ))
+          (net r_gcount_w2 (joined
+           (portRef Q (instanceRef FF_29))
+           (portRef D (instanceRef FF_9))
+          ))
+          (net r_gcount_w3 (joined
+           (portRef Q (instanceRef FF_28))
+           (portRef D (instanceRef FF_8))
+          ))
+          (net r_gcount_w4 (joined
+           (portRef Q (instanceRef FF_27))
+           (portRef D (instanceRef FF_7))
+          ))
+          (net r_gcount_w5 (joined
+           (portRef Q (instanceRef FF_26))
+           (portRef D (instanceRef FF_6))
+          ))
+          (net r_gcount_w6 (joined
+           (portRef Q (instanceRef FF_25))
+           (portRef D (instanceRef FF_5))
+          ))
+          (net r_gcount_w7 (joined
+           (portRef Q (instanceRef FF_24))
+           (portRef D (instanceRef FF_4))
+          ))
+          (net r_gcount_w8 (joined
+           (portRef Q (instanceRef FF_23))
+           (portRef D (instanceRef FF_3))
+          ))
+          (net r_gcount_w9 (joined
+           (portRef Q (instanceRef FF_22))
+           (portRef D (instanceRef FF_2))
+          ))
+          (net empty_d (joined
+           (portRef S0 (instanceRef a0))
+           (portRef D (instanceRef FF_1))
+          ))
+          (net full_d (joined
+           (portRef S0 (instanceRef a1))
+           (portRef D (instanceRef FF_0))
+          ))
+          (net w_gctr_ci (joined
+           (portRef COUT (instanceRef w_gctr_cia))
+           (portRef CIN (instanceRef w_gctr_0))
+          ))
+          (net w_gctr_cia_S0_1 (joined
+           (portRef S0 (instanceRef w_gctr_cia))
+          ))
+          (net w_gctr_cia_S1_1 (joined
+           (portRef S1 (instanceRef w_gctr_cia))
+          ))
+          (net co0 (joined
+           (portRef COUT (instanceRef w_gctr_0))
+           (portRef CIN (instanceRef w_gctr_1))
+          ))
+          (net co1 (joined
+           (portRef COUT (instanceRef w_gctr_1))
+           (portRef CIN (instanceRef w_gctr_2))
+          ))
+          (net co2 (joined
+           (portRef COUT (instanceRef w_gctr_2))
+           (portRef CIN (instanceRef w_gctr_3))
+          ))
+          (net co3 (joined
+           (portRef COUT (instanceRef w_gctr_3))
+           (portRef CIN (instanceRef w_gctr_4))
+          ))
+          (net co4 (joined
+           (portRef COUT (instanceRef w_gctr_4))
+          ))
+          (net r_gctr_ci (joined
+           (portRef COUT (instanceRef r_gctr_cia))
+           (portRef CIN (instanceRef r_gctr_0))
+          ))
+          (net r_gctr_cia_S0_1 (joined
+           (portRef S0 (instanceRef r_gctr_cia))
+          ))
+          (net r_gctr_cia_S1_1 (joined
+           (portRef S1 (instanceRef r_gctr_cia))
+          ))
+          (net co0_1 (joined
+           (portRef COUT (instanceRef r_gctr_0))
+           (portRef CIN (instanceRef r_gctr_1))
+          ))
+          (net co1_1 (joined
+           (portRef COUT (instanceRef r_gctr_1))
+           (portRef CIN (instanceRef r_gctr_2))
+          ))
+          (net co2_1 (joined
+           (portRef COUT (instanceRef r_gctr_2))
+           (portRef CIN (instanceRef r_gctr_3))
+          ))
+          (net co3_1 (joined
+           (portRef COUT (instanceRef r_gctr_3))
+           (portRef CIN (instanceRef r_gctr_4))
+          ))
+          (net co4_1 (joined
+           (portRef COUT (instanceRef r_gctr_4))
+          ))
+          (net cmp_ci (joined
+           (portRef COUT (instanceRef empty_cmp_ci_a))
+           (portRef CIN (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_ci_a_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_ci_a))
+          ))
+          (net empty_cmp_ci_a_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_ci_a))
+          ))
+          (net co0_2 (joined
+           (portRef COUT (instanceRef empty_cmp_0))
+           (portRef CIN (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_0_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_0_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_0))
+          ))
+          (net co1_2 (joined
+           (portRef COUT (instanceRef empty_cmp_1))
+           (portRef CIN (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_1_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_1_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_1))
+          ))
+          (net co2_2 (joined
+           (portRef COUT (instanceRef empty_cmp_2))
+           (portRef CIN (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_2_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_2_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_2))
+          ))
+          (net co3_2 (joined
+           (portRef COUT (instanceRef empty_cmp_3))
+           (portRef CIN (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_3_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_3_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_3))
+          ))
+          (net empty_d_c (joined
+           (portRef COUT (instanceRef empty_cmp_4))
+           (portRef CIN (instanceRef a0))
+          ))
+          (net empty_cmp_4_S0_1 (joined
+           (portRef S0 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_4_S1_1 (joined
+           (portRef S1 (instanceRef empty_cmp_4))
+          ))
+          (net a0_COUT_1 (joined
+           (portRef COUT (instanceRef a0))
+          ))
+          (net a0_S1_1 (joined
+           (portRef S1 (instanceRef a0))
+          ))
+          (net cmp_ci_1 (joined
+           (portRef COUT (instanceRef full_cmp_ci_a))
+           (portRef CIN (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_ci_a_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_ci_a))
+          ))
+          (net full_cmp_ci_a_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_ci_a))
+          ))
+          (net co0_3 (joined
+           (portRef COUT (instanceRef full_cmp_0))
+           (portRef CIN (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_0_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_0_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_0))
+          ))
+          (net co1_3 (joined
+           (portRef COUT (instanceRef full_cmp_1))
+           (portRef CIN (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_1_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_1_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_1))
+          ))
+          (net co2_3 (joined
+           (portRef COUT (instanceRef full_cmp_2))
+           (portRef CIN (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_2_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_2_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_2))
+          ))
+          (net co3_3 (joined
+           (portRef COUT (instanceRef full_cmp_3))
+           (portRef CIN (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_3_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_3_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_3))
+          ))
+          (net full_d_c (joined
+           (portRef COUT (instanceRef full_cmp_4))
+           (portRef CIN (instanceRef a1))
+          ))
+          (net full_cmp_4_S0_1 (joined
+           (portRef S0 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_4_S1_1 (joined
+           (portRef S1 (instanceRef full_cmp_4))
+          ))
+          (net a1_COUT_1 (joined
+           (portRef COUT (instanceRef a1))
+          ))
+          (net a1_S1_1 (joined
+           (portRef S1 (instanceRef a1))
+          ))
+          (net CIN (joined
+           (portRef CIN (instanceRef full_cmp_ci_a))
+          ))
+          (net CIN_0 (joined
+           (portRef CIN (instanceRef empty_cmp_ci_a))
+          ))
+          (net CIN_1 (joined
+           (portRef CIN (instanceRef r_gctr_cia))
+          ))
+          (net CIN_2 (joined
+           (portRef CIN (instanceRef w_gctr_cia))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "fifo32dc"))
+       )
+    )
+    (cell output_decoder8_2_1 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT))
+           (port decoder_valid (direction OUTPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))"))
+          )
+          (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net N_350_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef valid_internal_RNO_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+          ))
+          (net decoder_valid (joined
+           (portRef Q (instanceRef valid))
+           (portRef decoder_valid)
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef A (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef B (instanceRef un1_out_internal35_1_0_m4_0))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef C (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef valid_internal_RNO_0))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef valid_internal_RNO_0))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef valid_internal_RNO))
+          ))
+          (net N_42 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell tdc4ddr_short_4 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out 4))
+          ))
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out 0))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[2]") (joined
+           (portRef trig_c_i_0)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out 5))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out 1))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out 6))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out 2))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out 7))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out 3))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell fifo32dc_0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port fifo_in_data_0 (direction INPUT))
+           (port fifo_empty_0 (direction OUTPUT))
+           (port fifo_read_0 (direction INPUT))
+           (port fifo_wren (direction INPUT))
+         )
+         (contents
+          (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0410"))
+          )
+          (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x1004"))
+          )
+          (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0140"))
+          )
+          (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x4001"))
+          )
+          (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT)))
+           (property MEM_LPC_FILE (string "fifo32dc.lpc"))
+           (property MEM_INIT_FILE (string ""))
+           (property DATA_WIDTH_W (integer 36))
+           (property DATA_WIDTH_R (integer 36))
+           (property REGMODE (string "NOREG"))
+           (property RESETMODE (string "SYNC"))
+           (property GSR (string "ENABLED"))
+           (property CSDECODE_W (string "0b001"))
+           (property CSDECODE_R (string "0b000"))
+           (property ASYNC_RESET_RELEASE (string "SYNC"))
+           (property INIT_DATA (string "STATIC"))
+          )
+          (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net fifo_wren (joined
+           (portRef fifo_wren)
+           (portRef A (instanceRef AND2_t20))
+          ))
+          (net invout_1 (joined
+           (portRef Z (instanceRef INV_1))
+           (portRef B (instanceRef AND2_t20))
+          ))
+          (net wren_i (joined
+           (portRef Z (instanceRef AND2_t20))
+           (portRef B1 (instanceRef full_cmp_ci_a))
+           (portRef A1 (instanceRef full_cmp_ci_a))
+           (portRef SP (instanceRef FF_72))
+           (portRef SP (instanceRef FF_73))
+           (portRef SP (instanceRef FF_74))
+           (portRef SP (instanceRef FF_75))
+           (portRef SP (instanceRef FF_76))
+           (portRef SP (instanceRef FF_77))
+           (portRef SP (instanceRef FF_78))
+           (portRef SP (instanceRef FF_79))
+           (portRef SP (instanceRef FF_80))
+           (portRef SP (instanceRef FF_81))
+           (portRef SP (instanceRef FF_82))
+           (portRef SP (instanceRef FF_83))
+           (portRef SP (instanceRef FF_84))
+           (portRef SP (instanceRef FF_85))
+           (portRef SP (instanceRef FF_86))
+           (portRef SP (instanceRef FF_87))
+           (portRef SP (instanceRef FF_88))
+           (portRef SP (instanceRef FF_89))
+           (portRef SP (instanceRef FF_90))
+           (portRef SP (instanceRef FF_91))
+           (portRef SP (instanceRef FF_92))
+           (portRef SP (instanceRef FF_93))
+           (portRef SP (instanceRef FF_94))
+           (portRef SP (instanceRef FF_95))
+           (portRef SP (instanceRef FF_96))
+           (portRef SP (instanceRef FF_97))
+           (portRef SP (instanceRef FF_98))
+           (portRef SP (instanceRef FF_99))
+           (portRef SP (instanceRef FF_100))
+           (portRef SP (instanceRef FF_101))
+           (portRef CEW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net Full (joined
+           (portRef Q (instanceRef FF_0))
+           (portRef A (instanceRef INV_1))
+          ))
+          (net (rename fifo_read_0 "fifo_read[1]") (joined
+           (portRef fifo_read_0)
+           (portRef A (instanceRef AND2_t19))
+          ))
+          (net invout_0 (joined
+           (portRef Z (instanceRef INV_0))
+           (portRef B (instanceRef AND2_t19))
+          ))
+          (net rden_i (joined
+           (portRef Z (instanceRef AND2_t19))
+           (portRef B1 (instanceRef empty_cmp_ci_a))
+           (portRef A1 (instanceRef empty_cmp_ci_a))
+           (portRef SP (instanceRef FF_42))
+           (portRef SP (instanceRef FF_43))
+           (portRef SP (instanceRef FF_44))
+           (portRef SP (instanceRef FF_45))
+           (portRef SP (instanceRef FF_46))
+           (portRef SP (instanceRef FF_47))
+           (portRef SP (instanceRef FF_48))
+           (portRef SP (instanceRef FF_49))
+           (portRef SP (instanceRef FF_50))
+           (portRef SP (instanceRef FF_51))
+           (portRef SP (instanceRef FF_52))
+           (portRef SP (instanceRef FF_53))
+           (portRef SP (instanceRef FF_54))
+           (portRef SP (instanceRef FF_55))
+           (portRef SP (instanceRef FF_56))
+           (portRef SP (instanceRef FF_57))
+           (portRef SP (instanceRef FF_58))
+           (portRef SP (instanceRef FF_59))
+           (portRef SP (instanceRef FF_60))
+           (portRef SP (instanceRef FF_61))
+           (portRef SP (instanceRef FF_62))
+           (portRef SP (instanceRef FF_63))
+           (portRef SP (instanceRef FF_64))
+           (portRef SP (instanceRef FF_65))
+           (portRef SP (instanceRef FF_66))
+           (portRef SP (instanceRef FF_67))
+           (portRef SP (instanceRef FF_68))
+           (portRef SP (instanceRef FF_69))
+           (portRef SP (instanceRef FF_70))
+           (portRef SP (instanceRef FF_71))
+           (portRef OCER (instanceRef pdp_ram_0_0_0))
+           (portRef CER (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename fifo_empty_0 "fifo_empty[1]") (joined
+           (portRef Q (instanceRef FF_1))
+           (portRef A (instanceRef INV_0))
+           (portRef fifo_empty_0)
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef B1 (instanceRef a1))
+           (portRef A1 (instanceRef a1))
+           (portRef B0 (instanceRef a1))
+           (portRef A0 (instanceRef a1))
+           (portRef B0 (instanceRef full_cmp_ci_a))
+           (portRef A0 (instanceRef full_cmp_ci_a))
+           (portRef B1 (instanceRef a0))
+           (portRef A1 (instanceRef a0))
+           (portRef B0 (instanceRef a0))
+           (portRef A0 (instanceRef a0))
+           (portRef B0 (instanceRef empty_cmp_ci_a))
+           (portRef A0 (instanceRef empty_cmp_ci_a))
+           (portRef B1 (instanceRef r_gctr_4))
+           (portRef B0 (instanceRef r_gctr_4))
+           (portRef B1 (instanceRef r_gctr_3))
+           (portRef B0 (instanceRef r_gctr_3))
+           (portRef B1 (instanceRef r_gctr_2))
+           (portRef B0 (instanceRef r_gctr_2))
+           (portRef B1 (instanceRef r_gctr_1))
+           (portRef B0 (instanceRef r_gctr_1))
+           (portRef B1 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_cia))
+           (portRef A0 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_4))
+           (portRef B0 (instanceRef w_gctr_4))
+           (portRef B1 (instanceRef w_gctr_3))
+           (portRef B0 (instanceRef w_gctr_3))
+           (portRef B1 (instanceRef w_gctr_2))
+           (portRef B0 (instanceRef w_gctr_2))
+           (portRef B1 (instanceRef w_gctr_1))
+           (portRef B0 (instanceRef w_gctr_1))
+           (portRef B1 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_cia))
+           (portRef A0 (instanceRef w_gctr_cia))
+           (portRef CD (instanceRef FF_0))
+           (portRef CD (instanceRef FF_12))
+           (portRef CD (instanceRef FF_13))
+           (portRef CD (instanceRef FF_14))
+           (portRef CD (instanceRef FF_15))
+           (portRef CD (instanceRef FF_16))
+           (portRef CD (instanceRef FF_17))
+           (portRef CD (instanceRef FF_18))
+           (portRef CD (instanceRef FF_19))
+           (portRef CD (instanceRef FF_20))
+           (portRef CD (instanceRef FF_21))
+           (portRef CD (instanceRef FF_32))
+           (portRef CD (instanceRef FF_33))
+           (portRef CD (instanceRef FF_34))
+           (portRef CD (instanceRef FF_35))
+           (portRef CD (instanceRef FF_36))
+           (portRef CD (instanceRef FF_37))
+           (portRef CD (instanceRef FF_38))
+           (portRef CD (instanceRef FF_39))
+           (portRef CD (instanceRef FF_40))
+           (portRef CD (instanceRef FF_41))
+           (portRef CD (instanceRef FF_72))
+           (portRef CD (instanceRef FF_73))
+           (portRef CD (instanceRef FF_74))
+           (portRef CD (instanceRef FF_75))
+           (portRef CD (instanceRef FF_76))
+           (portRef CD (instanceRef FF_77))
+           (portRef CD (instanceRef FF_78))
+           (portRef CD (instanceRef FF_79))
+           (portRef CD (instanceRef FF_80))
+           (portRef CD (instanceRef FF_81))
+           (portRef CD (instanceRef FF_82))
+           (portRef CD (instanceRef FF_83))
+           (portRef CD (instanceRef FF_84))
+           (portRef CD (instanceRef FF_85))
+           (portRef CD (instanceRef FF_86))
+           (portRef CD (instanceRef FF_87))
+           (portRef CD (instanceRef FF_88))
+           (portRef CD (instanceRef FF_89))
+           (portRef CD (instanceRef FF_90))
+           (portRef CD (instanceRef FF_91))
+           (portRef CD (instanceRef FF_92))
+           (portRef CD (instanceRef FF_93))
+           (portRef CD (instanceRef FF_94))
+           (portRef CD (instanceRef FF_95))
+           (portRef CD (instanceRef FF_96))
+           (portRef CD (instanceRef FF_97))
+           (portRef CD (instanceRef FF_98))
+           (portRef CD (instanceRef FF_99))
+           (portRef CD (instanceRef FF_100))
+           (portRef PD (instanceRef FF_101))
+           (portRef RST (instanceRef pdp_ram_0_0_0))
+           (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI35 (instanceRef pdp_ram_0_0_0))
+           (portRef DI34 (instanceRef pdp_ram_0_0_0))
+           (portRef DI33 (instanceRef pdp_ram_0_0_0))
+           (portRef DI32 (instanceRef pdp_ram_0_0_0))
+           (portRef DI31 (instanceRef pdp_ram_0_0_0))
+           (portRef DI30 (instanceRef pdp_ram_0_0_0))
+           (portRef DI29 (instanceRef pdp_ram_0_0_0))
+           (portRef DI28 (instanceRef pdp_ram_0_0_0))
+           (portRef DI25 (instanceRef pdp_ram_0_0_0))
+           (portRef DI23 (instanceRef pdp_ram_0_0_0))
+           (portRef DI22 (instanceRef pdp_ram_0_0_0))
+           (portRef DI21 (instanceRef pdp_ram_0_0_0))
+           (portRef DI20 (instanceRef pdp_ram_0_0_0))
+           (portRef DI19 (instanceRef pdp_ram_0_0_0))
+           (portRef DI18 (instanceRef pdp_ram_0_0_0))
+           (portRef DI17 (instanceRef pdp_ram_0_0_0))
+           (portRef DI16 (instanceRef pdp_ram_0_0_0))
+           (portRef DI14 (instanceRef pdp_ram_0_0_0))
+           (portRef DI10 (instanceRef pdp_ram_0_0_0))
+           (portRef DI8 (instanceRef pdp_ram_0_0_0))
+           (portRef DI7 (instanceRef pdp_ram_0_0_0))
+           (portRef DI6 (instanceRef pdp_ram_0_0_0))
+           (portRef DI5 (instanceRef pdp_ram_0_0_0))
+           (portRef DI4 (instanceRef pdp_ram_0_0_0))
+           (portRef DI3 (instanceRef pdp_ram_0_0_0))
+           (portRef DI2 (instanceRef pdp_ram_0_0_0))
+           (portRef DI1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI0 (instanceRef pdp_ram_0_0_0))
+           (portRef AD0 (instanceRef LUT4_0))
+           (portRef AD0 (instanceRef LUT4_1))
+           (portRef AD0 (instanceRef LUT4_2))
+           (portRef AD0 (instanceRef LUT4_3))
+           (portRef AD0 (instanceRef LUT4_5))
+           (portRef AD1 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_10))
+           (portRef AD1 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_15))
+           (portRef AD1 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_20))
+           (portRef AD1 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_21))
+           (portRef B (instanceRef OR2_t18))
+           (portRef A (instanceRef OR2_t18))
+          ))
+          (net rRst (joined
+           (portRef Z (instanceRef OR2_t18))
+           (portRef PD (instanceRef FF_1))
+           (portRef CD (instanceRef FF_2))
+           (portRef CD (instanceRef FF_3))
+           (portRef CD (instanceRef FF_4))
+           (portRef CD (instanceRef FF_5))
+           (portRef CD (instanceRef FF_6))
+           (portRef CD (instanceRef FF_7))
+           (portRef CD (instanceRef FF_8))
+           (portRef CD (instanceRef FF_9))
+           (portRef CD (instanceRef FF_10))
+           (portRef CD (instanceRef FF_11))
+           (portRef CD (instanceRef FF_22))
+           (portRef CD (instanceRef FF_23))
+           (portRef CD (instanceRef FF_24))
+           (portRef CD (instanceRef FF_25))
+           (portRef CD (instanceRef FF_26))
+           (portRef CD (instanceRef FF_27))
+           (portRef CD (instanceRef FF_28))
+           (portRef CD (instanceRef FF_29))
+           (portRef CD (instanceRef FF_30))
+           (portRef CD (instanceRef FF_31))
+           (portRef CD (instanceRef FF_42))
+           (portRef CD (instanceRef FF_43))
+           (portRef CD (instanceRef FF_44))
+           (portRef CD (instanceRef FF_45))
+           (portRef CD (instanceRef FF_46))
+           (portRef CD (instanceRef FF_47))
+           (portRef CD (instanceRef FF_48))
+           (portRef CD (instanceRef FF_49))
+           (portRef CD (instanceRef FF_50))
+           (portRef CD (instanceRef FF_51))
+           (portRef CD (instanceRef FF_52))
+           (portRef CD (instanceRef FF_53))
+           (portRef CD (instanceRef FF_54))
+           (portRef CD (instanceRef FF_55))
+           (portRef CD (instanceRef FF_56))
+           (portRef CD (instanceRef FF_57))
+           (portRef CD (instanceRef FF_58))
+           (portRef CD (instanceRef FF_59))
+           (portRef CD (instanceRef FF_60))
+           (portRef CD (instanceRef FF_61))
+           (portRef CD (instanceRef FF_62))
+           (portRef CD (instanceRef FF_63))
+           (portRef CD (instanceRef FF_64))
+           (portRef CD (instanceRef FF_65))
+           (portRef CD (instanceRef FF_66))
+           (portRef CD (instanceRef FF_67))
+           (portRef CD (instanceRef FF_68))
+           (portRef CD (instanceRef FF_69))
+           (portRef CD (instanceRef FF_70))
+           (portRef PD (instanceRef FF_71))
+          ))
+          (net wcount_0 (joined
+           (portRef Q (instanceRef FF_101))
+           (portRef A0 (instanceRef full_cmp_0))
+           (portRef A0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_81))
+           (portRef A (instanceRef XOR2_t17))
+          ))
+          (net wcount_1 (joined
+           (portRef Q (instanceRef FF_100))
+           (portRef A1 (instanceRef full_cmp_0))
+           (portRef A1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_80))
+           (portRef A (instanceRef XOR2_t16))
+           (portRef B (instanceRef XOR2_t17))
+          ))
+          (net w_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t17))
+           (portRef D (instanceRef FF_91))
+          ))
+          (net wcount_2 (joined
+           (portRef Q (instanceRef FF_99))
+           (portRef A0 (instanceRef full_cmp_1))
+           (portRef A0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_79))
+           (portRef A (instanceRef XOR2_t15))
+           (portRef B (instanceRef XOR2_t16))
+          ))
+          (net w_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t16))
+           (portRef D (instanceRef FF_90))
+          ))
+          (net wcount_3 (joined
+           (portRef Q (instanceRef FF_98))
+           (portRef A1 (instanceRef full_cmp_1))
+           (portRef A1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_78))
+           (portRef A (instanceRef XOR2_t14))
+           (portRef B (instanceRef XOR2_t15))
+          ))
+          (net w_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t15))
+           (portRef D (instanceRef FF_89))
+          ))
+          (net wcount_4 (joined
+           (portRef Q (instanceRef FF_97))
+           (portRef A0 (instanceRef full_cmp_2))
+           (portRef A0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_77))
+           (portRef A (instanceRef XOR2_t13))
+           (portRef B (instanceRef XOR2_t14))
+          ))
+          (net w_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t14))
+           (portRef D (instanceRef FF_88))
+          ))
+          (net wcount_5 (joined
+           (portRef Q (instanceRef FF_96))
+           (portRef A1 (instanceRef full_cmp_2))
+           (portRef A1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_76))
+           (portRef A (instanceRef XOR2_t12))
+           (portRef B (instanceRef XOR2_t13))
+          ))
+          (net w_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t13))
+           (portRef D (instanceRef FF_87))
+          ))
+          (net wcount_6 (joined
+           (portRef Q (instanceRef FF_95))
+           (portRef A0 (instanceRef full_cmp_3))
+           (portRef A0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_75))
+           (portRef A (instanceRef XOR2_t11))
+           (portRef B (instanceRef XOR2_t12))
+          ))
+          (net w_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t12))
+           (portRef D (instanceRef FF_86))
+          ))
+          (net wcount_7 (joined
+           (portRef Q (instanceRef FF_94))
+           (portRef A1 (instanceRef full_cmp_3))
+           (portRef A1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_74))
+           (portRef A (instanceRef XOR2_t10))
+           (portRef B (instanceRef XOR2_t11))
+          ))
+          (net w_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t11))
+           (portRef D (instanceRef FF_85))
+          ))
+          (net wcount_8 (joined
+           (portRef Q (instanceRef FF_93))
+           (portRef A0 (instanceRef full_cmp_4))
+           (portRef A0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_73))
+           (portRef A (instanceRef XOR2_t9))
+           (portRef B (instanceRef XOR2_t10))
+          ))
+          (net w_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t10))
+           (portRef D (instanceRef FF_84))
+          ))
+          (net wcount_9 (joined
+           (portRef Q (instanceRef FF_92))
+           (portRef A1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_72))
+           (portRef D (instanceRef FF_82))
+           (portRef AD2 (instanceRef LUT4_0))
+           (portRef AD2 (instanceRef LUT4_1))
+           (portRef B (instanceRef XOR2_t9))
+          ))
+          (net w_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t9))
+           (portRef D (instanceRef FF_83))
+          ))
+          (net rcount_0 (joined
+           (portRef Q (instanceRef FF_71))
+           (portRef A0 (instanceRef empty_cmp_0))
+           (portRef A0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_51))
+           (portRef A (instanceRef XOR2_t8))
+          ))
+          (net rcount_1 (joined
+           (portRef Q (instanceRef FF_70))
+           (portRef A1 (instanceRef empty_cmp_0))
+           (portRef A1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_50))
+           (portRef A (instanceRef XOR2_t7))
+           (portRef B (instanceRef XOR2_t8))
+          ))
+          (net r_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t8))
+           (portRef D (instanceRef FF_61))
+          ))
+          (net rcount_2 (joined
+           (portRef Q (instanceRef FF_69))
+           (portRef A0 (instanceRef empty_cmp_1))
+           (portRef A0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_49))
+           (portRef A (instanceRef XOR2_t6))
+           (portRef B (instanceRef XOR2_t7))
+          ))
+          (net r_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t7))
+           (portRef D (instanceRef FF_60))
+          ))
+          (net rcount_3 (joined
+           (portRef Q (instanceRef FF_68))
+           (portRef A1 (instanceRef empty_cmp_1))
+           (portRef A1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_48))
+           (portRef A (instanceRef XOR2_t5))
+           (portRef B (instanceRef XOR2_t6))
+          ))
+          (net r_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t6))
+           (portRef D (instanceRef FF_59))
+          ))
+          (net rcount_4 (joined
+           (portRef Q (instanceRef FF_67))
+           (portRef A0 (instanceRef empty_cmp_2))
+           (portRef A0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_47))
+           (portRef A (instanceRef XOR2_t4))
+           (portRef B (instanceRef XOR2_t5))
+          ))
+          (net r_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t5))
+           (portRef D (instanceRef FF_58))
+          ))
+          (net rcount_5 (joined
+           (portRef Q (instanceRef FF_66))
+           (portRef A1 (instanceRef empty_cmp_2))
+           (portRef A1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_46))
+           (portRef A (instanceRef XOR2_t3))
+           (portRef B (instanceRef XOR2_t4))
+          ))
+          (net r_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t4))
+           (portRef D (instanceRef FF_57))
+          ))
+          (net rcount_6 (joined
+           (portRef Q (instanceRef FF_65))
+           (portRef A0 (instanceRef empty_cmp_3))
+           (portRef A0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_45))
+           (portRef A (instanceRef XOR2_t2))
+           (portRef B (instanceRef XOR2_t3))
+          ))
+          (net r_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t3))
+           (portRef D (instanceRef FF_56))
+          ))
+          (net rcount_7 (joined
+           (portRef Q (instanceRef FF_64))
+           (portRef A1 (instanceRef empty_cmp_3))
+           (portRef A1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_44))
+           (portRef A (instanceRef XOR2_t1))
+           (portRef B (instanceRef XOR2_t2))
+          ))
+          (net r_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t2))
+           (portRef D (instanceRef FF_55))
+          ))
+          (net rcount_8 (joined
+           (portRef Q (instanceRef FF_63))
+           (portRef A0 (instanceRef empty_cmp_4))
+           (portRef A0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_43))
+           (portRef A (instanceRef XOR2_t0))
+           (portRef B (instanceRef XOR2_t1))
+          ))
+          (net r_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t1))
+           (portRef D (instanceRef FF_54))
+          ))
+          (net rcount_9 (joined
+           (portRef Q (instanceRef FF_62))
+           (portRef A1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_42))
+           (portRef D (instanceRef FF_52))
+           (portRef AD2 (instanceRef LUT4_2))
+           (portRef AD2 (instanceRef LUT4_3))
+           (portRef B (instanceRef XOR2_t0))
+          ))
+          (net r_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t0))
+           (portRef D (instanceRef FF_53))
+          ))
+          (net w_gcount_r29 (joined
+           (portRef Q (instanceRef FF_12))
+           (portRef AD1 (instanceRef LUT4_2))
+           (portRef AD1 (instanceRef LUT4_3))
+           (portRef AD1 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r28 (joined
+           (portRef Q (instanceRef FF_13))
+           (portRef AD2 (instanceRef LUT4_20))
+           (portRef AD3 (instanceRef LUT4_21))
+           (portRef AD1 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r27 (joined
+           (portRef Q (instanceRef FF_14))
+           (portRef AD1 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r26 (joined
+           (portRef Q (instanceRef FF_15))
+           (portRef AD1 (instanceRef LUT4_18))
+           (portRef AD2 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_23))
+          ))
+          (net w_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_23))
+           (portRef B0 (instanceRef empty_cmp_3))
+           (portRef AD3 (instanceRef LUT4_14))
+           (portRef AD3 (instanceRef LUT4_15))
+           (portRef AD3 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_17))
+          ))
+          (net w_gcount_r25 (joined
+           (portRef Q (instanceRef FF_16))
+           (portRef AD1 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_18))
+           (portRef AD3 (instanceRef LUT4_19))
+           (portRef AD0 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r24 (joined
+           (portRef Q (instanceRef FF_17))
+           (portRef AD2 (instanceRef LUT4_17))
+           (portRef AD3 (instanceRef LUT4_18))
+           (portRef AD1 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r23 (joined
+           (portRef Q (instanceRef FF_18))
+           (portRef AD3 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r22 (joined
+           (portRef Q (instanceRef FF_19))
+           (portRef AD3 (instanceRef LUT4_22))
+          ))
+          (net w_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_22))
+           (portRef AD2 (instanceRef LUT4_14))
+           (portRef AD2 (instanceRef LUT4_15))
+           (portRef AD2 (instanceRef LUT4_16))
+          ))
+          (net wcount_r8 (joined
+           (portRef DO0 (instanceRef LUT4_21))
+           (portRef B0 (instanceRef empty_cmp_4))
+           (portRef AD0 (instanceRef LUT4_19))
+          ))
+          (net wcount_r7 (joined
+           (portRef DO0 (instanceRef LUT4_20))
+           (portRef B1 (instanceRef empty_cmp_3))
+           (portRef AD0 (instanceRef LUT4_18))
+          ))
+          (net wcount_r5 (joined
+           (portRef DO0 (instanceRef LUT4_19))
+           (portRef B1 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r4 (joined
+           (portRef DO0 (instanceRef LUT4_18))
+           (portRef B0 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r3 (joined
+           (portRef DO0 (instanceRef LUT4_17))
+           (portRef B1 (instanceRef empty_cmp_1))
+          ))
+          (net wcount_r2 (joined
+           (portRef DO0 (instanceRef LUT4_16))
+           (portRef B0 (instanceRef empty_cmp_1))
+          ))
+          (net w_gcount_r21 (joined
+           (portRef Q (instanceRef FF_20))
+           (portRef AD0 (instanceRef LUT4_14))
+           (portRef AD1 (instanceRef LUT4_15))
+          ))
+          (net wcount_r1 (joined
+           (portRef DO0 (instanceRef LUT4_15))
+           (portRef B1 (instanceRef empty_cmp_0))
+          ))
+          (net w_gcount_r20 (joined
+           (portRef Q (instanceRef FF_21))
+           (portRef AD1 (instanceRef LUT4_14))
+          ))
+          (net wcount_r0 (joined
+           (portRef DO0 (instanceRef LUT4_14))
+           (portRef B0 (instanceRef empty_cmp_0))
+          ))
+          (net r_gcount_w29 (joined
+           (portRef Q (instanceRef FF_2))
+           (portRef AD1 (instanceRef LUT4_0))
+           (portRef AD1 (instanceRef LUT4_1))
+           (portRef AD1 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w28 (joined
+           (portRef Q (instanceRef FF_3))
+           (portRef AD2 (instanceRef LUT4_10))
+           (portRef AD3 (instanceRef LUT4_11))
+           (portRef AD1 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w27 (joined
+           (portRef Q (instanceRef FF_4))
+           (portRef AD1 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w26 (joined
+           (portRef Q (instanceRef FF_5))
+           (portRef AD1 (instanceRef LUT4_8))
+           (portRef AD2 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_13))
+          ))
+          (net r_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_13))
+           (portRef B0 (instanceRef full_cmp_3))
+           (portRef AD3 (instanceRef LUT4_4))
+           (portRef AD3 (instanceRef LUT4_5))
+           (portRef AD3 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_7))
+          ))
+          (net r_gcount_w25 (joined
+           (portRef Q (instanceRef FF_6))
+           (portRef AD1 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_8))
+           (portRef AD3 (instanceRef LUT4_9))
+           (portRef AD0 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w24 (joined
+           (portRef Q (instanceRef FF_7))
+           (portRef AD2 (instanceRef LUT4_7))
+           (portRef AD3 (instanceRef LUT4_8))
+           (portRef AD1 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w23 (joined
+           (portRef Q (instanceRef FF_8))
+           (portRef AD3 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w22 (joined
+           (portRef Q (instanceRef FF_9))
+           (portRef AD3 (instanceRef LUT4_12))
+          ))
+          (net r_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_12))
+           (portRef AD2 (instanceRef LUT4_4))
+           (portRef AD2 (instanceRef LUT4_5))
+           (portRef AD2 (instanceRef LUT4_6))
+          ))
+          (net rcount_w8 (joined
+           (portRef DO0 (instanceRef LUT4_11))
+           (portRef B0 (instanceRef full_cmp_4))
+           (portRef AD0 (instanceRef LUT4_9))
+          ))
+          (net rcount_w7 (joined
+           (portRef DO0 (instanceRef LUT4_10))
+           (portRef B1 (instanceRef full_cmp_3))
+           (portRef AD0 (instanceRef LUT4_8))
+          ))
+          (net rcount_w5 (joined
+           (portRef DO0 (instanceRef LUT4_9))
+           (portRef B1 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w4 (joined
+           (portRef DO0 (instanceRef LUT4_8))
+           (portRef B0 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w3 (joined
+           (portRef DO0 (instanceRef LUT4_7))
+           (portRef B1 (instanceRef full_cmp_1))
+          ))
+          (net rcount_w2 (joined
+           (portRef DO0 (instanceRef LUT4_6))
+           (portRef B0 (instanceRef full_cmp_1))
+          ))
+          (net r_gcount_w21 (joined
+           (portRef Q (instanceRef FF_10))
+           (portRef AD0 (instanceRef LUT4_4))
+           (portRef AD1 (instanceRef LUT4_5))
+          ))
+          (net rcount_w1 (joined
+           (portRef DO0 (instanceRef LUT4_5))
+           (portRef B1 (instanceRef full_cmp_0))
+          ))
+          (net r_gcount_w20 (joined
+           (portRef Q (instanceRef FF_11))
+           (portRef AD1 (instanceRef LUT4_4))
+          ))
+          (net rcount_w0 (joined
+           (portRef DO0 (instanceRef LUT4_4))
+           (portRef B0 (instanceRef full_cmp_0))
+          ))
+          (net rptr_9 (joined
+           (portRef Q (instanceRef FF_42))
+           (portRef AD3 (instanceRef LUT4_2))
+           (portRef AD3 (instanceRef LUT4_3))
+          ))
+          (net empty_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_3))
+           (portRef A1 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_2))
+           (portRef B1 (instanceRef empty_cmp_4))
+          ))
+          (net wptr_9 (joined
+           (portRef Q (instanceRef FF_72))
+           (portRef AD3 (instanceRef LUT4_0))
+           (portRef AD3 (instanceRef LUT4_1))
+          ))
+          (net full_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_1))
+           (portRef A1 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_0))
+           (portRef B1 (instanceRef full_cmp_4))
+          ))
+          (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined
+           (portRef fifo_in_data_0)
+           (portRef DI27 (instanceRef pdp_ram_0_0_0))
+           (portRef DI26 (instanceRef pdp_ram_0_0_0))
+           (portRef DI24 (instanceRef pdp_ram_0_0_0))
+           (portRef DI15 (instanceRef pdp_ram_0_0_0))
+           (portRef DI13 (instanceRef pdp_ram_0_0_0))
+           (portRef DI12 (instanceRef pdp_ram_0_0_0))
+           (portRef DI11 (instanceRef pdp_ram_0_0_0))
+           (portRef DI9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_0 (joined
+           (portRef Q (instanceRef FF_81))
+           (portRef ADW0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_1 (joined
+           (portRef Q (instanceRef FF_80))
+           (portRef ADW1 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_2 (joined
+           (portRef Q (instanceRef FF_79))
+           (portRef ADW2 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_3 (joined
+           (portRef Q (instanceRef FF_78))
+           (portRef ADW3 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_4 (joined
+           (portRef Q (instanceRef FF_77))
+           (portRef ADW4 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_5 (joined
+           (portRef Q (instanceRef FF_76))
+           (portRef ADW5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_6 (joined
+           (portRef Q (instanceRef FF_75))
+           (portRef ADW6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_7 (joined
+           (portRef Q (instanceRef FF_74))
+           (portRef ADW7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_8 (joined
+           (portRef Q (instanceRef FF_73))
+           (portRef ADW8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef a1))
+           (portRef C1 (instanceRef a1))
+           (portRef D0 (instanceRef a1))
+           (portRef C0 (instanceRef a1))
+           (portRef D1 (instanceRef full_cmp_4))
+           (portRef C1 (instanceRef full_cmp_4))
+           (portRef D0 (instanceRef full_cmp_4))
+           (portRef C0 (instanceRef full_cmp_4))
+           (portRef D1 (instanceRef full_cmp_3))
+           (portRef C1 (instanceRef full_cmp_3))
+           (portRef D0 (instanceRef full_cmp_3))
+           (portRef C0 (instanceRef full_cmp_3))
+           (portRef D1 (instanceRef full_cmp_2))
+           (portRef C1 (instanceRef full_cmp_2))
+           (portRef D0 (instanceRef full_cmp_2))
+           (portRef C0 (instanceRef full_cmp_2))
+           (portRef D1 (instanceRef full_cmp_1))
+           (portRef C1 (instanceRef full_cmp_1))
+           (portRef D0 (instanceRef full_cmp_1))
+           (portRef C0 (instanceRef full_cmp_1))
+           (portRef D1 (instanceRef full_cmp_0))
+           (portRef C1 (instanceRef full_cmp_0))
+           (portRef D0 (instanceRef full_cmp_0))
+           (portRef C0 (instanceRef full_cmp_0))
+           (portRef D1 (instanceRef full_cmp_ci_a))
+           (portRef C1 (instanceRef full_cmp_ci_a))
+           (portRef D0 (instanceRef full_cmp_ci_a))
+           (portRef C0 (instanceRef full_cmp_ci_a))
+           (portRef D1 (instanceRef a0))
+           (portRef C1 (instanceRef a0))
+           (portRef D0 (instanceRef a0))
+           (portRef C0 (instanceRef a0))
+           (portRef D1 (instanceRef empty_cmp_4))
+           (portRef C1 (instanceRef empty_cmp_4))
+           (portRef D0 (instanceRef empty_cmp_4))
+           (portRef C0 (instanceRef empty_cmp_4))
+           (portRef D1 (instanceRef empty_cmp_3))
+           (portRef C1 (instanceRef empty_cmp_3))
+           (portRef D0 (instanceRef empty_cmp_3))
+           (portRef C0 (instanceRef empty_cmp_3))
+           (portRef D1 (instanceRef empty_cmp_2))
+           (portRef C1 (instanceRef empty_cmp_2))
+           (portRef D0 (instanceRef empty_cmp_2))
+           (portRef C0 (instanceRef empty_cmp_2))
+           (portRef D1 (instanceRef empty_cmp_1))
+           (portRef C1 (instanceRef empty_cmp_1))
+           (portRef D0 (instanceRef empty_cmp_1))
+           (portRef C0 (instanceRef empty_cmp_1))
+           (portRef D1 (instanceRef empty_cmp_0))
+           (portRef C1 (instanceRef empty_cmp_0))
+           (portRef D0 (instanceRef empty_cmp_0))
+           (portRef C0 (instanceRef empty_cmp_0))
+           (portRef D1 (instanceRef empty_cmp_ci_a))
+           (portRef C1 (instanceRef empty_cmp_ci_a))
+           (portRef D0 (instanceRef empty_cmp_ci_a))
+           (portRef C0 (instanceRef empty_cmp_ci_a))
+           (portRef D1 (instanceRef r_gctr_4))
+           (portRef C1 (instanceRef r_gctr_4))
+           (portRef D0 (instanceRef r_gctr_4))
+           (portRef C0 (instanceRef r_gctr_4))
+           (portRef D1 (instanceRef r_gctr_3))
+           (portRef C1 (instanceRef r_gctr_3))
+           (portRef D0 (instanceRef r_gctr_3))
+           (portRef C0 (instanceRef r_gctr_3))
+           (portRef D1 (instanceRef r_gctr_2))
+           (portRef C1 (instanceRef r_gctr_2))
+           (portRef D0 (instanceRef r_gctr_2))
+           (portRef C0 (instanceRef r_gctr_2))
+           (portRef D1 (instanceRef r_gctr_1))
+           (portRef C1 (instanceRef r_gctr_1))
+           (portRef D0 (instanceRef r_gctr_1))
+           (portRef C0 (instanceRef r_gctr_1))
+           (portRef D1 (instanceRef r_gctr_0))
+           (portRef C1 (instanceRef r_gctr_0))
+           (portRef D0 (instanceRef r_gctr_0))
+           (portRef C0 (instanceRef r_gctr_0))
+           (portRef D1 (instanceRef r_gctr_cia))
+           (portRef C1 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef r_gctr_cia))
+           (portRef A1 (instanceRef r_gctr_cia))
+           (portRef D0 (instanceRef r_gctr_cia))
+           (portRef C0 (instanceRef r_gctr_cia))
+           (portRef D1 (instanceRef w_gctr_4))
+           (portRef C1 (instanceRef w_gctr_4))
+           (portRef D0 (instanceRef w_gctr_4))
+           (portRef C0 (instanceRef w_gctr_4))
+           (portRef D1 (instanceRef w_gctr_3))
+           (portRef C1 (instanceRef w_gctr_3))
+           (portRef D0 (instanceRef w_gctr_3))
+           (portRef C0 (instanceRef w_gctr_3))
+           (portRef D1 (instanceRef w_gctr_2))
+           (portRef C1 (instanceRef w_gctr_2))
+           (portRef D0 (instanceRef w_gctr_2))
+           (portRef C0 (instanceRef w_gctr_2))
+           (portRef D1 (instanceRef w_gctr_1))
+           (portRef C1 (instanceRef w_gctr_1))
+           (portRef D0 (instanceRef w_gctr_1))
+           (portRef C0 (instanceRef w_gctr_1))
+           (portRef D1 (instanceRef w_gctr_0))
+           (portRef C1 (instanceRef w_gctr_0))
+           (portRef D0 (instanceRef w_gctr_0))
+           (portRef C0 (instanceRef w_gctr_0))
+           (portRef D1 (instanceRef w_gctr_cia))
+           (portRef C1 (instanceRef w_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_cia))
+           (portRef A1 (instanceRef w_gctr_cia))
+           (portRef D0 (instanceRef w_gctr_cia))
+           (portRef C0 (instanceRef w_gctr_cia))
+           (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+           (portRef BE3 (instanceRef pdp_ram_0_0_0))
+           (portRef BE2 (instanceRef pdp_ram_0_0_0))
+           (portRef BE1 (instanceRef pdp_ram_0_0_0))
+           (portRef BE0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef CK (instanceRef FF_0))
+           (portRef CK (instanceRef FF_1))
+           (portRef CK (instanceRef FF_2))
+           (portRef CK (instanceRef FF_3))
+           (portRef CK (instanceRef FF_4))
+           (portRef CK (instanceRef FF_5))
+           (portRef CK (instanceRef FF_6))
+           (portRef CK (instanceRef FF_7))
+           (portRef CK (instanceRef FF_8))
+           (portRef CK (instanceRef FF_9))
+           (portRef CK (instanceRef FF_10))
+           (portRef CK (instanceRef FF_11))
+           (portRef CK (instanceRef FF_12))
+           (portRef CK (instanceRef FF_13))
+           (portRef CK (instanceRef FF_14))
+           (portRef CK (instanceRef FF_15))
+           (portRef CK (instanceRef FF_16))
+           (portRef CK (instanceRef FF_17))
+           (portRef CK (instanceRef FF_18))
+           (portRef CK (instanceRef FF_19))
+           (portRef CK (instanceRef FF_20))
+           (portRef CK (instanceRef FF_21))
+           (portRef CK (instanceRef FF_22))
+           (portRef CK (instanceRef FF_23))
+           (portRef CK (instanceRef FF_24))
+           (portRef CK (instanceRef FF_25))
+           (portRef CK (instanceRef FF_26))
+           (portRef CK (instanceRef FF_27))
+           (portRef CK (instanceRef FF_28))
+           (portRef CK (instanceRef FF_29))
+           (portRef CK (instanceRef FF_30))
+           (portRef CK (instanceRef FF_31))
+           (portRef CK (instanceRef FF_32))
+           (portRef CK (instanceRef FF_33))
+           (portRef CK (instanceRef FF_34))
+           (portRef CK (instanceRef FF_35))
+           (portRef CK (instanceRef FF_36))
+           (portRef CK (instanceRef FF_37))
+           (portRef CK (instanceRef FF_38))
+           (portRef CK (instanceRef FF_39))
+           (portRef CK (instanceRef FF_40))
+           (portRef CK (instanceRef FF_41))
+           (portRef CK (instanceRef FF_42))
+           (portRef CK (instanceRef FF_43))
+           (portRef CK (instanceRef FF_44))
+           (portRef CK (instanceRef FF_45))
+           (portRef CK (instanceRef FF_46))
+           (portRef CK (instanceRef FF_47))
+           (portRef CK (instanceRef FF_48))
+           (portRef CK (instanceRef FF_49))
+           (portRef CK (instanceRef FF_50))
+           (portRef CK (instanceRef FF_51))
+           (portRef CK (instanceRef FF_52))
+           (portRef CK (instanceRef FF_53))
+           (portRef CK (instanceRef FF_54))
+           (portRef CK (instanceRef FF_55))
+           (portRef CK (instanceRef FF_56))
+           (portRef CK (instanceRef FF_57))
+           (portRef CK (instanceRef FF_58))
+           (portRef CK (instanceRef FF_59))
+           (portRef CK (instanceRef FF_60))
+           (portRef CK (instanceRef FF_61))
+           (portRef CK (instanceRef FF_62))
+           (portRef CK (instanceRef FF_63))
+           (portRef CK (instanceRef FF_64))
+           (portRef CK (instanceRef FF_65))
+           (portRef CK (instanceRef FF_66))
+           (portRef CK (instanceRef FF_67))
+           (portRef CK (instanceRef FF_68))
+           (portRef CK (instanceRef FF_69))
+           (portRef CK (instanceRef FF_70))
+           (portRef CK (instanceRef FF_71))
+           (portRef CK (instanceRef FF_72))
+           (portRef CK (instanceRef FF_73))
+           (portRef CK (instanceRef FF_74))
+           (portRef CK (instanceRef FF_75))
+           (portRef CK (instanceRef FF_76))
+           (portRef CK (instanceRef FF_77))
+           (portRef CK (instanceRef FF_78))
+           (portRef CK (instanceRef FF_79))
+           (portRef CK (instanceRef FF_80))
+           (portRef CK (instanceRef FF_81))
+           (portRef CK (instanceRef FF_82))
+           (portRef CK (instanceRef FF_83))
+           (portRef CK (instanceRef FF_84))
+           (portRef CK (instanceRef FF_85))
+           (portRef CK (instanceRef FF_86))
+           (portRef CK (instanceRef FF_87))
+           (portRef CK (instanceRef FF_88))
+           (portRef CK (instanceRef FF_89))
+           (portRef CK (instanceRef FF_90))
+           (portRef CK (instanceRef FF_91))
+           (portRef CK (instanceRef FF_92))
+           (portRef CK (instanceRef FF_93))
+           (portRef CK (instanceRef FF_94))
+           (portRef CK (instanceRef FF_95))
+           (portRef CK (instanceRef FF_96))
+           (portRef CK (instanceRef FF_97))
+           (portRef CK (instanceRef FF_98))
+           (portRef CK (instanceRef FF_99))
+           (portRef CK (instanceRef FF_100))
+           (portRef CK (instanceRef FF_101))
+           (portRef CLKR (instanceRef pdp_ram_0_0_0))
+           (portRef CLKW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_0 (joined
+           (portRef Q (instanceRef FF_51))
+           (portRef ADR5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_1 (joined
+           (portRef Q (instanceRef FF_50))
+           (portRef ADR6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_2 (joined
+           (portRef Q (instanceRef FF_49))
+           (portRef ADR7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_3 (joined
+           (portRef Q (instanceRef FF_48))
+           (portRef ADR8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_4 (joined
+           (portRef Q (instanceRef FF_47))
+           (portRef ADR9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_5 (joined
+           (portRef Q (instanceRef FF_46))
+           (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_6 (joined
+           (portRef Q (instanceRef FF_45))
+           (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_7 (joined
+           (portRef Q (instanceRef FF_44))
+           (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_8 (joined
+           (portRef Q (instanceRef FF_43))
+           (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef DO0 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef DO1 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef DO2 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef DO3 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef DO4 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef DO5 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename Q_1_24 "Q_1[24]") (joined
+           (portRef DO6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_25 "Q_1[25]") (joined
+           (portRef DO7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_26 "Q_1[26]") (joined
+           (portRef DO8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_27 "Q_1[27]") (joined
+           (portRef DO9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_28 "Q_1[28]") (joined
+           (portRef DO10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_29 "Q_1[29]") (joined
+           (portRef DO11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_30 "Q_1[30]") (joined
+           (portRef DO12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_31 "Q_1[31]") (joined
+           (portRef DO13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO14_0 (joined
+           (portRef DO14 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO15_0 (joined
+           (portRef DO15 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO16_0 (joined
+           (portRef DO16 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO17_0 (joined
+           (portRef DO17 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef DO18 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef DO19 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef DO20 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef DO21 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef DO22 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef DO23 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef DO24 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef DO25 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef DO26 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef DO27 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef DO28 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef DO29 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef DO30 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef DO31 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef DO32 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef DO33 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef DO34 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef DO35 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net iwcount_0 (joined
+           (portRef S0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_101))
+          ))
+          (net iwcount_1 (joined
+           (portRef S1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_100))
+          ))
+          (net iwcount_2 (joined
+           (portRef S0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_99))
+          ))
+          (net iwcount_3 (joined
+           (portRef S1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_98))
+          ))
+          (net iwcount_4 (joined
+           (portRef S0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_97))
+          ))
+          (net iwcount_5 (joined
+           (portRef S1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_96))
+          ))
+          (net iwcount_6 (joined
+           (portRef S0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_95))
+          ))
+          (net iwcount_7 (joined
+           (portRef S1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_94))
+          ))
+          (net iwcount_8 (joined
+           (portRef S0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_93))
+          ))
+          (net iwcount_9 (joined
+           (portRef S1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_92))
+          ))
+          (net w_gcount_0 (joined
+           (portRef Q (instanceRef FF_91))
+           (portRef D (instanceRef FF_41))
+          ))
+          (net w_gcount_1 (joined
+           (portRef Q (instanceRef FF_90))
+           (portRef D (instanceRef FF_40))
+          ))
+          (net w_gcount_2 (joined
+           (portRef Q (instanceRef FF_89))
+           (portRef D (instanceRef FF_39))
+          ))
+          (net w_gcount_3 (joined
+           (portRef Q (instanceRef FF_88))
+           (portRef D (instanceRef FF_38))
+          ))
+          (net w_gcount_4 (joined
+           (portRef Q (instanceRef FF_87))
+           (portRef D (instanceRef FF_37))
+          ))
+          (net w_gcount_5 (joined
+           (portRef Q (instanceRef FF_86))
+           (portRef D (instanceRef FF_36))
+          ))
+          (net w_gcount_6 (joined
+           (portRef Q (instanceRef FF_85))
+           (portRef D (instanceRef FF_35))
+          ))
+          (net w_gcount_7 (joined
+           (portRef Q (instanceRef FF_84))
+           (portRef D (instanceRef FF_34))
+          ))
+          (net w_gcount_8 (joined
+           (portRef Q (instanceRef FF_83))
+           (portRef D (instanceRef FF_33))
+          ))
+          (net w_gcount_9 (joined
+           (portRef Q (instanceRef FF_82))
+           (portRef D (instanceRef FF_32))
+          ))
+          (net ircount_0 (joined
+           (portRef S0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_71))
+          ))
+          (net ircount_1 (joined
+           (portRef S1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_70))
+          ))
+          (net ircount_2 (joined
+           (portRef S0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_69))
+          ))
+          (net ircount_3 (joined
+           (portRef S1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_68))
+          ))
+          (net ircount_4 (joined
+           (portRef S0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_67))
+          ))
+          (net ircount_5 (joined
+           (portRef S1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_66))
+          ))
+          (net ircount_6 (joined
+           (portRef S0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_65))
+          ))
+          (net ircount_7 (joined
+           (portRef S1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_64))
+          ))
+          (net ircount_8 (joined
+           (portRef S0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_63))
+          ))
+          (net ircount_9 (joined
+           (portRef S1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_62))
+          ))
+          (net r_gcount_0 (joined
+           (portRef Q (instanceRef FF_61))
+           (portRef D (instanceRef FF_31))
+          ))
+          (net r_gcount_1 (joined
+           (portRef Q (instanceRef FF_60))
+           (portRef D (instanceRef FF_30))
+          ))
+          (net r_gcount_2 (joined
+           (portRef Q (instanceRef FF_59))
+           (portRef D (instanceRef FF_29))
+          ))
+          (net r_gcount_3 (joined
+           (portRef Q (instanceRef FF_58))
+           (portRef D (instanceRef FF_28))
+          ))
+          (net r_gcount_4 (joined
+           (portRef Q (instanceRef FF_57))
+           (portRef D (instanceRef FF_27))
+          ))
+          (net r_gcount_5 (joined
+           (portRef Q (instanceRef FF_56))
+           (portRef D (instanceRef FF_26))
+          ))
+          (net r_gcount_6 (joined
+           (portRef Q (instanceRef FF_55))
+           (portRef D (instanceRef FF_25))
+          ))
+          (net r_gcount_7 (joined
+           (portRef Q (instanceRef FF_54))
+           (portRef D (instanceRef FF_24))
+          ))
+          (net r_gcount_8 (joined
+           (portRef Q (instanceRef FF_53))
+           (portRef D (instanceRef FF_23))
+          ))
+          (net r_gcount_9 (joined
+           (portRef Q (instanceRef FF_52))
+           (portRef D (instanceRef FF_22))
+          ))
+          (net w_gcount_r0 (joined
+           (portRef Q (instanceRef FF_41))
+           (portRef D (instanceRef FF_21))
+          ))
+          (net w_gcount_r1 (joined
+           (portRef Q (instanceRef FF_40))
+           (portRef D (instanceRef FF_20))
+          ))
+          (net w_gcount_r2 (joined
+           (portRef Q (instanceRef FF_39))
+           (portRef D (instanceRef FF_19))
+          ))
+          (net w_gcount_r3 (joined
+           (portRef Q (instanceRef FF_38))
+           (portRef D (instanceRef FF_18))
+          ))
+          (net w_gcount_r4 (joined
+           (portRef Q (instanceRef FF_37))
+           (portRef D (instanceRef FF_17))
+          ))
+          (net w_gcount_r5 (joined
+           (portRef Q (instanceRef FF_36))
+           (portRef D (instanceRef FF_16))
+          ))
+          (net w_gcount_r6 (joined
+           (portRef Q (instanceRef FF_35))
+           (portRef D (instanceRef FF_15))
+          ))
+          (net w_gcount_r7 (joined
+           (portRef Q (instanceRef FF_34))
+           (portRef D (instanceRef FF_14))
+          ))
+          (net w_gcount_r8 (joined
+           (portRef Q (instanceRef FF_33))
+           (portRef D (instanceRef FF_13))
+          ))
+          (net w_gcount_r9 (joined
+           (portRef Q (instanceRef FF_32))
+           (portRef D (instanceRef FF_12))
+          ))
+          (net r_gcount_w0 (joined
+           (portRef Q (instanceRef FF_31))
+           (portRef D (instanceRef FF_11))
+          ))
+          (net r_gcount_w1 (joined
+           (portRef Q (instanceRef FF_30))
+           (portRef D (instanceRef FF_10))
+          ))
+          (net r_gcount_w2 (joined
+           (portRef Q (instanceRef FF_29))
+           (portRef D (instanceRef FF_9))
+          ))
+          (net r_gcount_w3 (joined
+           (portRef Q (instanceRef FF_28))
+           (portRef D (instanceRef FF_8))
+          ))
+          (net r_gcount_w4 (joined
+           (portRef Q (instanceRef FF_27))
+           (portRef D (instanceRef FF_7))
+          ))
+          (net r_gcount_w5 (joined
+           (portRef Q (instanceRef FF_26))
+           (portRef D (instanceRef FF_6))
+          ))
+          (net r_gcount_w6 (joined
+           (portRef Q (instanceRef FF_25))
+           (portRef D (instanceRef FF_5))
+          ))
+          (net r_gcount_w7 (joined
+           (portRef Q (instanceRef FF_24))
+           (portRef D (instanceRef FF_4))
+          ))
+          (net r_gcount_w8 (joined
+           (portRef Q (instanceRef FF_23))
+           (portRef D (instanceRef FF_3))
+          ))
+          (net r_gcount_w9 (joined
+           (portRef Q (instanceRef FF_22))
+           (portRef D (instanceRef FF_2))
+          ))
+          (net empty_d (joined
+           (portRef S0 (instanceRef a0))
+           (portRef D (instanceRef FF_1))
+          ))
+          (net full_d (joined
+           (portRef S0 (instanceRef a1))
+           (portRef D (instanceRef FF_0))
+          ))
+          (net w_gctr_ci (joined
+           (portRef COUT (instanceRef w_gctr_cia))
+           (portRef CIN (instanceRef w_gctr_0))
+          ))
+          (net w_gctr_cia_S0_0 (joined
+           (portRef S0 (instanceRef w_gctr_cia))
+          ))
+          (net w_gctr_cia_S1_0 (joined
+           (portRef S1 (instanceRef w_gctr_cia))
+          ))
+          (net co0 (joined
+           (portRef COUT (instanceRef w_gctr_0))
+           (portRef CIN (instanceRef w_gctr_1))
+          ))
+          (net co1 (joined
+           (portRef COUT (instanceRef w_gctr_1))
+           (portRef CIN (instanceRef w_gctr_2))
+          ))
+          (net co2 (joined
+           (portRef COUT (instanceRef w_gctr_2))
+           (portRef CIN (instanceRef w_gctr_3))
+          ))
+          (net co3 (joined
+           (portRef COUT (instanceRef w_gctr_3))
+           (portRef CIN (instanceRef w_gctr_4))
+          ))
+          (net co4 (joined
+           (portRef COUT (instanceRef w_gctr_4))
+          ))
+          (net r_gctr_ci (joined
+           (portRef COUT (instanceRef r_gctr_cia))
+           (portRef CIN (instanceRef r_gctr_0))
+          ))
+          (net r_gctr_cia_S0_0 (joined
+           (portRef S0 (instanceRef r_gctr_cia))
+          ))
+          (net r_gctr_cia_S1_0 (joined
+           (portRef S1 (instanceRef r_gctr_cia))
+          ))
+          (net co0_1 (joined
+           (portRef COUT (instanceRef r_gctr_0))
+           (portRef CIN (instanceRef r_gctr_1))
+          ))
+          (net co1_1 (joined
+           (portRef COUT (instanceRef r_gctr_1))
+           (portRef CIN (instanceRef r_gctr_2))
+          ))
+          (net co2_1 (joined
+           (portRef COUT (instanceRef r_gctr_2))
+           (portRef CIN (instanceRef r_gctr_3))
+          ))
+          (net co3_1 (joined
+           (portRef COUT (instanceRef r_gctr_3))
+           (portRef CIN (instanceRef r_gctr_4))
+          ))
+          (net co4_1 (joined
+           (portRef COUT (instanceRef r_gctr_4))
+          ))
+          (net cmp_ci (joined
+           (portRef COUT (instanceRef empty_cmp_ci_a))
+           (portRef CIN (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_ci_a_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_ci_a))
+          ))
+          (net empty_cmp_ci_a_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_ci_a))
+          ))
+          (net co0_2 (joined
+           (portRef COUT (instanceRef empty_cmp_0))
+           (portRef CIN (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_0_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_0_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_0))
+          ))
+          (net co1_2 (joined
+           (portRef COUT (instanceRef empty_cmp_1))
+           (portRef CIN (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_1_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_1_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_1))
+          ))
+          (net co2_2 (joined
+           (portRef COUT (instanceRef empty_cmp_2))
+           (portRef CIN (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_2_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_2_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_2))
+          ))
+          (net co3_2 (joined
+           (portRef COUT (instanceRef empty_cmp_3))
+           (portRef CIN (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_3_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_3_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_3))
+          ))
+          (net empty_d_c (joined
+           (portRef COUT (instanceRef empty_cmp_4))
+           (portRef CIN (instanceRef a0))
+          ))
+          (net empty_cmp_4_S0_0 (joined
+           (portRef S0 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_4_S1_0 (joined
+           (portRef S1 (instanceRef empty_cmp_4))
+          ))
+          (net a0_COUT_0 (joined
+           (portRef COUT (instanceRef a0))
+          ))
+          (net a0_S1_0 (joined
+           (portRef S1 (instanceRef a0))
+          ))
+          (net cmp_ci_1 (joined
+           (portRef COUT (instanceRef full_cmp_ci_a))
+           (portRef CIN (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_ci_a_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_ci_a))
+          ))
+          (net full_cmp_ci_a_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_ci_a))
+          ))
+          (net co0_3 (joined
+           (portRef COUT (instanceRef full_cmp_0))
+           (portRef CIN (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_0_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_0_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_0))
+          ))
+          (net co1_3 (joined
+           (portRef COUT (instanceRef full_cmp_1))
+           (portRef CIN (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_1_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_1_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_1))
+          ))
+          (net co2_3 (joined
+           (portRef COUT (instanceRef full_cmp_2))
+           (portRef CIN (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_2_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_2_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_2))
+          ))
+          (net co3_3 (joined
+           (portRef COUT (instanceRef full_cmp_3))
+           (portRef CIN (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_3_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_3_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_3))
+          ))
+          (net full_d_c (joined
+           (portRef COUT (instanceRef full_cmp_4))
+           (portRef CIN (instanceRef a1))
+          ))
+          (net full_cmp_4_S0_0 (joined
+           (portRef S0 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_4_S1_0 (joined
+           (portRef S1 (instanceRef full_cmp_4))
+          ))
+          (net a1_COUT_0 (joined
+           (portRef COUT (instanceRef a1))
+          ))
+          (net a1_S1_0 (joined
+           (portRef S1 (instanceRef a1))
+          ))
+          (net CIN (joined
+           (portRef CIN (instanceRef full_cmp_ci_a))
+          ))
+          (net CIN_0 (joined
+           (portRef CIN (instanceRef empty_cmp_ci_a))
+          ))
+          (net CIN_1 (joined
+           (portRef CIN (instanceRef r_gctr_cia))
+          ))
+          (net CIN_2 (joined
+           (portRef CIN (instanceRef w_gctr_cia))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "fifo32dc"))
+       )
+    )
+    (cell output_decoder8_2_0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT))
+           (port decoder_valid (direction OUTPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))"))
+          )
+          (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net N_351_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef valid_internal_RNO_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+          ))
+          (net decoder_valid (joined
+           (portRef Q (instanceRef valid))
+           (portRef decoder_valid)
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef A (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef B (instanceRef un1_out_internal35_1_0_m4_0))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef C (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef valid_internal_RNO_0))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef valid_internal_RNO_0))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef valid_internal_RNO))
+          ))
+          (net N_42 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell tdc4ddr_short_3 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out 4))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out 0))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[1]") (joined
+           (portRef trig_c_i_0)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out 5))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out 1))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out 6))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out 2))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out 7))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out 3))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell fifo32dc (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port fifo_in_data_0 (direction INPUT))
+           (port fifo_read_0 (direction INPUT))
+           (port fifo_empty1_c (direction OUTPUT))
+           (port fifo_wren (direction INPUT))
+         )
+         (contents
+          (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0410"))
+          )
+          (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x1004"))
+          )
+          (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0140"))
+          )
+          (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x4001"))
+          )
+          (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT)))
+           (property MEM_LPC_FILE (string "fifo32dc.lpc"))
+           (property MEM_INIT_FILE (string ""))
+           (property DATA_WIDTH_W (integer 36))
+           (property DATA_WIDTH_R (integer 36))
+           (property REGMODE (string "NOREG"))
+           (property RESETMODE (string "SYNC"))
+           (property GSR (string "ENABLED"))
+           (property CSDECODE_W (string "0b001"))
+           (property CSDECODE_R (string "0b000"))
+           (property ASYNC_RESET_RELEASE (string "SYNC"))
+           (property INIT_DATA (string "STATIC"))
+          )
+          (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net fifo_wren (joined
+           (portRef fifo_wren)
+           (portRef A (instanceRef AND2_t20))
+          ))
+          (net invout_1 (joined
+           (portRef Z (instanceRef INV_1))
+           (portRef B (instanceRef AND2_t20))
+          ))
+          (net wren_i (joined
+           (portRef Z (instanceRef AND2_t20))
+           (portRef B1 (instanceRef full_cmp_ci_a))
+           (portRef A1 (instanceRef full_cmp_ci_a))
+           (portRef SP (instanceRef FF_72))
+           (portRef SP (instanceRef FF_73))
+           (portRef SP (instanceRef FF_74))
+           (portRef SP (instanceRef FF_75))
+           (portRef SP (instanceRef FF_76))
+           (portRef SP (instanceRef FF_77))
+           (portRef SP (instanceRef FF_78))
+           (portRef SP (instanceRef FF_79))
+           (portRef SP (instanceRef FF_80))
+           (portRef SP (instanceRef FF_81))
+           (portRef SP (instanceRef FF_82))
+           (portRef SP (instanceRef FF_83))
+           (portRef SP (instanceRef FF_84))
+           (portRef SP (instanceRef FF_85))
+           (portRef SP (instanceRef FF_86))
+           (portRef SP (instanceRef FF_87))
+           (portRef SP (instanceRef FF_88))
+           (portRef SP (instanceRef FF_89))
+           (portRef SP (instanceRef FF_90))
+           (portRef SP (instanceRef FF_91))
+           (portRef SP (instanceRef FF_92))
+           (portRef SP (instanceRef FF_93))
+           (portRef SP (instanceRef FF_94))
+           (portRef SP (instanceRef FF_95))
+           (portRef SP (instanceRef FF_96))
+           (portRef SP (instanceRef FF_97))
+           (portRef SP (instanceRef FF_98))
+           (portRef SP (instanceRef FF_99))
+           (portRef SP (instanceRef FF_100))
+           (portRef SP (instanceRef FF_101))
+           (portRef CEW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net Full (joined
+           (portRef Q (instanceRef FF_0))
+           (portRef A (instanceRef INV_1))
+          ))
+          (net (rename fifo_read_0 "fifo_read[0]") (joined
+           (portRef fifo_read_0)
+           (portRef A (instanceRef AND2_t19))
+          ))
+          (net invout_0 (joined
+           (portRef Z (instanceRef INV_0))
+           (portRef B (instanceRef AND2_t19))
+          ))
+          (net rden_i (joined
+           (portRef Z (instanceRef AND2_t19))
+           (portRef B1 (instanceRef empty_cmp_ci_a))
+           (portRef A1 (instanceRef empty_cmp_ci_a))
+           (portRef SP (instanceRef FF_42))
+           (portRef SP (instanceRef FF_43))
+           (portRef SP (instanceRef FF_44))
+           (portRef SP (instanceRef FF_45))
+           (portRef SP (instanceRef FF_46))
+           (portRef SP (instanceRef FF_47))
+           (portRef SP (instanceRef FF_48))
+           (portRef SP (instanceRef FF_49))
+           (portRef SP (instanceRef FF_50))
+           (portRef SP (instanceRef FF_51))
+           (portRef SP (instanceRef FF_52))
+           (portRef SP (instanceRef FF_53))
+           (portRef SP (instanceRef FF_54))
+           (portRef SP (instanceRef FF_55))
+           (portRef SP (instanceRef FF_56))
+           (portRef SP (instanceRef FF_57))
+           (portRef SP (instanceRef FF_58))
+           (portRef SP (instanceRef FF_59))
+           (portRef SP (instanceRef FF_60))
+           (portRef SP (instanceRef FF_61))
+           (portRef SP (instanceRef FF_62))
+           (portRef SP (instanceRef FF_63))
+           (portRef SP (instanceRef FF_64))
+           (portRef SP (instanceRef FF_65))
+           (portRef SP (instanceRef FF_66))
+           (portRef SP (instanceRef FF_67))
+           (portRef SP (instanceRef FF_68))
+           (portRef SP (instanceRef FF_69))
+           (portRef SP (instanceRef FF_70))
+           (portRef SP (instanceRef FF_71))
+           (portRef OCER (instanceRef pdp_ram_0_0_0))
+           (portRef CER (instanceRef pdp_ram_0_0_0))
+          ))
+          (net fifo_empty1_c (joined
+           (portRef Q (instanceRef FF_1))
+           (portRef A (instanceRef INV_0))
+           (portRef fifo_empty1_c)
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef B1 (instanceRef a1))
+           (portRef A1 (instanceRef a1))
+           (portRef B0 (instanceRef a1))
+           (portRef A0 (instanceRef a1))
+           (portRef B0 (instanceRef full_cmp_ci_a))
+           (portRef A0 (instanceRef full_cmp_ci_a))
+           (portRef B1 (instanceRef a0))
+           (portRef A1 (instanceRef a0))
+           (portRef B0 (instanceRef a0))
+           (portRef A0 (instanceRef a0))
+           (portRef B0 (instanceRef empty_cmp_ci_a))
+           (portRef A0 (instanceRef empty_cmp_ci_a))
+           (portRef B1 (instanceRef r_gctr_4))
+           (portRef B0 (instanceRef r_gctr_4))
+           (portRef B1 (instanceRef r_gctr_3))
+           (portRef B0 (instanceRef r_gctr_3))
+           (portRef B1 (instanceRef r_gctr_2))
+           (portRef B0 (instanceRef r_gctr_2))
+           (portRef B1 (instanceRef r_gctr_1))
+           (portRef B0 (instanceRef r_gctr_1))
+           (portRef B1 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_cia))
+           (portRef A0 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_4))
+           (portRef B0 (instanceRef w_gctr_4))
+           (portRef B1 (instanceRef w_gctr_3))
+           (portRef B0 (instanceRef w_gctr_3))
+           (portRef B1 (instanceRef w_gctr_2))
+           (portRef B0 (instanceRef w_gctr_2))
+           (portRef B1 (instanceRef w_gctr_1))
+           (portRef B0 (instanceRef w_gctr_1))
+           (portRef B1 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_cia))
+           (portRef A0 (instanceRef w_gctr_cia))
+           (portRef CD (instanceRef FF_0))
+           (portRef CD (instanceRef FF_12))
+           (portRef CD (instanceRef FF_13))
+           (portRef CD (instanceRef FF_14))
+           (portRef CD (instanceRef FF_15))
+           (portRef CD (instanceRef FF_16))
+           (portRef CD (instanceRef FF_17))
+           (portRef CD (instanceRef FF_18))
+           (portRef CD (instanceRef FF_19))
+           (portRef CD (instanceRef FF_20))
+           (portRef CD (instanceRef FF_21))
+           (portRef CD (instanceRef FF_32))
+           (portRef CD (instanceRef FF_33))
+           (portRef CD (instanceRef FF_34))
+           (portRef CD (instanceRef FF_35))
+           (portRef CD (instanceRef FF_36))
+           (portRef CD (instanceRef FF_37))
+           (portRef CD (instanceRef FF_38))
+           (portRef CD (instanceRef FF_39))
+           (portRef CD (instanceRef FF_40))
+           (portRef CD (instanceRef FF_41))
+           (portRef CD (instanceRef FF_72))
+           (portRef CD (instanceRef FF_73))
+           (portRef CD (instanceRef FF_74))
+           (portRef CD (instanceRef FF_75))
+           (portRef CD (instanceRef FF_76))
+           (portRef CD (instanceRef FF_77))
+           (portRef CD (instanceRef FF_78))
+           (portRef CD (instanceRef FF_79))
+           (portRef CD (instanceRef FF_80))
+           (portRef CD (instanceRef FF_81))
+           (portRef CD (instanceRef FF_82))
+           (portRef CD (instanceRef FF_83))
+           (portRef CD (instanceRef FF_84))
+           (portRef CD (instanceRef FF_85))
+           (portRef CD (instanceRef FF_86))
+           (portRef CD (instanceRef FF_87))
+           (portRef CD (instanceRef FF_88))
+           (portRef CD (instanceRef FF_89))
+           (portRef CD (instanceRef FF_90))
+           (portRef CD (instanceRef FF_91))
+           (portRef CD (instanceRef FF_92))
+           (portRef CD (instanceRef FF_93))
+           (portRef CD (instanceRef FF_94))
+           (portRef CD (instanceRef FF_95))
+           (portRef CD (instanceRef FF_96))
+           (portRef CD (instanceRef FF_97))
+           (portRef CD (instanceRef FF_98))
+           (portRef CD (instanceRef FF_99))
+           (portRef CD (instanceRef FF_100))
+           (portRef PD (instanceRef FF_101))
+           (portRef RST (instanceRef pdp_ram_0_0_0))
+           (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+           (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+           (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+           (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI35 (instanceRef pdp_ram_0_0_0))
+           (portRef DI34 (instanceRef pdp_ram_0_0_0))
+           (portRef DI33 (instanceRef pdp_ram_0_0_0))
+           (portRef DI32 (instanceRef pdp_ram_0_0_0))
+           (portRef DI31 (instanceRef pdp_ram_0_0_0))
+           (portRef DI30 (instanceRef pdp_ram_0_0_0))
+           (portRef DI29 (instanceRef pdp_ram_0_0_0))
+           (portRef DI28 (instanceRef pdp_ram_0_0_0))
+           (portRef DI25 (instanceRef pdp_ram_0_0_0))
+           (portRef DI23 (instanceRef pdp_ram_0_0_0))
+           (portRef DI22 (instanceRef pdp_ram_0_0_0))
+           (portRef DI21 (instanceRef pdp_ram_0_0_0))
+           (portRef DI20 (instanceRef pdp_ram_0_0_0))
+           (portRef DI19 (instanceRef pdp_ram_0_0_0))
+           (portRef DI18 (instanceRef pdp_ram_0_0_0))
+           (portRef DI17 (instanceRef pdp_ram_0_0_0))
+           (portRef DI16 (instanceRef pdp_ram_0_0_0))
+           (portRef DI14 (instanceRef pdp_ram_0_0_0))
+           (portRef DI10 (instanceRef pdp_ram_0_0_0))
+           (portRef DI8 (instanceRef pdp_ram_0_0_0))
+           (portRef DI7 (instanceRef pdp_ram_0_0_0))
+           (portRef DI6 (instanceRef pdp_ram_0_0_0))
+           (portRef DI5 (instanceRef pdp_ram_0_0_0))
+           (portRef DI4 (instanceRef pdp_ram_0_0_0))
+           (portRef DI3 (instanceRef pdp_ram_0_0_0))
+           (portRef DI2 (instanceRef pdp_ram_0_0_0))
+           (portRef DI1 (instanceRef pdp_ram_0_0_0))
+           (portRef DI0 (instanceRef pdp_ram_0_0_0))
+           (portRef AD0 (instanceRef LUT4_0))
+           (portRef AD0 (instanceRef LUT4_1))
+           (portRef AD0 (instanceRef LUT4_2))
+           (portRef AD0 (instanceRef LUT4_3))
+           (portRef AD0 (instanceRef LUT4_5))
+           (portRef AD1 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_10))
+           (portRef AD1 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_15))
+           (portRef AD1 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_20))
+           (portRef AD1 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_21))
+           (portRef B (instanceRef OR2_t18))
+           (portRef A (instanceRef OR2_t18))
+          ))
+          (net rRst (joined
+           (portRef Z (instanceRef OR2_t18))
+           (portRef PD (instanceRef FF_1))
+           (portRef CD (instanceRef FF_2))
+           (portRef CD (instanceRef FF_3))
+           (portRef CD (instanceRef FF_4))
+           (portRef CD (instanceRef FF_5))
+           (portRef CD (instanceRef FF_6))
+           (portRef CD (instanceRef FF_7))
+           (portRef CD (instanceRef FF_8))
+           (portRef CD (instanceRef FF_9))
+           (portRef CD (instanceRef FF_10))
+           (portRef CD (instanceRef FF_11))
+           (portRef CD (instanceRef FF_22))
+           (portRef CD (instanceRef FF_23))
+           (portRef CD (instanceRef FF_24))
+           (portRef CD (instanceRef FF_25))
+           (portRef CD (instanceRef FF_26))
+           (portRef CD (instanceRef FF_27))
+           (portRef CD (instanceRef FF_28))
+           (portRef CD (instanceRef FF_29))
+           (portRef CD (instanceRef FF_30))
+           (portRef CD (instanceRef FF_31))
+           (portRef CD (instanceRef FF_42))
+           (portRef CD (instanceRef FF_43))
+           (portRef CD (instanceRef FF_44))
+           (portRef CD (instanceRef FF_45))
+           (portRef CD (instanceRef FF_46))
+           (portRef CD (instanceRef FF_47))
+           (portRef CD (instanceRef FF_48))
+           (portRef CD (instanceRef FF_49))
+           (portRef CD (instanceRef FF_50))
+           (portRef CD (instanceRef FF_51))
+           (portRef CD (instanceRef FF_52))
+           (portRef CD (instanceRef FF_53))
+           (portRef CD (instanceRef FF_54))
+           (portRef CD (instanceRef FF_55))
+           (portRef CD (instanceRef FF_56))
+           (portRef CD (instanceRef FF_57))
+           (portRef CD (instanceRef FF_58))
+           (portRef CD (instanceRef FF_59))
+           (portRef CD (instanceRef FF_60))
+           (portRef CD (instanceRef FF_61))
+           (portRef CD (instanceRef FF_62))
+           (portRef CD (instanceRef FF_63))
+           (portRef CD (instanceRef FF_64))
+           (portRef CD (instanceRef FF_65))
+           (portRef CD (instanceRef FF_66))
+           (portRef CD (instanceRef FF_67))
+           (portRef CD (instanceRef FF_68))
+           (portRef CD (instanceRef FF_69))
+           (portRef CD (instanceRef FF_70))
+           (portRef PD (instanceRef FF_71))
+          ))
+          (net wcount_0 (joined
+           (portRef Q (instanceRef FF_101))
+           (portRef A0 (instanceRef full_cmp_0))
+           (portRef A0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_81))
+           (portRef A (instanceRef XOR2_t17))
+          ))
+          (net wcount_1 (joined
+           (portRef Q (instanceRef FF_100))
+           (portRef A1 (instanceRef full_cmp_0))
+           (portRef A1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_80))
+           (portRef A (instanceRef XOR2_t16))
+           (portRef B (instanceRef XOR2_t17))
+          ))
+          (net w_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t17))
+           (portRef D (instanceRef FF_91))
+          ))
+          (net wcount_2 (joined
+           (portRef Q (instanceRef FF_99))
+           (portRef A0 (instanceRef full_cmp_1))
+           (portRef A0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_79))
+           (portRef A (instanceRef XOR2_t15))
+           (portRef B (instanceRef XOR2_t16))
+          ))
+          (net w_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t16))
+           (portRef D (instanceRef FF_90))
+          ))
+          (net wcount_3 (joined
+           (portRef Q (instanceRef FF_98))
+           (portRef A1 (instanceRef full_cmp_1))
+           (portRef A1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_78))
+           (portRef A (instanceRef XOR2_t14))
+           (portRef B (instanceRef XOR2_t15))
+          ))
+          (net w_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t15))
+           (portRef D (instanceRef FF_89))
+          ))
+          (net wcount_4 (joined
+           (portRef Q (instanceRef FF_97))
+           (portRef A0 (instanceRef full_cmp_2))
+           (portRef A0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_77))
+           (portRef A (instanceRef XOR2_t13))
+           (portRef B (instanceRef XOR2_t14))
+          ))
+          (net w_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t14))
+           (portRef D (instanceRef FF_88))
+          ))
+          (net wcount_5 (joined
+           (portRef Q (instanceRef FF_96))
+           (portRef A1 (instanceRef full_cmp_2))
+           (portRef A1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_76))
+           (portRef A (instanceRef XOR2_t12))
+           (portRef B (instanceRef XOR2_t13))
+          ))
+          (net w_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t13))
+           (portRef D (instanceRef FF_87))
+          ))
+          (net wcount_6 (joined
+           (portRef Q (instanceRef FF_95))
+           (portRef A0 (instanceRef full_cmp_3))
+           (portRef A0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_75))
+           (portRef A (instanceRef XOR2_t11))
+           (portRef B (instanceRef XOR2_t12))
+          ))
+          (net w_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t12))
+           (portRef D (instanceRef FF_86))
+          ))
+          (net wcount_7 (joined
+           (portRef Q (instanceRef FF_94))
+           (portRef A1 (instanceRef full_cmp_3))
+           (portRef A1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_74))
+           (portRef A (instanceRef XOR2_t10))
+           (portRef B (instanceRef XOR2_t11))
+          ))
+          (net w_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t11))
+           (portRef D (instanceRef FF_85))
+          ))
+          (net wcount_8 (joined
+           (portRef Q (instanceRef FF_93))
+           (portRef A0 (instanceRef full_cmp_4))
+           (portRef A0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_73))
+           (portRef A (instanceRef XOR2_t9))
+           (portRef B (instanceRef XOR2_t10))
+          ))
+          (net w_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t10))
+           (portRef D (instanceRef FF_84))
+          ))
+          (net wcount_9 (joined
+           (portRef Q (instanceRef FF_92))
+           (portRef A1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_72))
+           (portRef D (instanceRef FF_82))
+           (portRef AD2 (instanceRef LUT4_0))
+           (portRef AD2 (instanceRef LUT4_1))
+           (portRef B (instanceRef XOR2_t9))
+          ))
+          (net w_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t9))
+           (portRef D (instanceRef FF_83))
+          ))
+          (net rcount_0 (joined
+           (portRef Q (instanceRef FF_71))
+           (portRef A0 (instanceRef empty_cmp_0))
+           (portRef A0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_51))
+           (portRef A (instanceRef XOR2_t8))
+          ))
+          (net rcount_1 (joined
+           (portRef Q (instanceRef FF_70))
+           (portRef A1 (instanceRef empty_cmp_0))
+           (portRef A1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_50))
+           (portRef A (instanceRef XOR2_t7))
+           (portRef B (instanceRef XOR2_t8))
+          ))
+          (net r_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t8))
+           (portRef D (instanceRef FF_61))
+          ))
+          (net rcount_2 (joined
+           (portRef Q (instanceRef FF_69))
+           (portRef A0 (instanceRef empty_cmp_1))
+           (portRef A0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_49))
+           (portRef A (instanceRef XOR2_t6))
+           (portRef B (instanceRef XOR2_t7))
+          ))
+          (net r_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t7))
+           (portRef D (instanceRef FF_60))
+          ))
+          (net rcount_3 (joined
+           (portRef Q (instanceRef FF_68))
+           (portRef A1 (instanceRef empty_cmp_1))
+           (portRef A1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_48))
+           (portRef A (instanceRef XOR2_t5))
+           (portRef B (instanceRef XOR2_t6))
+          ))
+          (net r_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t6))
+           (portRef D (instanceRef FF_59))
+          ))
+          (net rcount_4 (joined
+           (portRef Q (instanceRef FF_67))
+           (portRef A0 (instanceRef empty_cmp_2))
+           (portRef A0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_47))
+           (portRef A (instanceRef XOR2_t4))
+           (portRef B (instanceRef XOR2_t5))
+          ))
+          (net r_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t5))
+           (portRef D (instanceRef FF_58))
+          ))
+          (net rcount_5 (joined
+           (portRef Q (instanceRef FF_66))
+           (portRef A1 (instanceRef empty_cmp_2))
+           (portRef A1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_46))
+           (portRef A (instanceRef XOR2_t3))
+           (portRef B (instanceRef XOR2_t4))
+          ))
+          (net r_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t4))
+           (portRef D (instanceRef FF_57))
+          ))
+          (net rcount_6 (joined
+           (portRef Q (instanceRef FF_65))
+           (portRef A0 (instanceRef empty_cmp_3))
+           (portRef A0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_45))
+           (portRef A (instanceRef XOR2_t2))
+           (portRef B (instanceRef XOR2_t3))
+          ))
+          (net r_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t3))
+           (portRef D (instanceRef FF_56))
+          ))
+          (net rcount_7 (joined
+           (portRef Q (instanceRef FF_64))
+           (portRef A1 (instanceRef empty_cmp_3))
+           (portRef A1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_44))
+           (portRef A (instanceRef XOR2_t1))
+           (portRef B (instanceRef XOR2_t2))
+          ))
+          (net r_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t2))
+           (portRef D (instanceRef FF_55))
+          ))
+          (net rcount_8 (joined
+           (portRef Q (instanceRef FF_63))
+           (portRef A0 (instanceRef empty_cmp_4))
+           (portRef A0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_43))
+           (portRef A (instanceRef XOR2_t0))
+           (portRef B (instanceRef XOR2_t1))
+          ))
+          (net r_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t1))
+           (portRef D (instanceRef FF_54))
+          ))
+          (net rcount_9 (joined
+           (portRef Q (instanceRef FF_62))
+           (portRef A1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_42))
+           (portRef D (instanceRef FF_52))
+           (portRef AD2 (instanceRef LUT4_2))
+           (portRef AD2 (instanceRef LUT4_3))
+           (portRef B (instanceRef XOR2_t0))
+          ))
+          (net r_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t0))
+           (portRef D (instanceRef FF_53))
+          ))
+          (net w_gcount_r29 (joined
+           (portRef Q (instanceRef FF_12))
+           (portRef AD1 (instanceRef LUT4_2))
+           (portRef AD1 (instanceRef LUT4_3))
+           (portRef AD1 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r28 (joined
+           (portRef Q (instanceRef FF_13))
+           (portRef AD2 (instanceRef LUT4_20))
+           (portRef AD3 (instanceRef LUT4_21))
+           (portRef AD1 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r27 (joined
+           (portRef Q (instanceRef FF_14))
+           (portRef AD1 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r26 (joined
+           (portRef Q (instanceRef FF_15))
+           (portRef AD1 (instanceRef LUT4_18))
+           (portRef AD2 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_23))
+          ))
+          (net w_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_23))
+           (portRef B0 (instanceRef empty_cmp_3))
+           (portRef AD3 (instanceRef LUT4_14))
+           (portRef AD3 (instanceRef LUT4_15))
+           (portRef AD3 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_17))
+          ))
+          (net w_gcount_r25 (joined
+           (portRef Q (instanceRef FF_16))
+           (portRef AD1 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_18))
+           (portRef AD3 (instanceRef LUT4_19))
+           (portRef AD0 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r24 (joined
+           (portRef Q (instanceRef FF_17))
+           (portRef AD2 (instanceRef LUT4_17))
+           (portRef AD3 (instanceRef LUT4_18))
+           (portRef AD1 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r23 (joined
+           (portRef Q (instanceRef FF_18))
+           (portRef AD3 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r22 (joined
+           (portRef Q (instanceRef FF_19))
+           (portRef AD3 (instanceRef LUT4_22))
+          ))
+          (net w_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_22))
+           (portRef AD2 (instanceRef LUT4_14))
+           (portRef AD2 (instanceRef LUT4_15))
+           (portRef AD2 (instanceRef LUT4_16))
+          ))
+          (net wcount_r8 (joined
+           (portRef DO0 (instanceRef LUT4_21))
+           (portRef B0 (instanceRef empty_cmp_4))
+           (portRef AD0 (instanceRef LUT4_19))
+          ))
+          (net wcount_r7 (joined
+           (portRef DO0 (instanceRef LUT4_20))
+           (portRef B1 (instanceRef empty_cmp_3))
+           (portRef AD0 (instanceRef LUT4_18))
+          ))
+          (net wcount_r5 (joined
+           (portRef DO0 (instanceRef LUT4_19))
+           (portRef B1 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r4 (joined
+           (portRef DO0 (instanceRef LUT4_18))
+           (portRef B0 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r3 (joined
+           (portRef DO0 (instanceRef LUT4_17))
+           (portRef B1 (instanceRef empty_cmp_1))
+          ))
+          (net wcount_r2 (joined
+           (portRef DO0 (instanceRef LUT4_16))
+           (portRef B0 (instanceRef empty_cmp_1))
+          ))
+          (net w_gcount_r21 (joined
+           (portRef Q (instanceRef FF_20))
+           (portRef AD0 (instanceRef LUT4_14))
+           (portRef AD1 (instanceRef LUT4_15))
+          ))
+          (net wcount_r1 (joined
+           (portRef DO0 (instanceRef LUT4_15))
+           (portRef B1 (instanceRef empty_cmp_0))
+          ))
+          (net w_gcount_r20 (joined
+           (portRef Q (instanceRef FF_21))
+           (portRef AD1 (instanceRef LUT4_14))
+          ))
+          (net wcount_r0 (joined
+           (portRef DO0 (instanceRef LUT4_14))
+           (portRef B0 (instanceRef empty_cmp_0))
+          ))
+          (net r_gcount_w29 (joined
+           (portRef Q (instanceRef FF_2))
+           (portRef AD1 (instanceRef LUT4_0))
+           (portRef AD1 (instanceRef LUT4_1))
+           (portRef AD1 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w28 (joined
+           (portRef Q (instanceRef FF_3))
+           (portRef AD2 (instanceRef LUT4_10))
+           (portRef AD3 (instanceRef LUT4_11))
+           (portRef AD1 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w27 (joined
+           (portRef Q (instanceRef FF_4))
+           (portRef AD1 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w26 (joined
+           (portRef Q (instanceRef FF_5))
+           (portRef AD1 (instanceRef LUT4_8))
+           (portRef AD2 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_13))
+          ))
+          (net r_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_13))
+           (portRef B0 (instanceRef full_cmp_3))
+           (portRef AD3 (instanceRef LUT4_4))
+           (portRef AD3 (instanceRef LUT4_5))
+           (portRef AD3 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_7))
+          ))
+          (net r_gcount_w25 (joined
+           (portRef Q (instanceRef FF_6))
+           (portRef AD1 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_8))
+           (portRef AD3 (instanceRef LUT4_9))
+           (portRef AD0 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w24 (joined
+           (portRef Q (instanceRef FF_7))
+           (portRef AD2 (instanceRef LUT4_7))
+           (portRef AD3 (instanceRef LUT4_8))
+           (portRef AD1 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w23 (joined
+           (portRef Q (instanceRef FF_8))
+           (portRef AD3 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w22 (joined
+           (portRef Q (instanceRef FF_9))
+           (portRef AD3 (instanceRef LUT4_12))
+          ))
+          (net r_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_12))
+           (portRef AD2 (instanceRef LUT4_4))
+           (portRef AD2 (instanceRef LUT4_5))
+           (portRef AD2 (instanceRef LUT4_6))
+          ))
+          (net rcount_w8 (joined
+           (portRef DO0 (instanceRef LUT4_11))
+           (portRef B0 (instanceRef full_cmp_4))
+           (portRef AD0 (instanceRef LUT4_9))
+          ))
+          (net rcount_w7 (joined
+           (portRef DO0 (instanceRef LUT4_10))
+           (portRef B1 (instanceRef full_cmp_3))
+           (portRef AD0 (instanceRef LUT4_8))
+          ))
+          (net rcount_w5 (joined
+           (portRef DO0 (instanceRef LUT4_9))
+           (portRef B1 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w4 (joined
+           (portRef DO0 (instanceRef LUT4_8))
+           (portRef B0 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w3 (joined
+           (portRef DO0 (instanceRef LUT4_7))
+           (portRef B1 (instanceRef full_cmp_1))
+          ))
+          (net rcount_w2 (joined
+           (portRef DO0 (instanceRef LUT4_6))
+           (portRef B0 (instanceRef full_cmp_1))
+          ))
+          (net r_gcount_w21 (joined
+           (portRef Q (instanceRef FF_10))
+           (portRef AD0 (instanceRef LUT4_4))
+           (portRef AD1 (instanceRef LUT4_5))
+          ))
+          (net rcount_w1 (joined
+           (portRef DO0 (instanceRef LUT4_5))
+           (portRef B1 (instanceRef full_cmp_0))
+          ))
+          (net r_gcount_w20 (joined
+           (portRef Q (instanceRef FF_11))
+           (portRef AD1 (instanceRef LUT4_4))
+          ))
+          (net rcount_w0 (joined
+           (portRef DO0 (instanceRef LUT4_4))
+           (portRef B0 (instanceRef full_cmp_0))
+          ))
+          (net rptr_9 (joined
+           (portRef Q (instanceRef FF_42))
+           (portRef AD3 (instanceRef LUT4_2))
+           (portRef AD3 (instanceRef LUT4_3))
+          ))
+          (net empty_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_3))
+           (portRef A1 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_2))
+           (portRef B1 (instanceRef empty_cmp_4))
+          ))
+          (net wptr_9 (joined
+           (portRef Q (instanceRef FF_72))
+           (portRef AD3 (instanceRef LUT4_0))
+           (portRef AD3 (instanceRef LUT4_1))
+          ))
+          (net full_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_1))
+           (portRef A1 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_0))
+           (portRef B1 (instanceRef full_cmp_4))
+          ))
+          (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined
+           (portRef fifo_in_data_0)
+           (portRef DI27 (instanceRef pdp_ram_0_0_0))
+           (portRef DI26 (instanceRef pdp_ram_0_0_0))
+           (portRef DI24 (instanceRef pdp_ram_0_0_0))
+           (portRef DI15 (instanceRef pdp_ram_0_0_0))
+           (portRef DI13 (instanceRef pdp_ram_0_0_0))
+           (portRef DI12 (instanceRef pdp_ram_0_0_0))
+           (portRef DI11 (instanceRef pdp_ram_0_0_0))
+           (portRef DI9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_0 (joined
+           (portRef Q (instanceRef FF_81))
+           (portRef ADW0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_1 (joined
+           (portRef Q (instanceRef FF_80))
+           (portRef ADW1 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_2 (joined
+           (portRef Q (instanceRef FF_79))
+           (portRef ADW2 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_3 (joined
+           (portRef Q (instanceRef FF_78))
+           (portRef ADW3 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_4 (joined
+           (portRef Q (instanceRef FF_77))
+           (portRef ADW4 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_5 (joined
+           (portRef Q (instanceRef FF_76))
+           (portRef ADW5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_6 (joined
+           (portRef Q (instanceRef FF_75))
+           (portRef ADW6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_7 (joined
+           (portRef Q (instanceRef FF_74))
+           (portRef ADW7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net wptr_8 (joined
+           (portRef Q (instanceRef FF_73))
+           (portRef ADW8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef a1))
+           (portRef C1 (instanceRef a1))
+           (portRef D0 (instanceRef a1))
+           (portRef C0 (instanceRef a1))
+           (portRef D1 (instanceRef full_cmp_4))
+           (portRef C1 (instanceRef full_cmp_4))
+           (portRef D0 (instanceRef full_cmp_4))
+           (portRef C0 (instanceRef full_cmp_4))
+           (portRef D1 (instanceRef full_cmp_3))
+           (portRef C1 (instanceRef full_cmp_3))
+           (portRef D0 (instanceRef full_cmp_3))
+           (portRef C0 (instanceRef full_cmp_3))
+           (portRef D1 (instanceRef full_cmp_2))
+           (portRef C1 (instanceRef full_cmp_2))
+           (portRef D0 (instanceRef full_cmp_2))
+           (portRef C0 (instanceRef full_cmp_2))
+           (portRef D1 (instanceRef full_cmp_1))
+           (portRef C1 (instanceRef full_cmp_1))
+           (portRef D0 (instanceRef full_cmp_1))
+           (portRef C0 (instanceRef full_cmp_1))
+           (portRef D1 (instanceRef full_cmp_0))
+           (portRef C1 (instanceRef full_cmp_0))
+           (portRef D0 (instanceRef full_cmp_0))
+           (portRef C0 (instanceRef full_cmp_0))
+           (portRef D1 (instanceRef full_cmp_ci_a))
+           (portRef C1 (instanceRef full_cmp_ci_a))
+           (portRef D0 (instanceRef full_cmp_ci_a))
+           (portRef C0 (instanceRef full_cmp_ci_a))
+           (portRef D1 (instanceRef a0))
+           (portRef C1 (instanceRef a0))
+           (portRef D0 (instanceRef a0))
+           (portRef C0 (instanceRef a0))
+           (portRef D1 (instanceRef empty_cmp_4))
+           (portRef C1 (instanceRef empty_cmp_4))
+           (portRef D0 (instanceRef empty_cmp_4))
+           (portRef C0 (instanceRef empty_cmp_4))
+           (portRef D1 (instanceRef empty_cmp_3))
+           (portRef C1 (instanceRef empty_cmp_3))
+           (portRef D0 (instanceRef empty_cmp_3))
+           (portRef C0 (instanceRef empty_cmp_3))
+           (portRef D1 (instanceRef empty_cmp_2))
+           (portRef C1 (instanceRef empty_cmp_2))
+           (portRef D0 (instanceRef empty_cmp_2))
+           (portRef C0 (instanceRef empty_cmp_2))
+           (portRef D1 (instanceRef empty_cmp_1))
+           (portRef C1 (instanceRef empty_cmp_1))
+           (portRef D0 (instanceRef empty_cmp_1))
+           (portRef C0 (instanceRef empty_cmp_1))
+           (portRef D1 (instanceRef empty_cmp_0))
+           (portRef C1 (instanceRef empty_cmp_0))
+           (portRef D0 (instanceRef empty_cmp_0))
+           (portRef C0 (instanceRef empty_cmp_0))
+           (portRef D1 (instanceRef empty_cmp_ci_a))
+           (portRef C1 (instanceRef empty_cmp_ci_a))
+           (portRef D0 (instanceRef empty_cmp_ci_a))
+           (portRef C0 (instanceRef empty_cmp_ci_a))
+           (portRef D1 (instanceRef r_gctr_4))
+           (portRef C1 (instanceRef r_gctr_4))
+           (portRef D0 (instanceRef r_gctr_4))
+           (portRef C0 (instanceRef r_gctr_4))
+           (portRef D1 (instanceRef r_gctr_3))
+           (portRef C1 (instanceRef r_gctr_3))
+           (portRef D0 (instanceRef r_gctr_3))
+           (portRef C0 (instanceRef r_gctr_3))
+           (portRef D1 (instanceRef r_gctr_2))
+           (portRef C1 (instanceRef r_gctr_2))
+           (portRef D0 (instanceRef r_gctr_2))
+           (portRef C0 (instanceRef r_gctr_2))
+           (portRef D1 (instanceRef r_gctr_1))
+           (portRef C1 (instanceRef r_gctr_1))
+           (portRef D0 (instanceRef r_gctr_1))
+           (portRef C0 (instanceRef r_gctr_1))
+           (portRef D1 (instanceRef r_gctr_0))
+           (portRef C1 (instanceRef r_gctr_0))
+           (portRef D0 (instanceRef r_gctr_0))
+           (portRef C0 (instanceRef r_gctr_0))
+           (portRef D1 (instanceRef r_gctr_cia))
+           (portRef C1 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef r_gctr_cia))
+           (portRef A1 (instanceRef r_gctr_cia))
+           (portRef D0 (instanceRef r_gctr_cia))
+           (portRef C0 (instanceRef r_gctr_cia))
+           (portRef D1 (instanceRef w_gctr_4))
+           (portRef C1 (instanceRef w_gctr_4))
+           (portRef D0 (instanceRef w_gctr_4))
+           (portRef C0 (instanceRef w_gctr_4))
+           (portRef D1 (instanceRef w_gctr_3))
+           (portRef C1 (instanceRef w_gctr_3))
+           (portRef D0 (instanceRef w_gctr_3))
+           (portRef C0 (instanceRef w_gctr_3))
+           (portRef D1 (instanceRef w_gctr_2))
+           (portRef C1 (instanceRef w_gctr_2))
+           (portRef D0 (instanceRef w_gctr_2))
+           (portRef C0 (instanceRef w_gctr_2))
+           (portRef D1 (instanceRef w_gctr_1))
+           (portRef C1 (instanceRef w_gctr_1))
+           (portRef D0 (instanceRef w_gctr_1))
+           (portRef C0 (instanceRef w_gctr_1))
+           (portRef D1 (instanceRef w_gctr_0))
+           (portRef C1 (instanceRef w_gctr_0))
+           (portRef D0 (instanceRef w_gctr_0))
+           (portRef C0 (instanceRef w_gctr_0))
+           (portRef D1 (instanceRef w_gctr_cia))
+           (portRef C1 (instanceRef w_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_cia))
+           (portRef A1 (instanceRef w_gctr_cia))
+           (portRef D0 (instanceRef w_gctr_cia))
+           (portRef C0 (instanceRef w_gctr_cia))
+           (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+           (portRef BE3 (instanceRef pdp_ram_0_0_0))
+           (portRef BE2 (instanceRef pdp_ram_0_0_0))
+           (portRef BE1 (instanceRef pdp_ram_0_0_0))
+           (portRef BE0 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef CK (instanceRef FF_0))
+           (portRef CK (instanceRef FF_1))
+           (portRef CK (instanceRef FF_2))
+           (portRef CK (instanceRef FF_3))
+           (portRef CK (instanceRef FF_4))
+           (portRef CK (instanceRef FF_5))
+           (portRef CK (instanceRef FF_6))
+           (portRef CK (instanceRef FF_7))
+           (portRef CK (instanceRef FF_8))
+           (portRef CK (instanceRef FF_9))
+           (portRef CK (instanceRef FF_10))
+           (portRef CK (instanceRef FF_11))
+           (portRef CK (instanceRef FF_12))
+           (portRef CK (instanceRef FF_13))
+           (portRef CK (instanceRef FF_14))
+           (portRef CK (instanceRef FF_15))
+           (portRef CK (instanceRef FF_16))
+           (portRef CK (instanceRef FF_17))
+           (portRef CK (instanceRef FF_18))
+           (portRef CK (instanceRef FF_19))
+           (portRef CK (instanceRef FF_20))
+           (portRef CK (instanceRef FF_21))
+           (portRef CK (instanceRef FF_22))
+           (portRef CK (instanceRef FF_23))
+           (portRef CK (instanceRef FF_24))
+           (portRef CK (instanceRef FF_25))
+           (portRef CK (instanceRef FF_26))
+           (portRef CK (instanceRef FF_27))
+           (portRef CK (instanceRef FF_28))
+           (portRef CK (instanceRef FF_29))
+           (portRef CK (instanceRef FF_30))
+           (portRef CK (instanceRef FF_31))
+           (portRef CK (instanceRef FF_32))
+           (portRef CK (instanceRef FF_33))
+           (portRef CK (instanceRef FF_34))
+           (portRef CK (instanceRef FF_35))
+           (portRef CK (instanceRef FF_36))
+           (portRef CK (instanceRef FF_37))
+           (portRef CK (instanceRef FF_38))
+           (portRef CK (instanceRef FF_39))
+           (portRef CK (instanceRef FF_40))
+           (portRef CK (instanceRef FF_41))
+           (portRef CK (instanceRef FF_42))
+           (portRef CK (instanceRef FF_43))
+           (portRef CK (instanceRef FF_44))
+           (portRef CK (instanceRef FF_45))
+           (portRef CK (instanceRef FF_46))
+           (portRef CK (instanceRef FF_47))
+           (portRef CK (instanceRef FF_48))
+           (portRef CK (instanceRef FF_49))
+           (portRef CK (instanceRef FF_50))
+           (portRef CK (instanceRef FF_51))
+           (portRef CK (instanceRef FF_52))
+           (portRef CK (instanceRef FF_53))
+           (portRef CK (instanceRef FF_54))
+           (portRef CK (instanceRef FF_55))
+           (portRef CK (instanceRef FF_56))
+           (portRef CK (instanceRef FF_57))
+           (portRef CK (instanceRef FF_58))
+           (portRef CK (instanceRef FF_59))
+           (portRef CK (instanceRef FF_60))
+           (portRef CK (instanceRef FF_61))
+           (portRef CK (instanceRef FF_62))
+           (portRef CK (instanceRef FF_63))
+           (portRef CK (instanceRef FF_64))
+           (portRef CK (instanceRef FF_65))
+           (portRef CK (instanceRef FF_66))
+           (portRef CK (instanceRef FF_67))
+           (portRef CK (instanceRef FF_68))
+           (portRef CK (instanceRef FF_69))
+           (portRef CK (instanceRef FF_70))
+           (portRef CK (instanceRef FF_71))
+           (portRef CK (instanceRef FF_72))
+           (portRef CK (instanceRef FF_73))
+           (portRef CK (instanceRef FF_74))
+           (portRef CK (instanceRef FF_75))
+           (portRef CK (instanceRef FF_76))
+           (portRef CK (instanceRef FF_77))
+           (portRef CK (instanceRef FF_78))
+           (portRef CK (instanceRef FF_79))
+           (portRef CK (instanceRef FF_80))
+           (portRef CK (instanceRef FF_81))
+           (portRef CK (instanceRef FF_82))
+           (portRef CK (instanceRef FF_83))
+           (portRef CK (instanceRef FF_84))
+           (portRef CK (instanceRef FF_85))
+           (portRef CK (instanceRef FF_86))
+           (portRef CK (instanceRef FF_87))
+           (portRef CK (instanceRef FF_88))
+           (portRef CK (instanceRef FF_89))
+           (portRef CK (instanceRef FF_90))
+           (portRef CK (instanceRef FF_91))
+           (portRef CK (instanceRef FF_92))
+           (portRef CK (instanceRef FF_93))
+           (portRef CK (instanceRef FF_94))
+           (portRef CK (instanceRef FF_95))
+           (portRef CK (instanceRef FF_96))
+           (portRef CK (instanceRef FF_97))
+           (portRef CK (instanceRef FF_98))
+           (portRef CK (instanceRef FF_99))
+           (portRef CK (instanceRef FF_100))
+           (portRef CK (instanceRef FF_101))
+           (portRef CLKR (instanceRef pdp_ram_0_0_0))
+           (portRef CLKW (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_0 (joined
+           (portRef Q (instanceRef FF_51))
+           (portRef ADR5 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_1 (joined
+           (portRef Q (instanceRef FF_50))
+           (portRef ADR6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_2 (joined
+           (portRef Q (instanceRef FF_49))
+           (portRef ADR7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_3 (joined
+           (portRef Q (instanceRef FF_48))
+           (portRef ADR8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_4 (joined
+           (portRef Q (instanceRef FF_47))
+           (portRef ADR9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_5 (joined
+           (portRef Q (instanceRef FF_46))
+           (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_6 (joined
+           (portRef Q (instanceRef FF_45))
+           (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_7 (joined
+           (portRef Q (instanceRef FF_44))
+           (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net rptr_8 (joined
+           (portRef Q (instanceRef FF_43))
+           (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef DO0 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef DO1 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef DO2 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef DO3 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef DO4 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef DO5 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename Q_1_24 "Q_1[24]") (joined
+           (portRef DO6 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_25 "Q_1[25]") (joined
+           (portRef DO7 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_26 "Q_1[26]") (joined
+           (portRef DO8 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_27 "Q_1[27]") (joined
+           (portRef DO9 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_28 "Q_1[28]") (joined
+           (portRef DO10 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_29 "Q_1[29]") (joined
+           (portRef DO11 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_30 "Q_1[30]") (joined
+           (portRef DO12 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename Q_1_31 "Q_1[31]") (joined
+           (portRef DO13 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO14 (joined
+           (portRef DO14 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO15 (joined
+           (portRef DO15 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO16 (joined
+           (portRef DO16 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net pdp_ram_0_0_0_DO17 (joined
+           (portRef DO17 (instanceRef pdp_ram_0_0_0))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef DO18 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef DO19 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef DO20 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef DO21 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef DO22 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef DO23 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef DO24 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef DO25 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef DO26 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef DO27 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef DO28 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef DO29 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef DO30 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef DO31 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef DO32 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef DO33 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef DO34 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef DO35 (instanceRef pdp_ram_0_0_0))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net iwcount_0 (joined
+           (portRef S0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_101))
+          ))
+          (net iwcount_1 (joined
+           (portRef S1 (instanceRef w_gctr_0))
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+          ))
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+          ))
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+          ))
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+          ))
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+          ))
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+          ))
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+           (portRef CIN (instanceRef w_gctr_0))
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+          ))
+          (net w_gctr_cia_S1 (joined
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+          ))
+          (net co0 (joined
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+           (portRef CIN (instanceRef w_gctr_1))
+          ))
+          (net co1 (joined
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+           (portRef CIN (instanceRef w_gctr_2))
+          ))
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+           (portRef CIN (instanceRef w_gctr_3))
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+           (portRef CIN (instanceRef w_gctr_4))
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+           (portRef CIN (instanceRef r_gctr_0))
+          ))
+          (net r_gctr_cia_S0 (joined
+           (portRef S0 (instanceRef r_gctr_cia))
+          ))
+          (net r_gctr_cia_S1 (joined
+           (portRef S1 (instanceRef r_gctr_cia))
+          ))
+          (net co0_1 (joined
+           (portRef COUT (instanceRef r_gctr_0))
+           (portRef CIN (instanceRef r_gctr_1))
+          ))
+          (net co1_1 (joined
+           (portRef COUT (instanceRef r_gctr_1))
+           (portRef CIN (instanceRef r_gctr_2))
+          ))
+          (net co2_1 (joined
+           (portRef COUT (instanceRef r_gctr_2))
+           (portRef CIN (instanceRef r_gctr_3))
+          ))
+          (net co3_1 (joined
+           (portRef COUT (instanceRef r_gctr_3))
+           (portRef CIN (instanceRef r_gctr_4))
+          ))
+          (net co4_1 (joined
+           (portRef COUT (instanceRef r_gctr_4))
+          ))
+          (net cmp_ci (joined
+           (portRef COUT (instanceRef empty_cmp_ci_a))
+           (portRef CIN (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_ci_a_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_ci_a))
+          ))
+          (net empty_cmp_ci_a_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_ci_a))
+          ))
+          (net co0_2 (joined
+           (portRef COUT (instanceRef empty_cmp_0))
+           (portRef CIN (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_0_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_0_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_0))
+          ))
+          (net co1_2 (joined
+           (portRef COUT (instanceRef empty_cmp_1))
+           (portRef CIN (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_1_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_1_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_1))
+          ))
+          (net co2_2 (joined
+           (portRef COUT (instanceRef empty_cmp_2))
+           (portRef CIN (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_2_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_2_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_2))
+          ))
+          (net co3_2 (joined
+           (portRef COUT (instanceRef empty_cmp_3))
+           (portRef CIN (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_3_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_3_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_3))
+          ))
+          (net empty_d_c (joined
+           (portRef COUT (instanceRef empty_cmp_4))
+           (portRef CIN (instanceRef a0))
+          ))
+          (net empty_cmp_4_S0 (joined
+           (portRef S0 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_4_S1 (joined
+           (portRef S1 (instanceRef empty_cmp_4))
+          ))
+          (net a0_COUT (joined
+           (portRef COUT (instanceRef a0))
+          ))
+          (net a0_S1 (joined
+           (portRef S1 (instanceRef a0))
+          ))
+          (net cmp_ci_1 (joined
+           (portRef COUT (instanceRef full_cmp_ci_a))
+           (portRef CIN (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_ci_a_S0 (joined
+           (portRef S0 (instanceRef full_cmp_ci_a))
+          ))
+          (net full_cmp_ci_a_S1 (joined
+           (portRef S1 (instanceRef full_cmp_ci_a))
+          ))
+          (net co0_3 (joined
+           (portRef COUT (instanceRef full_cmp_0))
+           (portRef CIN (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_0_S0 (joined
+           (portRef S0 (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_0_S1 (joined
+           (portRef S1 (instanceRef full_cmp_0))
+          ))
+          (net co1_3 (joined
+           (portRef COUT (instanceRef full_cmp_1))
+           (portRef CIN (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_1_S0 (joined
+           (portRef S0 (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_1_S1 (joined
+           (portRef S1 (instanceRef full_cmp_1))
+          ))
+          (net co2_3 (joined
+           (portRef COUT (instanceRef full_cmp_2))
+           (portRef CIN (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_2_S0 (joined
+           (portRef S0 (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_2_S1 (joined
+           (portRef S1 (instanceRef full_cmp_2))
+          ))
+          (net co3_3 (joined
+           (portRef COUT (instanceRef full_cmp_3))
+           (portRef CIN (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_3_S0 (joined
+           (portRef S0 (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_3_S1 (joined
+           (portRef S1 (instanceRef full_cmp_3))
+          ))
+          (net full_d_c (joined
+           (portRef COUT (instanceRef full_cmp_4))
+           (portRef CIN (instanceRef a1))
+          ))
+          (net full_cmp_4_S0 (joined
+           (portRef S0 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_4_S1 (joined
+           (portRef S1 (instanceRef full_cmp_4))
+          ))
+          (net a1_COUT (joined
+           (portRef COUT (instanceRef a1))
+          ))
+          (net a1_S1 (joined
+           (portRef S1 (instanceRef a1))
+          ))
+          (net CIN (joined
+           (portRef CIN (instanceRef full_cmp_ci_a))
+          ))
+          (net CIN_0 (joined
+           (portRef CIN (instanceRef empty_cmp_ci_a))
+          ))
+          (net CIN_1 (joined
+           (portRef CIN (instanceRef r_gctr_cia))
+          ))
+          (net CIN_2 (joined
+           (portRef CIN (instanceRef w_gctr_cia))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "fifo32dc"))
+       )
+    )
+    (cell output_decoder8_2 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT))
+           (port decoder_valid (direction OUTPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))"))
+          )
+          (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))"))
+          )
+          (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C (B+!A))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net N_352_i (joined
+           (portRef Z (instanceRef valid_internal_RNO))
+           (portRef D (instanceRef valid_internal))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef dl_0__7))
+           (portRef CK (instanceRef dl_0__6))
+           (portRef CK (instanceRef dl_0__5))
+           (portRef CK (instanceRef dl_0__4))
+           (portRef CK (instanceRef dl_0__3))
+           (portRef CK (instanceRef dl_0__2))
+           (portRef CK (instanceRef dl_0__1))
+           (portRef CK (instanceRef dl_0__0))
+           (portRef CK (instanceRef dl_1__7))
+           (portRef CK (instanceRef dl_1__6))
+           (portRef CK (instanceRef dl_1__5))
+           (portRef CK (instanceRef dl_1__4))
+           (portRef CK (instanceRef dl_1__3))
+           (portRef CK (instanceRef dl_1__2))
+           (portRef CK (instanceRef dl_1__1))
+           (portRef CK (instanceRef dl_1__0))
+           (portRef CK (instanceRef in_synced_7))
+           (portRef CK (instanceRef in_synced_6))
+           (portRef CK (instanceRef in_synced_5))
+           (portRef CK (instanceRef in_synced_4))
+           (portRef CK (instanceRef in_synced_3))
+           (portRef CK (instanceRef in_synced_2))
+           (portRef CK (instanceRef in_synced_1))
+           (portRef CK (instanceRef in_synced_0))
+           (portRef CK (instanceRef valid))
+           (portRef CK (instanceRef valid_internal))
+          ))
+          (net in_synced7_rising_i (joined
+           (portRef Z (instanceRef valid_internal_RNO_0))
+           (portRef CD (instanceRef valid_internal))
+          ))
+          (net valid_internal (joined
+           (portRef Q (instanceRef valid_internal))
+           (portRef D (instanceRef valid))
+          ))
+          (net decoder_valid (joined
+           (portRef Q (instanceRef valid))
+           (portRef decoder_valid)
+          ))
+          (net (rename dl_1__0 "dl[1][0]") (joined
+           (portRef Q (instanceRef dl_1__0))
+           (portRef D (instanceRef in_synced_0))
+          ))
+          (net (rename in_synced_0 "in_synced[0]") (joined
+           (portRef Q (instanceRef in_synced_0))
+           (portRef A (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__1 "dl[1][1]") (joined
+           (portRef Q (instanceRef dl_1__1))
+           (portRef D (instanceRef in_synced_1))
+          ))
+          (net (rename in_synced_1 "in_synced[1]") (joined
+           (portRef Q (instanceRef in_synced_1))
+           (portRef B (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__2 "dl[1][2]") (joined
+           (portRef Q (instanceRef dl_1__2))
+           (portRef D (instanceRef in_synced_2))
+          ))
+          (net (rename in_synced_2 "in_synced[2]") (joined
+           (portRef Q (instanceRef in_synced_2))
+           (portRef A (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef C (instanceRef valid_internal_RNO))
+          ))
+          (net (rename dl_1__3 "dl[1][3]") (joined
+           (portRef Q (instanceRef dl_1__3))
+           (portRef D (instanceRef in_synced_3))
+          ))
+          (net (rename in_synced_3 "in_synced[3]") (joined
+           (portRef Q (instanceRef in_synced_3))
+           (portRef B (instanceRef un1_out_internal35_1_0_m4_0))
+          ))
+          (net (rename dl_1__4 "dl[1][4]") (joined
+           (portRef Q (instanceRef dl_1__4))
+           (portRef D (instanceRef in_synced_4))
+          ))
+          (net (rename in_synced_4 "in_synced[4]") (joined
+           (portRef Q (instanceRef in_synced_4))
+           (portRef C (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef B (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__5 "dl[1][5]") (joined
+           (portRef Q (instanceRef dl_1__5))
+           (portRef D (instanceRef in_synced_5))
+          ))
+          (net (rename in_synced_5 "in_synced[5]") (joined
+           (portRef Q (instanceRef in_synced_5))
+           (portRef C (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__6 "dl[1][6]") (joined
+           (portRef Q (instanceRef dl_1__6))
+           (portRef D (instanceRef in_synced_6))
+          ))
+          (net (rename in_synced_6 "in_synced[6]") (joined
+           (portRef Q (instanceRef in_synced_6))
+           (portRef D (instanceRef un1_out_internal35_1_0_0))
+          ))
+          (net (rename dl_1__7 "dl[1][7]") (joined
+           (portRef Q (instanceRef dl_1__7))
+           (portRef A (instanceRef valid_internal_RNO_0))
+           (portRef D (instanceRef in_synced_7))
+          ))
+          (net (rename in_synced_7 "in_synced[7]") (joined
+           (portRef Q (instanceRef in_synced_7))
+           (portRef B (instanceRef valid_internal_RNO_0))
+          ))
+          (net (rename dl_0__0 "dl[0][0]") (joined
+           (portRef Q (instanceRef dl_0__0))
+           (portRef D (instanceRef dl_1__0))
+          ))
+          (net (rename dl_0__1 "dl[0][1]") (joined
+           (portRef Q (instanceRef dl_0__1))
+           (portRef D (instanceRef dl_1__1))
+          ))
+          (net (rename dl_0__2 "dl[0][2]") (joined
+           (portRef Q (instanceRef dl_0__2))
+           (portRef D (instanceRef dl_1__2))
+          ))
+          (net (rename dl_0__3 "dl[0][3]") (joined
+           (portRef Q (instanceRef dl_0__3))
+           (portRef D (instanceRef dl_1__3))
+          ))
+          (net (rename dl_0__4 "dl[0][4]") (joined
+           (portRef Q (instanceRef dl_0__4))
+           (portRef D (instanceRef dl_1__4))
+          ))
+          (net (rename dl_0__5 "dl[0][5]") (joined
+           (portRef Q (instanceRef dl_0__5))
+           (portRef D (instanceRef dl_1__5))
+          ))
+          (net (rename dl_0__6 "dl[0][6]") (joined
+           (portRef Q (instanceRef dl_0__6))
+           (portRef D (instanceRef dl_1__6))
+          ))
+          (net (rename dl_0__7 "dl[0][7]") (joined
+           (portRef Q (instanceRef dl_0__7))
+           (portRef D (instanceRef dl_1__7))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7))
+           (portRef D (instanceRef dl_0__0))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6))
+           (portRef D (instanceRef dl_0__1))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5))
+           (portRef D (instanceRef dl_0__2))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4))
+           (portRef D (instanceRef dl_0__3))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3))
+           (portRef D (instanceRef dl_0__4))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2))
+           (portRef D (instanceRef dl_0__5))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1))
+           (portRef D (instanceRef dl_0__6))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0))
+           (portRef D (instanceRef dl_0__7))
+          ))
+          (net un1_out_internal35_1_0_0 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_0))
+           (portRef D (instanceRef valid_internal_RNO))
+          ))
+          (net N_42 (joined
+           (portRef Z (instanceRef un1_out_internal35_1_0_m4_0))
+           (portRef A (instanceRef un1_out_internal35_1_0_0))
+          ))
+         )
+        (property orig_inst_of (string "output_decoder8"))
+       )
+    )
+    (cell tdc4ddr_short_2 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename out_buffered1_3 "out_buffered1[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_3))
+           (portRef D (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_3))
+           (portRef CK (instanceRef genblk1_3__out_buffered_3))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_3))
+           (portRef (member tdc_out 4))
+          ))
+          (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_3))
+           (portRef D (instanceRef genblk1_3__out_buffered1_3))
+          ))
+          (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined
+           (portRef Q (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CK (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered_7))
+           (portRef CK (instanceRef genblk1_3__out_buffered1_7))
+          ))
+          (net (rename out_buffered1_7 "out_buffered1[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered1_7))
+           (portRef D (instanceRef genblk1_3__out_buffered_7))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef Q (instanceRef genblk1_3__out_buffered_7))
+           (portRef (member tdc_out 0))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[0]") (joined
+           (portRef trig_c_i_0)
+           (portRef D (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_7))
+           (portRef D (instanceRef genblk1_3__in_clk_synced_3))
+          ))
+          (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef D (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered_2))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_2))
+          ))
+          (net (rename out_buffered1_2 "out_buffered1[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_2))
+           (portRef D (instanceRef genblk1_2__out_buffered_2))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_2))
+           (portRef (member tdc_out 5))
+          ))
+          (net (rename out_buffered1_6 "out_buffered1[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered1_6))
+           (portRef D (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CK (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered1_6))
+           (portRef CK (instanceRef genblk1_2__out_buffered_6))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef Q (instanceRef genblk1_2__out_buffered_6))
+           (portRef (member tdc_out 1))
+          ))
+          (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined
+           (portRef Q (instanceRef genblk1_2__in_clk_synced_6))
+           (portRef D (instanceRef genblk1_2__out_buffered1_6))
+          ))
+          (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef D (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered_1))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_1))
+          ))
+          (net (rename out_buffered1_1 "out_buffered1[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_1))
+           (portRef D (instanceRef genblk1_1__out_buffered_1))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_1))
+           (portRef (member tdc_out 6))
+          ))
+          (net (rename out_buffered1_5 "out_buffered1[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered1_5))
+           (portRef D (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CK (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered1_5))
+           (portRef CK (instanceRef genblk1_1__out_buffered_5))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef Q (instanceRef genblk1_1__out_buffered_5))
+           (portRef (member tdc_out 2))
+          ))
+          (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined
+           (portRef Q (instanceRef genblk1_1__in_clk_synced_5))
+           (portRef D (instanceRef genblk1_1__out_buffered1_5))
+          ))
+          (net (rename out_buffered1_0 "out_buffered1[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_0))
+           (portRef D (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_0))
+           (portRef CK (instanceRef genblk1_0__out_buffered_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_0))
+           (portRef (member tdc_out 7))
+          ))
+          (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_0))
+           (portRef D (instanceRef genblk1_0__out_buffered1_0))
+          ))
+          (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined
+           (portRef Q (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef D (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CK (instanceRef genblk1_0__in_clk_synced_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered_4))
+           (portRef CK (instanceRef genblk1_0__out_buffered1_4))
+          ))
+          (net (rename out_buffered1_4 "out_buffered1[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered1_4))
+           (portRef D (instanceRef genblk1_0__out_buffered_4))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef Q (instanceRef genblk1_0__out_buffered_4))
+           (portRef (member tdc_out 3))
+          ))
+         )
+        (property orig_inst_of (string "tdc4ddr_short"))
+       )
+    )
+    (cell fifo40_dc (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename fee_data_out_c "FEE_DATA_OUT_c[31:0]") 32) (direction OUTPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port (array (rename data_buffer "data_buffer[33:0]") 34) (direction INPUT))
+           (port rd_clk_c (direction INPUT))
+           (port last_buf_empty_c (direction OUTPUT))
+           (port fifo_rden_c (direction INPUT))
+           (port buffer_wr_enable (direction INPUT))
+         )
+         (contents
+          (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
+          )
+          (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))
+          )
+          (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT)))
+          )
+          (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x6996"))
+          )
+          (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0410"))
+          )
+          (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x1004"))
+          )
+          (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x0140"))
+          )
+          (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT)))
+           (property initval (string "0x4001"))
+          )
+          (instance pdp_ram_0_0_1 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT)))
+           (property MEM_LPC_FILE (string "fifo40_dc.lpc"))
+           (property MEM_INIT_FILE (string ""))
+           (property DATA_WIDTH_W (integer 36))
+           (property DATA_WIDTH_R (integer 36))
+           (property REGMODE (string "NOREG"))
+           (property RESETMODE (string "ASYNC"))
+           (property GSR (string "ENABLED"))
+           (property CSDECODE_W (string "0b001"))
+           (property CSDECODE_R (string "0b000"))
+           (property ASYNC_RESET_RELEASE (string "SYNC"))
+           (property INIT_DATA (string "STATIC"))
+          )
+          (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT)))
+           (property GSR (string "ENABLED"))
+          )
+          (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x99AA"))
+           (property INIT1 (string "0x99AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x66AA"))
+           (property INIT1 (string "0x66AA"))
+           (property INJECT1_0 (string "NO"))
+           (property INJECT1_1 (string "NO"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net buffer_wr_enable (joined
+           (portRef buffer_wr_enable)
+           (portRef A (instanceRef AND2_t20))
+          ))
+          (net invout_1 (joined
+           (portRef Z (instanceRef INV_1))
+           (portRef B (instanceRef AND2_t20))
+          ))
+          (net wren_i (joined
+           (portRef Z (instanceRef AND2_t20))
+           (portRef B1 (instanceRef full_cmp_ci_a))
+           (portRef A1 (instanceRef full_cmp_ci_a))
+           (portRef SP (instanceRef FF_72))
+           (portRef SP (instanceRef FF_73))
+           (portRef SP (instanceRef FF_74))
+           (portRef SP (instanceRef FF_75))
+           (portRef SP (instanceRef FF_76))
+           (portRef SP (instanceRef FF_77))
+           (portRef SP (instanceRef FF_78))
+           (portRef SP (instanceRef FF_79))
+           (portRef SP (instanceRef FF_80))
+           (portRef SP (instanceRef FF_81))
+           (portRef SP (instanceRef FF_82))
+           (portRef SP (instanceRef FF_83))
+           (portRef SP (instanceRef FF_84))
+           (portRef SP (instanceRef FF_85))
+           (portRef SP (instanceRef FF_86))
+           (portRef SP (instanceRef FF_87))
+           (portRef SP (instanceRef FF_88))
+           (portRef SP (instanceRef FF_89))
+           (portRef SP (instanceRef FF_90))
+           (portRef SP (instanceRef FF_91))
+           (portRef SP (instanceRef FF_92))
+           (portRef SP (instanceRef FF_93))
+           (portRef SP (instanceRef FF_94))
+           (portRef SP (instanceRef FF_95))
+           (portRef SP (instanceRef FF_96))
+           (portRef SP (instanceRef FF_97))
+           (portRef SP (instanceRef FF_98))
+           (portRef SP (instanceRef FF_99))
+           (portRef SP (instanceRef FF_100))
+           (portRef SP (instanceRef FF_101))
+           (portRef CEW (instanceRef pdp_ram_0_0_1))
+          ))
+          (net Full (joined
+           (portRef Q (instanceRef FF_0))
+           (portRef A (instanceRef INV_1))
+          ))
+          (net fifo_rden_c (joined
+           (portRef fifo_rden_c)
+           (portRef A (instanceRef AND2_t19))
+          ))
+          (net invout_0 (joined
+           (portRef Z (instanceRef INV_0))
+           (portRef B (instanceRef AND2_t19))
+          ))
+          (net rden_i (joined
+           (portRef Z (instanceRef AND2_t19))
+           (portRef B1 (instanceRef empty_cmp_ci_a))
+           (portRef A1 (instanceRef empty_cmp_ci_a))
+           (portRef SP (instanceRef FF_42))
+           (portRef SP (instanceRef FF_43))
+           (portRef SP (instanceRef FF_44))
+           (portRef SP (instanceRef FF_45))
+           (portRef SP (instanceRef FF_46))
+           (portRef SP (instanceRef FF_47))
+           (portRef SP (instanceRef FF_48))
+           (portRef SP (instanceRef FF_49))
+           (portRef SP (instanceRef FF_50))
+           (portRef SP (instanceRef FF_51))
+           (portRef SP (instanceRef FF_52))
+           (portRef SP (instanceRef FF_53))
+           (portRef SP (instanceRef FF_54))
+           (portRef SP (instanceRef FF_55))
+           (portRef SP (instanceRef FF_56))
+           (portRef SP (instanceRef FF_57))
+           (portRef SP (instanceRef FF_58))
+           (portRef SP (instanceRef FF_59))
+           (portRef SP (instanceRef FF_60))
+           (portRef SP (instanceRef FF_61))
+           (portRef SP (instanceRef FF_62))
+           (portRef SP (instanceRef FF_63))
+           (portRef SP (instanceRef FF_64))
+           (portRef SP (instanceRef FF_65))
+           (portRef SP (instanceRef FF_66))
+           (portRef SP (instanceRef FF_67))
+           (portRef SP (instanceRef FF_68))
+           (portRef SP (instanceRef FF_69))
+           (portRef SP (instanceRef FF_70))
+           (portRef SP (instanceRef FF_71))
+           (portRef OCER (instanceRef pdp_ram_0_0_1))
+           (portRef CER (instanceRef pdp_ram_0_0_1))
+          ))
+          (net last_buf_empty_c (joined
+           (portRef Q (instanceRef FF_1))
+           (portRef A (instanceRef INV_0))
+           (portRef last_buf_empty_c)
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef B1 (instanceRef a1))
+           (portRef A1 (instanceRef a1))
+           (portRef B0 (instanceRef a1))
+           (portRef A0 (instanceRef a1))
+           (portRef B0 (instanceRef full_cmp_ci_a))
+           (portRef A0 (instanceRef full_cmp_ci_a))
+           (portRef B1 (instanceRef a0))
+           (portRef A1 (instanceRef a0))
+           (portRef B0 (instanceRef a0))
+           (portRef A0 (instanceRef a0))
+           (portRef B0 (instanceRef empty_cmp_ci_a))
+           (portRef A0 (instanceRef empty_cmp_ci_a))
+           (portRef B1 (instanceRef r_gctr_4))
+           (portRef B0 (instanceRef r_gctr_4))
+           (portRef B1 (instanceRef r_gctr_3))
+           (portRef B0 (instanceRef r_gctr_3))
+           (portRef B1 (instanceRef r_gctr_2))
+           (portRef B0 (instanceRef r_gctr_2))
+           (portRef B1 (instanceRef r_gctr_1))
+           (portRef B0 (instanceRef r_gctr_1))
+           (portRef B1 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_0))
+           (portRef B0 (instanceRef r_gctr_cia))
+           (portRef A0 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_4))
+           (portRef B0 (instanceRef w_gctr_4))
+           (portRef B1 (instanceRef w_gctr_3))
+           (portRef B0 (instanceRef w_gctr_3))
+           (portRef B1 (instanceRef w_gctr_2))
+           (portRef B0 (instanceRef w_gctr_2))
+           (portRef B1 (instanceRef w_gctr_1))
+           (portRef B0 (instanceRef w_gctr_1))
+           (portRef B1 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_0))
+           (portRef B0 (instanceRef w_gctr_cia))
+           (portRef A0 (instanceRef w_gctr_cia))
+           (portRef CD (instanceRef FF_0))
+           (portRef CD (instanceRef FF_12))
+           (portRef CD (instanceRef FF_13))
+           (portRef CD (instanceRef FF_14))
+           (portRef CD (instanceRef FF_15))
+           (portRef CD (instanceRef FF_16))
+           (portRef CD (instanceRef FF_17))
+           (portRef CD (instanceRef FF_18))
+           (portRef CD (instanceRef FF_19))
+           (portRef CD (instanceRef FF_20))
+           (portRef CD (instanceRef FF_21))
+           (portRef CD (instanceRef FF_32))
+           (portRef CD (instanceRef FF_33))
+           (portRef CD (instanceRef FF_34))
+           (portRef CD (instanceRef FF_35))
+           (portRef CD (instanceRef FF_36))
+           (portRef CD (instanceRef FF_37))
+           (portRef CD (instanceRef FF_38))
+           (portRef CD (instanceRef FF_39))
+           (portRef CD (instanceRef FF_40))
+           (portRef CD (instanceRef FF_41))
+           (portRef CD (instanceRef FF_72))
+           (portRef CD (instanceRef FF_73))
+           (portRef CD (instanceRef FF_74))
+           (portRef CD (instanceRef FF_75))
+           (portRef CD (instanceRef FF_76))
+           (portRef CD (instanceRef FF_77))
+           (portRef CD (instanceRef FF_78))
+           (portRef CD (instanceRef FF_79))
+           (portRef CD (instanceRef FF_80))
+           (portRef CD (instanceRef FF_81))
+           (portRef CD (instanceRef FF_82))
+           (portRef CD (instanceRef FF_83))
+           (portRef CD (instanceRef FF_84))
+           (portRef CD (instanceRef FF_85))
+           (portRef CD (instanceRef FF_86))
+           (portRef CD (instanceRef FF_87))
+           (portRef CD (instanceRef FF_88))
+           (portRef CD (instanceRef FF_89))
+           (portRef CD (instanceRef FF_90))
+           (portRef CD (instanceRef FF_91))
+           (portRef CD (instanceRef FF_92))
+           (portRef CD (instanceRef FF_93))
+           (portRef CD (instanceRef FF_94))
+           (portRef CD (instanceRef FF_95))
+           (portRef CD (instanceRef FF_96))
+           (portRef CD (instanceRef FF_97))
+           (portRef CD (instanceRef FF_98))
+           (portRef CD (instanceRef FF_99))
+           (portRef CD (instanceRef FF_100))
+           (portRef PD (instanceRef FF_101))
+           (portRef RST (instanceRef pdp_ram_0_0_1))
+           (portRef CSR2 (instanceRef pdp_ram_0_0_1))
+           (portRef CSR1 (instanceRef pdp_ram_0_0_1))
+           (portRef CSR0 (instanceRef pdp_ram_0_0_1))
+           (portRef ADR4 (instanceRef pdp_ram_0_0_1))
+           (portRef ADR3 (instanceRef pdp_ram_0_0_1))
+           (portRef ADR2 (instanceRef pdp_ram_0_0_1))
+           (portRef ADR1 (instanceRef pdp_ram_0_0_1))
+           (portRef ADR0 (instanceRef pdp_ram_0_0_1))
+           (portRef CSW2 (instanceRef pdp_ram_0_0_1))
+           (portRef CSW1 (instanceRef pdp_ram_0_0_1))
+           (portRef DI35 (instanceRef pdp_ram_0_0_1))
+           (portRef DI34 (instanceRef pdp_ram_0_0_1))
+           (portRef AD0 (instanceRef LUT4_0))
+           (portRef AD0 (instanceRef LUT4_1))
+           (portRef AD0 (instanceRef LUT4_2))
+           (portRef AD0 (instanceRef LUT4_3))
+           (portRef AD0 (instanceRef LUT4_5))
+           (portRef AD1 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_10))
+           (portRef AD1 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_15))
+           (portRef AD1 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_20))
+           (portRef AD1 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_21))
+           (portRef B (instanceRef OR2_t18))
+           (portRef A (instanceRef OR2_t18))
+          ))
+          (net rRst (joined
+           (portRef Z (instanceRef OR2_t18))
+           (portRef PD (instanceRef FF_1))
+           (portRef CD (instanceRef FF_2))
+           (portRef CD (instanceRef FF_3))
+           (portRef CD (instanceRef FF_4))
+           (portRef CD (instanceRef FF_5))
+           (portRef CD (instanceRef FF_6))
+           (portRef CD (instanceRef FF_7))
+           (portRef CD (instanceRef FF_8))
+           (portRef CD (instanceRef FF_9))
+           (portRef CD (instanceRef FF_10))
+           (portRef CD (instanceRef FF_11))
+           (portRef CD (instanceRef FF_22))
+           (portRef CD (instanceRef FF_23))
+           (portRef CD (instanceRef FF_24))
+           (portRef CD (instanceRef FF_25))
+           (portRef CD (instanceRef FF_26))
+           (portRef CD (instanceRef FF_27))
+           (portRef CD (instanceRef FF_28))
+           (portRef CD (instanceRef FF_29))
+           (portRef CD (instanceRef FF_30))
+           (portRef CD (instanceRef FF_31))
+           (portRef CD (instanceRef FF_42))
+           (portRef CD (instanceRef FF_43))
+           (portRef CD (instanceRef FF_44))
+           (portRef CD (instanceRef FF_45))
+           (portRef CD (instanceRef FF_46))
+           (portRef CD (instanceRef FF_47))
+           (portRef CD (instanceRef FF_48))
+           (portRef CD (instanceRef FF_49))
+           (portRef CD (instanceRef FF_50))
+           (portRef CD (instanceRef FF_51))
+           (portRef CD (instanceRef FF_52))
+           (portRef CD (instanceRef FF_53))
+           (portRef CD (instanceRef FF_54))
+           (portRef CD (instanceRef FF_55))
+           (portRef CD (instanceRef FF_56))
+           (portRef CD (instanceRef FF_57))
+           (portRef CD (instanceRef FF_58))
+           (portRef CD (instanceRef FF_59))
+           (portRef CD (instanceRef FF_60))
+           (portRef CD (instanceRef FF_61))
+           (portRef CD (instanceRef FF_62))
+           (portRef CD (instanceRef FF_63))
+           (portRef CD (instanceRef FF_64))
+           (portRef CD (instanceRef FF_65))
+           (portRef CD (instanceRef FF_66))
+           (portRef CD (instanceRef FF_67))
+           (portRef CD (instanceRef FF_68))
+           (portRef CD (instanceRef FF_69))
+           (portRef CD (instanceRef FF_70))
+           (portRef PD (instanceRef FF_71))
+          ))
+          (net wcount_0 (joined
+           (portRef Q (instanceRef FF_101))
+           (portRef A0 (instanceRef full_cmp_0))
+           (portRef A0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_81))
+           (portRef A (instanceRef XOR2_t17))
+          ))
+          (net wcount_1 (joined
+           (portRef Q (instanceRef FF_100))
+           (portRef A1 (instanceRef full_cmp_0))
+           (portRef A1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_80))
+           (portRef A (instanceRef XOR2_t16))
+           (portRef B (instanceRef XOR2_t17))
+          ))
+          (net w_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t17))
+           (portRef D (instanceRef FF_91))
+          ))
+          (net wcount_2 (joined
+           (portRef Q (instanceRef FF_99))
+           (portRef A0 (instanceRef full_cmp_1))
+           (portRef A0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_79))
+           (portRef A (instanceRef XOR2_t15))
+           (portRef B (instanceRef XOR2_t16))
+          ))
+          (net w_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t16))
+           (portRef D (instanceRef FF_90))
+          ))
+          (net wcount_3 (joined
+           (portRef Q (instanceRef FF_98))
+           (portRef A1 (instanceRef full_cmp_1))
+           (portRef A1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_78))
+           (portRef A (instanceRef XOR2_t14))
+           (portRef B (instanceRef XOR2_t15))
+          ))
+          (net w_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t15))
+           (portRef D (instanceRef FF_89))
+          ))
+          (net wcount_4 (joined
+           (portRef Q (instanceRef FF_97))
+           (portRef A0 (instanceRef full_cmp_2))
+           (portRef A0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_77))
+           (portRef A (instanceRef XOR2_t13))
+           (portRef B (instanceRef XOR2_t14))
+          ))
+          (net w_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t14))
+           (portRef D (instanceRef FF_88))
+          ))
+          (net wcount_5 (joined
+           (portRef Q (instanceRef FF_96))
+           (portRef A1 (instanceRef full_cmp_2))
+           (portRef A1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_76))
+           (portRef A (instanceRef XOR2_t12))
+           (portRef B (instanceRef XOR2_t13))
+          ))
+          (net w_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t13))
+           (portRef D (instanceRef FF_87))
+          ))
+          (net wcount_6 (joined
+           (portRef Q (instanceRef FF_95))
+           (portRef A0 (instanceRef full_cmp_3))
+           (portRef A0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_75))
+           (portRef A (instanceRef XOR2_t11))
+           (portRef B (instanceRef XOR2_t12))
+          ))
+          (net w_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t12))
+           (portRef D (instanceRef FF_86))
+          ))
+          (net wcount_7 (joined
+           (portRef Q (instanceRef FF_94))
+           (portRef A1 (instanceRef full_cmp_3))
+           (portRef A1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_74))
+           (portRef A (instanceRef XOR2_t10))
+           (portRef B (instanceRef XOR2_t11))
+          ))
+          (net w_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t11))
+           (portRef D (instanceRef FF_85))
+          ))
+          (net wcount_8 (joined
+           (portRef Q (instanceRef FF_93))
+           (portRef A0 (instanceRef full_cmp_4))
+           (portRef A0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_73))
+           (portRef A (instanceRef XOR2_t9))
+           (portRef B (instanceRef XOR2_t10))
+          ))
+          (net w_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t10))
+           (portRef D (instanceRef FF_84))
+          ))
+          (net wcount_9 (joined
+           (portRef Q (instanceRef FF_92))
+           (portRef A1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_72))
+           (portRef D (instanceRef FF_82))
+           (portRef AD2 (instanceRef LUT4_0))
+           (portRef AD2 (instanceRef LUT4_1))
+           (portRef B (instanceRef XOR2_t9))
+          ))
+          (net w_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t9))
+           (portRef D (instanceRef FF_83))
+          ))
+          (net rcount_0 (joined
+           (portRef Q (instanceRef FF_71))
+           (portRef A0 (instanceRef empty_cmp_0))
+           (portRef A0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_51))
+           (portRef A (instanceRef XOR2_t8))
+          ))
+          (net rcount_1 (joined
+           (portRef Q (instanceRef FF_70))
+           (portRef A1 (instanceRef empty_cmp_0))
+           (portRef A1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_50))
+           (portRef A (instanceRef XOR2_t7))
+           (portRef B (instanceRef XOR2_t8))
+          ))
+          (net r_gdata_0 (joined
+           (portRef Z (instanceRef XOR2_t8))
+           (portRef D (instanceRef FF_61))
+          ))
+          (net rcount_2 (joined
+           (portRef Q (instanceRef FF_69))
+           (portRef A0 (instanceRef empty_cmp_1))
+           (portRef A0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_49))
+           (portRef A (instanceRef XOR2_t6))
+           (portRef B (instanceRef XOR2_t7))
+          ))
+          (net r_gdata_1 (joined
+           (portRef Z (instanceRef XOR2_t7))
+           (portRef D (instanceRef FF_60))
+          ))
+          (net rcount_3 (joined
+           (portRef Q (instanceRef FF_68))
+           (portRef A1 (instanceRef empty_cmp_1))
+           (portRef A1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_48))
+           (portRef A (instanceRef XOR2_t5))
+           (portRef B (instanceRef XOR2_t6))
+          ))
+          (net r_gdata_2 (joined
+           (portRef Z (instanceRef XOR2_t6))
+           (portRef D (instanceRef FF_59))
+          ))
+          (net rcount_4 (joined
+           (portRef Q (instanceRef FF_67))
+           (portRef A0 (instanceRef empty_cmp_2))
+           (portRef A0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_47))
+           (portRef A (instanceRef XOR2_t4))
+           (portRef B (instanceRef XOR2_t5))
+          ))
+          (net r_gdata_3 (joined
+           (portRef Z (instanceRef XOR2_t5))
+           (portRef D (instanceRef FF_58))
+          ))
+          (net rcount_5 (joined
+           (portRef Q (instanceRef FF_66))
+           (portRef A1 (instanceRef empty_cmp_2))
+           (portRef A1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_46))
+           (portRef A (instanceRef XOR2_t3))
+           (portRef B (instanceRef XOR2_t4))
+          ))
+          (net r_gdata_4 (joined
+           (portRef Z (instanceRef XOR2_t4))
+           (portRef D (instanceRef FF_57))
+          ))
+          (net rcount_6 (joined
+           (portRef Q (instanceRef FF_65))
+           (portRef A0 (instanceRef empty_cmp_3))
+           (portRef A0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_45))
+           (portRef A (instanceRef XOR2_t2))
+           (portRef B (instanceRef XOR2_t3))
+          ))
+          (net r_gdata_5 (joined
+           (portRef Z (instanceRef XOR2_t3))
+           (portRef D (instanceRef FF_56))
+          ))
+          (net rcount_7 (joined
+           (portRef Q (instanceRef FF_64))
+           (portRef A1 (instanceRef empty_cmp_3))
+           (portRef A1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_44))
+           (portRef A (instanceRef XOR2_t1))
+           (portRef B (instanceRef XOR2_t2))
+          ))
+          (net r_gdata_6 (joined
+           (portRef Z (instanceRef XOR2_t2))
+           (portRef D (instanceRef FF_55))
+          ))
+          (net rcount_8 (joined
+           (portRef Q (instanceRef FF_63))
+           (portRef A0 (instanceRef empty_cmp_4))
+           (portRef A0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_43))
+           (portRef A (instanceRef XOR2_t0))
+           (portRef B (instanceRef XOR2_t1))
+          ))
+          (net r_gdata_7 (joined
+           (portRef Z (instanceRef XOR2_t1))
+           (portRef D (instanceRef FF_54))
+          ))
+          (net rcount_9 (joined
+           (portRef Q (instanceRef FF_62))
+           (portRef A1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_42))
+           (portRef D (instanceRef FF_52))
+           (portRef AD2 (instanceRef LUT4_2))
+           (portRef AD2 (instanceRef LUT4_3))
+           (portRef B (instanceRef XOR2_t0))
+          ))
+          (net r_gdata_8 (joined
+           (portRef Z (instanceRef XOR2_t0))
+           (portRef D (instanceRef FF_53))
+          ))
+          (net w_gcount_r29 (joined
+           (portRef Q (instanceRef FF_12))
+           (portRef AD1 (instanceRef LUT4_2))
+           (portRef AD1 (instanceRef LUT4_3))
+           (portRef AD1 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_21))
+           (portRef AD0 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r28 (joined
+           (portRef Q (instanceRef FF_13))
+           (portRef AD2 (instanceRef LUT4_20))
+           (portRef AD3 (instanceRef LUT4_21))
+           (portRef AD1 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r27 (joined
+           (portRef Q (instanceRef FF_14))
+           (portRef AD1 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_20))
+           (portRef AD2 (instanceRef LUT4_23))
+          ))
+          (net w_gcount_r26 (joined
+           (portRef Q (instanceRef FF_15))
+           (portRef AD1 (instanceRef LUT4_18))
+           (portRef AD2 (instanceRef LUT4_19))
+           (portRef AD3 (instanceRef LUT4_23))
+          ))
+          (net w_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_23))
+           (portRef B0 (instanceRef empty_cmp_3))
+           (portRef AD3 (instanceRef LUT4_14))
+           (portRef AD3 (instanceRef LUT4_15))
+           (portRef AD3 (instanceRef LUT4_16))
+           (portRef AD0 (instanceRef LUT4_17))
+          ))
+          (net w_gcount_r25 (joined
+           (portRef Q (instanceRef FF_16))
+           (portRef AD1 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_18))
+           (portRef AD3 (instanceRef LUT4_19))
+           (portRef AD0 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r24 (joined
+           (portRef Q (instanceRef FF_17))
+           (portRef AD2 (instanceRef LUT4_17))
+           (portRef AD3 (instanceRef LUT4_18))
+           (portRef AD1 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r23 (joined
+           (portRef Q (instanceRef FF_18))
+           (portRef AD3 (instanceRef LUT4_17))
+           (portRef AD2 (instanceRef LUT4_22))
+          ))
+          (net w_gcount_r22 (joined
+           (portRef Q (instanceRef FF_19))
+           (portRef AD3 (instanceRef LUT4_22))
+          ))
+          (net w_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_22))
+           (portRef AD2 (instanceRef LUT4_14))
+           (portRef AD2 (instanceRef LUT4_15))
+           (portRef AD2 (instanceRef LUT4_16))
+          ))
+          (net wcount_r8 (joined
+           (portRef DO0 (instanceRef LUT4_21))
+           (portRef B0 (instanceRef empty_cmp_4))
+           (portRef AD0 (instanceRef LUT4_19))
+          ))
+          (net wcount_r7 (joined
+           (portRef DO0 (instanceRef LUT4_20))
+           (portRef B1 (instanceRef empty_cmp_3))
+           (portRef AD0 (instanceRef LUT4_18))
+          ))
+          (net wcount_r5 (joined
+           (portRef DO0 (instanceRef LUT4_19))
+           (portRef B1 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r4 (joined
+           (portRef DO0 (instanceRef LUT4_18))
+           (portRef B0 (instanceRef empty_cmp_2))
+          ))
+          (net wcount_r3 (joined
+           (portRef DO0 (instanceRef LUT4_17))
+           (portRef B1 (instanceRef empty_cmp_1))
+          ))
+          (net wcount_r2 (joined
+           (portRef DO0 (instanceRef LUT4_16))
+           (portRef B0 (instanceRef empty_cmp_1))
+          ))
+          (net w_gcount_r21 (joined
+           (portRef Q (instanceRef FF_20))
+           (portRef AD0 (instanceRef LUT4_14))
+           (portRef AD1 (instanceRef LUT4_15))
+          ))
+          (net wcount_r1 (joined
+           (portRef DO0 (instanceRef LUT4_15))
+           (portRef B1 (instanceRef empty_cmp_0))
+          ))
+          (net w_gcount_r20 (joined
+           (portRef Q (instanceRef FF_21))
+           (portRef AD1 (instanceRef LUT4_14))
+          ))
+          (net wcount_r0 (joined
+           (portRef DO0 (instanceRef LUT4_14))
+           (portRef B0 (instanceRef empty_cmp_0))
+          ))
+          (net r_gcount_w29 (joined
+           (portRef Q (instanceRef FF_2))
+           (portRef AD1 (instanceRef LUT4_0))
+           (portRef AD1 (instanceRef LUT4_1))
+           (portRef AD1 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_11))
+           (portRef AD0 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w28 (joined
+           (portRef Q (instanceRef FF_3))
+           (portRef AD2 (instanceRef LUT4_10))
+           (portRef AD3 (instanceRef LUT4_11))
+           (portRef AD1 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w27 (joined
+           (portRef Q (instanceRef FF_4))
+           (portRef AD1 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_10))
+           (portRef AD2 (instanceRef LUT4_13))
+          ))
+          (net r_gcount_w26 (joined
+           (portRef Q (instanceRef FF_5))
+           (portRef AD1 (instanceRef LUT4_8))
+           (portRef AD2 (instanceRef LUT4_9))
+           (portRef AD3 (instanceRef LUT4_13))
+          ))
+          (net r_g2b_xor_cluster_0 (joined
+           (portRef DO0 (instanceRef LUT4_13))
+           (portRef B0 (instanceRef full_cmp_3))
+           (portRef AD3 (instanceRef LUT4_4))
+           (portRef AD3 (instanceRef LUT4_5))
+           (portRef AD3 (instanceRef LUT4_6))
+           (portRef AD0 (instanceRef LUT4_7))
+          ))
+          (net r_gcount_w25 (joined
+           (portRef Q (instanceRef FF_6))
+           (portRef AD1 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_8))
+           (portRef AD3 (instanceRef LUT4_9))
+           (portRef AD0 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w24 (joined
+           (portRef Q (instanceRef FF_7))
+           (portRef AD2 (instanceRef LUT4_7))
+           (portRef AD3 (instanceRef LUT4_8))
+           (portRef AD1 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w23 (joined
+           (portRef Q (instanceRef FF_8))
+           (portRef AD3 (instanceRef LUT4_7))
+           (portRef AD2 (instanceRef LUT4_12))
+          ))
+          (net r_gcount_w22 (joined
+           (portRef Q (instanceRef FF_9))
+           (portRef AD3 (instanceRef LUT4_12))
+          ))
+          (net r_g2b_xor_cluster_1 (joined
+           (portRef DO0 (instanceRef LUT4_12))
+           (portRef AD2 (instanceRef LUT4_4))
+           (portRef AD2 (instanceRef LUT4_5))
+           (portRef AD2 (instanceRef LUT4_6))
+          ))
+          (net rcount_w8 (joined
+           (portRef DO0 (instanceRef LUT4_11))
+           (portRef B0 (instanceRef full_cmp_4))
+           (portRef AD0 (instanceRef LUT4_9))
+          ))
+          (net rcount_w7 (joined
+           (portRef DO0 (instanceRef LUT4_10))
+           (portRef B1 (instanceRef full_cmp_3))
+           (portRef AD0 (instanceRef LUT4_8))
+          ))
+          (net rcount_w5 (joined
+           (portRef DO0 (instanceRef LUT4_9))
+           (portRef B1 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w4 (joined
+           (portRef DO0 (instanceRef LUT4_8))
+           (portRef B0 (instanceRef full_cmp_2))
+          ))
+          (net rcount_w3 (joined
+           (portRef DO0 (instanceRef LUT4_7))
+           (portRef B1 (instanceRef full_cmp_1))
+          ))
+          (net rcount_w2 (joined
+           (portRef DO0 (instanceRef LUT4_6))
+           (portRef B0 (instanceRef full_cmp_1))
+          ))
+          (net r_gcount_w21 (joined
+           (portRef Q (instanceRef FF_10))
+           (portRef AD0 (instanceRef LUT4_4))
+           (portRef AD1 (instanceRef LUT4_5))
+          ))
+          (net rcount_w1 (joined
+           (portRef DO0 (instanceRef LUT4_5))
+           (portRef B1 (instanceRef full_cmp_0))
+          ))
+          (net r_gcount_w20 (joined
+           (portRef Q (instanceRef FF_11))
+           (portRef AD1 (instanceRef LUT4_4))
+          ))
+          (net rcount_w0 (joined
+           (portRef DO0 (instanceRef LUT4_4))
+           (portRef B0 (instanceRef full_cmp_0))
+          ))
+          (net rptr_9 (joined
+           (portRef Q (instanceRef FF_42))
+           (portRef AD3 (instanceRef LUT4_2))
+           (portRef AD3 (instanceRef LUT4_3))
+          ))
+          (net empty_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_3))
+           (portRef A1 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_2))
+           (portRef B1 (instanceRef empty_cmp_4))
+          ))
+          (net wptr_9 (joined
+           (portRef Q (instanceRef FF_72))
+           (portRef AD3 (instanceRef LUT4_0))
+           (portRef AD3 (instanceRef LUT4_1))
+          ))
+          (net full_cmp_set (joined
+           (portRef DO0 (instanceRef LUT4_1))
+           (portRef A1 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_clr (joined
+           (portRef DO0 (instanceRef LUT4_0))
+           (portRef B1 (instanceRef full_cmp_4))
+          ))
+          (net (rename data_buffer_0 "data_buffer[0]") (joined
+           (portRef (member data_buffer 33))
+           (portRef DI0 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_1 "data_buffer[1]") (joined
+           (portRef (member data_buffer 32))
+           (portRef DI1 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_2 "data_buffer[2]") (joined
+           (portRef (member data_buffer 31))
+           (portRef DI2 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_3 "data_buffer[3]") (joined
+           (portRef (member data_buffer 30))
+           (portRef DI3 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_4 "data_buffer[4]") (joined
+           (portRef (member data_buffer 29))
+           (portRef DI4 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_5 "data_buffer[5]") (joined
+           (portRef (member data_buffer 28))
+           (portRef DI5 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_6 "data_buffer[6]") (joined
+           (portRef (member data_buffer 27))
+           (portRef DI6 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_7 "data_buffer[7]") (joined
+           (portRef (member data_buffer 26))
+           (portRef DI7 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_8 "data_buffer[8]") (joined
+           (portRef (member data_buffer 25))
+           (portRef DI8 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_9 "data_buffer[9]") (joined
+           (portRef (member data_buffer 24))
+           (portRef DI9 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_10 "data_buffer[10]") (joined
+           (portRef (member data_buffer 23))
+           (portRef DI10 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_11 "data_buffer[11]") (joined
+           (portRef (member data_buffer 22))
+           (portRef DI11 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_12 "data_buffer[12]") (joined
+           (portRef (member data_buffer 21))
+           (portRef DI12 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_13 "data_buffer[13]") (joined
+           (portRef (member data_buffer 20))
+           (portRef DI13 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_14 "data_buffer[14]") (joined
+           (portRef (member data_buffer 19))
+           (portRef DI14 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_15 "data_buffer[15]") (joined
+           (portRef (member data_buffer 18))
+           (portRef DI15 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_16 "data_buffer[16]") (joined
+           (portRef (member data_buffer 17))
+           (portRef DI16 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_17 "data_buffer[17]") (joined
+           (portRef (member data_buffer 16))
+           (portRef DI17 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_18 "data_buffer[18]") (joined
+           (portRef (member data_buffer 15))
+           (portRef DI18 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_19 "data_buffer[19]") (joined
+           (portRef (member data_buffer 14))
+           (portRef DI19 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_20 "data_buffer[20]") (joined
+           (portRef (member data_buffer 13))
+           (portRef DI20 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_21 "data_buffer[21]") (joined
+           (portRef (member data_buffer 12))
+           (portRef DI21 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_22 "data_buffer[22]") (joined
+           (portRef (member data_buffer 11))
+           (portRef DI22 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_23 "data_buffer[23]") (joined
+           (portRef (member data_buffer 10))
+           (portRef DI23 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_24 "data_buffer[24]") (joined
+           (portRef (member data_buffer 9))
+           (portRef DI24 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_25 "data_buffer[25]") (joined
+           (portRef (member data_buffer 8))
+           (portRef DI25 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_26 "data_buffer[26]") (joined
+           (portRef (member data_buffer 7))
+           (portRef DI26 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_27 "data_buffer[27]") (joined
+           (portRef (member data_buffer 6))
+           (portRef DI27 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_28 "data_buffer[28]") (joined
+           (portRef (member data_buffer 5))
+           (portRef DI28 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_29 "data_buffer[29]") (joined
+           (portRef (member data_buffer 4))
+           (portRef DI29 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_30 "data_buffer[30]") (joined
+           (portRef (member data_buffer 3))
+           (portRef DI30 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_31 "data_buffer[31]") (joined
+           (portRef (member data_buffer 2))
+           (portRef DI31 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_32 "data_buffer[32]") (joined
+           (portRef (member data_buffer 1))
+           (portRef DI32 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename data_buffer_33 "data_buffer[33]") (joined
+           (portRef (member data_buffer 0))
+           (portRef DI33 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_0 (joined
+           (portRef Q (instanceRef FF_81))
+           (portRef ADW0 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_1 (joined
+           (portRef Q (instanceRef FF_80))
+           (portRef ADW1 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_2 (joined
+           (portRef Q (instanceRef FF_79))
+           (portRef ADW2 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_3 (joined
+           (portRef Q (instanceRef FF_78))
+           (portRef ADW3 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_4 (joined
+           (portRef Q (instanceRef FF_77))
+           (portRef ADW4 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_5 (joined
+           (portRef Q (instanceRef FF_76))
+           (portRef ADW5 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_6 (joined
+           (portRef Q (instanceRef FF_75))
+           (portRef ADW6 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_7 (joined
+           (portRef Q (instanceRef FF_74))
+           (portRef ADW7 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net wptr_8 (joined
+           (portRef Q (instanceRef FF_73))
+           (portRef ADW8 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef a1))
+           (portRef C1 (instanceRef a1))
+           (portRef D0 (instanceRef a1))
+           (portRef C0 (instanceRef a1))
+           (portRef D1 (instanceRef full_cmp_4))
+           (portRef C1 (instanceRef full_cmp_4))
+           (portRef D0 (instanceRef full_cmp_4))
+           (portRef C0 (instanceRef full_cmp_4))
+           (portRef D1 (instanceRef full_cmp_3))
+           (portRef C1 (instanceRef full_cmp_3))
+           (portRef D0 (instanceRef full_cmp_3))
+           (portRef C0 (instanceRef full_cmp_3))
+           (portRef D1 (instanceRef full_cmp_2))
+           (portRef C1 (instanceRef full_cmp_2))
+           (portRef D0 (instanceRef full_cmp_2))
+           (portRef C0 (instanceRef full_cmp_2))
+           (portRef D1 (instanceRef full_cmp_1))
+           (portRef C1 (instanceRef full_cmp_1))
+           (portRef D0 (instanceRef full_cmp_1))
+           (portRef C0 (instanceRef full_cmp_1))
+           (portRef D1 (instanceRef full_cmp_0))
+           (portRef C1 (instanceRef full_cmp_0))
+           (portRef D0 (instanceRef full_cmp_0))
+           (portRef C0 (instanceRef full_cmp_0))
+           (portRef D1 (instanceRef full_cmp_ci_a))
+           (portRef C1 (instanceRef full_cmp_ci_a))
+           (portRef D0 (instanceRef full_cmp_ci_a))
+           (portRef C0 (instanceRef full_cmp_ci_a))
+           (portRef D1 (instanceRef a0))
+           (portRef C1 (instanceRef a0))
+           (portRef D0 (instanceRef a0))
+           (portRef C0 (instanceRef a0))
+           (portRef D1 (instanceRef empty_cmp_4))
+           (portRef C1 (instanceRef empty_cmp_4))
+           (portRef D0 (instanceRef empty_cmp_4))
+           (portRef C0 (instanceRef empty_cmp_4))
+           (portRef D1 (instanceRef empty_cmp_3))
+           (portRef C1 (instanceRef empty_cmp_3))
+           (portRef D0 (instanceRef empty_cmp_3))
+           (portRef C0 (instanceRef empty_cmp_3))
+           (portRef D1 (instanceRef empty_cmp_2))
+           (portRef C1 (instanceRef empty_cmp_2))
+           (portRef D0 (instanceRef empty_cmp_2))
+           (portRef C0 (instanceRef empty_cmp_2))
+           (portRef D1 (instanceRef empty_cmp_1))
+           (portRef C1 (instanceRef empty_cmp_1))
+           (portRef D0 (instanceRef empty_cmp_1))
+           (portRef C0 (instanceRef empty_cmp_1))
+           (portRef D1 (instanceRef empty_cmp_0))
+           (portRef C1 (instanceRef empty_cmp_0))
+           (portRef D0 (instanceRef empty_cmp_0))
+           (portRef C0 (instanceRef empty_cmp_0))
+           (portRef D1 (instanceRef empty_cmp_ci_a))
+           (portRef C1 (instanceRef empty_cmp_ci_a))
+           (portRef D0 (instanceRef empty_cmp_ci_a))
+           (portRef C0 (instanceRef empty_cmp_ci_a))
+           (portRef D1 (instanceRef r_gctr_4))
+           (portRef C1 (instanceRef r_gctr_4))
+           (portRef D0 (instanceRef r_gctr_4))
+           (portRef C0 (instanceRef r_gctr_4))
+           (portRef D1 (instanceRef r_gctr_3))
+           (portRef C1 (instanceRef r_gctr_3))
+           (portRef D0 (instanceRef r_gctr_3))
+           (portRef C0 (instanceRef r_gctr_3))
+           (portRef D1 (instanceRef r_gctr_2))
+           (portRef C1 (instanceRef r_gctr_2))
+           (portRef D0 (instanceRef r_gctr_2))
+           (portRef C0 (instanceRef r_gctr_2))
+           (portRef D1 (instanceRef r_gctr_1))
+           (portRef C1 (instanceRef r_gctr_1))
+           (portRef D0 (instanceRef r_gctr_1))
+           (portRef C0 (instanceRef r_gctr_1))
+           (portRef D1 (instanceRef r_gctr_0))
+           (portRef C1 (instanceRef r_gctr_0))
+           (portRef D0 (instanceRef r_gctr_0))
+           (portRef C0 (instanceRef r_gctr_0))
+           (portRef D1 (instanceRef r_gctr_cia))
+           (portRef C1 (instanceRef r_gctr_cia))
+           (portRef B1 (instanceRef r_gctr_cia))
+           (portRef A1 (instanceRef r_gctr_cia))
+           (portRef D0 (instanceRef r_gctr_cia))
+           (portRef C0 (instanceRef r_gctr_cia))
+           (portRef D1 (instanceRef w_gctr_4))
+           (portRef C1 (instanceRef w_gctr_4))
+           (portRef D0 (instanceRef w_gctr_4))
+           (portRef C0 (instanceRef w_gctr_4))
+           (portRef D1 (instanceRef w_gctr_3))
+           (portRef C1 (instanceRef w_gctr_3))
+           (portRef D0 (instanceRef w_gctr_3))
+           (portRef C0 (instanceRef w_gctr_3))
+           (portRef D1 (instanceRef w_gctr_2))
+           (portRef C1 (instanceRef w_gctr_2))
+           (portRef D0 (instanceRef w_gctr_2))
+           (portRef C0 (instanceRef w_gctr_2))
+           (portRef D1 (instanceRef w_gctr_1))
+           (portRef C1 (instanceRef w_gctr_1))
+           (portRef D0 (instanceRef w_gctr_1))
+           (portRef C0 (instanceRef w_gctr_1))
+           (portRef D1 (instanceRef w_gctr_0))
+           (portRef C1 (instanceRef w_gctr_0))
+           (portRef D0 (instanceRef w_gctr_0))
+           (portRef C0 (instanceRef w_gctr_0))
+           (portRef D1 (instanceRef w_gctr_cia))
+           (portRef C1 (instanceRef w_gctr_cia))
+           (portRef B1 (instanceRef w_gctr_cia))
+           (portRef A1 (instanceRef w_gctr_cia))
+           (portRef D0 (instanceRef w_gctr_cia))
+           (portRef C0 (instanceRef w_gctr_cia))
+           (portRef CSW0 (instanceRef pdp_ram_0_0_1))
+           (portRef BE3 (instanceRef pdp_ram_0_0_1))
+           (portRef BE2 (instanceRef pdp_ram_0_0_1))
+           (portRef BE1 (instanceRef pdp_ram_0_0_1))
+           (portRef BE0 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef CK (instanceRef FF_0))
+           (portRef CK (instanceRef FF_2))
+           (portRef CK (instanceRef FF_3))
+           (portRef CK (instanceRef FF_4))
+           (portRef CK (instanceRef FF_5))
+           (portRef CK (instanceRef FF_6))
+           (portRef CK (instanceRef FF_7))
+           (portRef CK (instanceRef FF_8))
+           (portRef CK (instanceRef FF_9))
+           (portRef CK (instanceRef FF_10))
+           (portRef CK (instanceRef FF_11))
+           (portRef CK (instanceRef FF_22))
+           (portRef CK (instanceRef FF_23))
+           (portRef CK (instanceRef FF_24))
+           (portRef CK (instanceRef FF_25))
+           (portRef CK (instanceRef FF_26))
+           (portRef CK (instanceRef FF_27))
+           (portRef CK (instanceRef FF_28))
+           (portRef CK (instanceRef FF_29))
+           (portRef CK (instanceRef FF_30))
+           (portRef CK (instanceRef FF_31))
+           (portRef CK (instanceRef FF_72))
+           (portRef CK (instanceRef FF_73))
+           (portRef CK (instanceRef FF_74))
+           (portRef CK (instanceRef FF_75))
+           (portRef CK (instanceRef FF_76))
+           (portRef CK (instanceRef FF_77))
+           (portRef CK (instanceRef FF_78))
+           (portRef CK (instanceRef FF_79))
+           (portRef CK (instanceRef FF_80))
+           (portRef CK (instanceRef FF_81))
+           (portRef CK (instanceRef FF_82))
+           (portRef CK (instanceRef FF_83))
+           (portRef CK (instanceRef FF_84))
+           (portRef CK (instanceRef FF_85))
+           (portRef CK (instanceRef FF_86))
+           (portRef CK (instanceRef FF_87))
+           (portRef CK (instanceRef FF_88))
+           (portRef CK (instanceRef FF_89))
+           (portRef CK (instanceRef FF_90))
+           (portRef CK (instanceRef FF_91))
+           (portRef CK (instanceRef FF_92))
+           (portRef CK (instanceRef FF_93))
+           (portRef CK (instanceRef FF_94))
+           (portRef CK (instanceRef FF_95))
+           (portRef CK (instanceRef FF_96))
+           (portRef CK (instanceRef FF_97))
+           (portRef CK (instanceRef FF_98))
+           (portRef CK (instanceRef FF_99))
+           (portRef CK (instanceRef FF_100))
+           (portRef CK (instanceRef FF_101))
+           (portRef CLKW (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_0 (joined
+           (portRef Q (instanceRef FF_51))
+           (portRef ADR5 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_1 (joined
+           (portRef Q (instanceRef FF_50))
+           (portRef ADR6 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_2 (joined
+           (portRef Q (instanceRef FF_49))
+           (portRef ADR7 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_3 (joined
+           (portRef Q (instanceRef FF_48))
+           (portRef ADR8 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_4 (joined
+           (portRef Q (instanceRef FF_47))
+           (portRef ADR9 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_5 (joined
+           (portRef Q (instanceRef FF_46))
+           (portRef ADR10 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_6 (joined
+           (portRef Q (instanceRef FF_45))
+           (portRef ADR11 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_7 (joined
+           (portRef Q (instanceRef FF_44))
+           (portRef ADR12 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rptr_8 (joined
+           (portRef Q (instanceRef FF_43))
+           (portRef ADR13 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net rd_clk_c (joined
+           (portRef rd_clk_c)
+           (portRef CK (instanceRef FF_1))
+           (portRef CK (instanceRef FF_12))
+           (portRef CK (instanceRef FF_13))
+           (portRef CK (instanceRef FF_14))
+           (portRef CK (instanceRef FF_15))
+           (portRef CK (instanceRef FF_16))
+           (portRef CK (instanceRef FF_17))
+           (portRef CK (instanceRef FF_18))
+           (portRef CK (instanceRef FF_19))
+           (portRef CK (instanceRef FF_20))
+           (portRef CK (instanceRef FF_21))
+           (portRef CK (instanceRef FF_32))
+           (portRef CK (instanceRef FF_33))
+           (portRef CK (instanceRef FF_34))
+           (portRef CK (instanceRef FF_35))
+           (portRef CK (instanceRef FF_36))
+           (portRef CK (instanceRef FF_37))
+           (portRef CK (instanceRef FF_38))
+           (portRef CK (instanceRef FF_39))
+           (portRef CK (instanceRef FF_40))
+           (portRef CK (instanceRef FF_41))
+           (portRef CK (instanceRef FF_42))
+           (portRef CK (instanceRef FF_43))
+           (portRef CK (instanceRef FF_44))
+           (portRef CK (instanceRef FF_45))
+           (portRef CK (instanceRef FF_46))
+           (portRef CK (instanceRef FF_47))
+           (portRef CK (instanceRef FF_48))
+           (portRef CK (instanceRef FF_49))
+           (portRef CK (instanceRef FF_50))
+           (portRef CK (instanceRef FF_51))
+           (portRef CK (instanceRef FF_52))
+           (portRef CK (instanceRef FF_53))
+           (portRef CK (instanceRef FF_54))
+           (portRef CK (instanceRef FF_55))
+           (portRef CK (instanceRef FF_56))
+           (portRef CK (instanceRef FF_57))
+           (portRef CK (instanceRef FF_58))
+           (portRef CK (instanceRef FF_59))
+           (portRef CK (instanceRef FF_60))
+           (portRef CK (instanceRef FF_61))
+           (portRef CK (instanceRef FF_62))
+           (portRef CK (instanceRef FF_63))
+           (portRef CK (instanceRef FF_64))
+           (portRef CK (instanceRef FF_65))
+           (portRef CK (instanceRef FF_66))
+           (portRef CK (instanceRef FF_67))
+           (portRef CK (instanceRef FF_68))
+           (portRef CK (instanceRef FF_69))
+           (portRef CK (instanceRef FF_70))
+           (portRef CK (instanceRef FF_71))
+           (portRef CLKR (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename FEE_DATA_OUT_c_18 "FEE_DATA_OUT_c[18]") (joined
+           (portRef DO0 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 13))
+          ))
+          (net (rename FEE_DATA_OUT_c_19 "FEE_DATA_OUT_c[19]") (joined
+           (portRef DO1 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 12))
+          ))
+          (net (rename FEE_DATA_OUT_c_20 "FEE_DATA_OUT_c[20]") (joined
+           (portRef DO2 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 11))
+          ))
+          (net (rename FEE_DATA_OUT_c_21 "FEE_DATA_OUT_c[21]") (joined
+           (portRef DO3 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 10))
+          ))
+          (net (rename FEE_DATA_OUT_c_22 "FEE_DATA_OUT_c[22]") (joined
+           (portRef DO4 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 9))
+          ))
+          (net (rename FEE_DATA_OUT_c_23 "FEE_DATA_OUT_c[23]") (joined
+           (portRef DO5 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 8))
+          ))
+          (net (rename FEE_DATA_OUT_c_24 "FEE_DATA_OUT_c[24]") (joined
+           (portRef DO6 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 7))
+          ))
+          (net (rename FEE_DATA_OUT_c_25 "FEE_DATA_OUT_c[25]") (joined
+           (portRef DO7 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 6))
+          ))
+          (net (rename FEE_DATA_OUT_c_26 "FEE_DATA_OUT_c[26]") (joined
+           (portRef DO8 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 5))
+          ))
+          (net (rename FEE_DATA_OUT_c_27 "FEE_DATA_OUT_c[27]") (joined
+           (portRef DO9 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 4))
+          ))
+          (net (rename FEE_DATA_OUT_c_28 "FEE_DATA_OUT_c[28]") (joined
+           (portRef DO10 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 3))
+          ))
+          (net (rename FEE_DATA_OUT_c_29 "FEE_DATA_OUT_c[29]") (joined
+           (portRef DO11 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 2))
+          ))
+          (net (rename FEE_DATA_OUT_c_30 "FEE_DATA_OUT_c[30]") (joined
+           (portRef DO12 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 1))
+          ))
+          (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined
+           (portRef DO13 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 0))
+          ))
+          (net (rename Q_1_32 "Q_1[32]") (joined
+           (portRef DO14 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename Q_1_33 "Q_1[33]") (joined
+           (portRef DO15 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename Q_1_34 "Q_1[34]") (joined
+           (portRef DO16 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename Q_1_35 "Q_1[35]") (joined
+           (portRef DO17 (instanceRef pdp_ram_0_0_1))
+          ))
+          (net (rename FEE_DATA_OUT_c_0 "FEE_DATA_OUT_c[0]") (joined
+           (portRef DO18 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 31))
+          ))
+          (net (rename FEE_DATA_OUT_c_1 "FEE_DATA_OUT_c[1]") (joined
+           (portRef DO19 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 30))
+          ))
+          (net (rename FEE_DATA_OUT_c_2 "FEE_DATA_OUT_c[2]") (joined
+           (portRef DO20 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 29))
+          ))
+          (net (rename FEE_DATA_OUT_c_3 "FEE_DATA_OUT_c[3]") (joined
+           (portRef DO21 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 28))
+          ))
+          (net (rename FEE_DATA_OUT_c_4 "FEE_DATA_OUT_c[4]") (joined
+           (portRef DO22 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 27))
+          ))
+          (net (rename FEE_DATA_OUT_c_5 "FEE_DATA_OUT_c[5]") (joined
+           (portRef DO23 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 26))
+          ))
+          (net (rename FEE_DATA_OUT_c_6 "FEE_DATA_OUT_c[6]") (joined
+           (portRef DO24 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 25))
+          ))
+          (net (rename FEE_DATA_OUT_c_7 "FEE_DATA_OUT_c[7]") (joined
+           (portRef DO25 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 24))
+          ))
+          (net (rename FEE_DATA_OUT_c_8 "FEE_DATA_OUT_c[8]") (joined
+           (portRef DO26 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 23))
+          ))
+          (net (rename FEE_DATA_OUT_c_9 "FEE_DATA_OUT_c[9]") (joined
+           (portRef DO27 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 22))
+          ))
+          (net (rename FEE_DATA_OUT_c_10 "FEE_DATA_OUT_c[10]") (joined
+           (portRef DO28 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 21))
+          ))
+          (net (rename FEE_DATA_OUT_c_11 "FEE_DATA_OUT_c[11]") (joined
+           (portRef DO29 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 20))
+          ))
+          (net (rename FEE_DATA_OUT_c_12 "FEE_DATA_OUT_c[12]") (joined
+           (portRef DO30 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 19))
+          ))
+          (net (rename FEE_DATA_OUT_c_13 "FEE_DATA_OUT_c[13]") (joined
+           (portRef DO31 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 18))
+          ))
+          (net (rename FEE_DATA_OUT_c_14 "FEE_DATA_OUT_c[14]") (joined
+           (portRef DO32 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 17))
+          ))
+          (net (rename FEE_DATA_OUT_c_15 "FEE_DATA_OUT_c[15]") (joined
+           (portRef DO33 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 16))
+          ))
+          (net (rename FEE_DATA_OUT_c_16 "FEE_DATA_OUT_c[16]") (joined
+           (portRef DO34 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 15))
+          ))
+          (net (rename FEE_DATA_OUT_c_17 "FEE_DATA_OUT_c[17]") (joined
+           (portRef DO35 (instanceRef pdp_ram_0_0_1))
+           (portRef (member fee_data_out_c 14))
+          ))
+          (net iwcount_0 (joined
+           (portRef S0 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_101))
+          ))
+          (net iwcount_1 (joined
+           (portRef S1 (instanceRef w_gctr_0))
+           (portRef D (instanceRef FF_100))
+          ))
+          (net iwcount_2 (joined
+           (portRef S0 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_99))
+          ))
+          (net iwcount_3 (joined
+           (portRef S1 (instanceRef w_gctr_1))
+           (portRef D (instanceRef FF_98))
+          ))
+          (net iwcount_4 (joined
+           (portRef S0 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_97))
+          ))
+          (net iwcount_5 (joined
+           (portRef S1 (instanceRef w_gctr_2))
+           (portRef D (instanceRef FF_96))
+          ))
+          (net iwcount_6 (joined
+           (portRef S0 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_95))
+          ))
+          (net iwcount_7 (joined
+           (portRef S1 (instanceRef w_gctr_3))
+           (portRef D (instanceRef FF_94))
+          ))
+          (net iwcount_8 (joined
+           (portRef S0 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_93))
+          ))
+          (net iwcount_9 (joined
+           (portRef S1 (instanceRef w_gctr_4))
+           (portRef D (instanceRef FF_92))
+          ))
+          (net w_gcount_0 (joined
+           (portRef Q (instanceRef FF_91))
+           (portRef D (instanceRef FF_41))
+          ))
+          (net w_gcount_1 (joined
+           (portRef Q (instanceRef FF_90))
+           (portRef D (instanceRef FF_40))
+          ))
+          (net w_gcount_2 (joined
+           (portRef Q (instanceRef FF_89))
+           (portRef D (instanceRef FF_39))
+          ))
+          (net w_gcount_3 (joined
+           (portRef Q (instanceRef FF_88))
+           (portRef D (instanceRef FF_38))
+          ))
+          (net w_gcount_4 (joined
+           (portRef Q (instanceRef FF_87))
+           (portRef D (instanceRef FF_37))
+          ))
+          (net w_gcount_5 (joined
+           (portRef Q (instanceRef FF_86))
+           (portRef D (instanceRef FF_36))
+          ))
+          (net w_gcount_6 (joined
+           (portRef Q (instanceRef FF_85))
+           (portRef D (instanceRef FF_35))
+          ))
+          (net w_gcount_7 (joined
+           (portRef Q (instanceRef FF_84))
+           (portRef D (instanceRef FF_34))
+          ))
+          (net w_gcount_8 (joined
+           (portRef Q (instanceRef FF_83))
+           (portRef D (instanceRef FF_33))
+          ))
+          (net w_gcount_9 (joined
+           (portRef Q (instanceRef FF_82))
+           (portRef D (instanceRef FF_32))
+          ))
+          (net ircount_0 (joined
+           (portRef S0 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_71))
+          ))
+          (net ircount_1 (joined
+           (portRef S1 (instanceRef r_gctr_0))
+           (portRef D (instanceRef FF_70))
+          ))
+          (net ircount_2 (joined
+           (portRef S0 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_69))
+          ))
+          (net ircount_3 (joined
+           (portRef S1 (instanceRef r_gctr_1))
+           (portRef D (instanceRef FF_68))
+          ))
+          (net ircount_4 (joined
+           (portRef S0 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_67))
+          ))
+          (net ircount_5 (joined
+           (portRef S1 (instanceRef r_gctr_2))
+           (portRef D (instanceRef FF_66))
+          ))
+          (net ircount_6 (joined
+           (portRef S0 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_65))
+          ))
+          (net ircount_7 (joined
+           (portRef S1 (instanceRef r_gctr_3))
+           (portRef D (instanceRef FF_64))
+          ))
+          (net ircount_8 (joined
+           (portRef S0 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_63))
+          ))
+          (net ircount_9 (joined
+           (portRef S1 (instanceRef r_gctr_4))
+           (portRef D (instanceRef FF_62))
+          ))
+          (net r_gcount_0 (joined
+           (portRef Q (instanceRef FF_61))
+           (portRef D (instanceRef FF_31))
+          ))
+          (net r_gcount_1 (joined
+           (portRef Q (instanceRef FF_60))
+           (portRef D (instanceRef FF_30))
+          ))
+          (net r_gcount_2 (joined
+           (portRef Q (instanceRef FF_59))
+           (portRef D (instanceRef FF_29))
+          ))
+          (net r_gcount_3 (joined
+           (portRef Q (instanceRef FF_58))
+           (portRef D (instanceRef FF_28))
+          ))
+          (net r_gcount_4 (joined
+           (portRef Q (instanceRef FF_57))
+           (portRef D (instanceRef FF_27))
+          ))
+          (net r_gcount_5 (joined
+           (portRef Q (instanceRef FF_56))
+           (portRef D (instanceRef FF_26))
+          ))
+          (net r_gcount_6 (joined
+           (portRef Q (instanceRef FF_55))
+           (portRef D (instanceRef FF_25))
+          ))
+          (net r_gcount_7 (joined
+           (portRef Q (instanceRef FF_54))
+           (portRef D (instanceRef FF_24))
+          ))
+          (net r_gcount_8 (joined
+           (portRef Q (instanceRef FF_53))
+           (portRef D (instanceRef FF_23))
+          ))
+          (net r_gcount_9 (joined
+           (portRef Q (instanceRef FF_52))
+           (portRef D (instanceRef FF_22))
+          ))
+          (net w_gcount_r0 (joined
+           (portRef Q (instanceRef FF_41))
+           (portRef D (instanceRef FF_21))
+          ))
+          (net w_gcount_r1 (joined
+           (portRef Q (instanceRef FF_40))
+           (portRef D (instanceRef FF_20))
+          ))
+          (net w_gcount_r2 (joined
+           (portRef Q (instanceRef FF_39))
+           (portRef D (instanceRef FF_19))
+          ))
+          (net w_gcount_r3 (joined
+           (portRef Q (instanceRef FF_38))
+           (portRef D (instanceRef FF_18))
+          ))
+          (net w_gcount_r4 (joined
+           (portRef Q (instanceRef FF_37))
+           (portRef D (instanceRef FF_17))
+          ))
+          (net w_gcount_r5 (joined
+           (portRef Q (instanceRef FF_36))
+           (portRef D (instanceRef FF_16))
+          ))
+          (net w_gcount_r6 (joined
+           (portRef Q (instanceRef FF_35))
+           (portRef D (instanceRef FF_15))
+          ))
+          (net w_gcount_r7 (joined
+           (portRef Q (instanceRef FF_34))
+           (portRef D (instanceRef FF_14))
+          ))
+          (net w_gcount_r8 (joined
+           (portRef Q (instanceRef FF_33))
+           (portRef D (instanceRef FF_13))
+          ))
+          (net w_gcount_r9 (joined
+           (portRef Q (instanceRef FF_32))
+           (portRef D (instanceRef FF_12))
+          ))
+          (net r_gcount_w0 (joined
+           (portRef Q (instanceRef FF_31))
+           (portRef D (instanceRef FF_11))
+          ))
+          (net r_gcount_w1 (joined
+           (portRef Q (instanceRef FF_30))
+           (portRef D (instanceRef FF_10))
+          ))
+          (net r_gcount_w2 (joined
+           (portRef Q (instanceRef FF_29))
+           (portRef D (instanceRef FF_9))
+          ))
+          (net r_gcount_w3 (joined
+           (portRef Q (instanceRef FF_28))
+           (portRef D (instanceRef FF_8))
+          ))
+          (net r_gcount_w4 (joined
+           (portRef Q (instanceRef FF_27))
+           (portRef D (instanceRef FF_7))
+          ))
+          (net r_gcount_w5 (joined
+           (portRef Q (instanceRef FF_26))
+           (portRef D (instanceRef FF_6))
+          ))
+          (net r_gcount_w6 (joined
+           (portRef Q (instanceRef FF_25))
+           (portRef D (instanceRef FF_5))
+          ))
+          (net r_gcount_w7 (joined
+           (portRef Q (instanceRef FF_24))
+           (portRef D (instanceRef FF_4))
+          ))
+          (net r_gcount_w8 (joined
+           (portRef Q (instanceRef FF_23))
+           (portRef D (instanceRef FF_3))
+          ))
+          (net r_gcount_w9 (joined
+           (portRef Q (instanceRef FF_22))
+           (portRef D (instanceRef FF_2))
+          ))
+          (net empty_d (joined
+           (portRef S0 (instanceRef a0))
+           (portRef D (instanceRef FF_1))
+          ))
+          (net full_d (joined
+           (portRef S0 (instanceRef a1))
+           (portRef D (instanceRef FF_0))
+          ))
+          (net w_gctr_ci (joined
+           (portRef COUT (instanceRef w_gctr_cia))
+           (portRef CIN (instanceRef w_gctr_0))
+          ))
+          (net w_gctr_cia_S0_2 (joined
+           (portRef S0 (instanceRef w_gctr_cia))
+          ))
+          (net w_gctr_cia_S1_2 (joined
+           (portRef S1 (instanceRef w_gctr_cia))
+          ))
+          (net co0 (joined
+           (portRef COUT (instanceRef w_gctr_0))
+           (portRef CIN (instanceRef w_gctr_1))
+          ))
+          (net co1 (joined
+           (portRef COUT (instanceRef w_gctr_1))
+           (portRef CIN (instanceRef w_gctr_2))
+          ))
+          (net co2 (joined
+           (portRef COUT (instanceRef w_gctr_2))
+           (portRef CIN (instanceRef w_gctr_3))
+          ))
+          (net co3 (joined
+           (portRef COUT (instanceRef w_gctr_3))
+           (portRef CIN (instanceRef w_gctr_4))
+          ))
+          (net co4 (joined
+           (portRef COUT (instanceRef w_gctr_4))
+          ))
+          (net r_gctr_ci (joined
+           (portRef COUT (instanceRef r_gctr_cia))
+           (portRef CIN (instanceRef r_gctr_0))
+          ))
+          (net r_gctr_cia_S0_2 (joined
+           (portRef S0 (instanceRef r_gctr_cia))
+          ))
+          (net r_gctr_cia_S1_2 (joined
+           (portRef S1 (instanceRef r_gctr_cia))
+          ))
+          (net co0_1 (joined
+           (portRef COUT (instanceRef r_gctr_0))
+           (portRef CIN (instanceRef r_gctr_1))
+          ))
+          (net co1_1 (joined
+           (portRef COUT (instanceRef r_gctr_1))
+           (portRef CIN (instanceRef r_gctr_2))
+          ))
+          (net co2_1 (joined
+           (portRef COUT (instanceRef r_gctr_2))
+           (portRef CIN (instanceRef r_gctr_3))
+          ))
+          (net co3_1 (joined
+           (portRef COUT (instanceRef r_gctr_3))
+           (portRef CIN (instanceRef r_gctr_4))
+          ))
+          (net co4_1 (joined
+           (portRef COUT (instanceRef r_gctr_4))
+          ))
+          (net cmp_ci (joined
+           (portRef COUT (instanceRef empty_cmp_ci_a))
+           (portRef CIN (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_ci_a_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_ci_a))
+          ))
+          (net empty_cmp_ci_a_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_ci_a))
+          ))
+          (net co0_2 (joined
+           (portRef COUT (instanceRef empty_cmp_0))
+           (portRef CIN (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_0_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_0))
+          ))
+          (net empty_cmp_0_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_0))
+          ))
+          (net co1_2 (joined
+           (portRef COUT (instanceRef empty_cmp_1))
+           (portRef CIN (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_1_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_1))
+          ))
+          (net empty_cmp_1_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_1))
+          ))
+          (net co2_2 (joined
+           (portRef COUT (instanceRef empty_cmp_2))
+           (portRef CIN (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_2_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_2))
+          ))
+          (net empty_cmp_2_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_2))
+          ))
+          (net co3_2 (joined
+           (portRef COUT (instanceRef empty_cmp_3))
+           (portRef CIN (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_3_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_3))
+          ))
+          (net empty_cmp_3_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_3))
+          ))
+          (net empty_d_c (joined
+           (portRef COUT (instanceRef empty_cmp_4))
+           (portRef CIN (instanceRef a0))
+          ))
+          (net empty_cmp_4_S0_2 (joined
+           (portRef S0 (instanceRef empty_cmp_4))
+          ))
+          (net empty_cmp_4_S1_2 (joined
+           (portRef S1 (instanceRef empty_cmp_4))
+          ))
+          (net a0_COUT_2 (joined
+           (portRef COUT (instanceRef a0))
+          ))
+          (net a0_S1_2 (joined
+           (portRef S1 (instanceRef a0))
+          ))
+          (net cmp_ci_1 (joined
+           (portRef COUT (instanceRef full_cmp_ci_a))
+           (portRef CIN (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_ci_a_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_ci_a))
+          ))
+          (net full_cmp_ci_a_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_ci_a))
+          ))
+          (net co0_3 (joined
+           (portRef COUT (instanceRef full_cmp_0))
+           (portRef CIN (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_0_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_0))
+          ))
+          (net full_cmp_0_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_0))
+          ))
+          (net co1_3 (joined
+           (portRef COUT (instanceRef full_cmp_1))
+           (portRef CIN (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_1_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_1))
+          ))
+          (net full_cmp_1_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_1))
+          ))
+          (net co2_3 (joined
+           (portRef COUT (instanceRef full_cmp_2))
+           (portRef CIN (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_2_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_2))
+          ))
+          (net full_cmp_2_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_2))
+          ))
+          (net co3_3 (joined
+           (portRef COUT (instanceRef full_cmp_3))
+           (portRef CIN (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_3_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_3))
+          ))
+          (net full_cmp_3_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_3))
+          ))
+          (net full_d_c (joined
+           (portRef COUT (instanceRef full_cmp_4))
+           (portRef CIN (instanceRef a1))
+          ))
+          (net full_cmp_4_S0_2 (joined
+           (portRef S0 (instanceRef full_cmp_4))
+          ))
+          (net full_cmp_4_S1_2 (joined
+           (portRef S1 (instanceRef full_cmp_4))
+          ))
+          (net a1_COUT_2 (joined
+           (portRef COUT (instanceRef a1))
+          ))
+          (net a1_S1_2 (joined
+           (portRef S1 (instanceRef a1))
+          ))
+          (net CIN (joined
+           (portRef CIN (instanceRef full_cmp_ci_a))
+          ))
+          (net CIN_0 (joined
+           (portRef CIN (instanceRef empty_cmp_ci_a))
+          ))
+          (net CIN_1 (joined
+           (portRef CIN (instanceRef r_gctr_cia))
+          ))
+          (net CIN_2 (joined
+           (portRef CIN (instanceRef w_gctr_cia))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "fifo40_dc"))
+       )
+    )
+    (cell hades_tdc_channel_raw_out (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port (array (rename hades_dbg2_coarse_c "hades_dbg2_coarse_c[8:0]") 9) (direction INPUT))
+           (port reset_dl_i_0 (direction INPUT))
+           (port (array (rename hades_raw_out "hades_raw_out[23:0]") 24) (direction OUTPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+           (port hades_trig_c_i (direction INPUT))
+           (port drop_cmp_buf_coarse_2_ac0_13_0 (direction INPUT))
+           (port drop_cmp_buf_coarse_2_c4 (direction INPUT))
+           (port drop_cmp_buf_coarse_2_ac0_9_0 (direction INPUT))
+           (port drop_cmp_buf_coarse_2_c5 (direction INPUT))
+           (port drop_cmp_buf_coarse_2_c3 (direction INPUT))
+           (port hades_raw_out_valid (direction OUTPUT))
+         )
+         (contents
+          (instance un1_coarse_1_0_I_9_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A+B !A)+D (!C (!B A+B !A)+C (!B !A+B A)))"))
+          )
+          (instance un1_buf_positive_0_I_9_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A+B !A)+D (!C (!B A+B !A)+C (!B !A+B A)))"))
+          )
+          (instance raw_out_valid (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_0 "raw_out[0]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_1 "raw_out[1]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_2 "raw_out[2]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_3 "raw_out[3]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_4 "raw_out[4]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_5 "raw_out[5]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_6 "raw_out[6]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_7 "raw_out[7]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_8 "raw_out[8]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_9 "raw_out[9]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_10 "raw_out[10]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_11 "raw_out[11]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_12 "raw_out[12]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_13 "raw_out[13]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_14 "raw_out[14]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_15 "raw_out[15]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_16 "raw_out[16]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_17 "raw_out[17]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_18 "raw_out[18]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_19 "raw_out[19]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_20 "raw_out[20]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_21 "raw_out[21]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_22 "raw_out[22]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename raw_out_23 "raw_out[23]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance buf_positive_ready (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_0 "buf_positive[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_1 "buf_positive[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_2 "buf_positive[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_3 "buf_positive[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_4 "buf_positive[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_5 "buf_positive[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_6 "buf_positive[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_7 "buf_positive[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_8 "buf_positive[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_9 "buf_positive[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_10 "buf_positive[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_positive_11 "buf_positive[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance buf_negative_ready (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_0 "buf_negative[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_1 "buf_negative[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_2 "buf_negative[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_3 "buf_negative[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_4 "buf_negative[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_5 "buf_negative[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_6 "buf_negative[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_7 "buf_negative[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_8 "buf_negative[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_9 "buf_negative[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_10 "buf_negative[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename buf_negative_11 "buf_negative[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance un1_buf_positive_0_I_9_0_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (!B A+B !A))+D (!C !B+C (!B !A+B A)))"))
+          )
+          (instance un1_coarse_1_0_I_9_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (!B A+B !A))+D (!C !B+C (!B !A+B A)))"))
+          )
+          (instance buf_positive_ready_4_iv_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (!C (B !A)+C (!B+!A)))"))
+          )
+          (instance buf_negative_ready_4_f0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D (!C (!B A)+C (!B A+B !A)))"))
+          )
+          (instance buf_negative_ready_RNIG7JA (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance un1_coarse_1_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x500c"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x1824"))
+          )
+          (instance un1_coarse_1_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x1441"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x1441"))
+          )
+          (instance un1_coarse_1_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x8111"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x1555"))
+          )
+          (instance un1_coarse_1_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0xa003"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x0000"))
+          )
+          (instance un1_buf_positive_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x500c"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x1824"))
+          )
+          (instance un1_buf_positive_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x1441"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x1441"))
+          )
+          (instance un1_buf_positive_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x8111"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x1555"))
+          )
+          (instance un1_buf_positive_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0xa003"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x0000"))
+          )
+          (instance trig_inv_inst1 (viewRef netlist (cellRef trig_inv))
+          )
+          (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_0))
+          )
+          (instance tdc_neg_inst (viewRef netlist (cellRef tdc4ddr_short_1))
+          )
+          (instance dec_inst (viewRef netlist (cellRef output_decoder8_0_0))
+          )
+          (instance dec_neg_inst (viewRef netlist (cellRef output_decoder8_0_1))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename buf_negative_5 "buf_negative[5]") (joined
+           (portRef Q (instanceRef buf_negative_5))
+           (portRef D (instanceRef raw_out_17))
+           (portRef A (instanceRef un1_coarse_1_0_I_9_0_RNO))
+          ))
+          (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined
+           (portRef (member hades_dbg2_coarse_c 6))
+           (portRef D (instanceRef buf_negative_5))
+           (portRef D (instanceRef buf_positive_5))
+           (portRef B (instanceRef un1_buf_positive_0_I_9_0_RNO))
+           (portRef B (instanceRef un1_coarse_1_0_I_9_0_RNO))
+          ))
+          (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined
+           (portRef (member hades_dbg2_coarse_c 7))
+           (portRef D1 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef D1 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef D (instanceRef buf_negative_4))
+           (portRef D (instanceRef buf_positive_4))
+           (portRef C (instanceRef un1_buf_positive_0_I_9_0_RNO))
+           (portRef C (instanceRef un1_coarse_1_0_I_9_0_RNO))
+          ))
+          (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined
+           (portRef (member hades_dbg2_coarse_c 8))
+           (portRef C1 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef C1 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef D (instanceRef buf_negative_3))
+           (portRef D (instanceRef buf_positive_3))
+           (portRef D (instanceRef un1_buf_positive_0_I_9_0_RNO))
+           (portRef D (instanceRef un1_coarse_1_0_I_9_0_RNO))
+          ))
+          (net un1_coarse_1_0_N_19 (joined
+           (portRef Z (instanceRef un1_coarse_1_0_I_9_0_RNO))
+           (portRef A0 (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net (rename buf_positive_5 "buf_positive[5]") (joined
+           (portRef Q (instanceRef buf_positive_5))
+           (portRef D (instanceRef raw_out_5))
+           (portRef A (instanceRef un1_buf_positive_0_I_9_0_RNO))
+          ))
+          (net un1_buf_positive_0_N_19 (joined
+           (portRef Z (instanceRef un1_buf_positive_0_I_9_0_RNO))
+           (portRef A0 (instanceRef un1_buf_positive_0_I_9_0))
+          ))
+          (net N_249_i (joined
+           (portRef Z (instanceRef buf_negative_ready_RNIG7JA))
+           (portRef SP (instanceRef raw_out_23))
+           (portRef SP (instanceRef raw_out_22))
+           (portRef SP (instanceRef raw_out_21))
+           (portRef SP (instanceRef raw_out_20))
+           (portRef SP (instanceRef raw_out_19))
+           (portRef SP (instanceRef raw_out_18))
+           (portRef SP (instanceRef raw_out_17))
+           (portRef SP (instanceRef raw_out_16))
+           (portRef SP (instanceRef raw_out_15))
+           (portRef SP (instanceRef raw_out_14))
+           (portRef SP (instanceRef raw_out_13))
+           (portRef SP (instanceRef raw_out_12))
+           (portRef SP (instanceRef raw_out_11))
+           (portRef SP (instanceRef raw_out_10))
+           (portRef SP (instanceRef raw_out_9))
+           (portRef SP (instanceRef raw_out_8))
+           (portRef SP (instanceRef raw_out_7))
+           (portRef SP (instanceRef raw_out_6))
+           (portRef SP (instanceRef raw_out_5))
+           (portRef SP (instanceRef raw_out_4))
+           (portRef SP (instanceRef raw_out_3))
+           (portRef SP (instanceRef raw_out_2))
+           (portRef SP (instanceRef raw_out_1))
+           (portRef SP (instanceRef raw_out_0))
+           (portRef D (instanceRef raw_out_valid))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef (member pll_clks 0) (instanceRef tdc_neg_inst))
+           (portRef (member pll_clks 0) (instanceRef tdc_inst))
+           (portRef CK (instanceRef buf_negative_11))
+           (portRef CK (instanceRef buf_negative_10))
+           (portRef CK (instanceRef buf_negative_9))
+           (portRef CK (instanceRef buf_negative_8))
+           (portRef CK (instanceRef buf_negative_7))
+           (portRef CK (instanceRef buf_negative_6))
+           (portRef CK (instanceRef buf_negative_5))
+           (portRef CK (instanceRef buf_negative_4))
+           (portRef CK (instanceRef buf_negative_3))
+           (portRef CK (instanceRef buf_negative_2))
+           (portRef CK (instanceRef buf_negative_1))
+           (portRef CK (instanceRef buf_negative_0))
+           (portRef CK (instanceRef buf_negative_ready))
+           (portRef CK (instanceRef buf_positive_11))
+           (portRef CK (instanceRef buf_positive_10))
+           (portRef CK (instanceRef buf_positive_9))
+           (portRef CK (instanceRef buf_positive_8))
+           (portRef CK (instanceRef buf_positive_7))
+           (portRef CK (instanceRef buf_positive_6))
+           (portRef CK (instanceRef buf_positive_5))
+           (portRef CK (instanceRef buf_positive_4))
+           (portRef CK (instanceRef buf_positive_3))
+           (portRef CK (instanceRef buf_positive_2))
+           (portRef CK (instanceRef buf_positive_1))
+           (portRef CK (instanceRef buf_positive_0))
+           (portRef CK (instanceRef buf_positive_ready))
+           (portRef CK (instanceRef raw_out_23))
+           (portRef CK (instanceRef raw_out_22))
+           (portRef CK (instanceRef raw_out_21))
+           (portRef CK (instanceRef raw_out_20))
+           (portRef CK (instanceRef raw_out_19))
+           (portRef CK (instanceRef raw_out_18))
+           (portRef CK (instanceRef raw_out_17))
+           (portRef CK (instanceRef raw_out_16))
+           (portRef CK (instanceRef raw_out_15))
+           (portRef CK (instanceRef raw_out_14))
+           (portRef CK (instanceRef raw_out_13))
+           (portRef CK (instanceRef raw_out_12))
+           (portRef CK (instanceRef raw_out_11))
+           (portRef CK (instanceRef raw_out_10))
+           (portRef CK (instanceRef raw_out_9))
+           (portRef CK (instanceRef raw_out_8))
+           (portRef CK (instanceRef raw_out_7))
+           (portRef CK (instanceRef raw_out_6))
+           (portRef CK (instanceRef raw_out_5))
+           (portRef CK (instanceRef raw_out_4))
+           (portRef CK (instanceRef raw_out_3))
+           (portRef CK (instanceRef raw_out_2))
+           (portRef CK (instanceRef raw_out_1))
+           (portRef CK (instanceRef raw_out_0))
+           (portRef CK (instanceRef raw_out_valid))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef reset_dl_0 (instanceRef dec_neg_inst))
+           (portRef reset_dl_0 (instanceRef dec_inst))
+           (portRef CD (instanceRef raw_out_23))
+           (portRef CD (instanceRef raw_out_22))
+           (portRef CD (instanceRef raw_out_21))
+           (portRef CD (instanceRef raw_out_20))
+           (portRef CD (instanceRef raw_out_19))
+           (portRef CD (instanceRef raw_out_18))
+           (portRef CD (instanceRef raw_out_17))
+           (portRef CD (instanceRef raw_out_16))
+           (portRef CD (instanceRef raw_out_15))
+           (portRef CD (instanceRef raw_out_14))
+           (portRef CD (instanceRef raw_out_13))
+           (portRef CD (instanceRef raw_out_12))
+           (portRef CD (instanceRef raw_out_11))
+           (portRef CD (instanceRef raw_out_10))
+           (portRef CD (instanceRef raw_out_9))
+           (portRef CD (instanceRef raw_out_8))
+           (portRef CD (instanceRef raw_out_7))
+           (portRef CD (instanceRef raw_out_6))
+           (portRef CD (instanceRef raw_out_5))
+           (portRef CD (instanceRef raw_out_4))
+           (portRef CD (instanceRef raw_out_3))
+           (portRef CD (instanceRef raw_out_2))
+           (portRef CD (instanceRef raw_out_1))
+           (portRef CD (instanceRef raw_out_0))
+           (portRef CD (instanceRef raw_out_valid))
+          ))
+          (net hades_raw_out_valid (joined
+           (portRef Q (instanceRef raw_out_valid))
+           (portRef hades_raw_out_valid)
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef C1 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef B1 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef A1 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef D0 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef C0 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef B0 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef A0 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef D0 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef C0 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef B0 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef A0 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef D1 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef C1 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef B1 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef A1 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef D0 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef C0 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef B0 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef A0 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef D0 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef C0 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef B0 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef A0 (instanceRef un1_coarse_1_0_I_1_0))
+          ))
+          (net (rename buf_positive_0 "buf_positive[0]") (joined
+           (portRef Q (instanceRef buf_positive_0))
+           (portRef D (instanceRef raw_out_0))
+          ))
+          (net (rename hades_raw_out_0 "hades_raw_out[0]") (joined
+           (portRef Q (instanceRef raw_out_0))
+           (portRef (member hades_raw_out 23))
+          ))
+          (net (rename buf_positive_1 "buf_positive[1]") (joined
+           (portRef Q (instanceRef buf_positive_1))
+           (portRef D (instanceRef raw_out_1))
+          ))
+          (net (rename hades_raw_out_1 "hades_raw_out[1]") (joined
+           (portRef Q (instanceRef raw_out_1))
+           (portRef (member hades_raw_out 22))
+          ))
+          (net (rename buf_positive_2 "buf_positive[2]") (joined
+           (portRef Q (instanceRef buf_positive_2))
+           (portRef D (instanceRef raw_out_2))
+          ))
+          (net (rename hades_raw_out_2 "hades_raw_out[2]") (joined
+           (portRef Q (instanceRef raw_out_2))
+           (portRef (member hades_raw_out 21))
+          ))
+          (net (rename buf_positive_3 "buf_positive[3]") (joined
+           (portRef Q (instanceRef buf_positive_3))
+           (portRef B1 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef D (instanceRef raw_out_3))
+          ))
+          (net (rename hades_raw_out_3 "hades_raw_out[3]") (joined
+           (portRef Q (instanceRef raw_out_3))
+           (portRef (member hades_raw_out 20))
+          ))
+          (net (rename buf_positive_4 "buf_positive[4]") (joined
+           (portRef Q (instanceRef buf_positive_4))
+           (portRef A1 (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef D (instanceRef raw_out_4))
+          ))
+          (net (rename hades_raw_out_4 "hades_raw_out[4]") (joined
+           (portRef Q (instanceRef raw_out_4))
+           (portRef (member hades_raw_out 19))
+          ))
+          (net (rename hades_raw_out_5 "hades_raw_out[5]") (joined
+           (portRef Q (instanceRef raw_out_5))
+           (portRef (member hades_raw_out 18))
+          ))
+          (net (rename buf_positive_6 "buf_positive[6]") (joined
+           (portRef Q (instanceRef buf_positive_6))
+           (portRef B0 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef D (instanceRef raw_out_6))
+          ))
+          (net (rename hades_raw_out_6 "hades_raw_out[6]") (joined
+           (portRef Q (instanceRef raw_out_6))
+           (portRef (member hades_raw_out 17))
+          ))
+          (net (rename buf_positive_7 "buf_positive[7]") (joined
+           (portRef Q (instanceRef buf_positive_7))
+           (portRef D (instanceRef un1_buf_positive_0_I_9_0_RNO_0))
+           (portRef D (instanceRef raw_out_7))
+          ))
+          (net (rename hades_raw_out_7 "hades_raw_out[7]") (joined
+           (portRef Q (instanceRef raw_out_7))
+           (portRef (member hades_raw_out 16))
+          ))
+          (net (rename buf_positive_8 "buf_positive[8]") (joined
+           (portRef Q (instanceRef buf_positive_8))
+           (portRef B1 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef D (instanceRef raw_out_8))
+          ))
+          (net (rename hades_raw_out_8 "hades_raw_out[8]") (joined
+           (portRef Q (instanceRef raw_out_8))
+           (portRef (member hades_raw_out 15))
+          ))
+          (net (rename buf_positive_9 "buf_positive[9]") (joined
+           (portRef Q (instanceRef buf_positive_9))
+           (portRef D (instanceRef raw_out_9))
+          ))
+          (net (rename hades_raw_out_9 "hades_raw_out[9]") (joined
+           (portRef Q (instanceRef raw_out_9))
+           (portRef (member hades_raw_out 14))
+          ))
+          (net (rename buf_positive_10 "buf_positive[10]") (joined
+           (portRef Q (instanceRef buf_positive_10))
+           (portRef D (instanceRef raw_out_10))
+          ))
+          (net (rename hades_raw_out_10 "hades_raw_out[10]") (joined
+           (portRef Q (instanceRef raw_out_10))
+           (portRef (member hades_raw_out 13))
+          ))
+          (net (rename buf_positive_11 "buf_positive[11]") (joined
+           (portRef Q (instanceRef buf_positive_11))
+           (portRef D (instanceRef raw_out_11))
+          ))
+          (net (rename hades_raw_out_11 "hades_raw_out[11]") (joined
+           (portRef Q (instanceRef raw_out_11))
+           (portRef (member hades_raw_out 12))
+          ))
+          (net (rename buf_negative_0 "buf_negative[0]") (joined
+           (portRef Q (instanceRef buf_negative_0))
+           (portRef D (instanceRef raw_out_12))
+          ))
+          (net (rename hades_raw_out_12 "hades_raw_out[12]") (joined
+           (portRef Q (instanceRef raw_out_12))
+           (portRef (member hades_raw_out 11))
+          ))
+          (net (rename buf_negative_1 "buf_negative[1]") (joined
+           (portRef Q (instanceRef buf_negative_1))
+           (portRef D (instanceRef raw_out_13))
+          ))
+          (net (rename hades_raw_out_13 "hades_raw_out[13]") (joined
+           (portRef Q (instanceRef raw_out_13))
+           (portRef (member hades_raw_out 10))
+          ))
+          (net (rename buf_negative_2 "buf_negative[2]") (joined
+           (portRef Q (instanceRef buf_negative_2))
+           (portRef D (instanceRef raw_out_14))
+          ))
+          (net (rename hades_raw_out_14 "hades_raw_out[14]") (joined
+           (portRef Q (instanceRef raw_out_14))
+           (portRef (member hades_raw_out 9))
+          ))
+          (net (rename buf_negative_3 "buf_negative[3]") (joined
+           (portRef Q (instanceRef buf_negative_3))
+           (portRef B1 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef D (instanceRef raw_out_15))
+          ))
+          (net (rename hades_raw_out_15 "hades_raw_out[15]") (joined
+           (portRef Q (instanceRef raw_out_15))
+           (portRef (member hades_raw_out 8))
+          ))
+          (net (rename buf_negative_4 "buf_negative[4]") (joined
+           (portRef Q (instanceRef buf_negative_4))
+           (portRef A1 (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef D (instanceRef raw_out_16))
+          ))
+          (net (rename hades_raw_out_16 "hades_raw_out[16]") (joined
+           (portRef Q (instanceRef raw_out_16))
+           (portRef (member hades_raw_out 7))
+          ))
+          (net (rename hades_raw_out_17 "hades_raw_out[17]") (joined
+           (portRef Q (instanceRef raw_out_17))
+           (portRef (member hades_raw_out 6))
+          ))
+          (net (rename buf_negative_6 "buf_negative[6]") (joined
+           (portRef Q (instanceRef buf_negative_6))
+           (portRef B0 (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef D (instanceRef raw_out_18))
+          ))
+          (net (rename hades_raw_out_18 "hades_raw_out[18]") (joined
+           (portRef Q (instanceRef raw_out_18))
+           (portRef (member hades_raw_out 5))
+          ))
+          (net (rename buf_negative_7 "buf_negative[7]") (joined
+           (portRef Q (instanceRef buf_negative_7))
+           (portRef D (instanceRef un1_coarse_1_0_I_9_RNO_0))
+           (portRef D (instanceRef raw_out_19))
+          ))
+          (net (rename hades_raw_out_19 "hades_raw_out[19]") (joined
+           (portRef Q (instanceRef raw_out_19))
+           (portRef (member hades_raw_out 4))
+          ))
+          (net (rename buf_negative_8 "buf_negative[8]") (joined
+           (portRef Q (instanceRef buf_negative_8))
+           (portRef B1 (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef D (instanceRef raw_out_20))
+          ))
+          (net (rename hades_raw_out_20 "hades_raw_out[20]") (joined
+           (portRef Q (instanceRef raw_out_20))
+           (portRef (member hades_raw_out 3))
+          ))
+          (net (rename buf_negative_9 "buf_negative[9]") (joined
+           (portRef Q (instanceRef buf_negative_9))
+           (portRef D (instanceRef raw_out_21))
+          ))
+          (net (rename hades_raw_out_21 "hades_raw_out[21]") (joined
+           (portRef Q (instanceRef raw_out_21))
+           (portRef (member hades_raw_out 2))
+          ))
+          (net (rename buf_negative_10 "buf_negative[10]") (joined
+           (portRef Q (instanceRef buf_negative_10))
+           (portRef D (instanceRef raw_out_22))
+          ))
+          (net (rename hades_raw_out_22 "hades_raw_out[22]") (joined
+           (portRef Q (instanceRef raw_out_22))
+           (portRef (member hades_raw_out 1))
+          ))
+          (net (rename buf_negative_11 "buf_negative[11]") (joined
+           (portRef Q (instanceRef buf_negative_11))
+           (portRef D (instanceRef raw_out_23))
+          ))
+          (net (rename hades_raw_out_23 "hades_raw_out[23]") (joined
+           (portRef Q (instanceRef raw_out_23))
+           (portRef (member hades_raw_out 0))
+          ))
+          (net N_7 (joined
+           (portRef Z (instanceRef buf_positive_ready_4_iv_i_0))
+           (portRef D (instanceRef buf_positive_ready))
+          ))
+          (net (rename reset_dl_i_0 "reset_dl_i[2]") (joined
+           (portRef reset_dl_i_0)
+           (portRef SP (instanceRef buf_negative_ready))
+           (portRef SP (instanceRef buf_positive_ready))
+          ))
+          (net buf_positive_ready (joined
+           (portRef Q (instanceRef buf_positive_ready))
+           (portRef buf_positive_ready (instanceRef dec_neg_inst))
+           (portRef B (instanceRef buf_negative_ready_RNIG7JA))
+           (portRef B (instanceRef buf_negative_ready_4_f0_0_0))
+           (portRef B (instanceRef buf_positive_ready_4_iv_i_0))
+          ))
+          (net (rename decoder_out_0 "decoder_out[0]") (joined
+           (portRef (member decoder_out 2) (instanceRef dec_inst))
+           (portRef D (instanceRef buf_positive_0))
+          ))
+          (net N_251_i (joined
+           (portRef N_251_i (instanceRef dec_inst))
+           (portRef SP (instanceRef buf_positive_11))
+           (portRef SP (instanceRef buf_positive_10))
+           (portRef SP (instanceRef buf_positive_9))
+           (portRef SP (instanceRef buf_positive_8))
+           (portRef SP (instanceRef buf_positive_7))
+           (portRef SP (instanceRef buf_positive_6))
+           (portRef SP (instanceRef buf_positive_5))
+           (portRef SP (instanceRef buf_positive_4))
+           (portRef SP (instanceRef buf_positive_3))
+           (portRef SP (instanceRef buf_positive_2))
+           (portRef SP (instanceRef buf_positive_1))
+           (portRef SP (instanceRef buf_positive_0))
+          ))
+          (net (rename decoder_out_1 "decoder_out[1]") (joined
+           (portRef (member decoder_out 1) (instanceRef dec_inst))
+           (portRef D (instanceRef buf_positive_1))
+          ))
+          (net (rename decoder_out_2 "decoder_out[2]") (joined
+           (portRef (member decoder_out 0) (instanceRef dec_inst))
+           (portRef D (instanceRef buf_positive_2))
+          ))
+          (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined
+           (portRef (member hades_dbg2_coarse_c 5))
+           (portRef D0 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef D0 (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef A (instanceRef un1_coarse_1_0_I_9_RNO_0))
+           (portRef A (instanceRef un1_buf_positive_0_I_9_0_RNO_0))
+           (portRef D (instanceRef buf_negative_6))
+           (portRef D (instanceRef buf_positive_6))
+          ))
+          (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined
+           (portRef (member hades_dbg2_coarse_c 4))
+           (portRef B (instanceRef un1_coarse_1_0_I_9_RNO_0))
+           (portRef B (instanceRef un1_buf_positive_0_I_9_0_RNO_0))
+           (portRef D (instanceRef buf_negative_7))
+           (portRef D (instanceRef buf_positive_7))
+          ))
+          (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined
+           (portRef (member hades_dbg2_coarse_c 3))
+           (portRef D1 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef D1 (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef D (instanceRef buf_negative_8))
+           (portRef D (instanceRef buf_positive_8))
+          ))
+          (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined
+           (portRef (member hades_dbg2_coarse_c 2))
+           (portRef A0 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef A0 (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef D (instanceRef buf_negative_9))
+           (portRef D (instanceRef buf_positive_9))
+          ))
+          (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined
+           (portRef (member hades_dbg2_coarse_c 1))
+           (portRef B0 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef B0 (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef D (instanceRef buf_negative_10))
+           (portRef D (instanceRef buf_positive_10))
+          ))
+          (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined
+           (portRef (member hades_dbg2_coarse_c 0))
+           (portRef A1 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef A1 (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef D (instanceRef buf_negative_11))
+           (portRef D (instanceRef buf_positive_11))
+          ))
+          (net buf_negative_ready_4 (joined
+           (portRef Z (instanceRef buf_negative_ready_4_f0_0_0))
+           (portRef D (instanceRef buf_negative_ready))
+          ))
+          (net buf_negative_ready (joined
+           (portRef Q (instanceRef buf_negative_ready))
+           (portRef A (instanceRef buf_negative_ready_RNIG7JA))
+           (portRef A (instanceRef buf_negative_ready_4_f0_0_0))
+           (portRef A (instanceRef buf_positive_ready_4_iv_i_0))
+          ))
+          (net (rename decoder_out_neg_0 "decoder_out_neg[0]") (joined
+           (portRef (member decoder_out_neg 2) (instanceRef dec_neg_inst))
+           (portRef D (instanceRef buf_negative_0))
+          ))
+          (net N_11_i (joined
+           (portRef N_11_i (instanceRef dec_neg_inst))
+           (portRef SP (instanceRef buf_negative_11))
+           (portRef SP (instanceRef buf_negative_10))
+           (portRef SP (instanceRef buf_negative_9))
+           (portRef SP (instanceRef buf_negative_8))
+           (portRef SP (instanceRef buf_negative_7))
+           (portRef SP (instanceRef buf_negative_6))
+           (portRef SP (instanceRef buf_negative_5))
+           (portRef SP (instanceRef buf_negative_4))
+           (portRef SP (instanceRef buf_negative_3))
+           (portRef SP (instanceRef buf_negative_2))
+           (portRef SP (instanceRef buf_negative_1))
+           (portRef SP (instanceRef buf_negative_0))
+          ))
+          (net (rename decoder_out_neg_1 "decoder_out_neg[1]") (joined
+           (portRef (member decoder_out_neg 1) (instanceRef dec_neg_inst))
+           (portRef D (instanceRef buf_negative_1))
+          ))
+          (net (rename decoder_out_neg_2 "decoder_out_neg[2]") (joined
+           (portRef (member decoder_out_neg 0) (instanceRef dec_neg_inst))
+           (portRef D (instanceRef buf_negative_2))
+          ))
+          (net drop_cmp_buf_coarse_2_c3 (joined
+           (portRef drop_cmp_buf_coarse_2_c3)
+           (portRef C0 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef C0 (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef C (instanceRef un1_coarse_1_0_I_9_RNO_0))
+           (portRef C (instanceRef un1_buf_positive_0_I_9_0_RNO_0))
+          ))
+          (net un1_buf_positive_0_N_14 (joined
+           (portRef Z (instanceRef un1_buf_positive_0_I_9_0_RNO_0))
+           (portRef A1 (instanceRef un1_buf_positive_0_I_9_0))
+          ))
+          (net un1_coarse_1_0_N_14 (joined
+           (portRef Z (instanceRef un1_coarse_1_0_I_9_RNO_0))
+           (portRef A1 (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net decoder_valid (joined
+           (portRef decoder_valid (instanceRef dec_inst))
+           (portRef C (instanceRef buf_positive_ready_4_iv_i_0))
+          ))
+          (net un1_buf_positive_i (joined
+           (portRef S0 (instanceRef un1_buf_positive_0_I_27_0))
+           (portRef D (instanceRef buf_positive_ready_4_iv_i_0))
+          ))
+          (net decoder_valid_neg (joined
+           (portRef decoder_valid_neg (instanceRef dec_neg_inst))
+           (portRef C (instanceRef buf_negative_ready_4_f0_0_0))
+          ))
+          (net un1_coarse_1_i (joined
+           (portRef S0 (instanceRef un1_coarse_1_0_I_27_0))
+           (portRef D (instanceRef buf_negative_ready_4_f0_0_0))
+          ))
+          (net (rename un1_coarse_1_0_data_tmp_0 "un1_coarse_1_0_data_tmp[0]") (joined
+           (portRef COUT (instanceRef un1_coarse_1_0_I_1_0))
+           (portRef CIN (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net un1_coarse_1_0_I_1_0_S0 (joined
+           (portRef S0 (instanceRef un1_coarse_1_0_I_1_0))
+          ))
+          (net un1_coarse_1_0_I_1_0_S1 (joined
+           (portRef S1 (instanceRef un1_coarse_1_0_I_1_0))
+          ))
+          (net drop_cmp_buf_coarse_2_c5 (joined
+           (portRef drop_cmp_buf_coarse_2_c5)
+           (portRef C1 (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef C1 (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net (rename un1_coarse_1_0_data_tmp_2 "un1_coarse_1_0_data_tmp[2]") (joined
+           (portRef COUT (instanceRef un1_coarse_1_0_I_9_0))
+           (portRef CIN (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net un1_coarse_1_0_I_9_0_S0 (joined
+           (portRef S0 (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net un1_coarse_1_0_I_9_0_S1 (joined
+           (portRef S1 (instanceRef un1_coarse_1_0_I_9_0))
+          ))
+          (net drop_cmp_buf_coarse_2_ac0_9_0 (joined
+           (portRef drop_cmp_buf_coarse_2_ac0_9_0)
+           (portRef C1 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef C0 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef C1 (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef C0 (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net drop_cmp_buf_coarse_2_c4 (joined
+           (portRef drop_cmp_buf_coarse_2_c4)
+           (portRef D1 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef D0 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef D1 (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef D0 (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net drop_cmp_buf_coarse_2_ac0_13_0 (joined
+           (portRef drop_cmp_buf_coarse_2_ac0_13_0)
+           (portRef B1 (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef B1 (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net un1_coarse_1_0_I_27_cry (joined
+           (portRef COUT (instanceRef un1_coarse_1_0_I_21_0))
+           (portRef CIN (instanceRef un1_coarse_1_0_I_27_0))
+          ))
+          (net un1_coarse_1_0_I_21_0_S0 (joined
+           (portRef S0 (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net un1_coarse_1_0_I_21_0_S1 (joined
+           (portRef S1 (instanceRef un1_coarse_1_0_I_21_0))
+          ))
+          (net un1_coarse_1_0_I_27_0_COUT (joined
+           (portRef COUT (instanceRef un1_coarse_1_0_I_27_0))
+          ))
+          (net un1_coarse_1_0_I_27_0_S1 (joined
+           (portRef S1 (instanceRef un1_coarse_1_0_I_27_0))
+          ))
+          (net (rename un1_buf_positive_0_data_tmp_0 "un1_buf_positive_0_data_tmp[0]") (joined
+           (portRef COUT (instanceRef un1_buf_positive_0_I_1_0))
+           (portRef CIN (instanceRef un1_buf_positive_0_I_9_0))
+          ))
+          (net un1_buf_positive_0_I_1_0_S0 (joined
+           (portRef S0 (instanceRef un1_buf_positive_0_I_1_0))
+          ))
+          (net un1_buf_positive_0_I_1_0_S1 (joined
+           (portRef S1 (instanceRef un1_buf_positive_0_I_1_0))
+          ))
+          (net (rename un1_buf_positive_0_data_tmp_2 "un1_buf_positive_0_data_tmp[2]") (joined
+           (portRef COUT (instanceRef un1_buf_positive_0_I_9_0))
+           (portRef CIN (instanceRef un1_buf_positive_0_I_21_0))
+          ))
+          (net un1_buf_positive_0_I_9_0_S0 (joined
+           (portRef S0 (instanceRef un1_buf_positive_0_I_9_0))
+          ))
+          (net un1_buf_positive_0_I_9_0_S1 (joined
+           (portRef S1 (instanceRef un1_buf_positive_0_I_9_0))
+          ))
+          (net un1_buf_positive_0_I_27_cry (joined
+           (portRef COUT (instanceRef un1_buf_positive_0_I_21_0))
+           (portRef CIN (instanceRef un1_buf_positive_0_I_27_0))
+          ))
+          (net un1_buf_positive_0_I_21_0_S0 (joined
+           (portRef S0 (instanceRef un1_buf_positive_0_I_21_0))
+          ))
+          (net un1_buf_positive_0_I_21_0_S1 (joined
+           (portRef S1 (instanceRef un1_buf_positive_0_I_21_0))
+          ))
+          (net un1_buf_positive_0_I_27_0_COUT (joined
+           (portRef COUT (instanceRef un1_buf_positive_0_I_27_0))
+          ))
+          (net un1_buf_positive_0_I_27_0_S1 (joined
+           (portRef S1 (instanceRef un1_buf_positive_0_I_27_0))
+          ))
+          (net hades_trig_c_i (joined
+           (portRef hades_trig_c_i)
+           (portRef hades_trig_c_i (instanceRef tdc_inst))
+           (portRef hades_trig_c_i (instanceRef trig_inv_inst1))
+          ))
+          (net trig_gate_neg (joined
+           (portRef trig_gate_neg (instanceRef trig_inv_inst1))
+           (portRef trig_gate_neg (instanceRef tdc_neg_inst))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7) (instanceRef tdc_inst))
+           (portRef (member tdc_out 7) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6) (instanceRef tdc_inst))
+           (portRef (member tdc_out 6) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5) (instanceRef tdc_inst))
+           (portRef (member tdc_out 5) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4) (instanceRef tdc_inst))
+           (portRef (member tdc_out 4) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3) (instanceRef tdc_inst))
+           (portRef (member tdc_out 3) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2) (instanceRef tdc_inst))
+           (portRef (member tdc_out 2) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1) (instanceRef tdc_inst))
+           (portRef (member tdc_out 1) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0) (instanceRef tdc_inst))
+           (portRef (member tdc_out 0) (instanceRef dec_inst))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef tdc_neg_inst))
+           (portRef (member pll_clks 3) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef tdc_neg_inst))
+           (portRef (member pll_clks 2) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef tdc_neg_inst))
+           (portRef (member pll_clks 1) (instanceRef tdc_inst))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CN_2 (instanceRef tdc_neg_inst))
+           (portRef CN_2 (instanceRef tdc_inst))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CN_1 (instanceRef tdc_neg_inst))
+           (portRef CN_1 (instanceRef tdc_inst))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CN_0 (instanceRef tdc_neg_inst))
+           (portRef CN_0 (instanceRef tdc_inst))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CN (instanceRef dec_neg_inst))
+           (portRef CN (instanceRef dec_inst))
+           (portRef CN (instanceRef tdc_neg_inst))
+           (portRef CN (instanceRef tdc_inst))
+          ))
+          (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined
+           (portRef (member tdc_out_neg 7) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 7) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined
+           (portRef (member tdc_out_neg 6) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 6) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined
+           (portRef (member tdc_out_neg 5) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 5) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined
+           (portRef (member tdc_out_neg 4) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 4) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined
+           (portRef (member tdc_out_neg 3) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 3) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined
+           (portRef (member tdc_out_neg 2) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 2) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined
+           (portRef (member tdc_out_neg 1) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 1) (instanceRef dec_neg_inst))
+          ))
+          (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined
+           (portRef (member tdc_out_neg 0) (instanceRef tdc_neg_inst))
+           (portRef (member tdc_out_neg 0) (instanceRef dec_neg_inst))
+          ))
+          (net N_1 (joined
+           (portRef CIN (instanceRef un1_buf_positive_0_I_1_0))
+          ))
+          (net N_2 (joined
+           (portRef CIN (instanceRef un1_coarse_1_0_I_1_0))
+          ))
+         )
+        (property TDC_WIDTH (integer 3))
+        (property COARSE_WIDTH (integer 9))
+        (property orig_inst_of (string "hades_tdc_channel_raw_out"))
+       )
+    )
+    (cell hades_LVL1_raw_out (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port (array (rename hades_invalid_dl_c "hades_invalid_dl_c[3:0]") 4) (direction INOUT))
+           (port reset_dl_0 (direction INPUT))
+           (port trig_dl_0 (direction INPUT))
+           (port (array (rename hit_i "hit_i[1:0]") 2) (direction INPUT))
+           (port valid_fast_RNI999V (direction OUTPUT))
+           (port CN_2 (direction OUTPUT))
+           (port CN_1 (direction OUTPUT))
+           (port CN_0 (direction OUTPUT))
+           (port CN (direction OUTPUT))
+           (port hades_lvl1_c_i (direction INPUT))
+           (port N_44 (direction OUTPUT))
+           (port N_40 (direction OUTPUT))
+           (port N_46_i (direction OUTPUT))
+           (port N_59_i (direction OUTPUT))
+           (port hades_offset_valid_c (direction OUTPUT))
+           (port offset_1_sqmuxa_i_0_1z (direction OUTPUT))
+           (port hades_window_end_c (direction OUTPUT))
+           (port N_50_i_i_1z (direction OUTPUT))
+           (port ANB0 (direction INPUT))
+           (port ANB1 (direction INPUT))
+           (port ANB2 (direction INPUT))
+           (port ANB3 (direction INPUT))
+           (port SUM1_0_0_1z (direction OUTPUT))
+           (port hades_raw_out_valid (direction INPUT))
+           (port hades_discard_c (direction OUTPUT))
+         )
+         (contents
+          (instance (rename window_RNO_0 "window_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A+B A)+C (!B+A))+D (!B !A+B A))"))
+          )
+          (instance (rename trig_dl_RNI41GL1_3 "trig_dl_RNI41GL1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+A))+D (B+A))"))
+          )
+          (instance SUM1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (!B A+B !A))"))
+          )
+          (instance N_50_i_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
+          )
+          (instance window_end (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename window_0 "window[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_1 "window[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_2 "window[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename window_3 "window[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_4 "window[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_5 "window[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_6 "window[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename window_7 "window[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename trig_dl_1 "trig_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename trig_dl_2 "trig_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename trig_dl_3 "trig_dl[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance offset_valid (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename invalid_dl_1 "invalid_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename invalid_dl_2 "invalid_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename invalid_dl_3 "invalid_dl[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance discard (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance un1_reset_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance offset_1_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (B+!A))+D !A)"))
+          )
+          (instance discard_en (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (B A)))"))
+          )
+          (instance un1_reset_0_a2_c (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance window_end5_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance un1_reset_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename window_6_7 "window_6[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_6 "window_6[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_5 "window_6[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_4 "window_6[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_3 "window_6[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_2 "window_6[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance (rename window_6_1 "window_6[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D C)"))
+          )
+          (instance window_0_sqmuxadup (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+A)))"))
+          )
+          (instance discard4_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance offset_valid_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance discard4_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance un1_invalid_dl (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance SUM0_1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A+B !A)"))
+          )
+          (instance SUM1_1_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A+B !A)"))
+          )
+          (instance SUM1_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance offset_1_sqmuxa_i_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance (rename window_RNIOA5C_2 "window_RNIOA5C[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename window_RNICU4C_3 "window_RNICU4C[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance SUM1_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+A))"))
+          )
+          (instance un1_window_8_cry_0_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x5003"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0xa90a"))
+          )
+          (instance un1_window_8_cry_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0xa90a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0xa90a"))
+          )
+          (instance un1_window_8_cry_3_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0xa90a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0xa90a"))
+          )
+          (instance un1_window_8_cry_5_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0xa90a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0xa90a"))
+          )
+          (instance un1_window_8_s_7_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x900a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x5003"))
+          )
+          (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short))
+          )
+          (instance dec_inst (viewRef netlist (cellRef output_decoder8_0))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename window_0 "window[0]") (joined
+           (portRef Q (instanceRef window_0))
+           (portRef A1 (instanceRef un1_window_8_cry_0_0))
+           (portRef A (instanceRef window_RNICU4C_3))
+           (portRef B (instanceRef un1_reset_0_a2_1))
+           (portRef B (instanceRef window_end5_0_a2))
+           (portRef C (instanceRef un1_reset_0_a2_c))
+           (portRef B (instanceRef discard_en))
+           (portRef C (instanceRef offset_1_sqmuxa_i_0))
+           (portRef A (instanceRef window_RNO_0))
+          ))
+          (net un1_reset_0_a2_2 (joined
+           (portRef Z (instanceRef un1_reset_0_a2_2))
+           (portRef B0 (instanceRef un1_window_8_s_7_0))
+           (portRef B (instanceRef window_RNO_0))
+          ))
+          (net valid_fast (joined
+           (portRef valid_fast_1z (instanceRef dec_inst))
+           (portRef B (instanceRef offset_1_sqmuxa_i_0_o2))
+           (portRef C (instanceRef window_RNO_0))
+          ))
+          (net hades_discard_c (joined
+           (portRef Q (instanceRef discard))
+           (portRef hades_discard_c (instanceRef dec_inst))
+           (portRef A (instanceRef offset_1_sqmuxa_i_0_o2))
+           (portRef A (instanceRef offset_valid_RNO))
+           (portRef A (instanceRef window_6_1))
+           (portRef A (instanceRef window_6_2))
+           (portRef A (instanceRef window_6_3))
+           (portRef A (instanceRef window_6_4))
+           (portRef A (instanceRef window_6_5))
+           (portRef A (instanceRef window_6_6))
+           (portRef A (instanceRef window_6_7))
+           (portRef B (instanceRef un1_reset_0_a2_c))
+           (portRef A (instanceRef un1_reset_0_a2_2))
+           (portRef D (instanceRef window_RNO_0))
+           (portRef hades_discard_c)
+          ))
+          (net (rename window_6_0 "window_6[0]") (joined
+           (portRef Z (instanceRef window_RNO_0))
+           (portRef D (instanceRef window_0))
+          ))
+          (net (rename trig_dl_3 "trig_dl[3]") (joined
+           (portRef Q (instanceRef trig_dl_3))
+           (portRef B (instanceRef window_0_sqmuxadup))
+           (portRef A (instanceRef trig_dl_RNI41GL1_3))
+          ))
+          (net (rename trig_dl_2 "trig_dl[2]") (joined
+           (portRef Q (instanceRef trig_dl_2))
+           (portRef A (instanceRef window_0_sqmuxadup))
+           (portRef D (instanceRef trig_dl_3))
+           (portRef B (instanceRef trig_dl_RNI41GL1_3))
+          ))
+          (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined
+           (portRef Q (instanceRef invalid_dl_3))
+           (portRef (member hades_invalid_dl_c 0))
+           (portRef B (instanceRef un1_invalid_dl))
+           (portRef C (instanceRef trig_dl_RNI41GL1_3))
+          ))
+          (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined
+           (portRef Q (instanceRef invalid_dl_2))
+           (portRef (member hades_invalid_dl_c 1))
+           (portRef A (instanceRef un1_invalid_dl))
+           (portRef D (instanceRef invalid_dl_3))
+           (portRef D (instanceRef trig_dl_RNI41GL1_3))
+          ))
+          (net window_0_sqmuxa (joined
+           (portRef Z (instanceRef trig_dl_RNI41GL1_3))
+           (portRef D (instanceRef discard_en))
+           (portRef D (instanceRef discard))
+          ))
+          (net (rename hit_i_1 "hit_i[1]") (joined
+           (portRef (member hit_i 0))
+           (portRef A (instanceRef SUM1_0_0_o2_0))
+           (portRef A (instanceRef SUM1_0_0))
+          ))
+          (net (rename hit_i_0 "hit_i[0]") (joined
+           (portRef (member hit_i 1))
+           (portRef B (instanceRef SUM1_0_0_o2_0))
+           (portRef B (instanceRef SUM1_0_0_o2))
+           (portRef B (instanceRef SUM0_1_0_x2))
+           (portRef B (instanceRef SUM1_0_0))
+          ))
+          (net hades_raw_out_valid (joined
+           (portRef hades_raw_out_valid)
+           (portRef C (instanceRef SUM1_0_0_o2_0))
+           (portRef A (instanceRef SUM1_0_0_o2))
+           (portRef A (instanceRef SUM0_1_0_x2))
+           (portRef C (instanceRef SUM1_0_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef un1_window_8_s_7_0))
+           (portRef C1 (instanceRef un1_window_8_s_7_0))
+           (portRef B1 (instanceRef un1_window_8_s_7_0))
+           (portRef A1 (instanceRef un1_window_8_s_7_0))
+           (portRef D0 (instanceRef un1_window_8_s_7_0))
+           (portRef C0 (instanceRef un1_window_8_s_7_0))
+           (portRef D1 (instanceRef un1_window_8_cry_5_0))
+           (portRef D0 (instanceRef un1_window_8_cry_5_0))
+           (portRef D1 (instanceRef un1_window_8_cry_3_0))
+           (portRef D0 (instanceRef un1_window_8_cry_3_0))
+           (portRef D1 (instanceRef un1_window_8_cry_1_0))
+           (portRef D0 (instanceRef un1_window_8_cry_1_0))
+           (portRef D1 (instanceRef un1_window_8_cry_0_0))
+           (portRef D0 (instanceRef un1_window_8_cry_0_0))
+           (portRef C0 (instanceRef un1_window_8_cry_0_0))
+           (portRef B0 (instanceRef un1_window_8_cry_0_0))
+           (portRef A0 (instanceRef un1_window_8_cry_0_0))
+          ))
+          (net (rename SUM1_0_0_1z "SUM1_0_0") (joined
+           (portRef Z (instanceRef SUM1_0_0))
+           (portRef SUM1_0_0_1z)
+          ))
+          (net ANB3 (joined
+           (portRef ANB3)
+           (portRef A (instanceRef N_50_i_i))
+          ))
+          (net ANB2 (joined
+           (portRef ANB2)
+           (portRef B (instanceRef N_50_i_i))
+          ))
+          (net ANB1 (joined
+           (portRef ANB1)
+           (portRef B (instanceRef SUM1_1_x2))
+           (portRef C (instanceRef N_50_i_i))
+          ))
+          (net ANB0 (joined
+           (portRef ANB0)
+           (portRef A (instanceRef SUM1_1_x2))
+           (portRef D (instanceRef N_50_i_i))
+          ))
+          (net (rename N_50_i_i_1z "N_50_i_i") (joined
+           (portRef Z (instanceRef N_50_i_i))
+           (portRef N_50_i_i_1z)
+          ))
+          (net window_end5 (joined
+           (portRef Z (instanceRef window_end5_0_a2))
+           (portRef D (instanceRef window_end))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef pll_clks_0 (instanceRef dec_inst))
+           (portRef (member pll_clks 0) (instanceRef tdc_inst))
+           (portRef CK (instanceRef discard))
+           (portRef CK (instanceRef invalid_dl_3))
+           (portRef CK (instanceRef invalid_dl_2))
+           (portRef CK (instanceRef invalid_dl_1))
+           (portRef CK (instanceRef offset_valid))
+           (portRef CK (instanceRef trig_dl_3))
+           (portRef CK (instanceRef trig_dl_2))
+           (portRef CK (instanceRef trig_dl_1))
+           (portRef CK (instanceRef window_7))
+           (portRef CK (instanceRef window_6))
+           (portRef CK (instanceRef window_5))
+           (portRef CK (instanceRef window_4))
+           (portRef CK (instanceRef window_3))
+           (portRef CK (instanceRef window_2))
+           (portRef CK (instanceRef window_1))
+           (portRef CK (instanceRef window_0))
+           (portRef CK (instanceRef window_end))
+          ))
+          (net hades_window_end_c (joined
+           (portRef Q (instanceRef window_end))
+           (portRef hades_window_end_c)
+          ))
+          (net window_0_sqmuxadup (joined
+           (portRef Z (instanceRef window_0_sqmuxadup))
+           (portRef CD (instanceRef window_7))
+           (portRef CD (instanceRef window_6))
+           (portRef CD (instanceRef window_5))
+           (portRef CD (instanceRef window_4))
+           (portRef CD (instanceRef window_3))
+           (portRef D (instanceRef window_2))
+           (portRef CD (instanceRef window_1))
+           (portRef CD (instanceRef window_0))
+          ))
+          (net (rename window_6_1 "window_6[1]") (joined
+           (portRef Z (instanceRef window_6_1))
+           (portRef D (instanceRef window_1))
+          ))
+          (net (rename window_1 "window[1]") (joined
+           (portRef Q (instanceRef window_1))
+           (portRef A0 (instanceRef un1_window_8_cry_1_0))
+           (portRef B (instanceRef window_RNICU4C_3))
+           (portRef C (instanceRef un1_reset_0_a2_1))
+           (portRef C (instanceRef window_end5_0_a2))
+           (portRef D (instanceRef un1_reset_0_a2_c))
+           (portRef C (instanceRef discard_en))
+           (portRef D (instanceRef offset_1_sqmuxa_i_0))
+          ))
+          (net (rename window_6_2 "window_6[2]") (joined
+           (portRef Z (instanceRef window_6_2))
+           (portRef PD (instanceRef window_2))
+          ))
+          (net (rename window_2 "window[2]") (joined
+           (portRef Q (instanceRef window_2))
+           (portRef A1 (instanceRef un1_window_8_cry_1_0))
+           (portRef A (instanceRef window_RNIOA5C_2))
+           (portRef A (instanceRef discard4_0_a2_0_3))
+          ))
+          (net (rename window_6_3 "window_6[3]") (joined
+           (portRef Z (instanceRef window_6_3))
+           (portRef D (instanceRef window_3))
+          ))
+          (net (rename window_3 "window[3]") (joined
+           (portRef Q (instanceRef window_3))
+           (portRef A0 (instanceRef un1_window_8_cry_3_0))
+           (portRef C (instanceRef window_RNICU4C_3))
+           (portRef B (instanceRef discard4_0_a2_0))
+          ))
+          (net (rename window_6_4 "window_6[4]") (joined
+           (portRef Z (instanceRef window_6_4))
+           (portRef D (instanceRef window_4))
+          ))
+          (net (rename window_4 "window[4]") (joined
+           (portRef Q (instanceRef window_4))
+           (portRef A1 (instanceRef un1_window_8_cry_3_0))
+           (portRef D (instanceRef window_RNICU4C_3))
+           (portRef C (instanceRef discard4_0_a2_0))
+          ))
+          (net (rename window_6_5 "window_6[5]") (joined
+           (portRef Z (instanceRef window_6_5))
+           (portRef D (instanceRef window_5))
+          ))
+          (net (rename window_5 "window[5]") (joined
+           (portRef Q (instanceRef window_5))
+           (portRef A0 (instanceRef un1_window_8_cry_5_0))
+           (portRef B (instanceRef window_RNIOA5C_2))
+           (portRef B (instanceRef discard4_0_a2_0_3))
+          ))
+          (net (rename window_6_6 "window_6[6]") (joined
+           (portRef Z (instanceRef window_6_6))
+           (portRef D (instanceRef window_6))
+          ))
+          (net (rename window_6 "window[6]") (joined
+           (portRef Q (instanceRef window_6))
+           (portRef A1 (instanceRef un1_window_8_cry_5_0))
+           (portRef C (instanceRef window_RNIOA5C_2))
+           (portRef C (instanceRef discard4_0_a2_0_3))
+          ))
+          (net (rename window_6_7 "window_6[7]") (joined
+           (portRef Z (instanceRef window_6_7))
+           (portRef D (instanceRef window_7))
+          ))
+          (net (rename window_7 "window[7]") (joined
+           (portRef Q (instanceRef window_7))
+           (portRef A0 (instanceRef un1_window_8_s_7_0))
+           (portRef D (instanceRef window_RNIOA5C_2))
+           (portRef D (instanceRef discard4_0_a2_0_3))
+          ))
+          (net (rename trig_dl_0 "trig_dl[0]") (joined
+           (portRef trig_dl_0)
+           (portRef D (instanceRef trig_dl_1))
+          ))
+          (net (rename trig_dl_1 "trig_dl[1]") (joined
+           (portRef Q (instanceRef trig_dl_1))
+           (portRef D (instanceRef trig_dl_2))
+          ))
+          (net N_39_i (joined
+           (portRef Z (instanceRef offset_valid_RNO))
+           (portRef D (instanceRef offset_valid))
+          ))
+          (net (rename offset_1_sqmuxa_i_0_1z "offset_1_sqmuxa_i_0") (joined
+           (portRef Z (instanceRef offset_1_sqmuxa_i_0))
+           (portRef offset_1_sqmuxa_i_0 (instanceRef dec_inst))
+           (portRef SP (instanceRef offset_valid))
+           (portRef offset_1_sqmuxa_i_0_1z)
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef reset_dl_0 (instanceRef dec_inst))
+           (portRef D (instanceRef window_0_sqmuxadup))
+           (portRef D (instanceRef window_6_1))
+           (portRef D (instanceRef window_6_2))
+           (portRef D (instanceRef window_6_3))
+           (portRef D (instanceRef window_6_4))
+           (portRef D (instanceRef window_6_5))
+           (portRef D (instanceRef window_6_6))
+           (portRef D (instanceRef window_6_7))
+           (portRef CD (instanceRef discard))
+           (portRef CD (instanceRef offset_valid))
+          ))
+          (net hades_offset_valid_c (joined
+           (portRef Q (instanceRef offset_valid))
+           (portRef hades_offset_valid_c)
+          ))
+          (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined
+           (portRef (member hades_invalid_dl_c 3))
+           (portRef D (instanceRef invalid_dl_1))
+          ))
+          (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined
+           (portRef Q (instanceRef invalid_dl_1))
+           (portRef (member hades_invalid_dl_c 2))
+           (portRef D (instanceRef invalid_dl_2))
+          ))
+          (net discard_en (joined
+           (portRef Z (instanceRef discard_en))
+           (portRef SP (instanceRef discard))
+          ))
+          (net un1_reset_0_a2_1 (joined
+           (portRef Z (instanceRef un1_reset_0_a2_1))
+           (portRef B (instanceRef un1_reset_0_a2_2))
+          ))
+          (net un1_reset_0_a2_2_0 (joined
+           (portRef un1_reset_0_a2_2_0 (instanceRef dec_inst))
+           (portRef B1 (instanceRef un1_window_8_cry_5_0))
+           (portRef B0 (instanceRef un1_window_8_cry_5_0))
+           (portRef B1 (instanceRef un1_window_8_cry_3_0))
+           (portRef B0 (instanceRef un1_window_8_cry_3_0))
+           (portRef B1 (instanceRef un1_window_8_cry_1_0))
+           (portRef B0 (instanceRef un1_window_8_cry_1_0))
+           (portRef B1 (instanceRef un1_window_8_cry_0_0))
+           (portRef C (instanceRef un1_reset_0_a2_2))
+          ))
+          (net N_39 (joined
+           (portRef Z (instanceRef offset_1_sqmuxa_i_0_o2))
+           (portRef A (instanceRef offset_1_sqmuxa_i_0))
+          ))
+          (net N_97 (joined
+           (portRef Z (instanceRef discard4_0_a2_0))
+           (portRef A (instanceRef un1_reset_0_a2_1))
+           (portRef A (instanceRef window_end5_0_a2))
+           (portRef A (instanceRef un1_reset_0_a2_c))
+           (portRef A (instanceRef discard_en))
+           (portRef B (instanceRef offset_1_sqmuxa_i_0))
+          ))
+          (net un1_reset_0_a2_c (joined
+           (portRef Z (instanceRef un1_reset_0_a2_c))
+           (portRef C1 (instanceRef un1_window_8_cry_5_0))
+           (portRef C0 (instanceRef un1_window_8_cry_5_0))
+           (portRef C1 (instanceRef un1_window_8_cry_3_0))
+           (portRef C0 (instanceRef un1_window_8_cry_3_0))
+           (portRef C1 (instanceRef un1_window_8_cry_1_0))
+           (portRef C0 (instanceRef un1_window_8_cry_1_0))
+           (portRef C1 (instanceRef un1_window_8_cry_0_0))
+          ))
+          (net decoder_valid (joined
+           (portRef decoder_valid (instanceRef dec_inst))
+           (portRef B (instanceRef offset_valid_RNO))
+           (portRef B (instanceRef window_6_1))
+           (portRef B (instanceRef window_6_2))
+           (portRef B (instanceRef window_6_3))
+           (portRef B (instanceRef window_6_4))
+           (portRef B (instanceRef window_6_5))
+           (portRef B (instanceRef window_6_6))
+           (portRef B (instanceRef window_6_7))
+          ))
+          (net un1_window_8_s_7_0_S0 (joined
+           (portRef S0 (instanceRef un1_window_8_s_7_0))
+           (portRef C (instanceRef window_6_7))
+          ))
+          (net un1_window_8_cry_5_0_S1 (joined
+           (portRef S1 (instanceRef un1_window_8_cry_5_0))
+           (portRef C (instanceRef window_6_6))
+          ))
+          (net un1_window_8_cry_5_0_S0 (joined
+           (portRef S0 (instanceRef un1_window_8_cry_5_0))
+           (portRef C (instanceRef window_6_5))
+          ))
+          (net un1_window_8_cry_3_0_S1 (joined
+           (portRef S1 (instanceRef un1_window_8_cry_3_0))
+           (portRef C (instanceRef window_6_4))
+          ))
+          (net un1_window_8_cry_3_0_S0 (joined
+           (portRef S0 (instanceRef un1_window_8_cry_3_0))
+           (portRef C (instanceRef window_6_3))
+          ))
+          (net un1_window_8_cry_1_0_S1 (joined
+           (portRef S1 (instanceRef un1_window_8_cry_1_0))
+           (portRef C (instanceRef window_6_2))
+          ))
+          (net un1_window_8_cry_1_0_S0 (joined
+           (portRef S0 (instanceRef un1_window_8_cry_1_0))
+           (portRef C (instanceRef window_6_1))
+          ))
+          (net un1_invalid_dl (joined
+           (portRef Z (instanceRef un1_invalid_dl))
+           (portRef C (instanceRef window_0_sqmuxadup))
+          ))
+          (net discard4_0_a2_0_3 (joined
+           (portRef Z (instanceRef discard4_0_a2_0_3))
+           (portRef A (instanceRef discard4_0_a2_0))
+          ))
+          (net N_59_i (joined
+           (portRef Z (instanceRef SUM0_1_0_x2))
+           (portRef N_59_i)
+          ))
+          (net N_46_i (joined
+           (portRef Z (instanceRef SUM1_1_x2))
+           (portRef N_46_i)
+          ))
+          (net N_40 (joined
+           (portRef Z (instanceRef SUM1_0_0_o2))
+           (portRef N_40)
+          ))
+          (net G_25_0_a3_4_0 (joined
+           (portRef Z (instanceRef window_RNIOA5C_2))
+           (portRef G_25_0_a3_4_0 (instanceRef dec_inst))
+          ))
+          (net G_25_0_a3_5_0 (joined
+           (portRef Z (instanceRef window_RNICU4C_3))
+           (portRef G_25_0_a3_5_0 (instanceRef dec_inst))
+          ))
+          (net N_44 (joined
+           (portRef Z (instanceRef SUM1_0_0_o2_0))
+           (portRef N_44)
+          ))
+          (net un1_window_8_cry_0 (joined
+           (portRef COUT (instanceRef un1_window_8_cry_0_0))
+           (portRef CIN (instanceRef un1_window_8_cry_1_0))
+          ))
+          (net un1_window_8_cry_0_0_S0 (joined
+           (portRef S0 (instanceRef un1_window_8_cry_0_0))
+          ))
+          (net un1_window_8_cry_0_0_S1 (joined
+           (portRef S1 (instanceRef un1_window_8_cry_0_0))
+          ))
+          (net un1_window_8_cry_2 (joined
+           (portRef COUT (instanceRef un1_window_8_cry_1_0))
+           (portRef CIN (instanceRef un1_window_8_cry_3_0))
+          ))
+          (net un1_window_8_cry_4 (joined
+           (portRef COUT (instanceRef un1_window_8_cry_3_0))
+           (portRef CIN (instanceRef un1_window_8_cry_5_0))
+          ))
+          (net un1_window_8_cry_6 (joined
+           (portRef COUT (instanceRef un1_window_8_cry_5_0))
+           (portRef CIN (instanceRef un1_window_8_s_7_0))
+          ))
+          (net un1_window_8_s_7_0_COUT (joined
+           (portRef COUT (instanceRef un1_window_8_s_7_0))
+          ))
+          (net un1_window_8_s_7_0_S1 (joined
+           (portRef S1 (instanceRef un1_window_8_s_7_0))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7) (instanceRef tdc_inst))
+           (portRef (member tdc_out 7) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6) (instanceRef tdc_inst))
+           (portRef (member tdc_out 6) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5) (instanceRef tdc_inst))
+           (portRef (member tdc_out 5) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4) (instanceRef tdc_inst))
+           (portRef (member tdc_out 4) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3) (instanceRef tdc_inst))
+           (portRef (member tdc_out 3) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2) (instanceRef tdc_inst))
+           (portRef (member tdc_out 2) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1) (instanceRef tdc_inst))
+           (portRef (member tdc_out 1) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0) (instanceRef tdc_inst))
+           (portRef (member tdc_out 0) (instanceRef dec_inst))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef tdc_inst))
+          ))
+          (net hades_lvl1_c_i (joined
+           (portRef hades_lvl1_c_i)
+           (portRef hades_lvl1_c_i (instanceRef tdc_inst))
+          ))
+          (net CN (joined
+           (portRef CN (instanceRef dec_inst))
+           (portRef CN_2 (instanceRef tdc_inst))
+           (portRef CN)
+          ))
+          (net CN_0 (joined
+           (portRef CN_1 (instanceRef tdc_inst))
+           (portRef CN_0)
+          ))
+          (net CN_1 (joined
+           (portRef CN_0 (instanceRef tdc_inst))
+           (portRef CN_1)
+          ))
+          (net CN_2 (joined
+           (portRef CN (instanceRef tdc_inst))
+           (portRef CN_2)
+          ))
+          (net (rename offset_5_0 "offset_5[0]") (joined
+           (portRef (member offset_5 2) (instanceRef dec_inst))
+           (portRef (member offset_5 2))
+          ))
+          (net (rename offset_5_1 "offset_5[1]") (joined
+           (portRef (member offset_5 1) (instanceRef dec_inst))
+           (portRef (member offset_5 1))
+          ))
+          (net (rename offset_5_2 "offset_5[2]") (joined
+           (portRef (member offset_5 0) (instanceRef dec_inst))
+           (portRef (member offset_5 0))
+          ))
+          (net valid_fast_RNI999V (joined
+           (portRef valid_fast_RNI999V_1z (instanceRef dec_inst))
+           (portRef valid_fast_RNI999V)
+          ))
+          (net N_1 (joined
+           (portRef CIN (instanceRef un1_window_8_cry_0_0))
+          ))
+         )
+        (property WINDOW_LENGTH (string "32'h000000ff"))
+        (property TDC_WIDTH (integer 3))
+        (property COARSE_WIDTH (integer 9))
+        (property orig_inst_of (string "hades_LVL1_raw_out"))
+       )
+    )
+    (cell EHXPLLL (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port CLKI (direction INPUT))
+           (port CLKFB (direction INPUT))
+           (port PHASESEL1 (direction INPUT))
+           (port PHASESEL0 (direction INPUT))
+           (port PHASEDIR (direction INPUT))
+           (port PHASESTEP (direction INPUT))
+           (port PHASELOADREG (direction INPUT))
+           (port STDBY (direction INPUT))
+           (port PLLWAKESYNC (direction INPUT))
+           (port RST (direction INPUT))
+           (port ENCLKOP (direction INPUT))
+           (port ENCLKOS (direction INPUT))
+           (port ENCLKOS2 (direction INPUT))
+           (port ENCLKOS3 (direction INPUT))
+           (port CLKOP (direction OUTPUT))
+           (port CLKOS (direction OUTPUT))
+           (port CLKOS2 (direction OUTPUT))
+           (port CLKOS3 (direction OUTPUT))
+           (port LOCK (direction OUTPUT))
+           (port INTLOCK (direction OUTPUT))
+           (port REFCLK (direction OUTPUT))
+           (port CLKINTFB (direction OUTPUT))
+         )
+        (property INTFB_WAKE (string "DISABLED"))
+        (property PLLRST_ENA (string "DISABLED"))
+        (property DPHASE_SOURCE (string "DISABLED"))
+        (property INT_LOCK_STICKY (string "ENABLED"))
+        (property SYNC_ENABLE (string "DISABLED"))
+        (property REFIN_RESET (string "DISABLED"))
+        (property STDBY_ENABLE (string "DISABLED"))
+        (property PLL_LOCK_DELAY (integer 200))
+        (property PLL_LOCK_MODE (integer 0))
+        (property OUTDIVIDER_MUXD (string "DIVD"))
+        (property OUTDIVIDER_MUXC (string "DIVC"))
+        (property OUTDIVIDER_MUXB (string "DIVB"))
+        (property OUTDIVIDER_MUXA (string "DIVA"))
+        (property CLKOS_TRIM_DELAY (integer 0))
+        (property CLKOS_TRIM_POL (string "FALLING"))
+        (property CLKOP_TRIM_DELAY (integer 0))
+        (property CLKOP_TRIM_POL (string "FALLING"))
+        (property FEEDBK_PATH (string "CLKOP"))
+        (property CLKOS3_FPHASE (integer 6))
+        (property CLKOS2_FPHASE (integer 4))
+        (property CLKOS_FPHASE (integer 2))
+        (property CLKOP_FPHASE (integer 0))
+        (property CLKOS3_CPHASE (integer 1))
+        (property CLKOS2_CPHASE (integer 1))
+        (property CLKOS_CPHASE (integer 1))
+        (property CLKOP_CPHASE (integer 1))
+        (property CLKOS3_ENABLE (string "ENABLED"))
+        (property CLKOS2_ENABLE (string "ENABLED"))
+        (property CLKOS_ENABLE (string "ENABLED"))
+        (property CLKOP_ENABLE (string "ENABLED"))
+        (property CLKOS3_DIV (integer 2))
+        (property CLKOS2_DIV (integer 2))
+        (property CLKOS_DIV (integer 2))
+        (property CLKOP_DIV (integer 2))
+        (property CLKFB_DIV (integer 3))
+        (property CLKI_DIV (integer 1))
+        (property orig_inst_of (string "EHXPLLL"))
+       )
+    )
+    (cell tdc_channel_fifo_out_3 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port fifo_read_0 (direction INPUT))
+           (port fifo_empty_0 (direction OUTPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_4))
+          )
+          (instance dec_inst (viewRef netlist (cellRef output_decoder8_2_1))
+          )
+          (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc_1))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net decoder_valid (joined
+           (portRef decoder_valid (instanceRef dec_inst))
+           (portRef D (instanceRef fifo_wren))
+           (portRef A (instanceRef fifo_in_data_11__fb))
+          ))
+          (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined
+           (portRef Q (instanceRef fifo_in_data_11))
+           (portRef fifo_in_data_0 (instanceRef fifo32dc_inst))
+           (portRef B (instanceRef fifo_in_data_11__fb))
+          ))
+          (net fb_0 (joined
+           (portRef Z (instanceRef fifo_in_data_11__fb))
+           (portRef D (instanceRef fifo_in_data_11))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CN (instanceRef dec_inst))
+           (portRef CN (instanceRef tdc_inst))
+           (portRef CK (instanceRef fifo_in_data_11))
+           (portRef CK (instanceRef fifo_wren))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef CD (instanceRef fifo_in_data_11))
+           (portRef CD (instanceRef fifo_wren))
+          ))
+          (net fifo_wren (joined
+           (portRef Q (instanceRef fifo_wren))
+           (portRef fifo_wren (instanceRef fifo32dc_inst))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7) (instanceRef tdc_inst))
+           (portRef (member tdc_out 7) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6) (instanceRef tdc_inst))
+           (portRef (member tdc_out 6) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5) (instanceRef tdc_inst))
+           (portRef (member tdc_out 5) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4) (instanceRef tdc_inst))
+           (portRef (member tdc_out 4) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3) (instanceRef tdc_inst))
+           (portRef (member tdc_out 3) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2) (instanceRef tdc_inst))
+           (portRef (member tdc_out 2) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1) (instanceRef tdc_inst))
+           (portRef (member tdc_out 1) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0) (instanceRef tdc_inst))
+           (portRef (member tdc_out 0) (instanceRef dec_inst))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef pll_clks_0 (instanceRef fifo32dc_inst))
+           (portRef (member pll_clks 0) (instanceRef tdc_inst))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[2]") (joined
+           (portRef trig_c_i_0)
+           (portRef trig_c_i_0 (instanceRef tdc_inst))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CN_2 (instanceRef tdc_inst))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CN_1 (instanceRef tdc_inst))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CN_0 (instanceRef tdc_inst))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename fifo_empty_0 "fifo_empty[2]") (joined
+           (portRef fifo_empty_0 (instanceRef fifo32dc_inst))
+           (portRef fifo_empty_0)
+          ))
+          (net (rename fifo_read_0 "fifo_read[2]") (joined
+           (portRef fifo_read_0)
+           (portRef fifo_read_0 (instanceRef fifo32dc_inst))
+          ))
+         )
+        (property orig_inst_of (string "tdc_channel_fifo_out"))
+       )
+    )
+    (cell tdc_channel_fifo_out_2 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port fifo_read_0 (direction INPUT))
+           (port fifo_empty_0 (direction OUTPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_3))
+          )
+          (instance dec_inst (viewRef netlist (cellRef output_decoder8_2_0))
+          )
+          (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc_0))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net decoder_valid (joined
+           (portRef decoder_valid (instanceRef dec_inst))
+           (portRef D (instanceRef fifo_wren))
+           (portRef A (instanceRef fifo_in_data_11__fb))
+          ))
+          (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined
+           (portRef Q (instanceRef fifo_in_data_11))
+           (portRef fifo_in_data_0 (instanceRef fifo32dc_inst))
+           (portRef B (instanceRef fifo_in_data_11__fb))
+          ))
+          (net fb_0 (joined
+           (portRef Z (instanceRef fifo_in_data_11__fb))
+           (portRef D (instanceRef fifo_in_data_11))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CN (instanceRef dec_inst))
+           (portRef CN (instanceRef tdc_inst))
+           (portRef CK (instanceRef fifo_in_data_11))
+           (portRef CK (instanceRef fifo_wren))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef CD (instanceRef fifo_in_data_11))
+           (portRef CD (instanceRef fifo_wren))
+          ))
+          (net fifo_wren (joined
+           (portRef Q (instanceRef fifo_wren))
+           (portRef fifo_wren (instanceRef fifo32dc_inst))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7) (instanceRef tdc_inst))
+           (portRef (member tdc_out 7) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6) (instanceRef tdc_inst))
+           (portRef (member tdc_out 6) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5) (instanceRef tdc_inst))
+           (portRef (member tdc_out 5) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4) (instanceRef tdc_inst))
+           (portRef (member tdc_out 4) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3) (instanceRef tdc_inst))
+           (portRef (member tdc_out 3) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2) (instanceRef tdc_inst))
+           (portRef (member tdc_out 2) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1) (instanceRef tdc_inst))
+           (portRef (member tdc_out 1) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0) (instanceRef tdc_inst))
+           (portRef (member tdc_out 0) (instanceRef dec_inst))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef pll_clks_0 (instanceRef fifo32dc_inst))
+           (portRef (member pll_clks 0) (instanceRef tdc_inst))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[1]") (joined
+           (portRef trig_c_i_0)
+           (portRef trig_c_i_0 (instanceRef tdc_inst))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CN_2 (instanceRef tdc_inst))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CN_1 (instanceRef tdc_inst))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CN_0 (instanceRef tdc_inst))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename fifo_empty_0 "fifo_empty[1]") (joined
+           (portRef fifo_empty_0 (instanceRef fifo32dc_inst))
+           (portRef fifo_empty_0)
+          ))
+          (net (rename fifo_read_0 "fifo_read[1]") (joined
+           (portRef fifo_read_0)
+           (portRef fifo_read_0 (instanceRef fifo32dc_inst))
+          ))
+         )
+        (property orig_inst_of (string "tdc_channel_fifo_out"))
+       )
+    )
+    (cell tdc_channel_fifo_out (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port fifo_read_0 (direction INPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT))
+           (port trig_c_i_0 (direction INPUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port fifo_empty1_c (direction OUTPUT))
+           (port CN_2 (direction INPUT))
+           (port CN_1 (direction INPUT))
+           (port CN_0 (direction INPUT))
+           (port CN (direction INPUT))
+         )
+         (contents
+          (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_2))
+          )
+          (instance dec_inst (viewRef netlist (cellRef output_decoder8_2))
+          )
+          (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net decoder_valid (joined
+           (portRef decoder_valid (instanceRef dec_inst))
+           (portRef D (instanceRef fifo_wren))
+           (portRef A (instanceRef fifo_in_data_11__fb))
+          ))
+          (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined
+           (portRef Q (instanceRef fifo_in_data_11))
+           (portRef fifo_in_data_0 (instanceRef fifo32dc_inst))
+           (portRef B (instanceRef fifo_in_data_11__fb))
+          ))
+          (net fb_0 (joined
+           (portRef Z (instanceRef fifo_in_data_11__fb))
+           (portRef D (instanceRef fifo_in_data_11))
+          ))
+          (net CN (joined
+           (portRef CN)
+           (portRef CN (instanceRef dec_inst))
+           (portRef CN (instanceRef tdc_inst))
+           (portRef CK (instanceRef fifo_in_data_11))
+           (portRef CK (instanceRef fifo_wren))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef CD (instanceRef fifo_in_data_11))
+           (portRef CD (instanceRef fifo_wren))
+          ))
+          (net fifo_wren (joined
+           (portRef Q (instanceRef fifo_wren))
+           (portRef fifo_wren (instanceRef fifo32dc_inst))
+          ))
+          (net (rename tdc_out_0 "tdc_out[0]") (joined
+           (portRef (member tdc_out 7) (instanceRef tdc_inst))
+           (portRef (member tdc_out 7) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_1 "tdc_out[1]") (joined
+           (portRef (member tdc_out 6) (instanceRef tdc_inst))
+           (portRef (member tdc_out 6) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_2 "tdc_out[2]") (joined
+           (portRef (member tdc_out 5) (instanceRef tdc_inst))
+           (portRef (member tdc_out 5) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_3 "tdc_out[3]") (joined
+           (portRef (member tdc_out 4) (instanceRef tdc_inst))
+           (portRef (member tdc_out 4) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_4 "tdc_out[4]") (joined
+           (portRef (member tdc_out 3) (instanceRef tdc_inst))
+           (portRef (member tdc_out 3) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_5 "tdc_out[5]") (joined
+           (portRef (member tdc_out 2) (instanceRef tdc_inst))
+           (portRef (member tdc_out 2) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_6 "tdc_out[6]") (joined
+           (portRef (member tdc_out 1) (instanceRef tdc_inst))
+           (portRef (member tdc_out 1) (instanceRef dec_inst))
+          ))
+          (net (rename tdc_out_7 "tdc_out[7]") (joined
+           (portRef (member tdc_out 0) (instanceRef tdc_inst))
+           (portRef (member tdc_out 0) (instanceRef dec_inst))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef tdc_inst))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef pll_clks_0 (instanceRef fifo32dc_inst))
+           (portRef (member pll_clks 0) (instanceRef tdc_inst))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[0]") (joined
+           (portRef trig_c_i_0)
+           (portRef trig_c_i_0 (instanceRef tdc_inst))
+          ))
+          (net CN_0 (joined
+           (portRef CN_0)
+           (portRef CN_2 (instanceRef tdc_inst))
+          ))
+          (net CN_1 (joined
+           (portRef CN_1)
+           (portRef CN_1 (instanceRef tdc_inst))
+          ))
+          (net CN_2 (joined
+           (portRef CN_2)
+           (portRef CN_0 (instanceRef tdc_inst))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 16))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 15))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 14))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 13))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 12))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 11))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 10))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 9))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 7))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 6))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 5))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 4))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 3))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 2))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 1))
+          ))
+          (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 0))
+          ))
+          (net (rename fifo_read_0 "fifo_read[0]") (joined
+           (portRef fifo_read_0)
+           (portRef fifo_read_0 (instanceRef fifo32dc_inst))
+          ))
+          (net fifo_empty1_c (joined
+           (portRef fifo_empty1_c (instanceRef fifo32dc_inst))
+           (portRef fifo_empty1_c)
+          ))
+         )
+        (property orig_inst_of (string "tdc_channel_fifo_out"))
+       )
+    )
+    (cell fifo_colector (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename fee_data_out_c "FEE_DATA_OUT_c[31:0]") 32) (direction OUTPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst_1[23:0]") 24) (direction INPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst_0[23:0]") 24) (direction INPUT))
+           (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction INPUT))
+           (port (array (rename fifo_empty "fifo_empty[2:1]") 2) (direction INPUT))
+           (port pll_clks_0 (direction INPUT))
+           (port (array (rename fifo_read "fifo_read[2:0]") 3) (direction OUTPUT))
+           (port fifo_rden_c (direction INPUT))
+           (port last_buf_empty_c (direction OUTPUT))
+           (port rd_clk_c (direction INPUT))
+           (port fifo_empty1_c (direction INPUT))
+         )
+         (contents
+          (instance (rename in_read_enable_0__fb "in_read_enable_0_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C A)"))
+          )
+          (instance in_empty_pmux_0_RNIDRET (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+!A)+C (B !A))"))
+          )
+          (instance (rename in_read_enable_2__fb "in_read_enable_2_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename in_read_enable_1__fb "in_read_enable_1_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename iterator_0 "iterator[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename iterator_1 "iterator[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename in_read_enable_0 "in_read_enable[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename in_read_enable_1 "in_read_enable[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename in_read_enable_2 "in_read_enable[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_0 "data_buffer[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_1 "data_buffer[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_2 "data_buffer[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_3 "data_buffer[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_4 "data_buffer[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_5 "data_buffer[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_6 "data_buffer[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_7 "data_buffer[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_8 "data_buffer[8]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_9 "data_buffer[9]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_10 "data_buffer[10]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_11 "data_buffer[11]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_12 "data_buffer[12]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_13 "data_buffer[13]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_14 "data_buffer[14]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_15 "data_buffer[15]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_16 "data_buffer[16]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_17 "data_buffer[17]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_18 "data_buffer[18]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_19 "data_buffer[19]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_20 "data_buffer[20]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_21 "data_buffer[21]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_22 "data_buffer[22]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_23 "data_buffer[23]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_24 "data_buffer[24]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_25 "data_buffer[25]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_26 "data_buffer[26]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_27 "data_buffer[27]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_28 "data_buffer[28]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_29 "data_buffer[29]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_30 "data_buffer[30]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_31 "data_buffer[31]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_32 "data_buffer[32]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename data_buffer_33 "data_buffer[33]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance buffer_wr_enable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance in_empty_pmux_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0 "data_buffer_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_1 "data_buffer_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_2 "data_buffer_3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_3 "data_buffer_3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_4 "data_buffer_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_5 "data_buffer_3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_6 "data_buffer_3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_7 "data_buffer_3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C (B+A))"))
+          )
+          (instance in_empty_pmux_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_0 "data_buffer_3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_1 "data_buffer_3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_2 "data_buffer_3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_3 "data_buffer_3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_4 "data_buffer_3_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_5 "data_buffer_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_6 "data_buffer_3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_8 "data_buffer_3_0[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_9 "data_buffer_3_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_10 "data_buffer_3_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_11 "data_buffer_3_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_12 "data_buffer_3_0[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_13 "data_buffer_3_0[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_14 "data_buffer_3_0[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_15 "data_buffer_3_0[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_16 "data_buffer_3_0[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_17 "data_buffer_3_0[17]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_18 "data_buffer_3_0[18]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_19 "data_buffer_3_0[19]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_20 "data_buffer_3_0[20]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_21 "data_buffer_3_0[21]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_22 "data_buffer_3_0[22]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_23 "data_buffer_3_0[23]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_24 "data_buffer_3_0[24]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_25 "data_buffer_3_0[25]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_26 "data_buffer_3_0[26]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_27 "data_buffer_3_0[27]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_28 "data_buffer_3_0[28]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_29 "data_buffer_3_0[29]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_30 "data_buffer_3_0[30]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_31 "data_buffer_3_0[31]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance (rename data_buffer_3_0_7 "data_buffer_3_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance un5_in_read_enable (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename iterator_RNI7U5I_1 "iterator_RNI7U5I[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance fifo40_inst (viewRef netlist (cellRef fifo40_dc))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename fifo_read_0 "fifo_read[0]") (joined
+           (portRef Q (instanceRef in_read_enable_0))
+           (portRef A (instanceRef in_read_enable_0__fb))
+           (portRef (member fifo_read 2))
+          ))
+          (net (rename iterator_1 "iterator[1]") (joined
+           (portRef Q (instanceRef iterator_1))
+           (portRef A (instanceRef iterator_RNI7U5I_1))
+           (portRef B (instanceRef un5_in_read_enable))
+           (portRef B (instanceRef data_buffer_3_7))
+           (portRef B (instanceRef data_buffer_3_6))
+           (portRef B (instanceRef data_buffer_3_5))
+           (portRef B (instanceRef data_buffer_3_4))
+           (portRef B (instanceRef data_buffer_3_3))
+           (portRef B (instanceRef data_buffer_3_2))
+           (portRef B (instanceRef data_buffer_3_1))
+           (portRef B (instanceRef data_buffer_3_0))
+           (portRef B (instanceRef in_empty_pmux_u))
+           (portRef D (instanceRef data_buffer_33))
+           (portRef A (instanceRef in_read_enable_2__fb))
+           (portRef B (instanceRef in_empty_pmux_0_RNIDRET))
+           (portRef B (instanceRef in_read_enable_0__fb))
+          ))
+          (net (rename iterator_0 "iterator[0]") (joined
+           (portRef Q (instanceRef iterator_0))
+           (portRef A (instanceRef un5_in_read_enable))
+           (portRef A (instanceRef data_buffer_3_0_7))
+           (portRef A (instanceRef data_buffer_3_0_31))
+           (portRef A (instanceRef data_buffer_3_0_30))
+           (portRef A (instanceRef data_buffer_3_0_29))
+           (portRef A (instanceRef data_buffer_3_0_28))
+           (portRef A (instanceRef data_buffer_3_0_27))
+           (portRef A (instanceRef data_buffer_3_0_26))
+           (portRef A (instanceRef data_buffer_3_0_25))
+           (portRef A (instanceRef data_buffer_3_0_24))
+           (portRef A (instanceRef data_buffer_3_0_23))
+           (portRef A (instanceRef data_buffer_3_0_22))
+           (portRef A (instanceRef data_buffer_3_0_21))
+           (portRef A (instanceRef data_buffer_3_0_20))
+           (portRef A (instanceRef data_buffer_3_0_19))
+           (portRef A (instanceRef data_buffer_3_0_18))
+           (portRef A (instanceRef data_buffer_3_0_17))
+           (portRef A (instanceRef data_buffer_3_0_16))
+           (portRef A (instanceRef data_buffer_3_0_15))
+           (portRef A (instanceRef data_buffer_3_0_14))
+           (portRef A (instanceRef data_buffer_3_0_13))
+           (portRef A (instanceRef data_buffer_3_0_12))
+           (portRef A (instanceRef data_buffer_3_0_11))
+           (portRef A (instanceRef data_buffer_3_0_10))
+           (portRef A (instanceRef data_buffer_3_0_9))
+           (portRef A (instanceRef data_buffer_3_0_8))
+           (portRef A (instanceRef data_buffer_3_0_6))
+           (portRef A (instanceRef data_buffer_3_0_5))
+           (portRef A (instanceRef data_buffer_3_0_4))
+           (portRef A (instanceRef data_buffer_3_0_3))
+           (portRef A (instanceRef data_buffer_3_0_2))
+           (portRef A (instanceRef data_buffer_3_0_1))
+           (portRef A (instanceRef data_buffer_3_0_0))
+           (portRef A (instanceRef in_empty_pmux_0))
+           (portRef D (instanceRef data_buffer_32))
+           (portRef D (instanceRef iterator_1))
+           (portRef A (instanceRef in_read_enable_1__fb))
+           (portRef C (instanceRef in_read_enable_0__fb))
+          ))
+          (net fb_0 (joined
+           (portRef Z (instanceRef in_read_enable_0__fb))
+           (portRef D (instanceRef in_read_enable_0))
+          ))
+          (net (rename fifo_empty_2 "fifo_empty[2]") (joined
+           (portRef (member fifo_empty 0))
+           (portRef B (instanceRef iterator_RNI7U5I_1))
+           (portRef C (instanceRef in_empty_pmux_u))
+           (portRef A (instanceRef in_empty_pmux_0_RNIDRET))
+          ))
+          (net in_empty_pmux_0 (joined
+           (portRef Z (instanceRef in_empty_pmux_0))
+           (portRef A (instanceRef in_empty_pmux_u))
+           (portRef C (instanceRef in_empty_pmux_0_RNIDRET))
+          ))
+          (net in_empty_pmux_i (joined
+           (portRef Z (instanceRef in_empty_pmux_0_RNIDRET))
+           (portRef D (instanceRef buffer_wr_enable))
+           (portRef SP (instanceRef data_buffer_33))
+           (portRef SP (instanceRef data_buffer_32))
+           (portRef SP (instanceRef data_buffer_31))
+           (portRef SP (instanceRef data_buffer_30))
+           (portRef SP (instanceRef data_buffer_29))
+           (portRef SP (instanceRef data_buffer_28))
+           (portRef SP (instanceRef data_buffer_27))
+           (portRef SP (instanceRef data_buffer_26))
+           (portRef SP (instanceRef data_buffer_25))
+           (portRef SP (instanceRef data_buffer_24))
+           (portRef SP (instanceRef data_buffer_23))
+           (portRef SP (instanceRef data_buffer_22))
+           (portRef SP (instanceRef data_buffer_21))
+           (portRef SP (instanceRef data_buffer_20))
+           (portRef SP (instanceRef data_buffer_19))
+           (portRef SP (instanceRef data_buffer_18))
+           (portRef SP (instanceRef data_buffer_17))
+           (portRef SP (instanceRef data_buffer_16))
+           (portRef SP (instanceRef data_buffer_15))
+           (portRef SP (instanceRef data_buffer_14))
+           (portRef SP (instanceRef data_buffer_13))
+           (portRef SP (instanceRef data_buffer_12))
+           (portRef SP (instanceRef data_buffer_11))
+           (portRef SP (instanceRef data_buffer_10))
+           (portRef SP (instanceRef data_buffer_9))
+           (portRef SP (instanceRef data_buffer_8))
+           (portRef SP (instanceRef data_buffer_7))
+           (portRef SP (instanceRef data_buffer_6))
+           (portRef SP (instanceRef data_buffer_5))
+           (portRef SP (instanceRef data_buffer_4))
+           (portRef SP (instanceRef data_buffer_3))
+           (portRef SP (instanceRef data_buffer_2))
+           (portRef SP (instanceRef data_buffer_1))
+           (portRef SP (instanceRef data_buffer_0))
+          ))
+          (net (rename fifo_read_2 "fifo_read[2]") (joined
+           (portRef Q (instanceRef in_read_enable_2))
+           (portRef B (instanceRef in_read_enable_2__fb))
+           (portRef (member fifo_read 0))
+          ))
+          (net fb_0_0 (joined
+           (portRef Z (instanceRef in_read_enable_2__fb))
+           (portRef D (instanceRef in_read_enable_2))
+          ))
+          (net (rename fifo_read_1 "fifo_read[1]") (joined
+           (portRef Q (instanceRef in_read_enable_1))
+           (portRef B (instanceRef in_read_enable_1__fb))
+           (portRef (member fifo_read 1))
+          ))
+          (net fb_0_1 (joined
+           (portRef Z (instanceRef in_read_enable_1__fb))
+           (portRef D (instanceRef in_read_enable_1))
+          ))
+          (net un5_in_read_enable (joined
+           (portRef Z (instanceRef un5_in_read_enable))
+           (portRef D (instanceRef iterator_0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[3]") (joined
+           (portRef pll_clks_0)
+           (portRef pll_clks_0 (instanceRef fifo40_inst))
+           (portRef CK (instanceRef buffer_wr_enable))
+           (portRef CK (instanceRef data_buffer_33))
+           (portRef CK (instanceRef data_buffer_32))
+           (portRef CK (instanceRef data_buffer_31))
+           (portRef CK (instanceRef data_buffer_30))
+           (portRef CK (instanceRef data_buffer_29))
+           (portRef CK (instanceRef data_buffer_28))
+           (portRef CK (instanceRef data_buffer_27))
+           (portRef CK (instanceRef data_buffer_26))
+           (portRef CK (instanceRef data_buffer_25))
+           (portRef CK (instanceRef data_buffer_24))
+           (portRef CK (instanceRef data_buffer_23))
+           (portRef CK (instanceRef data_buffer_22))
+           (portRef CK (instanceRef data_buffer_21))
+           (portRef CK (instanceRef data_buffer_20))
+           (portRef CK (instanceRef data_buffer_19))
+           (portRef CK (instanceRef data_buffer_18))
+           (portRef CK (instanceRef data_buffer_17))
+           (portRef CK (instanceRef data_buffer_16))
+           (portRef CK (instanceRef data_buffer_15))
+           (portRef CK (instanceRef data_buffer_14))
+           (portRef CK (instanceRef data_buffer_13))
+           (portRef CK (instanceRef data_buffer_12))
+           (portRef CK (instanceRef data_buffer_11))
+           (portRef CK (instanceRef data_buffer_10))
+           (portRef CK (instanceRef data_buffer_9))
+           (portRef CK (instanceRef data_buffer_8))
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+          (net fifo_empty1_c (joined
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+          (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined
+           (portRef (member fee_data_out_c 0) (instanceRef fifo40_inst))
+           (portRef (member fee_data_out_c 0))
+          ))
+          (net rd_clk_c (joined
+           (portRef rd_clk_c)
+           (portRef rd_clk_c (instanceRef fifo40_inst))
+          ))
+          (net last_buf_empty_c (joined
+           (portRef last_buf_empty_c (instanceRef fifo40_inst))
+           (portRef last_buf_empty_c)
+          ))
+          (net fifo_rden_c (joined
+           (portRef fifo_rden_c)
+           (portRef fifo_rden_c (instanceRef fifo40_inst))
+          ))
+         )
+        (property ADDRESS_WIDTH (integer 8))
+        (property DATA_WIDTH (integer 32))
+        (property CHANNELS (integer 3))
+        (property orig_inst_of (string "fifo_colector"))
+       )
+    )
+    (cell trb_adapter (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port LVL1_INVALID_TRG_IN_dl_0 (direction INPUT))
+           (port LVL1_TRG_DATA_VALID_IN_dl_0 (direction INPUT))
+           (port release_out_c (direction OUTPUT))
+           (port LVL1_TRG_DATA_VALI_IN_rising_c (direction OUTPUT))
+           (port last_buf_empty_c (direction INPUT))
+           (port burst_c (direction OUTPUT))
+           (port discard_c (direction OUTPUT))
+           (port fifo_rden_c (direction OUTPUT))
+           (port rd_clk_c (direction INPUT))
+           (port finished_c (direction OUTPUT))
+         )
+         (contents
+          (instance finished_prev (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance finished (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance buf_rden_prev (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance buf_rden (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename LVL1_TRG_DATA_VALID_IN_dl_1 "LVL1_TRG_DATA_VALID_IN_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename LVL1_TRG_DATA_VALID_IN_dl_2 "LVL1_TRG_DATA_VALID_IN_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename LVL1_INVALID_TRG_IN_dl_1 "LVL1_INVALID_TRG_IN_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance buf_rden4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C A)"))
+          )
+          (instance LVL1_TRG_DATA_VALI_IN_rising (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance release_out (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance burst (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net finished_c (joined
+           (portRef Q (instanceRef finished))
+           (portRef A (instanceRef release_out))
+           (portRef D (instanceRef finished_prev))
+           (portRef finished_c)
+          ))
+          (net rd_clk_c (joined
+           (portRef rd_clk_c)
+           (portRef CK (instanceRef LVL1_INVALID_TRG_IN_dl_1))
+           (portRef CK (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2))
+           (portRef CK (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1))
+           (portRef CK (instanceRef buf_rden))
+           (portRef CK (instanceRef buf_rden_prev))
+           (portRef CK (instanceRef finished))
+           (portRef CK (instanceRef finished_prev))
+          ))
+          (net finished_prev (joined
+           (portRef Q (instanceRef finished_prev))
+           (portRef B (instanceRef release_out))
+          ))
+          (net buf_rden_prev (joined
+           (portRef Q (instanceRef buf_rden_prev))
+           (portRef D (instanceRef finished))
+          ))
+          (net fifo_rden_c (joined
+           (portRef Q (instanceRef buf_rden))
+           (portRef B (instanceRef buf_rden4))
+           (portRef D (instanceRef buf_rden_prev))
+           (portRef CD (instanceRef finished))
+           (portRef fifo_rden_c)
+          ))
+          (net buf_rden4 (joined
+           (portRef Z (instanceRef buf_rden4))
+           (portRef D (instanceRef buf_rden))
+          ))
+          (net (rename LVL1_TRG_DATA_VALID_IN_dl_0 "LVL1_TRG_DATA_VALID_IN_dl[0]") (joined
+           (portRef LVL1_TRG_DATA_VALID_IN_dl_0)
+           (portRef D (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1))
+          ))
+          (net (rename LVL1_TRG_DATA_VALID_IN_dl_1 "LVL1_TRG_DATA_VALID_IN_dl[1]") (joined
+           (portRef Q (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1))
+           (portRef C (instanceRef burst))
+           (portRef A (instanceRef LVL1_TRG_DATA_VALI_IN_rising))
+           (portRef D (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2))
+          ))
+          (net (rename LVL1_TRG_DATA_VALID_IN_dl_2 "LVL1_TRG_DATA_VALID_IN_dl[2]") (joined
+           (portRef Q (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2))
+           (portRef B (instanceRef burst))
+           (portRef B (instanceRef LVL1_TRG_DATA_VALI_IN_rising))
+          ))
+          (net (rename LVL1_INVALID_TRG_IN_dl_0 "LVL1_INVALID_TRG_IN_dl[0]") (joined
+           (portRef LVL1_INVALID_TRG_IN_dl_0)
+           (portRef D (instanceRef LVL1_INVALID_TRG_IN_dl_1))
+          ))
+          (net discard_c (joined
+           (portRef Q (instanceRef LVL1_INVALID_TRG_IN_dl_1))
+           (portRef A (instanceRef burst))
+           (portRef discard_c)
+          ))
+          (net burst_c (joined
+           (portRef Z (instanceRef burst))
+           (portRef A (instanceRef buf_rden4))
+           (portRef burst_c)
+          ))
+          (net last_buf_empty_c (joined
+           (portRef last_buf_empty_c)
+           (portRef C (instanceRef buf_rden4))
+          ))
+          (net LVL1_TRG_DATA_VALI_IN_rising_c (joined
+           (portRef Z (instanceRef LVL1_TRG_DATA_VALI_IN_rising))
+           (portRef LVL1_TRG_DATA_VALI_IN_rising_c)
+          ))
+          (net release_out_c (joined
+           (portRef Z (instanceRef release_out))
+           (portRef release_out_c)
+          ))
+         )
+        (property orig_inst_of (string "trb_adapter"))
+       )
+    )
+    (cell hades_tdc_bundle (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port hades_raw_out_0 (direction OUTPUT))
+           (port hades_raw_out_1 (direction OUTPUT))
+           (port hades_raw_out_2 (direction OUTPUT))
+           (port hades_raw_out_12 (direction OUTPUT))
+           (port hades_raw_out_13 (direction OUTPUT))
+           (port hades_raw_out_14 (direction OUTPUT))
+           (port hades_raw_out_15 (direction OUTPUT))
+           (port hades_raw_out_16 (direction OUTPUT))
+           (port hades_raw_out_17 (direction OUTPUT))
+           (port hades_raw_out_18 (direction OUTPUT))
+           (port hades_raw_out_19 (direction OUTPUT))
+           (port hades_raw_out_20 (direction OUTPUT))
+           (port hades_raw_out_21 (direction OUTPUT))
+           (port hades_raw_out_22 (direction OUTPUT))
+           (port hades_raw_out_23 (direction OUTPUT))
+           (port trig_dl_0 (direction INPUT))
+           (port (array (rename hades_invalid_dl_c "hades_invalid_dl_c[3:0]") 4) (direction INOUT))
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT))
+           (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT))
+           (port (array (rename hades_dbg2_coarse_c "hades_dbg2_coarse_c[8:0]") 9) (direction OUTPUT))
+           (port (array (rename hades_drop_cmp_buf_c "hades_drop_cmp_buf_c[8:0]") 9) (direction OUTPUT))
+           (port (array (rename hades_drop_cmp_buf_coarse_c "hades_drop_cmp_buf_coarse_c[9:0]") 10) (direction OUTPUT))
+           (port reset_dl_0 (direction INPUT))
+           (port (array (rename hades_hit_valid_c "hades_hit_valid_c[3:0]") 4) (direction OUTPUT))
+           (port reset_dl_i_0 (direction INPUT))
+           (port (array (rename hades_dbg2_out_c "hades_dbg2_out_c[12:4]") 9) (direction OUTPUT))
+           (port hades_trig_c_i (direction INPUT))
+           (port offset_1_sqmuxa_i_0 (direction OUTPUT))
+           (port hades_offset_valid_c (direction OUTPUT))
+           (port hades_lvl1_c_i (direction INPUT))
+           (port CN_2 (direction OUTPUT))
+           (port CN_1 (direction OUTPUT))
+           (port CN_0 (direction OUTPUT))
+           (port CN (direction OUTPUT))
+           (port valid_fast_RNI999V (direction OUTPUT))
+           (port buf_out12_1z (direction OUTPUT))
+           (port hades_window_end_c (direction OUTPUT))
+           (port hades_discard_c (direction OUTPUT))
+           (port N_248_i (direction OUTPUT))
+           (port drop_cmp_buf_valid_0_sqmuxa (direction OUTPUT))
+           (port hades_buf_release_c (direction OUTPUT))
+           (port hades_buf_finished_c (direction OUTPUT))
+           (port hades_drop_cmp_buf_valid_c (direction OUTPUT))
+           (port un1_hit_i_2_0_a2_1z (direction OUTPUT))
+           (port ANB1 (direction OUTPUT))
+           (port ANB3 (direction OUTPUT))
+           (port ANB0 (direction OUTPUT))
+           (port ANB2 (direction OUTPUT))
+         )
+         (contents
+          (instance (rename coarse_RNI8DE6_0 "coarse_RNI8DE6[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance buf_finished_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename coarse_RNI6RPP_2 "coarse_RNI6RPP[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
+          )
+          (instance (rename hitbuffer_1__3 "hitbuffer_1_[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__4 "hitbuffer_1_[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__5 "hitbuffer_1_[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__6 "hitbuffer_1_[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__7 "hitbuffer_1_[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__8 "hitbuffer_1_[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__9 "hitbuffer_1_[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__10 "hitbuffer_1_[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hitbuffer_1__11 "hitbuffer_1_[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_valid_1_0 "hit_valid_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_valid_1_1 "hit_valid_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_valid_1_2 "hit_valid_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_valid_1_3 "hit_valid_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_out_i_0 "hit_out_i[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_out_i_1 "hit_out_i[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_out_i_2 "hit_out_i[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_out_i_3 "hit_out_i[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_i_0 "hit_i[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_i_1 "hit_i[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance drop_cmp_buf_valid (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_0 "drop_cmp_buf_coarse_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_1 "drop_cmp_buf_coarse_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_2 "drop_cmp_buf_coarse_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_3 "drop_cmp_buf_coarse_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_4 "drop_cmp_buf_coarse_1[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_5 "drop_cmp_buf_coarse_1[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_6 "drop_cmp_buf_coarse_1[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_7 "drop_cmp_buf_coarse_1[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_8 "drop_cmp_buf_coarse_1[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_coarse_1_9 "drop_cmp_buf_coarse_1[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_0 "drop_cmp_buf_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_1 "drop_cmp_buf_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_2 "drop_cmp_buf_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_3 "drop_cmp_buf_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_4 "drop_cmp_buf_1[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_5 "drop_cmp_buf_1[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_6 "drop_cmp_buf_1[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_7 "drop_cmp_buf_1[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename drop_cmp_buf_1_8 "drop_cmp_buf_1[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_0 "coarse[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_1 "coarse[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_2 "coarse[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_3 "coarse[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_4 "coarse[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_5 "coarse[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_6 "coarse[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_7 "coarse[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename coarse_8 "coarse[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance buf_release (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance buf_finished (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename hit_valid_1_RNO_1 "hit_valid_1_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C !B))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (!B A+B !A)))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance hit_valid_pmux_iv_0_a2_2_RNITDG11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A))"))
+          )
+          (instance (rename hit_out_i_RNO_0 "hit_out_i_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !A+D (!C !A+C (B !A)))"))
+          )
+          (instance (rename hit_valid_1_RNO_2 "hit_valid_1_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))"))
+          )
+          (instance (rename hit_valid_1_RNO_3 "hit_valid_1_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))"))
+          )
+          (instance (rename hit_valid_1_RNO_0 "hit_valid_1_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C !B)+D (C !B))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (!C (B A)+C (!B+!A)))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (!B A+B !A)))"))
+          )
+          (instance (rename hit_out_i_6_f1_0_2 "hit_out_i_6_f1_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B !A+B A)+D (C+(!B !A+B A)))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (!B A+B !A))"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance hit_valid_pmux_iv_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance hit_valid_pmux_iv_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance drop_cmp_buf_valid_4_iv_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C (B !A))"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+!A))"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance hit_valid_pmux_iv_0_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (B+A))"))
+          )
+          (instance drop_cmp_buf_valid_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance drop_cmp_buf_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance (rename hit_valid_4_i_o2_0_2 "hit_valid_4_i_o2_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance (rename hit_out_i_6_f1_0_o2_2 "hit_out_i_6_f1_0_o2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance buf_finished5_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance drop_cmp_buf_coarse_2_axbxc1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A+B !A)"))
+          )
+          (instance (rename hit_out_i_6_i_a2_0_0 "hit_out_i_6_i_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_9_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance drop_cmp_buf_coarse_2_ac0_13_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance buf_out12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance hit_valid_pmux_iv_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance un1_hit_i_2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A)))"))
+          )
+          (instance hit_valid25_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x500c"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x9009"))
+          )
+          (instance hit_valid25_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x9009"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x9009"))
+          )
+          (instance hit_valid25_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x9009"))
+           (property INJECT1_1 (string "YES"))
+           (property INJECT1_0 (string "YES"))
+           (property INIT1 (string "0x410a"))
+          )
+          (instance hit_valid25_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT)))
+           (property INIT0 (string "0x5003"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x0000"))
+          )
+          (instance hades_LVL1_raw_out_inst (viewRef netlist (cellRef hades_LVL1_raw_out))
+          )
+          (instance hades_tdc_channel_raw_out_inst (viewRef netlist (cellRef hades_tdc_channel_raw_out))
+          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined
+           (portRef Q (instanceRef coarse_0))
+           (portRef (member hades_dbg2_coarse_c 8) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc1))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_3))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc2))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_5))
+           (portRef D (instanceRef coarse_RNI6RPP_2))
+           (portRef A (instanceRef coarse_RNI8DE6_0))
+           (portRef (member hades_dbg2_coarse_c 8))
+          ))
+          (net (rename hades_dbg2_coarse_c_i_0 "hades_dbg2_coarse_c_i[0]") (joined
+           (portRef Z (instanceRef coarse_RNI8DE6_0))
+           (portRef D (instanceRef coarse_0))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_0))
+          ))
+          (net ANB2 (joined
+           (portRef Q (instanceRef hit_out_i_2))
+           (portRef ANB2 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef B (instanceRef hit_valid_pmux_iv_0_a2))
+           (portRef A (instanceRef hit_valid_pmux_iv_0_0))
+           (portRef A (instanceRef hit_out_i_6_f1_0_2))
+           (portRef B (instanceRef hit_out_i_RNO_0))
+           (portRef A (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11))
+           (portRef A (instanceRef buf_finished_RNO))
+           (portRef ANB2)
+          ))
+          (net ANB0 (joined
+           (portRef Q (instanceRef hit_out_i_0))
+           (portRef ANB0 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef A (instanceRef hit_valid_pmux_iv_0_a2_2))
+           (portRef A (instanceRef hit_out_i_6_f1_0_o2_2))
+           (portRef A (instanceRef hit_valid_pmux_iv_0_m2))
+           (portRef A (instanceRef hit_out_i_RNO_0))
+           (portRef B (instanceRef buf_finished_RNO))
+           (portRef ANB0)
+          ))
+          (net ANB3 (joined
+           (portRef Q (instanceRef hit_out_i_3))
+           (portRef ANB3 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef B (instanceRef hit_valid_pmux_iv_0_a2_2))
+           (portRef B (instanceRef buf_finished5_0_a2_0))
+           (portRef C (instanceRef hit_valid_pmux_iv_0_a2))
+           (portRef C (instanceRef buf_finished_RNO))
+           (portRef ANB3)
+          ))
+          (net ANB1 (joined
+           (portRef Q (instanceRef hit_out_i_1))
+           (portRef ANB1 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef C (instanceRef hit_valid_pmux_iv_0_a2_2))
+           (portRef A (instanceRef buf_finished5_0_a2_0))
+           (portRef B (instanceRef hit_out_i_6_f1_0_o2_2))
+           (portRef A (instanceRef hit_valid_pmux_iv_0_a2))
+           (portRef D (instanceRef buf_finished_RNO))
+           (portRef ANB1)
+          ))
+          (net buf_finished5 (joined
+           (portRef Z (instanceRef buf_finished_RNO))
+           (portRef D (instanceRef buf_finished))
+          ))
+          (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined
+           (portRef Q (instanceRef coarse_3))
+           (portRef (member hades_dbg2_coarse_c 5) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_ac0_5))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_7))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc4))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc6))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc5))
+           (portRef A (instanceRef coarse_RNI6RPP_2))
+           (portRef (member hades_dbg2_coarse_c 5))
+          ))
+          (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined
+           (portRef Q (instanceRef coarse_2))
+           (portRef (member hades_dbg2_coarse_c 6) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_3))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc2))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_5))
+           (portRef B (instanceRef coarse_RNI6RPP_2))
+           (portRef (member hades_dbg2_coarse_c 6))
+          ))
+          (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined
+           (portRef Q (instanceRef coarse_1))
+           (portRef (member hades_dbg2_coarse_c 7) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc1))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_3))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc2))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_5))
+           (portRef C (instanceRef coarse_RNI6RPP_2))
+           (portRef (member hades_dbg2_coarse_c 7))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_3 "drop_cmp_buf_coarse_2[3]") (joined
+           (portRef Z (instanceRef coarse_RNI6RPP_2))
+           (portRef D (instanceRef coarse_3))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_3))
+          ))
+          (net (rename hades_raw_out_3 "hades_raw_out[3]") (joined
+           (portRef (member hades_raw_out 20) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__3))
+          ))
+          (net (rename un1_hit_i_2_0_a2_1z "un1_hit_i_2_0_a2") (joined
+           (portRef Z (instanceRef un1_hit_i_2_0_a2))
+           (portRef SP (instanceRef hitbuffer_1__11))
+           (portRef SP (instanceRef hitbuffer_1__10))
+           (portRef SP (instanceRef hitbuffer_1__9))
+           (portRef SP (instanceRef hitbuffer_1__8))
+           (portRef SP (instanceRef hitbuffer_1__7))
+           (portRef SP (instanceRef hitbuffer_1__6))
+           (portRef SP (instanceRef hitbuffer_1__5))
+           (portRef SP (instanceRef hitbuffer_1__4))
+           (portRef SP (instanceRef hitbuffer_1__3))
+           (portRef un1_hit_i_2_0_a2_1z)
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef (member pll_clks 0) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef (member pll_clks 0) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef CK (instanceRef buf_finished))
+           (portRef CK (instanceRef buf_release))
+           (portRef CK (instanceRef coarse_8))
+           (portRef CK (instanceRef coarse_7))
+           (portRef CK (instanceRef coarse_6))
+           (portRef CK (instanceRef coarse_5))
+           (portRef CK (instanceRef coarse_4))
+           (portRef CK (instanceRef coarse_3))
+           (portRef CK (instanceRef coarse_2))
+           (portRef CK (instanceRef coarse_1))
+           (portRef CK (instanceRef coarse_0))
+           (portRef CK (instanceRef drop_cmp_buf_1_8))
+           (portRef CK (instanceRef drop_cmp_buf_1_7))
+           (portRef CK (instanceRef drop_cmp_buf_1_6))
+           (portRef CK (instanceRef drop_cmp_buf_1_5))
+           (portRef CK (instanceRef drop_cmp_buf_1_4))
+           (portRef CK (instanceRef drop_cmp_buf_1_3))
+           (portRef CK (instanceRef drop_cmp_buf_1_2))
+           (portRef CK (instanceRef drop_cmp_buf_1_1))
+           (portRef CK (instanceRef drop_cmp_buf_1_0))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_9))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_8))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_7))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_6))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_5))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_4))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_3))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_2))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_1))
+           (portRef CK (instanceRef drop_cmp_buf_coarse_1_0))
+           (portRef CK (instanceRef drop_cmp_buf_valid))
+           (portRef CK (instanceRef hit_i_1))
+           (portRef CK (instanceRef hit_i_0))
+           (portRef CK (instanceRef hit_out_i_3))
+           (portRef CK (instanceRef hit_out_i_2))
+           (portRef CK (instanceRef hit_out_i_1))
+           (portRef CK (instanceRef hit_out_i_0))
+           (portRef CK (instanceRef hit_valid_1_3))
+           (portRef CK (instanceRef hit_valid_1_2))
+           (portRef CK (instanceRef hit_valid_1_1))
+           (portRef CK (instanceRef hit_valid_1_0))
+           (portRef CK (instanceRef hitbuffer_1__11))
+           (portRef CK (instanceRef hitbuffer_1__10))
+           (portRef CK (instanceRef hitbuffer_1__9))
+           (portRef CK (instanceRef hitbuffer_1__8))
+           (portRef CK (instanceRef hitbuffer_1__7))
+           (portRef CK (instanceRef hitbuffer_1__6))
+           (portRef CK (instanceRef hitbuffer_1__5))
+           (portRef CK (instanceRef hitbuffer_1__4))
+           (portRef CK (instanceRef hitbuffer_1__3))
+          ))
+          (net (rename hades_dbg2_out_c_4 "hades_dbg2_out_c[4]") (joined
+           (portRef Q (instanceRef hitbuffer_1__3))
+           (portRef D (instanceRef drop_cmp_buf_1_0))
+           (portRef (member hades_dbg2_out_c 8))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef D1 (instanceRef hit_valid25_0_I_27_0))
+           (portRef C1 (instanceRef hit_valid25_0_I_27_0))
+           (portRef B1 (instanceRef hit_valid25_0_I_27_0))
+           (portRef A1 (instanceRef hit_valid25_0_I_27_0))
+           (portRef D0 (instanceRef hit_valid25_0_I_27_0))
+           (portRef C0 (instanceRef hit_valid25_0_I_27_0))
+           (portRef B0 (instanceRef hit_valid25_0_I_27_0))
+           (portRef A0 (instanceRef hit_valid25_0_I_27_0))
+           (portRef D1 (instanceRef hit_valid25_0_I_21_0))
+           (portRef D0 (instanceRef hit_valid25_0_I_1_0))
+           (portRef C0 (instanceRef hit_valid25_0_I_1_0))
+           (portRef B0 (instanceRef hit_valid25_0_I_1_0))
+           (portRef A0 (instanceRef hit_valid25_0_I_1_0))
+          ))
+          (net (rename hades_raw_out_4 "hades_raw_out[4]") (joined
+           (portRef (member hades_raw_out 19) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__4))
+          ))
+          (net (rename hades_dbg2_out_c_5 "hades_dbg2_out_c[5]") (joined
+           (portRef Q (instanceRef hitbuffer_1__4))
+           (portRef D (instanceRef drop_cmp_buf_1_1))
+           (portRef (member hades_dbg2_out_c 7))
+          ))
+          (net (rename hades_raw_out_5 "hades_raw_out[5]") (joined
+           (portRef (member hades_raw_out 18) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__5))
+          ))
+          (net (rename hades_dbg2_out_c_6 "hades_dbg2_out_c[6]") (joined
+           (portRef Q (instanceRef hitbuffer_1__5))
+           (portRef D (instanceRef drop_cmp_buf_1_2))
+           (portRef (member hades_dbg2_out_c 6))
+          ))
+          (net (rename hades_raw_out_6 "hades_raw_out[6]") (joined
+           (portRef (member hades_raw_out 17) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__6))
+          ))
+          (net (rename hades_dbg2_out_c_7 "hades_dbg2_out_c[7]") (joined
+           (portRef Q (instanceRef hitbuffer_1__6))
+           (portRef D (instanceRef drop_cmp_buf_1_3))
+           (portRef (member hades_dbg2_out_c 5))
+          ))
+          (net (rename hades_raw_out_7 "hades_raw_out[7]") (joined
+           (portRef (member hades_raw_out 16) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__7))
+          ))
+          (net (rename hades_dbg2_out_c_8 "hades_dbg2_out_c[8]") (joined
+           (portRef Q (instanceRef hitbuffer_1__7))
+           (portRef D (instanceRef drop_cmp_buf_1_4))
+           (portRef (member hades_dbg2_out_c 4))
+          ))
+          (net (rename hades_raw_out_8 "hades_raw_out[8]") (joined
+           (portRef (member hades_raw_out 15) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__8))
+          ))
+          (net (rename hades_dbg2_out_c_9 "hades_dbg2_out_c[9]") (joined
+           (portRef Q (instanceRef hitbuffer_1__8))
+           (portRef D (instanceRef drop_cmp_buf_1_5))
+           (portRef (member hades_dbg2_out_c 3))
+          ))
+          (net (rename hades_raw_out_9 "hades_raw_out[9]") (joined
+           (portRef (member hades_raw_out 14) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__9))
+          ))
+          (net (rename hades_dbg2_out_c_10 "hades_dbg2_out_c[10]") (joined
+           (portRef Q (instanceRef hitbuffer_1__9))
+           (portRef D (instanceRef drop_cmp_buf_1_6))
+           (portRef (member hades_dbg2_out_c 2))
+          ))
+          (net (rename hades_raw_out_10 "hades_raw_out[10]") (joined
+           (portRef (member hades_raw_out 13) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__10))
+          ))
+          (net (rename hades_dbg2_out_c_11 "hades_dbg2_out_c[11]") (joined
+           (portRef Q (instanceRef hitbuffer_1__10))
+           (portRef D (instanceRef drop_cmp_buf_1_7))
+           (portRef (member hades_dbg2_out_c 1))
+          ))
+          (net (rename hades_raw_out_11 "hades_raw_out[11]") (joined
+           (portRef (member hades_raw_out 12) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef hitbuffer_1__11))
+          ))
+          (net (rename hades_dbg2_out_c_12 "hades_dbg2_out_c[12]") (joined
+           (portRef Q (instanceRef hitbuffer_1__11))
+           (portRef D (instanceRef drop_cmp_buf_1_8))
+           (portRef (member hades_dbg2_out_c 0))
+          ))
+          (net N_246_i (joined
+           (portRef Z (instanceRef hit_valid_1_RNO_0))
+           (portRef D (instanceRef hit_valid_1_0))
+          ))
+          (net (rename reset_dl_i_0 "reset_dl_i[2]") (joined
+           (portRef reset_dl_i_0)
+           (portRef reset_dl_i_0 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef SP (instanceRef drop_cmp_buf_valid))
+           (portRef SP (instanceRef hit_valid_1_3))
+           (portRef SP (instanceRef hit_valid_1_2))
+           (portRef SP (instanceRef hit_valid_1_1))
+           (portRef SP (instanceRef hit_valid_1_0))
+          ))
+          (net (rename hades_hit_valid_c_0 "hades_hit_valid_c[0]") (joined
+           (portRef Q (instanceRef hit_valid_1_0))
+           (portRef D (instanceRef hit_valid_pmux_iv_0_0))
+           (portRef C (instanceRef hit_valid_1_RNO_0))
+           (portRef (member hades_hit_valid_c 3))
+          ))
+          (net N_243_i (joined
+           (portRef Z (instanceRef hit_valid_1_RNO_1))
+           (portRef D (instanceRef hit_valid_1_1))
+          ))
+          (net (rename hades_hit_valid_c_1 "hades_hit_valid_c[1]") (joined
+           (portRef Q (instanceRef hit_valid_1_1))
+           (portRef A (instanceRef drop_cmp_buf_0_sqmuxa_0_a2))
+           (portRef B (instanceRef hit_valid_pmux_iv_0_m2))
+           (portRef B (instanceRef drop_cmp_buf_valid_4_iv_i))
+           (portRef C (instanceRef hit_valid_1_RNO_1))
+           (portRef (member hades_hit_valid_c 2))
+          ))
+          (net N_245_i (joined
+           (portRef Z (instanceRef hit_valid_1_RNO_2))
+           (portRef D (instanceRef hit_valid_1_2))
+          ))
+          (net (rename hades_hit_valid_c_2 "hades_hit_valid_c[2]") (joined
+           (portRef Q (instanceRef hit_valid_1_2))
+           (portRef C (instanceRef hit_valid_pmux_iv_0_m2))
+           (portRef C (instanceRef hit_valid_1_RNO_2))
+           (portRef (member hades_hit_valid_c 1))
+          ))
+          (net N_244_i (joined
+           (portRef Z (instanceRef hit_valid_1_RNO_3))
+           (portRef D (instanceRef hit_valid_1_3))
+          ))
+          (net (rename hades_hit_valid_c_3 "hades_hit_valid_c[3]") (joined
+           (portRef Q (instanceRef hit_valid_1_3))
+           (portRef B (instanceRef buf_out12))
+           (portRef C (instanceRef hit_valid_1_RNO_3))
+           (portRef (member hades_hit_valid_c 0))
+          ))
+          (net N_247_i (joined
+           (portRef Z (instanceRef hit_out_i_RNO_0))
+           (portRef D (instanceRef hit_out_i_0))
+          ))
+          (net (rename reset_dl_0 "reset_dl[2]") (joined
+           (portRef reset_dl_0)
+           (portRef reset_dl_0 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef reset_dl_0 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef A (instanceRef un1_hit_i_2_0_a2))
+           (portRef B (instanceRef drop_cmp_buf_0_sqmuxa_0_a2))
+           (portRef C (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11))
+           (portRef CD (instanceRef buf_finished))
+           (portRef CD (instanceRef buf_release))
+           (portRef CD (instanceRef coarse_8))
+           (portRef CD (instanceRef coarse_7))
+           (portRef CD (instanceRef coarse_6))
+           (portRef CD (instanceRef coarse_5))
+           (portRef CD (instanceRef coarse_4))
+           (portRef CD (instanceRef coarse_3))
+           (portRef CD (instanceRef coarse_2))
+           (portRef CD (instanceRef coarse_1))
+           (portRef CD (instanceRef coarse_0))
+           (portRef CD (instanceRef hit_i_1))
+           (portRef CD (instanceRef hit_i_0))
+           (portRef CD (instanceRef hit_out_i_3))
+           (portRef CD (instanceRef hit_out_i_2))
+           (portRef CD (instanceRef hit_out_i_1))
+           (portRef CD (instanceRef hit_out_i_0))
+          ))
+          (net N_46_i (joined
+           (portRef N_46_i (instanceRef hades_LVL1_raw_out_inst))
+           (portRef D (instanceRef hit_out_i_1))
+          ))
+          (net (rename hit_out_i_6_2 "hit_out_i_6[2]") (joined
+           (portRef Z (instanceRef hit_out_i_6_f1_0_2))
+           (portRef D (instanceRef hit_out_i_2))
+          ))
+          (net N_50_i_i (joined
+           (portRef N_50_i_i_1z (instanceRef hades_LVL1_raw_out_inst))
+           (portRef D (instanceRef hit_out_i_3))
+          ))
+          (net N_59_i (joined
+           (portRef N_59_i (instanceRef hades_LVL1_raw_out_inst))
+           (portRef D (instanceRef hit_i_0))
+          ))
+          (net (rename hit_i_0 "hit_i[0]") (joined
+           (portRef Q (instanceRef hit_i_0))
+           (portRef (member hit_i 1) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef C (instanceRef un1_hit_i_2_0_a2))
+           (portRef B (instanceRef hit_valid_4_i_o2_0_2))
+          ))
+          (net SUM1_0_0 (joined
+           (portRef SUM1_0_0_1z (instanceRef hades_LVL1_raw_out_inst))
+           (portRef D (instanceRef hit_i_1))
+          ))
+          (net (rename hit_i_1 "hit_i[1]") (joined
+           (portRef Q (instanceRef hit_i_1))
+           (portRef (member hit_i 0) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef D (instanceRef un1_hit_i_2_0_a2))
+           (portRef D (instanceRef hit_valid_1_RNO_0))
+           (portRef D (instanceRef hit_valid_1_RNO_3))
+           (portRef D (instanceRef hit_valid_1_RNO_2))
+          ))
+          (net drop_cmp_buf_valid_4_iv_i (joined
+           (portRef Z (instanceRef drop_cmp_buf_valid_4_iv_i))
+           (portRef D (instanceRef drop_cmp_buf_valid))
+          ))
+          (net hades_drop_cmp_buf_valid_c (joined
+           (portRef Q (instanceRef drop_cmp_buf_valid))
+           (portRef A (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2))
+           (portRef A (instanceRef drop_cmp_buf_valid_4_iv_i))
+           (portRef hades_drop_cmp_buf_valid_c)
+          ))
+          (net drop_cmp_buf_0_sqmuxa (joined
+           (portRef Z (instanceRef drop_cmp_buf_0_sqmuxa_0_a2))
+           (portRef SP (instanceRef drop_cmp_buf_1_8))
+           (portRef SP (instanceRef drop_cmp_buf_1_7))
+           (portRef SP (instanceRef drop_cmp_buf_1_6))
+           (portRef SP (instanceRef drop_cmp_buf_1_5))
+           (portRef SP (instanceRef drop_cmp_buf_1_4))
+           (portRef SP (instanceRef drop_cmp_buf_1_3))
+           (portRef SP (instanceRef drop_cmp_buf_1_2))
+           (portRef SP (instanceRef drop_cmp_buf_1_1))
+           (portRef SP (instanceRef drop_cmp_buf_1_0))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_9))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_8))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_7))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_6))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_5))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_4))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_3))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_2))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_1))
+           (portRef SP (instanceRef drop_cmp_buf_coarse_1_0))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_0 "hades_drop_cmp_buf_coarse_c[0]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_0))
+           (portRef C1 (instanceRef hit_valid25_0_I_1_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 9))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_1 "drop_cmp_buf_coarse_2[1]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc1))
+           (portRef D (instanceRef coarse_1))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_1))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_1 "hades_drop_cmp_buf_coarse_c[1]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_1))
+           (portRef A1 (instanceRef hit_valid25_0_I_1_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 8))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_2 "drop_cmp_buf_coarse_2[2]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc2))
+           (portRef D (instanceRef coarse_2))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_2))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_2 "hades_drop_cmp_buf_coarse_c[2]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_2))
+           (portRef C0 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 7))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_3 "hades_drop_cmp_buf_coarse_c[3]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_3))
+           (portRef A0 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 6))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_4 "drop_cmp_buf_coarse_2[4]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc4))
+           (portRef D (instanceRef coarse_4))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_4))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_4 "hades_drop_cmp_buf_coarse_c[4]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_4))
+           (portRef C1 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 5))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_5 "drop_cmp_buf_coarse_2[5]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc5))
+           (portRef D (instanceRef coarse_5))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_5))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_5 "hades_drop_cmp_buf_coarse_c[5]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_5))
+           (portRef A1 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 4))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_6 "drop_cmp_buf_coarse_2[6]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc6))
+           (portRef D (instanceRef coarse_6))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_6))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_6 "hades_drop_cmp_buf_coarse_c[6]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_6))
+           (portRef C0 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 3))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_7 "drop_cmp_buf_coarse_2[7]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc7))
+           (portRef D (instanceRef coarse_7))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_7))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_7 "hades_drop_cmp_buf_coarse_c[7]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_7))
+           (portRef A0 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 2))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_8 "drop_cmp_buf_coarse_2[8]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc8))
+           (portRef D (instanceRef coarse_8))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_8))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_8 "hades_drop_cmp_buf_coarse_c[8]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_8))
+           (portRef B1 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 1))
+          ))
+          (net (rename drop_cmp_buf_coarse_2_9 "drop_cmp_buf_coarse_2[9]") (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_15))
+           (portRef D (instanceRef drop_cmp_buf_coarse_1_9))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_9 "hades_drop_cmp_buf_coarse_c[9]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_coarse_1_9))
+           (portRef A1 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_coarse_c 0))
+          ))
+          (net (rename hades_drop_cmp_buf_c_0 "hades_drop_cmp_buf_c[0]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_0))
+           (portRef D1 (instanceRef hit_valid25_0_I_1_0))
+           (portRef (member hades_drop_cmp_buf_c 8))
+          ))
+          (net (rename hades_drop_cmp_buf_c_1 "hades_drop_cmp_buf_c[1]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_1))
+           (portRef B1 (instanceRef hit_valid25_0_I_1_0))
+           (portRef (member hades_drop_cmp_buf_c 7))
+          ))
+          (net (rename hades_drop_cmp_buf_c_2 "hades_drop_cmp_buf_c[2]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_2))
+           (portRef D0 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_c 6))
+          ))
+          (net (rename hades_drop_cmp_buf_c_3 "hades_drop_cmp_buf_c[3]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_3))
+           (portRef B0 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_c 5))
+          ))
+          (net (rename hades_drop_cmp_buf_c_4 "hades_drop_cmp_buf_c[4]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_4))
+           (portRef D1 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_c 4))
+          ))
+          (net (rename hades_drop_cmp_buf_c_5 "hades_drop_cmp_buf_c[5]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_5))
+           (portRef B1 (instanceRef hit_valid25_0_I_9_0))
+           (portRef (member hades_drop_cmp_buf_c 3))
+          ))
+          (net (rename hades_drop_cmp_buf_c_6 "hades_drop_cmp_buf_c[6]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_6))
+           (portRef D0 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_c 2))
+          ))
+          (net (rename hades_drop_cmp_buf_c_7 "hades_drop_cmp_buf_c[7]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_7))
+           (portRef B0 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_c 1))
+          ))
+          (net (rename hades_drop_cmp_buf_c_8 "hades_drop_cmp_buf_c[8]") (joined
+           (portRef Q (instanceRef drop_cmp_buf_1_8))
+           (portRef C1 (instanceRef hit_valid25_0_I_21_0))
+           (portRef (member hades_drop_cmp_buf_c 0))
+          ))
+          (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined
+           (portRef Q (instanceRef coarse_4))
+           (portRef (member hades_dbg2_coarse_c 4) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_9_0))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_7))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc4))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc5))
+           (portRef (member hades_dbg2_coarse_c 4))
+          ))
+          (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined
+           (portRef Q (instanceRef coarse_5))
+           (portRef (member hades_dbg2_coarse_c 3) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_9_0))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc5))
+           (portRef (member hades_dbg2_coarse_c 3))
+          ))
+          (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined
+           (portRef Q (instanceRef coarse_6))
+           (portRef (member hades_dbg2_coarse_c 2) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_13_0))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc6))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc7))
+           (portRef (member hades_dbg2_coarse_c 2))
+          ))
+          (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined
+           (portRef Q (instanceRef coarse_7))
+           (portRef (member hades_dbg2_coarse_c 1) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_13_0))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc7))
+           (portRef (member hades_dbg2_coarse_c 1))
+          ))
+          (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined
+           (portRef Q (instanceRef coarse_8))
+           (portRef (member hades_dbg2_coarse_c 0) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_15))
+           (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc8))
+           (portRef (member hades_dbg2_coarse_c 0))
+          ))
+          (net hades_buf_finished_c (joined
+           (portRef Q (instanceRef buf_finished))
+           (portRef D (instanceRef buf_release))
+           (portRef hades_buf_finished_c)
+          ))
+          (net hades_buf_release_c (joined
+           (portRef Q (instanceRef buf_release))
+           (portRef B (instanceRef hit_valid_1_RNO_0))
+           (portRef B (instanceRef hit_valid_1_RNO_3))
+           (portRef B (instanceRef hit_valid_1_RNO_2))
+           (portRef B (instanceRef hit_valid_1_RNO_1))
+           (portRef hades_buf_release_c)
+          ))
+          (net N_44 (joined
+           (portRef N_44 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef A (instanceRef hit_valid_1_RNO_1))
+          ))
+          (net drop_cmp_buf_valid_0_sqmuxa (joined
+           (portRef Z (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2))
+           (portRef D (instanceRef hit_valid_1_RNO_1))
+           (portRef drop_cmp_buf_valid_0_sqmuxa)
+          ))
+          (net drop_cmp_buf_coarse_2_ac0_9_0 (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_9_0))
+           (portRef drop_cmp_buf_coarse_2_ac0_9_0 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc6))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_15))
+           (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc8))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc7))
+          ))
+          (net drop_cmp_buf_coarse_2_c4 (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_5))
+           (portRef drop_cmp_buf_coarse_2_c4 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_ac0_15))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc8))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc7))
+          ))
+          (net drop_cmp_buf_coarse_2_ac0_13_0 (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_13_0))
+           (portRef drop_cmp_buf_coarse_2_ac0_13_0 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_15))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc8))
+          ))
+          (net N_90 (joined
+           (portRef Z (instanceRef hit_valid_pmux_iv_0_a2_2))
+           (portRef A (instanceRef buf_out12))
+           (portRef C (instanceRef hit_out_i_6_f1_0_2))
+           (portRef B (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11))
+          ))
+          (net N_248_i (joined
+           (portRef Z (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11))
+           (portRef N_248_i)
+          ))
+          (net N_80 (joined
+           (portRef Z (instanceRef buf_finished5_0_a2_0))
+           (portRef C (instanceRef hit_valid_pmux_iv_0_0))
+           (portRef C (instanceRef hit_out_i_RNO_0))
+          ))
+          (net (rename hit_out_i_6_i_a2_0_0 "hit_out_i_6_i_a2_0[0]") (joined
+           (portRef Z (instanceRef hit_out_i_6_i_a2_0_0))
+           (portRef D (instanceRef hit_out_i_RNO_0))
+          ))
+          (net N_42 (joined
+           (portRef Z (instanceRef hit_valid_4_i_o2_0_2))
+           (portRef A (instanceRef hit_valid_1_RNO_0))
+           (portRef A (instanceRef hit_valid_1_RNO_2))
+          ))
+          (net N_40 (joined
+           (portRef N_40 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef A (instanceRef hit_valid_1_RNO_3))
+          ))
+          (net drop_cmp_buf_coarse_2_c3 (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_3))
+           (portRef drop_cmp_buf_coarse_2_c3 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_7))
+           (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc4))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc6))
+           (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc5))
+          ))
+          (net N_41 (joined
+           (portRef Z (instanceRef hit_out_i_6_f1_0_o2_2))
+           (portRef B (instanceRef hit_out_i_6_f1_0_2))
+          ))
+          (net hades_discard_c (joined
+           (portRef hades_discard_c (instanceRef hades_LVL1_raw_out_inst))
+           (portRef A (instanceRef hit_out_i_6_i_a2_0_0))
+           (portRef D (instanceRef hit_out_i_6_f1_0_2))
+           (portRef hades_discard_c)
+          ))
+          (net drop_cmp_buf_coarse_2_c5 (joined
+           (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_7))
+           (portRef drop_cmp_buf_coarse_2_c5 (instanceRef hades_tdc_channel_raw_out_inst))
+          ))
+          (net N_66 (joined
+           (portRef Z (instanceRef hit_valid_pmux_iv_0_a2))
+           (portRef B (instanceRef hit_valid_pmux_iv_0_0))
+          ))
+          (net hit_valid_pmux_iv_0_0 (joined
+           (portRef Z (instanceRef hit_valid_pmux_iv_0_0))
+           (portRef C (instanceRef buf_out12))
+          ))
+          (net N_45 (joined
+           (portRef Z (instanceRef hit_valid_pmux_iv_0_m2))
+           (portRef D (instanceRef hit_valid_pmux_iv_0_a2))
+          ))
+          (net hit_valid25 (joined
+           (portRef S0 (instanceRef hit_valid25_0_I_27_0))
+           (portRef B (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2))
+           (portRef C (instanceRef drop_cmp_buf_valid_4_iv_i))
+          ))
+          (net hades_raw_out_valid (joined
+           (portRef hades_raw_out_valid (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_valid (instanceRef hades_LVL1_raw_out_inst))
+           (portRef B (instanceRef un1_hit_i_2_0_a2))
+           (portRef A (instanceRef hit_valid_4_i_o2_0_2))
+          ))
+          (net hades_window_end_c (joined
+           (portRef hades_window_end_c (instanceRef hades_LVL1_raw_out_inst))
+           (portRef B (instanceRef hit_out_i_6_i_a2_0_0))
+           (portRef hades_window_end_c)
+          ))
+          (net (rename buf_out12_1z "buf_out12") (joined
+           (portRef Z (instanceRef buf_out12))
+           (portRef buf_out12_1z)
+          ))
+          (net (rename hit_valid25_0_data_tmp_0 "hit_valid25_0_data_tmp[0]") (joined
+           (portRef COUT (instanceRef hit_valid25_0_I_1_0))
+           (portRef CIN (instanceRef hit_valid25_0_I_9_0))
+          ))
+          (net hit_valid25_0_I_1_0_S0 (joined
+           (portRef S0 (instanceRef hit_valid25_0_I_1_0))
+          ))
+          (net hit_valid25_0_I_1_0_S1 (joined
+           (portRef S1 (instanceRef hit_valid25_0_I_1_0))
+          ))
+          (net (rename hit_valid25_0_data_tmp_2 "hit_valid25_0_data_tmp[2]") (joined
+           (portRef COUT (instanceRef hit_valid25_0_I_9_0))
+           (portRef CIN (instanceRef hit_valid25_0_I_21_0))
+          ))
+          (net hit_valid25_0_I_9_0_S0 (joined
+           (portRef S0 (instanceRef hit_valid25_0_I_9_0))
+          ))
+          (net hit_valid25_0_I_9_0_S1 (joined
+           (portRef S1 (instanceRef hit_valid25_0_I_9_0))
+          ))
+          (net hit_valid25_0_I_27_cry (joined
+           (portRef COUT (instanceRef hit_valid25_0_I_21_0))
+           (portRef CIN (instanceRef hit_valid25_0_I_27_0))
+          ))
+          (net hit_valid25_0_I_21_0_S0 (joined
+           (portRef S0 (instanceRef hit_valid25_0_I_21_0))
+          ))
+          (net hit_valid25_0_I_21_0_S1 (joined
+           (portRef S1 (instanceRef hit_valid25_0_I_21_0))
+          ))
+          (net hit_valid25_0_I_27_0_COUT (joined
+           (portRef COUT (instanceRef hit_valid25_0_I_27_0))
+          ))
+          (net hit_valid25_0_I_27_0_S1 (joined
+           (portRef S1 (instanceRef hit_valid25_0_I_27_0))
+          ))
+          (net (rename offset_5_0 "offset_5[0]") (joined
+           (portRef (member offset_5 2) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member offset_5 2))
+          ))
+          (net (rename offset_5_1 "offset_5[1]") (joined
+           (portRef (member offset_5 1) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member offset_5 1))
+          ))
+          (net (rename offset_5_2 "offset_5[2]") (joined
+           (portRef (member offset_5 0) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member offset_5 0))
+          ))
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3))
+           (portRef (member pll_clks 3) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef (member pll_clks 3) (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef (member pll_clks 2) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef (member pll_clks 2) (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef (member pll_clks 1) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef (member pll_clks 1) (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined
+           (portRef (member hades_invalid_dl_c 3))
+           (portRef (member hades_invalid_dl_c 3) (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined
+           (portRef (member hades_invalid_dl_c 2) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member hades_invalid_dl_c 2))
+          ))
+          (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined
+           (portRef (member hades_invalid_dl_c 1) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member hades_invalid_dl_c 1))
+          ))
+          (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined
+           (portRef (member hades_invalid_dl_c 0) (instanceRef hades_LVL1_raw_out_inst))
+           (portRef (member hades_invalid_dl_c 0))
+          ))
+          (net (rename trig_dl_0 "trig_dl[0]") (joined
+           (portRef trig_dl_0)
+           (portRef trig_dl_0 (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net valid_fast_RNI999V (joined
+           (portRef valid_fast_RNI999V (instanceRef hades_LVL1_raw_out_inst))
+           (portRef valid_fast_RNI999V)
+          ))
+          (net CN (joined
+           (portRef CN_2 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef CN_1 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef CN)
+          ))
+          (net CN_0 (joined
+           (portRef CN_1 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef CN_0 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef CN_0)
+          ))
+          (net CN_1 (joined
+           (portRef CN_0 (instanceRef hades_LVL1_raw_out_inst))
+           (portRef CN (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef CN_1)
+          ))
+          (net CN_2 (joined
+           (portRef CN (instanceRef hades_LVL1_raw_out_inst))
+           (portRef CN_2 (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef CN_2)
+          ))
+          (net hades_lvl1_c_i (joined
+           (portRef hades_lvl1_c_i)
+           (portRef hades_lvl1_c_i (instanceRef hades_LVL1_raw_out_inst))
+          ))
+          (net hades_offset_valid_c (joined
+           (portRef hades_offset_valid_c (instanceRef hades_LVL1_raw_out_inst))
+           (portRef hades_offset_valid_c)
+          ))
+          (net offset_1_sqmuxa_i_0 (joined
+           (portRef offset_1_sqmuxa_i_0_1z (instanceRef hades_LVL1_raw_out_inst))
+           (portRef offset_1_sqmuxa_i_0)
+          ))
+          (net (rename hades_raw_out_0 "hades_raw_out[0]") (joined
+           (portRef (member hades_raw_out 23) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_0)
+          ))
+          (net (rename hades_raw_out_1 "hades_raw_out[1]") (joined
+           (portRef (member hades_raw_out 22) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_1)
+          ))
+          (net (rename hades_raw_out_2 "hades_raw_out[2]") (joined
+           (portRef (member hades_raw_out 21) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_2)
+          ))
+          (net (rename hades_raw_out_12 "hades_raw_out[12]") (joined
+           (portRef (member hades_raw_out 11) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_12)
+          ))
+          (net (rename hades_raw_out_13 "hades_raw_out[13]") (joined
+           (portRef (member hades_raw_out 10) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_13)
+          ))
+          (net (rename hades_raw_out_14 "hades_raw_out[14]") (joined
+           (portRef (member hades_raw_out 9) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_14)
+          ))
+          (net (rename hades_raw_out_15 "hades_raw_out[15]") (joined
+           (portRef (member hades_raw_out 8) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_15)
+          ))
+          (net (rename hades_raw_out_16 "hades_raw_out[16]") (joined
+           (portRef (member hades_raw_out 7) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_16)
+          ))
+          (net (rename hades_raw_out_17 "hades_raw_out[17]") (joined
+           (portRef (member hades_raw_out 6) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_17)
+          ))
+          (net (rename hades_raw_out_18 "hades_raw_out[18]") (joined
+           (portRef (member hades_raw_out 5) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_18)
+          ))
+          (net (rename hades_raw_out_19 "hades_raw_out[19]") (joined
+           (portRef (member hades_raw_out 4) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_19)
+          ))
+          (net (rename hades_raw_out_20 "hades_raw_out[20]") (joined
+           (portRef (member hades_raw_out 3) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_20)
+          ))
+          (net (rename hades_raw_out_21 "hades_raw_out[21]") (joined
+           (portRef (member hades_raw_out 2) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_21)
+          ))
+          (net (rename hades_raw_out_22 "hades_raw_out[22]") (joined
+           (portRef (member hades_raw_out 1) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_22)
+          ))
+          (net (rename hades_raw_out_23 "hades_raw_out[23]") (joined
+           (portRef (member hades_raw_out 0) (instanceRef hades_tdc_channel_raw_out_inst))
+           (portRef hades_raw_out_23)
+          ))
+          (net hades_trig_c_i (joined
+           (portRef hades_trig_c_i)
+           (portRef hades_trig_c_i (instanceRef hades_tdc_channel_raw_out_inst))
+          ))
+          (net N_73 (joined
+           (portRef CIN (instanceRef hit_valid25_0_I_1_0))
+          ))
+         )
+        (property COARSE_WIDTH_INTERNAL (integer 9))
+        (property HITBUFFER_DEPTH (integer 4))
+        (property TDC_WIDTH (integer 3))
+        (property COARSE_WIDTH (integer 9))
+        (property TRIG_WIDTH (integer 1))
+        (property orig_inst_of (string "hades_tdc_bundle"))
+       )
+    )
+    (cell pll0 (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction OUTPUT))
+           (port clk_c (direction INPUT))
+         )
+         (contents
+          (instance PLLInst_0 (viewRef verilog (cellRef EHXPLLL))
+           (property FREQUENCY_PIN_CLKOS3 (string "300.000000"))
+           (property FREQUENCY_PIN_CLKOS2 (string "300.000000"))
+           (property FREQUENCY_PIN_CLKOS (string "300.000000"))
+           (property FREQUENCY_PIN_CLKOP (string "300.000000"))
+           (property FREQUENCY_PIN_CLKI (string "100.000000"))
+           (property ICP_CURRENT (string "9"))
+           (property LPF_RESISTOR (string "72"))
+           (property FEEDBK_PATH (string "CLKOP"))
+           (property CLKI_DIV (integer 1))
+           (property CLKFB_DIV (integer 3))
+           (property CLKOP_DIV (integer 2))
+           (property CLKOS_DIV (integer 2))
+           (property CLKOS2_DIV (integer 2))
+           (property CLKOS3_DIV (integer 2))
+           (property CLKOP_ENABLE (string "ENABLED"))
+           (property OUTDIVIDER_MUXA (string "DIVA"))
+           (property CLKOS_ENABLE (string "ENABLED"))
+           (property OUTDIVIDER_MUXB (string "DIVB"))
+           (property CLKOS2_ENABLE (string "ENABLED"))
+           (property OUTDIVIDER_MUXC (string "DIVC"))
+           (property CLKOS3_ENABLE (string "ENABLED"))
+           (property OUTDIVIDER_MUXD (string "DIVD"))
+           (property CLKOP_TRIM_POL (string "FALLING"))
+           (property CLKOP_TRIM_DELAY (integer 0))
+           (property CLKOS_TRIM_POL (string "FALLING"))
+           (property CLKOS_TRIM_DELAY (integer 0))
+           (property PLL_LOCK_MODE (integer 0))
+           (property CLKOP_CPHASE (integer 1))
+           (property CLKOP_FPHASE (integer 0))
+           (property CLKOS_CPHASE (integer 1))
+           (property CLKOS_FPHASE (integer 2))
+           (property CLKOS2_CPHASE (integer 1))
+           (property CLKOS2_FPHASE (integer 4))
+           (property CLKOS3_CPHASE (integer 1))
+           (property CLKOS3_FPHASE (integer 6))
+           (property DPHASE_SOURCE (string "DISABLED"))
+           (property STDBY_ENABLE (string "DISABLED"))
+           (property INTFB_WAKE (string "DISABLED"))
+           (property PLLRST_ENA (string "DISABLED"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (net (rename CLKOS2_inferred_clock "pll_clks[2]") (joined
+           (portRef (member pll_clks 1))
+           (portRef CLKOS2 (instanceRef PLLInst_0))
+          ))
+          (net (rename CLKOS_inferred_clock "pll_clks[1]") (joined
+           (portRef (member pll_clks 2))
+           (portRef CLKOS (instanceRef PLLInst_0))
+          ))
+          (net (rename CLKOP_inferred_clock "pll_clks[0]") (joined
+           (portRef CLKFB (instanceRef PLLInst_0))
+           (portRef (member pll_clks 3))
+           (portRef CLKOP (instanceRef PLLInst_0))
+          ))
+          (net (rename CLKOS3_inferred_clock "pll_clks[3]") (joined
+           (portRef (member pll_clks 0))
+           (portRef CLKOS3 (instanceRef PLLInst_0))
+          ))
+          (net clk_c (joined
+           (portRef clk_c)
+           (portRef CLKI (instanceRef PLLInst_0))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef ENCLKOS3 (instanceRef PLLInst_0))
+           (portRef ENCLKOS2 (instanceRef PLLInst_0))
+           (portRef ENCLKOS (instanceRef PLLInst_0))
+           (portRef ENCLKOP (instanceRef PLLInst_0))
+           (portRef RST (instanceRef PLLInst_0))
+           (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+           (portRef STDBY (instanceRef PLLInst_0))
+           (portRef PHASELOADREG (instanceRef PLLInst_0))
+           (portRef PHASESTEP (instanceRef PLLInst_0))
+           (portRef PHASEDIR (instanceRef PLLInst_0))
+           (portRef PHASESEL0 (instanceRef PLLInst_0))
+           (portRef PHASESEL1 (instanceRef PLLInst_0))
+          ))
+          (net LOCK (joined
+           (portRef LOCK (instanceRef PLLInst_0))
+          ))
+          (net INTLOCK (joined
+           (portRef INTLOCK (instanceRef PLLInst_0))
+          ))
+          (net REFCLK (joined
+           (portRef REFCLK (instanceRef PLLInst_0))
+          ))
+          (net CLKINTFB (joined
+           (portRef CLKINTFB (instanceRef PLLInst_0))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "pll0"))
+       )
+    )
+    (cell top_tf (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port clk (direction INPUT))
+           (port rd_clk (direction INPUT))
+           (port reset_dc (direction INPUT))
+           (port (array (rename trig "trig[2:0]") 3) (direction INPUT))
+           (port (array (rename fifo_data_out "fifo_data_out[31:0]") 32) (direction OUTPUT))
+           (port fifo_rden (direction OUTPUT))
+           (port fifo_empty1 (direction OUTPUT))
+           (port LVL1_TRG_DATA_VALID_IN (direction INPUT))
+           (port LVL1_INVALID_TRG_IN (direction INPUT))
+           (port (array (rename fee_data_out "FEE_DATA_OUT[31:0]") 32) (direction OUTPUT))
+           (port FEE_DATA_WRITE_OUT (direction OUTPUT))
+           (port FEE_DATAFINISHED_OUT (direction OUTPUT))
+           (port FEE_TRG_RELEASE_OUT (direction OUTPUT))
+           (port LVL1_TRG_DATA_VALI_IN_rising (direction OUTPUT))
+           (port burst (direction OUTPUT))
+           (port discard (direction OUTPUT))
+           (port last_buf_empty (direction OUTPUT))
+           (port finished (direction OUTPUT))
+           (port release_out (direction OUTPUT))
+           (port hades_trig (direction INPUT))
+           (port hades_raw_out_valid (direction OUTPUT))
+           (port (array (rename hades_raw_valid_vect "hades_raw_valid_vect[1:0]") 2) (direction OUTPUT))
+           (port hades_lvl1 (direction INPUT))
+           (port hades_lvl1_invalid (direction INPUT))
+           (port (array (rename hades_offset "hades_offset[8:0]") 9) (direction OUTPUT))
+           (port hades_offset_valid (direction OUTPUT))
+           (port hades_window_end (direction OUTPUT))
+           (port hades_buf_out_valid (direction OUTPUT))
+           (port hades_buf_release (direction OUTPUT))
+           (port hades_buf_finished (direction OUTPUT))
+           (port (array (rename hades_hit_out_i "hades_hit_out_i[3:0]") 4) (direction OUTPUT))
+           (port (array (rename hades_hit_valid "hades_hit_valid[3:0]") 4) (direction OUTPUT))
+           (port hades_discard (direction OUTPUT))
+           (port (array (rename hades_invalid_dl "hades_invalid_dl[3:0]") 4) (direction OUTPUT))
+           (port (array (rename hades_buf_drop "hades_buf_drop[3:0]") 4) (direction OUTPUT))
+           (port (array (rename hades_dbg2_out "hades_dbg2_out[31:0]") 32) (direction OUTPUT))
+           (port (array (rename hades_dbg2_coarse "hades_dbg2_coarse[8:0]") 9) (direction OUTPUT))
+           (port (array (rename hades_drop_cmp_buf "hades_drop_cmp_buf[11:0]") 12) (direction OUTPUT))
+           (port (array (rename hades_drop_cmp_buf_coarse "hades_drop_cmp_buf_coarse[11:0]") 12) (direction OUTPUT))
+           (port hades_drop_cmp_buf_valid (direction OUTPUT))
+         )
+         (contents
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance (rename reset_dl_RNISCAF_2 "reset_dl_RNISCAF[2]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_RNII4FF_0 "trig_pad_RNII4FF[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_RNIJ5FF_1 "trig_pad_RNIJ5FF[1]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_RNIK6FF_2 "trig_pad_RNIK6FF[2]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance hades_trig_pad_RNIE1B4 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance hades_lvl1_pad_RNINMH5 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0 "trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0 "trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename reset_dl_0io_1 "reset_dl_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance trb_adapter_inst_FEE_TRG_RELEASE_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance trb_adapter_inst_FEE_DATA_WRITE_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance trb_adapter_inst_FEE_DATAFINISHED_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance hades_tdc_bundle_inst_referenced_out_validio (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_0 "hades_tdc_bundle_inst_hitbuffer_1_io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_1 "hades_tdc_bundle_inst_hitbuffer_1_io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_2 "hades_tdc_bundle_inst_hitbuffer_1_io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_12 "hades_tdc_bundle_inst_hitbuffer_1_io[12]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_13 "hades_tdc_bundle_inst_hitbuffer_1_io[13]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_14 "hades_tdc_bundle_inst_hitbuffer_1_io[14]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_15 "hades_tdc_bundle_inst_hitbuffer_1_io[15]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_16 "hades_tdc_bundle_inst_hitbuffer_1_io[16]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_17 "hades_tdc_bundle_inst_hitbuffer_1_io[17]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_18 "hades_tdc_bundle_inst_hitbuffer_1_io[18]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_19 "hades_tdc_bundle_inst_hitbuffer_1_io[19]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_20 "hades_tdc_bundle_inst_hitbuffer_1_io[20]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_21 "hades_tdc_bundle_inst_hitbuffer_1_io[21]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_22 "hades_tdc_bundle_inst_hitbuffer_1_io[22]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_23 "hades_tdc_bundle_inst_hitbuffer_1_io[23]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance hades_tdc_bundle_inst_buf_out_validio (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename hades_tdc_bundle_inst_buf_drop_1io_1 "hades_tdc_bundle_inst_buf_drop_1io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename reset_dl_2 "reset_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance hades_drop_cmp_buf_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_11 "hades_drop_cmp_buf_coarse_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_10 "hades_drop_cmp_buf_coarse_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_9 "hades_drop_cmp_buf_coarse_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_8 "hades_drop_cmp_buf_coarse_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_7 "hades_drop_cmp_buf_coarse_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_6 "hades_drop_cmp_buf_coarse_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_5 "hades_drop_cmp_buf_coarse_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_4 "hades_drop_cmp_buf_coarse_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_3 "hades_drop_cmp_buf_coarse_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_2 "hades_drop_cmp_buf_coarse_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_1 "hades_drop_cmp_buf_coarse_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_coarse_pad_0 "hades_drop_cmp_buf_coarse_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_11 "hades_drop_cmp_buf_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_10 "hades_drop_cmp_buf_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_9 "hades_drop_cmp_buf_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_8 "hades_drop_cmp_buf_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_7 "hades_drop_cmp_buf_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_6 "hades_drop_cmp_buf_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_5 "hades_drop_cmp_buf_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_4 "hades_drop_cmp_buf_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_3 "hades_drop_cmp_buf_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_2 "hades_drop_cmp_buf_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_1 "hades_drop_cmp_buf_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_drop_cmp_buf_pad_0 "hades_drop_cmp_buf_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_8 "hades_dbg2_coarse_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_7 "hades_dbg2_coarse_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_6 "hades_dbg2_coarse_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_5 "hades_dbg2_coarse_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_4 "hades_dbg2_coarse_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_3 "hades_dbg2_coarse_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_2 "hades_dbg2_coarse_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_1 "hades_dbg2_coarse_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_coarse_pad_0 "hades_dbg2_coarse_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_31 "hades_dbg2_out_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_30 "hades_dbg2_out_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_29 "hades_dbg2_out_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_28 "hades_dbg2_out_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_27 "hades_dbg2_out_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_26 "hades_dbg2_out_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_25 "hades_dbg2_out_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_24 "hades_dbg2_out_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_23 "hades_dbg2_out_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_22 "hades_dbg2_out_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_21 "hades_dbg2_out_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_20 "hades_dbg2_out_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_19 "hades_dbg2_out_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_18 "hades_dbg2_out_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_17 "hades_dbg2_out_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_16 "hades_dbg2_out_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_15 "hades_dbg2_out_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_14 "hades_dbg2_out_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_13 "hades_dbg2_out_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_12 "hades_dbg2_out_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_11 "hades_dbg2_out_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_10 "hades_dbg2_out_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_9 "hades_dbg2_out_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_8 "hades_dbg2_out_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_7 "hades_dbg2_out_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_6 "hades_dbg2_out_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_5 "hades_dbg2_out_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_4 "hades_dbg2_out_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_3 "hades_dbg2_out_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_2 "hades_dbg2_out_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_1 "hades_dbg2_out_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_dbg2_out_pad_0 "hades_dbg2_out_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_buf_drop_pad_3 "hades_buf_drop_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_buf_drop_pad_2 "hades_buf_drop_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_buf_drop_pad_1 "hades_buf_drop_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_buf_drop_pad_0 "hades_buf_drop_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_invalid_dl_pad_3 "hades_invalid_dl_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_invalid_dl_pad_2 "hades_invalid_dl_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_invalid_dl_pad_1 "hades_invalid_dl_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_invalid_dl_pad_0 "hades_invalid_dl_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_discard_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_valid_pad_3 "hades_hit_valid_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_valid_pad_2 "hades_hit_valid_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_valid_pad_1 "hades_hit_valid_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_valid_pad_0 "hades_hit_valid_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_out_i_pad_3 "hades_hit_out_i_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_out_i_pad_2 "hades_hit_out_i_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_out_i_pad_1 "hades_hit_out_i_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_hit_out_i_pad_0 "hades_hit_out_i_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_buf_finished_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_buf_release_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_buf_out_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_window_end_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_offset_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_8 "hades_offset_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_7 "hades_offset_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_6 "hades_offset_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_5 "hades_offset_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_4 "hades_offset_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_3 "hades_offset_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_2 "hades_offset_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_1 "hades_offset_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename hades_offset_pad_0 "hades_offset_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_lvl1_invalid_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance hades_lvl1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
+          )
+          (instance (rename hades_raw_valid_vect_pad_1 "hades_raw_valid_vect_pad[1]") (viewRef PRIM (cellRef OBZ (libraryRef LUCENT)))          )
+          (instance (rename hades_raw_valid_vect_pad_0 "hades_raw_valid_vect_pad[0]") (viewRef PRIM (cellRef OBZ (libraryRef LUCENT)))          )
+          (instance hades_raw_out_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance hades_trig_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance release_out_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance finished_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance last_buf_empty_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance discard_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance burst_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance LVL1_TRG_DATA_VALI_IN_rising_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance FEE_TRG_RELEASE_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance FEE_DATAFINISHED_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance FEE_DATA_WRITE_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_31 "FEE_DATA_OUT_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_30 "FEE_DATA_OUT_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_29 "FEE_DATA_OUT_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_28 "FEE_DATA_OUT_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_27 "FEE_DATA_OUT_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_26 "FEE_DATA_OUT_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_25 "FEE_DATA_OUT_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_24 "FEE_DATA_OUT_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_23 "FEE_DATA_OUT_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_22 "FEE_DATA_OUT_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_21 "FEE_DATA_OUT_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_20 "FEE_DATA_OUT_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_19 "FEE_DATA_OUT_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_18 "FEE_DATA_OUT_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_17 "FEE_DATA_OUT_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_16 "FEE_DATA_OUT_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_15 "FEE_DATA_OUT_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_14 "FEE_DATA_OUT_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_13 "FEE_DATA_OUT_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_12 "FEE_DATA_OUT_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_11 "FEE_DATA_OUT_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_10 "FEE_DATA_OUT_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_9 "FEE_DATA_OUT_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_8 "FEE_DATA_OUT_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_7 "FEE_DATA_OUT_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_6 "FEE_DATA_OUT_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_5 "FEE_DATA_OUT_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_4 "FEE_DATA_OUT_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_3 "FEE_DATA_OUT_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_2 "FEE_DATA_OUT_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_1 "FEE_DATA_OUT_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename FEE_DATA_OUT_pad_0 "FEE_DATA_OUT_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance LVL1_INVALID_TRG_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance LVL1_TRG_DATA_VALID_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance fifo_empty1_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance fifo_rden_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_31 "fifo_data_out_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_30 "fifo_data_out_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_29 "fifo_data_out_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_28 "fifo_data_out_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_27 "fifo_data_out_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_26 "fifo_data_out_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_25 "fifo_data_out_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_24 "fifo_data_out_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_23 "fifo_data_out_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_22 "fifo_data_out_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_21 "fifo_data_out_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_20 "fifo_data_out_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_19 "fifo_data_out_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_18 "fifo_data_out_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_17 "fifo_data_out_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_16 "fifo_data_out_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_15 "fifo_data_out_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_14 "fifo_data_out_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_13 "fifo_data_out_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_12 "fifo_data_out_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_11 "fifo_data_out_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_10 "fifo_data_out_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_9 "fifo_data_out_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_8 "fifo_data_out_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_7 "fifo_data_out_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_6 "fifo_data_out_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_5 "fifo_data_out_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_4 "fifo_data_out_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_3 "fifo_data_out_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_2 "fifo_data_out_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_1 "fifo_data_out_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename fifo_data_out_pad_0 "fifo_data_out_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_2 "trig_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_1 "trig_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename trig_pad_0 "trig_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance reset_dc_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance rd_clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance pll0inst (viewRef netlist (cellRef pll0))
+          )
+          (instance hades_tdc_bundle_inst (viewRef netlist (cellRef hades_tdc_bundle))
+          )
+          (instance trb_adapter_inst (viewRef netlist (cellRef trb_adapter))
+          )
+          (instance fifo_colector_inst (viewRef netlist (cellRef fifo_colector))
+          )
+          (instance (rename genblk1_0__tdc_channel_fifo_out_inst "genblk1[0].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out))
+          )
+          (instance (rename genblk1_1__tdc_channel_fifo_out_inst "genblk1[1].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out_2))
+          )
+          (instance (rename genblk1_2__tdc_channel_fifo_out_inst "genblk1[2].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out_3))
+          )
+          (net (rename pll_clks_0 "pll_clks[0]") (joined
+           (portRef (member pll_clks 3) (instanceRef pll0inst))
+           (portRef (member pll_clks 3) (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 3) (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 3) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 3) (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net (rename pll_clks_1 "pll_clks[1]") (joined
+           (portRef (member pll_clks 2) (instanceRef pll0inst))
+           (portRef (member pll_clks 2) (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 2) (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 2) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 2) (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net (rename pll_clks_2 "pll_clks[2]") (joined
+           (portRef (member pll_clks 1) (instanceRef pll0inst))
+           (portRef (member pll_clks 1) (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 1) (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 1) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 1) (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net (rename pll_clks_3 "pll_clks[3]") (joined
+           (portRef (member pll_clks 0) (instanceRef pll0inst))
+           (portRef (member pll_clks 0) (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 0) (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef (member pll_clks 0) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef pll_clks_0 (instanceRef fifo_colector_inst))
+           (portRef (member pll_clks 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef CK (instanceRef reset_dl_2))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_buf_out_validio))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_referenced_out_validio))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0))
+           (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0))
+           (portRef SCLK (instanceRef reset_dl_0io_1))
+          ))
+          (net (rename reset_dl_2 "reset_dl[2]") (joined
+           (portRef Q (instanceRef reset_dl_2))
+           (portRef reset_dl_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef reset_dl_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef reset_dl_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef reset_dl_0 (instanceRef hades_tdc_bundle_inst))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1))
+           (portRef CD (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio))
+           (portRef CD (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio))
+           (portRef CD (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio))
+           (portRef A (instanceRef reset_dl_RNISCAF_2))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_0 "genblk1[0].un1_tdc_channel_fifo_out_inst[0]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_1 "genblk1[0].un1_tdc_channel_fifo_out_inst[1]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_2 "genblk1[0].un1_tdc_channel_fifo_out_inst[2]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_3 "genblk1[0].un1_tdc_channel_fifo_out_inst[3]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_4 "genblk1[0].un1_tdc_channel_fifo_out_inst[4]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_5 "genblk1[0].un1_tdc_channel_fifo_out_inst[5]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_6 "genblk1[0].un1_tdc_channel_fifo_out_inst[6]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_7 "genblk1[0].un1_tdc_channel_fifo_out_inst[7]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_1 16) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_8 "genblk1[0].un1_tdc_channel_fifo_out_inst[8]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 15) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_9 "genblk1[0].un1_tdc_channel_fifo_out_inst[9]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 14) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_10 "genblk1[0].un1_tdc_channel_fifo_out_inst[10]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 13) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_11 "genblk1[0].un1_tdc_channel_fifo_out_inst[11]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 12) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_12 "genblk1[0].un1_tdc_channel_fifo_out_inst[12]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 11) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_13 "genblk1[0].un1_tdc_channel_fifo_out_inst[13]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 10) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_14 "genblk1[0].un1_tdc_channel_fifo_out_inst[14]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_0 9) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_15 "genblk1[0].un1_tdc_channel_fifo_out_inst[15]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_16 "genblk1[0].un1_tdc_channel_fifo_out_inst[16]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_1 7) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_17 "genblk1[0].un1_tdc_channel_fifo_out_inst[17]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_1 6) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_18 "genblk1[0].un1_tdc_channel_fifo_out_inst[18]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_1 5) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_19 "genblk1[0].un1_tdc_channel_fifo_out_inst[19]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef (member un1_tdc_channel_fifo_out_inst_1 4) (instanceRef fifo_colector_inst))
+          ))
+          (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_20 "genblk1[0].un1_tdc_channel_fifo_out_inst[20]") (joined
+           (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
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+           (portRef fifo_read_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename reset_dl_1 "reset_dl[1]") (joined
+           (portRef Q (instanceRef reset_dl_0io_1))
+           (portRef D (instanceRef reset_dl_2))
+          ))
+          (net (rename trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0 "trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]") (joined
+           (portRef Q (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0))
+           (portRef LVL1_TRG_DATA_VALID_IN_dl_0 (instanceRef trb_adapter_inst))
+          ))
+          (net (rename trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0 "trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0]") (joined
+           (portRef Q (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0))
+           (portRef LVL1_INVALID_TRG_IN_dl_0 (instanceRef trb_adapter_inst))
+          ))
+          (net un1_hit_i_2_0_a2 (joined
+           (portRef un1_hit_i_2_0_a2_1z (instanceRef hades_tdc_bundle_inst))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_0 "hades_tdc_bundle_inst.hades_raw_out[0]") (joined
+           (portRef hades_raw_out_0 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_1 "hades_tdc_bundle_inst.hades_raw_out[1]") (joined
+           (portRef hades_raw_out_1 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_2 "hades_tdc_bundle_inst.hades_raw_out[2]") (joined
+           (portRef hades_raw_out_2 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_12 "hades_tdc_bundle_inst.hades_raw_out[12]") (joined
+           (portRef hades_raw_out_12 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_13 "hades_tdc_bundle_inst.hades_raw_out[13]") (joined
+           (portRef hades_raw_out_13 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_14 "hades_tdc_bundle_inst.hades_raw_out[14]") (joined
+           (portRef hades_raw_out_14 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_15 "hades_tdc_bundle_inst.hades_raw_out[15]") (joined
+           (portRef hades_raw_out_15 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_16 "hades_tdc_bundle_inst.hades_raw_out[16]") (joined
+           (portRef hades_raw_out_16 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_17 "hades_tdc_bundle_inst.hades_raw_out[17]") (joined
+           (portRef hades_raw_out_17 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_18 "hades_tdc_bundle_inst.hades_raw_out[18]") (joined
+           (portRef hades_raw_out_18 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_19 "hades_tdc_bundle_inst.hades_raw_out[19]") (joined
+           (portRef hades_raw_out_19 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_20 "hades_tdc_bundle_inst.hades_raw_out[20]") (joined
+           (portRef hades_raw_out_20 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_21 "hades_tdc_bundle_inst.hades_raw_out[21]") (joined
+           (portRef hades_raw_out_21 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_22 "hades_tdc_bundle_inst.hades_raw_out[22]") (joined
+           (portRef hades_raw_out_22 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_raw_out_23 "hades_tdc_bundle_inst.hades_raw_out[23]") (joined
+           (portRef hades_raw_out_23 (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23))
+          ))
+          (net (rename hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa "hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa") (joined
+           (portRef drop_cmp_buf_valid_0_sqmuxa (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0]") (joined
+           (portRef (member offset_5 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1]") (joined
+           (portRef (member offset_5 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2]") (joined
+           (portRef (member offset_5 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0))
+           (portRef trig_dl_0 (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0") (joined
+           (portRef offset_1_sqmuxa_i_0 (instanceRef hades_tdc_bundle_inst))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0))
+          ))
+          (net ANB0 (joined
+           (portRef ANB0 (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_out_i_pad_0))
+          ))
+          (net ANB1 (joined
+           (portRef ANB1 (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_out_i_pad_1))
+          ))
+          (net ANB2 (joined
+           (portRef ANB2 (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_out_i_pad_2))
+          ))
+          (net ANB3 (joined
+           (portRef ANB3 (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_out_i_pad_3))
+          ))
+          (net (rename hades_tdc_bundle_inst_buf_out12 "hades_tdc_bundle_inst.buf_out12") (joined
+           (portRef buf_out12_1z (instanceRef hades_tdc_bundle_inst))
+           (portRef D (instanceRef hades_tdc_bundle_inst_buf_out_validio))
+          ))
+          (net valid_fast_RNI999V (joined
+           (portRef valid_fast_RNI999V (instanceRef hades_tdc_bundle_inst))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0))
+          ))
+          (net N_248_i (joined
+           (portRef N_248_i (instanceRef hades_tdc_bundle_inst))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_buf_out_validio))
+          ))
+          (net (rename genblk1_0__tdc_channel_fifo_out_inst_fifo_wren_CN "genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN") (joined
+           (portRef CN_2 (instanceRef hades_tdc_bundle_inst))
+           (portRef CN (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef CN (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef CN (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_0__out_buffered_4__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.CN") (joined
+           (portRef CN_1 (instanceRef hades_tdc_bundle_inst))
+           (portRef CN_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef CN_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef CN_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_1__out_buffered_5__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.CN") (joined
+           (portRef CN_0 (instanceRef hades_tdc_bundle_inst))
+           (portRef CN_1 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef CN_1 (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef CN_1 (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_2__out_buffered_6__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.CN") (joined
+           (portRef CN (instanceRef hades_tdc_bundle_inst))
+           (portRef CN_2 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+           (portRef CN_2 (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+           (portRef CN_2 (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef T (instanceRef hades_raw_valid_vect_pad_0))
+           (portRef T (instanceRef hades_raw_valid_vect_pad_1))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_referenced_out_validio))
+           (portRef SP (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio))
+           (portRef SP (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio))
+           (portRef SP (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0))
+           (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0))
+           (portRef SP (instanceRef reset_dl_0io_1))
+           (portRef SP (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0))
+           (portRef SP (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0))
+           (portRef GSR (instanceRef GSR_INST))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef I (instanceRef hades_raw_valid_vect_pad_0))
+           (portRef I (instanceRef hades_raw_valid_vect_pad_1))
+           (portRef I (instanceRef hades_buf_drop_pad_0))
+           (portRef I (instanceRef hades_buf_drop_pad_2))
+           (portRef I (instanceRef hades_buf_drop_pad_3))
+           (portRef I (instanceRef hades_dbg2_out_pad_3))
+           (portRef I (instanceRef hades_dbg2_out_pad_13))
+           (portRef I (instanceRef hades_dbg2_out_pad_14))
+           (portRef I (instanceRef hades_dbg2_out_pad_15))
+           (portRef I (instanceRef hades_dbg2_out_pad_19))
+           (portRef I (instanceRef hades_dbg2_out_pad_29))
+           (portRef I (instanceRef hades_dbg2_out_pad_30))
+           (portRef I (instanceRef hades_dbg2_out_pad_31))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_9))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_10))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_11))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_10))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_11))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_buf_out_validio))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_referenced_out_validio))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0))
+           (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0))
+           (portRef CD (instanceRef reset_dl_0io_1))
+           (portRef CD (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0))
+           (portRef CD (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0))
+          ))
+          (net clk_c (joined
+           (portRef O (instanceRef clk_pad))
+           (portRef clk_c (instanceRef pll0inst))
+          ))
+          (net clk (joined
+           (portRef clk)
+           (portRef I (instanceRef clk_pad))
+          ))
+          (net rd_clk_c (joined
+           (portRef O (instanceRef rd_clk_pad))
+           (portRef rd_clk_c (instanceRef fifo_colector_inst))
+           (portRef rd_clk_c (instanceRef trb_adapter_inst))
+           (portRef SCLK (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio))
+           (portRef SCLK (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio))
+           (portRef SCLK (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio))
+           (portRef SCLK (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0))
+           (portRef SCLK (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0))
+          ))
+          (net rd_clk (joined
+           (portRef rd_clk)
+           (portRef I (instanceRef rd_clk_pad))
+          ))
+          (net reset_dc_c (joined
+           (portRef O (instanceRef reset_dc_pad))
+           (portRef D (instanceRef reset_dl_0io_1))
+          ))
+          (net reset_dc (joined
+           (portRef reset_dc)
+           (portRef I (instanceRef reset_dc_pad))
+          ))
+          (net (rename trig_c_0 "trig_c[0]") (joined
+           (portRef O (instanceRef trig_pad_0))
+           (portRef A (instanceRef trig_pad_RNII4FF_0))
+          ))
+          (net (rename trig_0 "trig[0]") (joined
+           (portRef (member trig 2))
+           (portRef I (instanceRef trig_pad_0))
+          ))
+          (net (rename trig_c_1 "trig_c[1]") (joined
+           (portRef O (instanceRef trig_pad_1))
+           (portRef A (instanceRef trig_pad_RNIJ5FF_1))
+          ))
+          (net (rename trig_1 "trig[1]") (joined
+           (portRef (member trig 1))
+           (portRef I (instanceRef trig_pad_1))
+          ))
+          (net (rename trig_c_2 "trig_c[2]") (joined
+           (portRef O (instanceRef trig_pad_2))
+           (portRef A (instanceRef trig_pad_RNIK6FF_2))
+          ))
+          (net (rename trig_2 "trig[2]") (joined
+           (portRef (member trig 0))
+           (portRef I (instanceRef trig_pad_2))
+          ))
+          (net (rename fifo_data_out_0 "fifo_data_out[0]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_0))
+           (portRef (member fifo_data_out 31))
+          ))
+          (net (rename fifo_data_out_1 "fifo_data_out[1]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_1))
+           (portRef (member fifo_data_out 30))
+          ))
+          (net (rename fifo_data_out_2 "fifo_data_out[2]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_2))
+           (portRef (member fifo_data_out 29))
+          ))
+          (net (rename fifo_data_out_3 "fifo_data_out[3]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_3))
+           (portRef (member fifo_data_out 28))
+          ))
+          (net (rename fifo_data_out_4 "fifo_data_out[4]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_4))
+           (portRef (member fifo_data_out 27))
+          ))
+          (net (rename fifo_data_out_5 "fifo_data_out[5]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_5))
+           (portRef (member fifo_data_out 26))
+          ))
+          (net (rename fifo_data_out_6 "fifo_data_out[6]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_6))
+           (portRef (member fifo_data_out 25))
+          ))
+          (net (rename fifo_data_out_7 "fifo_data_out[7]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_7))
+           (portRef (member fifo_data_out 24))
+          ))
+          (net (rename fifo_data_out_8 "fifo_data_out[8]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_8))
+           (portRef (member fifo_data_out 23))
+          ))
+          (net (rename fifo_data_out_9 "fifo_data_out[9]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_9))
+           (portRef (member fifo_data_out 22))
+          ))
+          (net (rename fifo_data_out_10 "fifo_data_out[10]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_10))
+           (portRef (member fifo_data_out 21))
+          ))
+          (net (rename fifo_data_out_11 "fifo_data_out[11]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_11))
+           (portRef (member fifo_data_out 20))
+          ))
+          (net (rename fifo_data_out_12 "fifo_data_out[12]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_12))
+           (portRef (member fifo_data_out 19))
+          ))
+          (net (rename fifo_data_out_13 "fifo_data_out[13]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_13))
+           (portRef (member fifo_data_out 18))
+          ))
+          (net (rename fifo_data_out_14 "fifo_data_out[14]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_14))
+           (portRef (member fifo_data_out 17))
+          ))
+          (net (rename fifo_data_out_15 "fifo_data_out[15]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_15))
+           (portRef (member fifo_data_out 16))
+          ))
+          (net (rename fifo_data_out_16 "fifo_data_out[16]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_16))
+           (portRef (member fifo_data_out 15))
+          ))
+          (net (rename fifo_data_out_17 "fifo_data_out[17]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_17))
+           (portRef (member fifo_data_out 14))
+          ))
+          (net (rename fifo_data_out_18 "fifo_data_out[18]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_18))
+           (portRef (member fifo_data_out 13))
+          ))
+          (net (rename fifo_data_out_19 "fifo_data_out[19]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_19))
+           (portRef (member fifo_data_out 12))
+          ))
+          (net (rename fifo_data_out_20 "fifo_data_out[20]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_20))
+           (portRef (member fifo_data_out 11))
+          ))
+          (net (rename fifo_data_out_21 "fifo_data_out[21]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_21))
+           (portRef (member fifo_data_out 10))
+          ))
+          (net (rename fifo_data_out_22 "fifo_data_out[22]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_22))
+           (portRef (member fifo_data_out 9))
+          ))
+          (net (rename fifo_data_out_23 "fifo_data_out[23]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_23))
+           (portRef (member fifo_data_out 8))
+          ))
+          (net (rename fifo_data_out_24 "fifo_data_out[24]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_24))
+           (portRef (member fifo_data_out 7))
+          ))
+          (net (rename fifo_data_out_25 "fifo_data_out[25]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_25))
+           (portRef (member fifo_data_out 6))
+          ))
+          (net (rename fifo_data_out_26 "fifo_data_out[26]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_26))
+           (portRef (member fifo_data_out 5))
+          ))
+          (net (rename fifo_data_out_27 "fifo_data_out[27]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_27))
+           (portRef (member fifo_data_out 4))
+          ))
+          (net (rename fifo_data_out_28 "fifo_data_out[28]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_28))
+           (portRef (member fifo_data_out 3))
+          ))
+          (net (rename fifo_data_out_29 "fifo_data_out[29]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_29))
+           (portRef (member fifo_data_out 2))
+          ))
+          (net (rename fifo_data_out_30 "fifo_data_out[30]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_30))
+           (portRef (member fifo_data_out 1))
+          ))
+          (net (rename fifo_data_out_31 "fifo_data_out[31]") (joined
+           (portRef O (instanceRef fifo_data_out_pad_31))
+           (portRef (member fifo_data_out 0))
+          ))
+          (net fifo_rden_c (joined
+           (portRef fifo_rden_c (instanceRef trb_adapter_inst))
+           (portRef fifo_rden_c (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_rden_pad))
+           (portRef D (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio))
+          ))
+          (net fifo_rden (joined
+           (portRef O (instanceRef fifo_rden_pad))
+           (portRef fifo_rden)
+          ))
+          (net fifo_empty1_c (joined
+           (portRef fifo_empty1_c (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+           (portRef fifo_empty1_c (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_empty1_pad))
+          ))
+          (net fifo_empty1 (joined
+           (portRef O (instanceRef fifo_empty1_pad))
+           (portRef fifo_empty1)
+          ))
+          (net LVL1_TRG_DATA_VALID_IN_c (joined
+           (portRef O (instanceRef LVL1_TRG_DATA_VALID_IN_pad))
+           (portRef D (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0))
+          ))
+          (net LVL1_TRG_DATA_VALID_IN (joined
+           (portRef LVL1_TRG_DATA_VALID_IN)
+           (portRef I (instanceRef LVL1_TRG_DATA_VALID_IN_pad))
+          ))
+          (net LVL1_INVALID_TRG_IN_c (joined
+           (portRef O (instanceRef LVL1_INVALID_TRG_IN_pad))
+           (portRef D (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0))
+          ))
+          (net LVL1_INVALID_TRG_IN (joined
+           (portRef LVL1_INVALID_TRG_IN)
+           (portRef I (instanceRef LVL1_INVALID_TRG_IN_pad))
+          ))
+          (net (rename FEE_DATA_OUT_c_0 "FEE_DATA_OUT_c[0]") (joined
+           (portRef (member fee_data_out_c 31) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_0))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_0))
+          ))
+          (net (rename FEE_DATA_OUT_0 "FEE_DATA_OUT[0]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_0))
+           (portRef (member fee_data_out 31))
+          ))
+          (net (rename FEE_DATA_OUT_c_1 "FEE_DATA_OUT_c[1]") (joined
+           (portRef (member fee_data_out_c 30) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_1))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_1))
+          ))
+          (net (rename FEE_DATA_OUT_1 "FEE_DATA_OUT[1]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_1))
+           (portRef (member fee_data_out 30))
+          ))
+          (net (rename FEE_DATA_OUT_c_2 "FEE_DATA_OUT_c[2]") (joined
+           (portRef (member fee_data_out_c 29) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_2))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_2))
+          ))
+          (net (rename FEE_DATA_OUT_2 "FEE_DATA_OUT[2]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_2))
+           (portRef (member fee_data_out 29))
+          ))
+          (net (rename FEE_DATA_OUT_c_3 "FEE_DATA_OUT_c[3]") (joined
+           (portRef (member fee_data_out_c 28) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_3))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_3))
+          ))
+          (net (rename FEE_DATA_OUT_3 "FEE_DATA_OUT[3]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_3))
+           (portRef (member fee_data_out 28))
+          ))
+          (net (rename FEE_DATA_OUT_c_4 "FEE_DATA_OUT_c[4]") (joined
+           (portRef (member fee_data_out_c 27) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_4))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_4))
+          ))
+          (net (rename FEE_DATA_OUT_4 "FEE_DATA_OUT[4]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_4))
+           (portRef (member fee_data_out 27))
+          ))
+          (net (rename FEE_DATA_OUT_c_5 "FEE_DATA_OUT_c[5]") (joined
+           (portRef (member fee_data_out_c 26) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_5))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_5))
+          ))
+          (net (rename FEE_DATA_OUT_5 "FEE_DATA_OUT[5]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_5))
+           (portRef (member fee_data_out 26))
+          ))
+          (net (rename FEE_DATA_OUT_c_6 "FEE_DATA_OUT_c[6]") (joined
+           (portRef (member fee_data_out_c 25) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_6))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_6))
+          ))
+          (net (rename FEE_DATA_OUT_6 "FEE_DATA_OUT[6]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_6))
+           (portRef (member fee_data_out 25))
+          ))
+          (net (rename FEE_DATA_OUT_c_7 "FEE_DATA_OUT_c[7]") (joined
+           (portRef (member fee_data_out_c 24) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_7))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_7))
+          ))
+          (net (rename FEE_DATA_OUT_7 "FEE_DATA_OUT[7]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_7))
+           (portRef (member fee_data_out 24))
+          ))
+          (net (rename FEE_DATA_OUT_c_8 "FEE_DATA_OUT_c[8]") (joined
+           (portRef (member fee_data_out_c 23) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_8))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_8))
+          ))
+          (net (rename FEE_DATA_OUT_8 "FEE_DATA_OUT[8]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_8))
+           (portRef (member fee_data_out 23))
+          ))
+          (net (rename FEE_DATA_OUT_c_9 "FEE_DATA_OUT_c[9]") (joined
+           (portRef (member fee_data_out_c 22) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_9))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_9))
+          ))
+          (net (rename FEE_DATA_OUT_9 "FEE_DATA_OUT[9]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_9))
+           (portRef (member fee_data_out 22))
+          ))
+          (net (rename FEE_DATA_OUT_c_10 "FEE_DATA_OUT_c[10]") (joined
+           (portRef (member fee_data_out_c 21) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_10))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_10))
+          ))
+          (net (rename FEE_DATA_OUT_10 "FEE_DATA_OUT[10]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_10))
+           (portRef (member fee_data_out 21))
+          ))
+          (net (rename FEE_DATA_OUT_c_11 "FEE_DATA_OUT_c[11]") (joined
+           (portRef (member fee_data_out_c 20) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_11))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_11))
+          ))
+          (net (rename FEE_DATA_OUT_11 "FEE_DATA_OUT[11]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_11))
+           (portRef (member fee_data_out 20))
+          ))
+          (net (rename FEE_DATA_OUT_c_12 "FEE_DATA_OUT_c[12]") (joined
+           (portRef (member fee_data_out_c 19) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_12))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_12))
+          ))
+          (net (rename FEE_DATA_OUT_12 "FEE_DATA_OUT[12]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_12))
+           (portRef (member fee_data_out 19))
+          ))
+          (net (rename FEE_DATA_OUT_c_13 "FEE_DATA_OUT_c[13]") (joined
+           (portRef (member fee_data_out_c 18) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_13))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_13))
+          ))
+          (net (rename FEE_DATA_OUT_13 "FEE_DATA_OUT[13]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_13))
+           (portRef (member fee_data_out 18))
+          ))
+          (net (rename FEE_DATA_OUT_c_14 "FEE_DATA_OUT_c[14]") (joined
+           (portRef (member fee_data_out_c 17) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_14))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_14))
+          ))
+          (net (rename FEE_DATA_OUT_14 "FEE_DATA_OUT[14]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_14))
+           (portRef (member fee_data_out 17))
+          ))
+          (net (rename FEE_DATA_OUT_c_15 "FEE_DATA_OUT_c[15]") (joined
+           (portRef (member fee_data_out_c 16) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_15))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_15))
+          ))
+          (net (rename FEE_DATA_OUT_15 "FEE_DATA_OUT[15]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_15))
+           (portRef (member fee_data_out 16))
+          ))
+          (net (rename FEE_DATA_OUT_c_16 "FEE_DATA_OUT_c[16]") (joined
+           (portRef (member fee_data_out_c 15) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_16))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_16))
+          ))
+          (net (rename FEE_DATA_OUT_16 "FEE_DATA_OUT[16]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_16))
+           (portRef (member fee_data_out 15))
+          ))
+          (net (rename FEE_DATA_OUT_c_17 "FEE_DATA_OUT_c[17]") (joined
+           (portRef (member fee_data_out_c 14) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_17))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_17))
+          ))
+          (net (rename FEE_DATA_OUT_17 "FEE_DATA_OUT[17]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_17))
+           (portRef (member fee_data_out 14))
+          ))
+          (net (rename FEE_DATA_OUT_c_18 "FEE_DATA_OUT_c[18]") (joined
+           (portRef (member fee_data_out_c 13) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_18))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_18))
+          ))
+          (net (rename FEE_DATA_OUT_18 "FEE_DATA_OUT[18]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_18))
+           (portRef (member fee_data_out 13))
+          ))
+          (net (rename FEE_DATA_OUT_c_19 "FEE_DATA_OUT_c[19]") (joined
+           (portRef (member fee_data_out_c 12) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_19))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_19))
+          ))
+          (net (rename FEE_DATA_OUT_19 "FEE_DATA_OUT[19]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_19))
+           (portRef (member fee_data_out 12))
+          ))
+          (net (rename FEE_DATA_OUT_c_20 "FEE_DATA_OUT_c[20]") (joined
+           (portRef (member fee_data_out_c 11) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_20))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_20))
+          ))
+          (net (rename FEE_DATA_OUT_20 "FEE_DATA_OUT[20]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_20))
+           (portRef (member fee_data_out 11))
+          ))
+          (net (rename FEE_DATA_OUT_c_21 "FEE_DATA_OUT_c[21]") (joined
+           (portRef (member fee_data_out_c 10) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_21))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_21))
+          ))
+          (net (rename FEE_DATA_OUT_21 "FEE_DATA_OUT[21]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_21))
+           (portRef (member fee_data_out 10))
+          ))
+          (net (rename FEE_DATA_OUT_c_22 "FEE_DATA_OUT_c[22]") (joined
+           (portRef (member fee_data_out_c 9) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_22))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_22))
+          ))
+          (net (rename FEE_DATA_OUT_22 "FEE_DATA_OUT[22]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_22))
+           (portRef (member fee_data_out 9))
+          ))
+          (net (rename FEE_DATA_OUT_c_23 "FEE_DATA_OUT_c[23]") (joined
+           (portRef (member fee_data_out_c 8) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_23))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_23))
+          ))
+          (net (rename FEE_DATA_OUT_23 "FEE_DATA_OUT[23]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_23))
+           (portRef (member fee_data_out 8))
+          ))
+          (net (rename FEE_DATA_OUT_c_24 "FEE_DATA_OUT_c[24]") (joined
+           (portRef (member fee_data_out_c 7) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_24))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_24))
+          ))
+          (net (rename FEE_DATA_OUT_24 "FEE_DATA_OUT[24]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_24))
+           (portRef (member fee_data_out 7))
+          ))
+          (net (rename FEE_DATA_OUT_c_25 "FEE_DATA_OUT_c[25]") (joined
+           (portRef (member fee_data_out_c 6) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_25))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_25))
+          ))
+          (net (rename FEE_DATA_OUT_25 "FEE_DATA_OUT[25]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_25))
+           (portRef (member fee_data_out 6))
+          ))
+          (net (rename FEE_DATA_OUT_c_26 "FEE_DATA_OUT_c[26]") (joined
+           (portRef (member fee_data_out_c 5) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_26))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_26))
+          ))
+          (net (rename FEE_DATA_OUT_26 "FEE_DATA_OUT[26]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_26))
+           (portRef (member fee_data_out 5))
+          ))
+          (net (rename FEE_DATA_OUT_c_27 "FEE_DATA_OUT_c[27]") (joined
+           (portRef (member fee_data_out_c 4) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_27))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_27))
+          ))
+          (net (rename FEE_DATA_OUT_27 "FEE_DATA_OUT[27]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_27))
+           (portRef (member fee_data_out 4))
+          ))
+          (net (rename FEE_DATA_OUT_c_28 "FEE_DATA_OUT_c[28]") (joined
+           (portRef (member fee_data_out_c 3) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_28))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_28))
+          ))
+          (net (rename FEE_DATA_OUT_28 "FEE_DATA_OUT[28]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_28))
+           (portRef (member fee_data_out 3))
+          ))
+          (net (rename FEE_DATA_OUT_c_29 "FEE_DATA_OUT_c[29]") (joined
+           (portRef (member fee_data_out_c 2) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_29))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_29))
+          ))
+          (net (rename FEE_DATA_OUT_29 "FEE_DATA_OUT[29]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_29))
+           (portRef (member fee_data_out 2))
+          ))
+          (net (rename FEE_DATA_OUT_c_30 "FEE_DATA_OUT_c[30]") (joined
+           (portRef (member fee_data_out_c 1) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_30))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_30))
+          ))
+          (net (rename FEE_DATA_OUT_30 "FEE_DATA_OUT[30]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_30))
+           (portRef (member fee_data_out 1))
+          ))
+          (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined
+           (portRef (member fee_data_out_c 0) (instanceRef fifo_colector_inst))
+           (portRef I (instanceRef fifo_data_out_pad_31))
+           (portRef I (instanceRef FEE_DATA_OUT_pad_31))
+          ))
+          (net (rename FEE_DATA_OUT_31 "FEE_DATA_OUT[31]") (joined
+           (portRef O (instanceRef FEE_DATA_OUT_pad_31))
+           (portRef (member fee_data_out 0))
+          ))
+          (net FEE_DATA_WRITE_OUT_c (joined
+           (portRef Q (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio))
+           (portRef I (instanceRef FEE_DATA_WRITE_OUT_pad))
+          ))
+          (net FEE_DATA_WRITE_OUT (joined
+           (portRef O (instanceRef FEE_DATA_WRITE_OUT_pad))
+           (portRef FEE_DATA_WRITE_OUT)
+          ))
+          (net FEE_DATAFINISHED_OUT_c (joined
+           (portRef Q (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio))
+           (portRef I (instanceRef FEE_DATAFINISHED_OUT_pad))
+          ))
+          (net FEE_DATAFINISHED_OUT (joined
+           (portRef O (instanceRef FEE_DATAFINISHED_OUT_pad))
+           (portRef FEE_DATAFINISHED_OUT)
+          ))
+          (net FEE_TRG_RELEASE_OUT_c (joined
+           (portRef Q (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio))
+           (portRef I (instanceRef FEE_TRG_RELEASE_OUT_pad))
+          ))
+          (net FEE_TRG_RELEASE_OUT (joined
+           (portRef O (instanceRef FEE_TRG_RELEASE_OUT_pad))
+           (portRef FEE_TRG_RELEASE_OUT)
+          ))
+          (net LVL1_TRG_DATA_VALI_IN_rising_c (joined
+           (portRef LVL1_TRG_DATA_VALI_IN_rising_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef LVL1_TRG_DATA_VALI_IN_rising_pad))
+          ))
+          (net LVL1_TRG_DATA_VALI_IN_rising (joined
+           (portRef O (instanceRef LVL1_TRG_DATA_VALI_IN_rising_pad))
+           (portRef LVL1_TRG_DATA_VALI_IN_rising)
+          ))
+          (net burst_c (joined
+           (portRef burst_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef burst_pad))
+          ))
+          (net burst (joined
+           (portRef O (instanceRef burst_pad))
+           (portRef burst)
+          ))
+          (net discard_c (joined
+           (portRef discard_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef discard_pad))
+          ))
+          (net discard (joined
+           (portRef O (instanceRef discard_pad))
+           (portRef discard)
+          ))
+          (net last_buf_empty_c (joined
+           (portRef last_buf_empty_c (instanceRef fifo_colector_inst))
+           (portRef last_buf_empty_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef last_buf_empty_pad))
+          ))
+          (net last_buf_empty (joined
+           (portRef O (instanceRef last_buf_empty_pad))
+           (portRef last_buf_empty)
+          ))
+          (net finished_c (joined
+           (portRef finished_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef finished_pad))
+           (portRef D (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio))
+          ))
+          (net finished (joined
+           (portRef O (instanceRef finished_pad))
+           (portRef finished)
+          ))
+          (net release_out_c (joined
+           (portRef release_out_c (instanceRef trb_adapter_inst))
+           (portRef I (instanceRef release_out_pad))
+           (portRef D (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio))
+          ))
+          (net release_out (joined
+           (portRef O (instanceRef release_out_pad))
+           (portRef release_out)
+          ))
+          (net hades_trig_c (joined
+           (portRef O (instanceRef hades_trig_pad))
+           (portRef A (instanceRef hades_trig_pad_RNIE1B4))
+          ))
+          (net hades_trig (joined
+           (portRef hades_trig)
+           (portRef I (instanceRef hades_trig_pad))
+          ))
+          (net hades_raw_out_valid_c (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_referenced_out_validio))
+           (portRef I (instanceRef hades_raw_out_valid_pad))
+          ))
+          (net hades_raw_out_valid (joined
+           (portRef O (instanceRef hades_raw_out_valid_pad))
+           (portRef hades_raw_out_valid)
+          ))
+          (net (rename hades_raw_valid_vect_0 "hades_raw_valid_vect[0]") (joined
+           (portRef O (instanceRef hades_raw_valid_vect_pad_0))
+           (portRef (member hades_raw_valid_vect 1))
+          ))
+          (net (rename hades_raw_valid_vect_1 "hades_raw_valid_vect[1]") (joined
+           (portRef O (instanceRef hades_raw_valid_vect_pad_1))
+           (portRef (member hades_raw_valid_vect 0))
+          ))
+          (net hades_lvl1_c (joined
+           (portRef O (instanceRef hades_lvl1_pad))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0))
+           (portRef A (instanceRef hades_lvl1_pad_RNINMH5))
+          ))
+          (net hades_lvl1 (joined
+           (portRef hades_lvl1)
+           (portRef I (instanceRef hades_lvl1_pad))
+          ))
+          (net hades_lvl1_invalid_c (joined
+           (portRef O (instanceRef hades_lvl1_invalid_pad))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0))
+          ))
+          (net hades_lvl1_invalid (joined
+           (portRef hades_lvl1_invalid)
+           (portRef I (instanceRef hades_lvl1_invalid_pad))
+          ))
+          (net (rename hades_offset_c_0 "hades_offset_c[0]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0))
+           (portRef I (instanceRef hades_offset_pad_0))
+          ))
+          (net (rename hades_offset_0 "hades_offset[0]") (joined
+           (portRef O (instanceRef hades_offset_pad_0))
+           (portRef (member hades_offset 8))
+          ))
+          (net (rename hades_offset_c_1 "hades_offset_c[1]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1))
+           (portRef I (instanceRef hades_offset_pad_1))
+          ))
+          (net (rename hades_offset_1 "hades_offset[1]") (joined
+           (portRef O (instanceRef hades_offset_pad_1))
+           (portRef (member hades_offset 7))
+          ))
+          (net (rename hades_offset_c_2 "hades_offset_c[2]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2))
+           (portRef I (instanceRef hades_offset_pad_2))
+          ))
+          (net (rename hades_offset_2 "hades_offset[2]") (joined
+           (portRef O (instanceRef hades_offset_pad_2))
+           (portRef (member hades_offset 6))
+          ))
+          (net (rename hades_offset_c_3 "hades_offset_c[3]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3))
+           (portRef I (instanceRef hades_offset_pad_3))
+          ))
+          (net (rename hades_offset_3 "hades_offset[3]") (joined
+           (portRef O (instanceRef hades_offset_pad_3))
+           (portRef (member hades_offset 5))
+          ))
+          (net (rename hades_offset_c_4 "hades_offset_c[4]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4))
+           (portRef I (instanceRef hades_offset_pad_4))
+          ))
+          (net (rename hades_offset_4 "hades_offset[4]") (joined
+           (portRef O (instanceRef hades_offset_pad_4))
+           (portRef (member hades_offset 4))
+          ))
+          (net (rename hades_offset_c_5 "hades_offset_c[5]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5))
+           (portRef I (instanceRef hades_offset_pad_5))
+          ))
+          (net (rename hades_offset_5 "hades_offset[5]") (joined
+           (portRef O (instanceRef hades_offset_pad_5))
+           (portRef (member hades_offset 3))
+          ))
+          (net (rename hades_offset_c_6 "hades_offset_c[6]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6))
+           (portRef I (instanceRef hades_offset_pad_6))
+          ))
+          (net (rename hades_offset_6 "hades_offset[6]") (joined
+           (portRef O (instanceRef hades_offset_pad_6))
+           (portRef (member hades_offset 2))
+          ))
+          (net (rename hades_offset_c_7 "hades_offset_c[7]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7))
+           (portRef I (instanceRef hades_offset_pad_7))
+          ))
+          (net (rename hades_offset_7 "hades_offset[7]") (joined
+           (portRef O (instanceRef hades_offset_pad_7))
+           (portRef (member hades_offset 1))
+          ))
+          (net (rename hades_offset_c_8 "hades_offset_c[8]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8))
+           (portRef I (instanceRef hades_offset_pad_8))
+          ))
+          (net (rename hades_offset_8 "hades_offset[8]") (joined
+           (portRef O (instanceRef hades_offset_pad_8))
+           (portRef (member hades_offset 0))
+          ))
+          (net hades_offset_valid_c (joined
+           (portRef hades_offset_valid_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_offset_valid_pad))
+           (portRef D (instanceRef hades_tdc_bundle_inst_referenced_out_validio))
+          ))
+          (net hades_offset_valid (joined
+           (portRef O (instanceRef hades_offset_valid_pad))
+           (portRef hades_offset_valid)
+          ))
+          (net hades_window_end_c (joined
+           (portRef hades_window_end_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_window_end_pad))
+          ))
+          (net hades_window_end (joined
+           (portRef O (instanceRef hades_window_end_pad))
+           (portRef hades_window_end)
+          ))
+          (net hades_buf_out_valid_c (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_buf_out_validio))
+           (portRef I (instanceRef hades_buf_out_valid_pad))
+          ))
+          (net hades_buf_out_valid (joined
+           (portRef O (instanceRef hades_buf_out_valid_pad))
+           (portRef hades_buf_out_valid)
+          ))
+          (net hades_buf_release_c (joined
+           (portRef hades_buf_release_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_buf_release_pad))
+          ))
+          (net hades_buf_release (joined
+           (portRef O (instanceRef hades_buf_release_pad))
+           (portRef hades_buf_release)
+          ))
+          (net hades_buf_finished_c (joined
+           (portRef hades_buf_finished_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_buf_finished_pad))
+          ))
+          (net hades_buf_finished (joined
+           (portRef O (instanceRef hades_buf_finished_pad))
+           (portRef hades_buf_finished)
+          ))
+          (net (rename hades_hit_out_i_0 "hades_hit_out_i[0]") (joined
+           (portRef O (instanceRef hades_hit_out_i_pad_0))
+           (portRef (member hades_hit_out_i 3))
+          ))
+          (net (rename hades_hit_out_i_1 "hades_hit_out_i[1]") (joined
+           (portRef O (instanceRef hades_hit_out_i_pad_1))
+           (portRef (member hades_hit_out_i 2))
+          ))
+          (net (rename hades_hit_out_i_2 "hades_hit_out_i[2]") (joined
+           (portRef O (instanceRef hades_hit_out_i_pad_2))
+           (portRef (member hades_hit_out_i 1))
+          ))
+          (net (rename hades_hit_out_i_3 "hades_hit_out_i[3]") (joined
+           (portRef O (instanceRef hades_hit_out_i_pad_3))
+           (portRef (member hades_hit_out_i 0))
+          ))
+          (net (rename hades_hit_valid_c_0 "hades_hit_valid_c[0]") (joined
+           (portRef (member hades_hit_valid_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_valid_pad_0))
+          ))
+          (net (rename hades_hit_valid_0 "hades_hit_valid[0]") (joined
+           (portRef O (instanceRef hades_hit_valid_pad_0))
+           (portRef (member hades_hit_valid 3))
+          ))
+          (net (rename hades_hit_valid_c_1 "hades_hit_valid_c[1]") (joined
+           (portRef (member hades_hit_valid_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_valid_pad_1))
+          ))
+          (net (rename hades_hit_valid_1 "hades_hit_valid[1]") (joined
+           (portRef O (instanceRef hades_hit_valid_pad_1))
+           (portRef (member hades_hit_valid 2))
+          ))
+          (net (rename hades_hit_valid_c_2 "hades_hit_valid_c[2]") (joined
+           (portRef (member hades_hit_valid_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_valid_pad_2))
+          ))
+          (net (rename hades_hit_valid_2 "hades_hit_valid[2]") (joined
+           (portRef O (instanceRef hades_hit_valid_pad_2))
+           (portRef (member hades_hit_valid 1))
+          ))
+          (net (rename hades_hit_valid_c_3 "hades_hit_valid_c[3]") (joined
+           (portRef (member hades_hit_valid_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_hit_valid_pad_3))
+          ))
+          (net (rename hades_hit_valid_3 "hades_hit_valid[3]") (joined
+           (portRef O (instanceRef hades_hit_valid_pad_3))
+           (portRef (member hades_hit_valid 0))
+          ))
+          (net hades_discard_c (joined
+           (portRef hades_discard_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_discard_pad))
+          ))
+          (net hades_discard (joined
+           (portRef O (instanceRef hades_discard_pad))
+           (portRef hades_discard)
+          ))
+          (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0))
+           (portRef (member hades_invalid_dl_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_invalid_dl_pad_0))
+          ))
+          (net (rename hades_invalid_dl_0 "hades_invalid_dl[0]") (joined
+           (portRef O (instanceRef hades_invalid_dl_pad_0))
+           (portRef (member hades_invalid_dl 3))
+          ))
+          (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined
+           (portRef (member hades_invalid_dl_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_invalid_dl_pad_1))
+          ))
+          (net (rename hades_invalid_dl_1 "hades_invalid_dl[1]") (joined
+           (portRef O (instanceRef hades_invalid_dl_pad_1))
+           (portRef (member hades_invalid_dl 2))
+          ))
+          (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined
+           (portRef (member hades_invalid_dl_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_invalid_dl_pad_2))
+          ))
+          (net (rename hades_invalid_dl_2 "hades_invalid_dl[2]") (joined
+           (portRef O (instanceRef hades_invalid_dl_pad_2))
+           (portRef (member hades_invalid_dl 1))
+          ))
+          (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined
+           (portRef (member hades_invalid_dl_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_invalid_dl_pad_3))
+          ))
+          (net (rename hades_invalid_dl_3 "hades_invalid_dl[3]") (joined
+           (portRef O (instanceRef hades_invalid_dl_pad_3))
+           (portRef (member hades_invalid_dl 0))
+          ))
+          (net (rename hades_buf_drop_0 "hades_buf_drop[0]") (joined
+           (portRef O (instanceRef hades_buf_drop_pad_0))
+           (portRef (member hades_buf_drop 3))
+          ))
+          (net (rename hades_buf_drop_c_1 "hades_buf_drop_c[1]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1))
+           (portRef I (instanceRef hades_buf_drop_pad_1))
+          ))
+          (net (rename hades_buf_drop_1 "hades_buf_drop[1]") (joined
+           (portRef O (instanceRef hades_buf_drop_pad_1))
+           (portRef (member hades_buf_drop 2))
+          ))
+          (net (rename hades_buf_drop_2 "hades_buf_drop[2]") (joined
+           (portRef O (instanceRef hades_buf_drop_pad_2))
+           (portRef (member hades_buf_drop 1))
+          ))
+          (net (rename hades_buf_drop_3 "hades_buf_drop[3]") (joined
+           (portRef O (instanceRef hades_buf_drop_pad_3))
+           (portRef (member hades_buf_drop 0))
+          ))
+          (net (rename hades_dbg2_out_c_0 "hades_dbg2_out_c[0]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0))
+           (portRef I (instanceRef hades_dbg2_out_pad_0))
+          ))
+          (net (rename hades_dbg2_out_0 "hades_dbg2_out[0]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_0))
+           (portRef (member hades_dbg2_out 31))
+          ))
+          (net (rename hades_dbg2_out_c_1 "hades_dbg2_out_c[1]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1))
+           (portRef I (instanceRef hades_dbg2_out_pad_1))
+          ))
+          (net (rename hades_dbg2_out_1 "hades_dbg2_out[1]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_1))
+           (portRef (member hades_dbg2_out 30))
+          ))
+          (net (rename hades_dbg2_out_c_2 "hades_dbg2_out_c[2]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2))
+           (portRef I (instanceRef hades_dbg2_out_pad_2))
+          ))
+          (net (rename hades_dbg2_out_2 "hades_dbg2_out[2]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_2))
+           (portRef (member hades_dbg2_out 29))
+          ))
+          (net (rename hades_dbg2_out_3 "hades_dbg2_out[3]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_3))
+           (portRef (member hades_dbg2_out 28))
+          ))
+          (net (rename hades_dbg2_out_c_4 "hades_dbg2_out_c[4]") (joined
+           (portRef (member hades_dbg2_out_c 8) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_4))
+          ))
+          (net (rename hades_dbg2_out_4 "hades_dbg2_out[4]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_4))
+           (portRef (member hades_dbg2_out 27))
+          ))
+          (net (rename hades_dbg2_out_c_5 "hades_dbg2_out_c[5]") (joined
+           (portRef (member hades_dbg2_out_c 7) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_5))
+          ))
+          (net (rename hades_dbg2_out_5 "hades_dbg2_out[5]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_5))
+           (portRef (member hades_dbg2_out 26))
+          ))
+          (net (rename hades_dbg2_out_c_6 "hades_dbg2_out_c[6]") (joined
+           (portRef (member hades_dbg2_out_c 6) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_6))
+          ))
+          (net (rename hades_dbg2_out_6 "hades_dbg2_out[6]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_6))
+           (portRef (member hades_dbg2_out 25))
+          ))
+          (net (rename hades_dbg2_out_c_7 "hades_dbg2_out_c[7]") (joined
+           (portRef (member hades_dbg2_out_c 5) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_7))
+          ))
+          (net (rename hades_dbg2_out_7 "hades_dbg2_out[7]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_7))
+           (portRef (member hades_dbg2_out 24))
+          ))
+          (net (rename hades_dbg2_out_c_8 "hades_dbg2_out_c[8]") (joined
+           (portRef (member hades_dbg2_out_c 4) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_8))
+          ))
+          (net (rename hades_dbg2_out_8 "hades_dbg2_out[8]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_8))
+           (portRef (member hades_dbg2_out 23))
+          ))
+          (net (rename hades_dbg2_out_c_9 "hades_dbg2_out_c[9]") (joined
+           (portRef (member hades_dbg2_out_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_9))
+          ))
+          (net (rename hades_dbg2_out_9 "hades_dbg2_out[9]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_9))
+           (portRef (member hades_dbg2_out 22))
+          ))
+          (net (rename hades_dbg2_out_c_10 "hades_dbg2_out_c[10]") (joined
+           (portRef (member hades_dbg2_out_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_10))
+          ))
+          (net (rename hades_dbg2_out_10 "hades_dbg2_out[10]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_10))
+           (portRef (member hades_dbg2_out 21))
+          ))
+          (net (rename hades_dbg2_out_c_11 "hades_dbg2_out_c[11]") (joined
+           (portRef (member hades_dbg2_out_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_11))
+          ))
+          (net (rename hades_dbg2_out_11 "hades_dbg2_out[11]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_11))
+           (portRef (member hades_dbg2_out 20))
+          ))
+          (net (rename hades_dbg2_out_c_12 "hades_dbg2_out_c[12]") (joined
+           (portRef (member hades_dbg2_out_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_out_pad_12))
+          ))
+          (net (rename hades_dbg2_out_12 "hades_dbg2_out[12]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_12))
+           (portRef (member hades_dbg2_out 19))
+          ))
+          (net (rename hades_dbg2_out_13 "hades_dbg2_out[13]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_13))
+           (portRef (member hades_dbg2_out 18))
+          ))
+          (net (rename hades_dbg2_out_14 "hades_dbg2_out[14]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_14))
+           (portRef (member hades_dbg2_out 17))
+          ))
+          (net (rename hades_dbg2_out_15 "hades_dbg2_out[15]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_15))
+           (portRef (member hades_dbg2_out 16))
+          ))
+          (net (rename hades_dbg2_out_c_16 "hades_dbg2_out_c[16]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12))
+           (portRef I (instanceRef hades_dbg2_out_pad_16))
+          ))
+          (net (rename hades_dbg2_out_16 "hades_dbg2_out[16]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_16))
+           (portRef (member hades_dbg2_out 15))
+          ))
+          (net (rename hades_dbg2_out_c_17 "hades_dbg2_out_c[17]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13))
+           (portRef I (instanceRef hades_dbg2_out_pad_17))
+          ))
+          (net (rename hades_dbg2_out_17 "hades_dbg2_out[17]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_17))
+           (portRef (member hades_dbg2_out 14))
+          ))
+          (net (rename hades_dbg2_out_c_18 "hades_dbg2_out_c[18]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14))
+           (portRef I (instanceRef hades_dbg2_out_pad_18))
+          ))
+          (net (rename hades_dbg2_out_18 "hades_dbg2_out[18]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_18))
+           (portRef (member hades_dbg2_out 13))
+          ))
+          (net (rename hades_dbg2_out_19 "hades_dbg2_out[19]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_19))
+           (portRef (member hades_dbg2_out 12))
+          ))
+          (net (rename hades_dbg2_out_c_20 "hades_dbg2_out_c[20]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15))
+           (portRef I (instanceRef hades_dbg2_out_pad_20))
+          ))
+          (net (rename hades_dbg2_out_20 "hades_dbg2_out[20]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_20))
+           (portRef (member hades_dbg2_out 11))
+          ))
+          (net (rename hades_dbg2_out_c_21 "hades_dbg2_out_c[21]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16))
+           (portRef I (instanceRef hades_dbg2_out_pad_21))
+          ))
+          (net (rename hades_dbg2_out_21 "hades_dbg2_out[21]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_21))
+           (portRef (member hades_dbg2_out 10))
+          ))
+          (net (rename hades_dbg2_out_c_22 "hades_dbg2_out_c[22]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17))
+           (portRef I (instanceRef hades_dbg2_out_pad_22))
+          ))
+          (net (rename hades_dbg2_out_22 "hades_dbg2_out[22]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_22))
+           (portRef (member hades_dbg2_out 9))
+          ))
+          (net (rename hades_dbg2_out_c_23 "hades_dbg2_out_c[23]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18))
+           (portRef I (instanceRef hades_dbg2_out_pad_23))
+          ))
+          (net (rename hades_dbg2_out_23 "hades_dbg2_out[23]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_23))
+           (portRef (member hades_dbg2_out 8))
+          ))
+          (net (rename hades_dbg2_out_c_24 "hades_dbg2_out_c[24]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19))
+           (portRef I (instanceRef hades_dbg2_out_pad_24))
+          ))
+          (net (rename hades_dbg2_out_24 "hades_dbg2_out[24]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_24))
+           (portRef (member hades_dbg2_out 7))
+          ))
+          (net (rename hades_dbg2_out_c_25 "hades_dbg2_out_c[25]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20))
+           (portRef I (instanceRef hades_dbg2_out_pad_25))
+          ))
+          (net (rename hades_dbg2_out_25 "hades_dbg2_out[25]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_25))
+           (portRef (member hades_dbg2_out 6))
+          ))
+          (net (rename hades_dbg2_out_c_26 "hades_dbg2_out_c[26]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21))
+           (portRef I (instanceRef hades_dbg2_out_pad_26))
+          ))
+          (net (rename hades_dbg2_out_26 "hades_dbg2_out[26]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_26))
+           (portRef (member hades_dbg2_out 5))
+          ))
+          (net (rename hades_dbg2_out_c_27 "hades_dbg2_out_c[27]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22))
+           (portRef I (instanceRef hades_dbg2_out_pad_27))
+          ))
+          (net (rename hades_dbg2_out_27 "hades_dbg2_out[27]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_27))
+           (portRef (member hades_dbg2_out 4))
+          ))
+          (net (rename hades_dbg2_out_c_28 "hades_dbg2_out_c[28]") (joined
+           (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23))
+           (portRef I (instanceRef hades_dbg2_out_pad_28))
+          ))
+          (net (rename hades_dbg2_out_28 "hades_dbg2_out[28]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_28))
+           (portRef (member hades_dbg2_out 3))
+          ))
+          (net (rename hades_dbg2_out_29 "hades_dbg2_out[29]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_29))
+           (portRef (member hades_dbg2_out 2))
+          ))
+          (net (rename hades_dbg2_out_30 "hades_dbg2_out[30]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_30))
+           (portRef (member hades_dbg2_out 1))
+          ))
+          (net (rename hades_dbg2_out_31 "hades_dbg2_out[31]") (joined
+           (portRef O (instanceRef hades_dbg2_out_pad_31))
+           (portRef (member hades_dbg2_out 0))
+          ))
+          (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined
+           (portRef (member hades_dbg2_coarse_c 8) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_0))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3))
+          ))
+          (net (rename hades_dbg2_coarse_0 "hades_dbg2_coarse[0]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_0))
+           (portRef (member hades_dbg2_coarse 8))
+          ))
+          (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined
+           (portRef (member hades_dbg2_coarse_c 7) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_1))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4))
+          ))
+          (net (rename hades_dbg2_coarse_1 "hades_dbg2_coarse[1]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_1))
+           (portRef (member hades_dbg2_coarse 7))
+          ))
+          (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined
+           (portRef (member hades_dbg2_coarse_c 6) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_2))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5))
+          ))
+          (net (rename hades_dbg2_coarse_2 "hades_dbg2_coarse[2]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_2))
+           (portRef (member hades_dbg2_coarse 6))
+          ))
+          (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined
+           (portRef (member hades_dbg2_coarse_c 5) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_3))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6))
+          ))
+          (net (rename hades_dbg2_coarse_3 "hades_dbg2_coarse[3]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_3))
+           (portRef (member hades_dbg2_coarse 5))
+          ))
+          (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined
+           (portRef (member hades_dbg2_coarse_c 4) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_4))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7))
+          ))
+          (net (rename hades_dbg2_coarse_4 "hades_dbg2_coarse[4]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_4))
+           (portRef (member hades_dbg2_coarse 4))
+          ))
+          (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined
+           (portRef (member hades_dbg2_coarse_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_5))
+           (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8))
+          ))
+          (net (rename hades_dbg2_coarse_5 "hades_dbg2_coarse[5]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_5))
+           (portRef (member hades_dbg2_coarse 3))
+          ))
+          (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined
+           (portRef (member hades_dbg2_coarse_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_6))
+          ))
+          (net (rename hades_dbg2_coarse_6 "hades_dbg2_coarse[6]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_6))
+           (portRef (member hades_dbg2_coarse 2))
+          ))
+          (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined
+           (portRef (member hades_dbg2_coarse_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_7))
+          ))
+          (net (rename hades_dbg2_coarse_7 "hades_dbg2_coarse[7]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_7))
+           (portRef (member hades_dbg2_coarse 1))
+          ))
+          (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined
+           (portRef (member hades_dbg2_coarse_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_dbg2_coarse_pad_8))
+          ))
+          (net (rename hades_dbg2_coarse_8 "hades_dbg2_coarse[8]") (joined
+           (portRef O (instanceRef hades_dbg2_coarse_pad_8))
+           (portRef (member hades_dbg2_coarse 0))
+          ))
+          (net (rename hades_drop_cmp_buf_c_0 "hades_drop_cmp_buf_c[0]") (joined
+           (portRef (member hades_drop_cmp_buf_c 8) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_0))
+          ))
+          (net (rename hades_drop_cmp_buf_0 "hades_drop_cmp_buf[0]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_0))
+           (portRef (member hades_drop_cmp_buf 11))
+          ))
+          (net (rename hades_drop_cmp_buf_c_1 "hades_drop_cmp_buf_c[1]") (joined
+           (portRef (member hades_drop_cmp_buf_c 7) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_1))
+          ))
+          (net (rename hades_drop_cmp_buf_1 "hades_drop_cmp_buf[1]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_1))
+           (portRef (member hades_drop_cmp_buf 10))
+          ))
+          (net (rename hades_drop_cmp_buf_c_2 "hades_drop_cmp_buf_c[2]") (joined
+           (portRef (member hades_drop_cmp_buf_c 6) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_2))
+          ))
+          (net (rename hades_drop_cmp_buf_2 "hades_drop_cmp_buf[2]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_2))
+           (portRef (member hades_drop_cmp_buf 9))
+          ))
+          (net (rename hades_drop_cmp_buf_c_3 "hades_drop_cmp_buf_c[3]") (joined
+           (portRef (member hades_drop_cmp_buf_c 5) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_3))
+          ))
+          (net (rename hades_drop_cmp_buf_3 "hades_drop_cmp_buf[3]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_3))
+           (portRef (member hades_drop_cmp_buf 8))
+          ))
+          (net (rename hades_drop_cmp_buf_c_4 "hades_drop_cmp_buf_c[4]") (joined
+           (portRef (member hades_drop_cmp_buf_c 4) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_4))
+          ))
+          (net (rename hades_drop_cmp_buf_4 "hades_drop_cmp_buf[4]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_4))
+           (portRef (member hades_drop_cmp_buf 7))
+          ))
+          (net (rename hades_drop_cmp_buf_c_5 "hades_drop_cmp_buf_c[5]") (joined
+           (portRef (member hades_drop_cmp_buf_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_5))
+          ))
+          (net (rename hades_drop_cmp_buf_5 "hades_drop_cmp_buf[5]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_5))
+           (portRef (member hades_drop_cmp_buf 6))
+          ))
+          (net (rename hades_drop_cmp_buf_c_6 "hades_drop_cmp_buf_c[6]") (joined
+           (portRef (member hades_drop_cmp_buf_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_6))
+          ))
+          (net (rename hades_drop_cmp_buf_6 "hades_drop_cmp_buf[6]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_6))
+           (portRef (member hades_drop_cmp_buf 5))
+          ))
+          (net (rename hades_drop_cmp_buf_c_7 "hades_drop_cmp_buf_c[7]") (joined
+           (portRef (member hades_drop_cmp_buf_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_7))
+          ))
+          (net (rename hades_drop_cmp_buf_7 "hades_drop_cmp_buf[7]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_7))
+           (portRef (member hades_drop_cmp_buf 4))
+          ))
+          (net (rename hades_drop_cmp_buf_c_8 "hades_drop_cmp_buf_c[8]") (joined
+           (portRef (member hades_drop_cmp_buf_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_pad_8))
+          ))
+          (net (rename hades_drop_cmp_buf_8 "hades_drop_cmp_buf[8]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_8))
+           (portRef (member hades_drop_cmp_buf 3))
+          ))
+          (net (rename hades_drop_cmp_buf_9 "hades_drop_cmp_buf[9]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_9))
+           (portRef (member hades_drop_cmp_buf 2))
+          ))
+          (net (rename hades_drop_cmp_buf_10 "hades_drop_cmp_buf[10]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_10))
+           (portRef (member hades_drop_cmp_buf 1))
+          ))
+          (net (rename hades_drop_cmp_buf_11 "hades_drop_cmp_buf[11]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_pad_11))
+           (portRef (member hades_drop_cmp_buf 0))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_0 "hades_drop_cmp_buf_coarse_c[0]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 9) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_0))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_0 "hades_drop_cmp_buf_coarse[0]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_0))
+           (portRef (member hades_drop_cmp_buf_coarse 11))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_1 "hades_drop_cmp_buf_coarse_c[1]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 8) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_1))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_1 "hades_drop_cmp_buf_coarse[1]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_1))
+           (portRef (member hades_drop_cmp_buf_coarse 10))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_2 "hades_drop_cmp_buf_coarse_c[2]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 7) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_2))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_2 "hades_drop_cmp_buf_coarse[2]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_2))
+           (portRef (member hades_drop_cmp_buf_coarse 9))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_3 "hades_drop_cmp_buf_coarse_c[3]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 6) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_3))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_3 "hades_drop_cmp_buf_coarse[3]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_3))
+           (portRef (member hades_drop_cmp_buf_coarse 8))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_4 "hades_drop_cmp_buf_coarse_c[4]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 5) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_4))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_4 "hades_drop_cmp_buf_coarse[4]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_4))
+           (portRef (member hades_drop_cmp_buf_coarse 7))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_5 "hades_drop_cmp_buf_coarse_c[5]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 4) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_5))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_5 "hades_drop_cmp_buf_coarse[5]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_5))
+           (portRef (member hades_drop_cmp_buf_coarse 6))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_6 "hades_drop_cmp_buf_coarse_c[6]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 3) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_6))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_6 "hades_drop_cmp_buf_coarse[6]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_6))
+           (portRef (member hades_drop_cmp_buf_coarse 5))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_7 "hades_drop_cmp_buf_coarse_c[7]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 2) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_7))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_7 "hades_drop_cmp_buf_coarse[7]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_7))
+           (portRef (member hades_drop_cmp_buf_coarse 4))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_8 "hades_drop_cmp_buf_coarse_c[8]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 1) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_8))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_8 "hades_drop_cmp_buf_coarse[8]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_8))
+           (portRef (member hades_drop_cmp_buf_coarse 3))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_c_9 "hades_drop_cmp_buf_coarse_c[9]") (joined
+           (portRef (member hades_drop_cmp_buf_coarse_c 0) (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_9))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_9 "hades_drop_cmp_buf_coarse[9]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_9))
+           (portRef (member hades_drop_cmp_buf_coarse 2))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_10 "hades_drop_cmp_buf_coarse[10]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_10))
+           (portRef (member hades_drop_cmp_buf_coarse 1))
+          ))
+          (net (rename hades_drop_cmp_buf_coarse_11 "hades_drop_cmp_buf_coarse[11]") (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_11))
+           (portRef (member hades_drop_cmp_buf_coarse 0))
+          ))
+          (net hades_drop_cmp_buf_valid_c (joined
+           (portRef hades_drop_cmp_buf_valid_c (instanceRef hades_tdc_bundle_inst))
+           (portRef I (instanceRef hades_drop_cmp_buf_valid_pad))
+          ))
+          (net hades_drop_cmp_buf_valid (joined
+           (portRef O (instanceRef hades_drop_cmp_buf_valid_pad))
+           (portRef hades_drop_cmp_buf_valid)
+          ))
+          (net hades_lvl1_c_i (joined
+           (portRef Z (instanceRef hades_lvl1_pad_RNINMH5))
+           (portRef hades_lvl1_c_i (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net hades_trig_c_i (joined
+           (portRef Z (instanceRef hades_trig_pad_RNIE1B4))
+           (portRef hades_trig_c_i (instanceRef hades_tdc_bundle_inst))
+          ))
+          (net (rename trig_c_i_2 "trig_c_i[2]") (joined
+           (portRef Z (instanceRef trig_pad_RNIK6FF_2))
+           (portRef trig_c_i_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename trig_c_i_1 "trig_c_i[1]") (joined
+           (portRef Z (instanceRef trig_pad_RNIJ5FF_1))
+           (portRef trig_c_i_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename trig_c_i_0 "trig_c_i[0]") (joined
+           (portRef Z (instanceRef trig_pad_RNII4FF_0))
+           (portRef trig_c_i_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst))
+          ))
+          (net (rename reset_dl_i_2 "reset_dl_i[2]") (joined
+           (portRef Z (instanceRef reset_dl_RNISCAF_2))
+           (portRef reset_dl_i_0 (instanceRef hades_tdc_bundle_inst))
+          ))
+         )
+        (property ADDRESS_WIDTH (integer 8))
+        (property DATA_WIDTH (integer 24))
+        (property CHANNELS (integer 3))
+        (property orig_inst_of (string "top_tf"))
+       )
+    )
+  )
+  (design top_tf (cellRef top_tf (libraryRef work))
+	(property PART (string "lfe5um5g_45f-8") ))
+)
diff --git a/impl1/s1_impl1.fse b/impl1/s1_impl1.fse
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/s1_impl1.htm b/impl1/s1_impl1.htm
new file mode 100644
index 0000000..7846630
--- /dev/null
+++ b/impl1/s1_impl1.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/s1_impl1_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/s1_impl1_toc.htm" name="tocFrame" />
+ 				 <frame src="syntmp/s1_impl1_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>
diff --git a/impl1/s1_impl1.ior b/impl1/s1_impl1.ior
new file mode 100644
index 0000000..a7ae11f
--- /dev/null
+++ b/impl1/s1_impl1.ior
@@ -0,0 +1,204 @@
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 9
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: M
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+// Design: top_tf
+// Package: CABGA381
+// ncd File: s1_impl1.ncd
+// Version: Diamond (64-bit) 3.11.2.446
+// Written on Wed Jun 16 09:20:37 2021
+// M: Minimum Performance Grade
+// iotiming s1_impl1.ncd s1_impl1.prf -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 9, 8):
+
+// Input Setup and Hold Times
+
+Port                   Clock  Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+LVL1_INVALID_TRG_IN    rd_clk R    -0.242      M       2.049     8
+LVL1_TRG_DATA_VALID_IN rd_clk R    -0.242      M       2.049     8
+hades_lvl1             clk    F     2.162      8       1.169     M
+hades_lvl1_invalid     clk    R    -0.529      8       1.138     M
+hades_trig             clk    F     2.282      8       0.712     M
+
+
+// Clock to Output Delay
+
+Port                         Clock  Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+FEE_DATAFINISHED_OUT         rd_clk R     5.311         8        2.067          M
+FEE_DATA_OUT[0]              rd_clk R     8.637         8        5.249          M
+FEE_DATA_OUT[10]             rd_clk R     7.965         8        4.919          M
+FEE_DATA_OUT[11]             rd_clk R     8.348         8        5.096          M
+FEE_DATA_OUT[12]             rd_clk R     8.295         8        5.082          M
+FEE_DATA_OUT[13]             rd_clk R     8.705         8        5.299          M
+FEE_DATA_OUT[14]             rd_clk R     8.495         8        5.173          M
+FEE_DATA_OUT[15]             rd_clk R     8.386         8        5.119          M
+FEE_DATA_OUT[16]             rd_clk R     9.036         8        5.453          M
+FEE_DATA_OUT[17]             rd_clk R     8.626         8        5.229          M
+FEE_DATA_OUT[18]             rd_clk R     8.622         8        5.246          M
+FEE_DATA_OUT[19]             rd_clk R     8.108         8        4.987          M
+FEE_DATA_OUT[1]              rd_clk R     8.763         8        5.277          M
+FEE_DATA_OUT[20]             rd_clk R     8.695         8        5.268          M
+FEE_DATA_OUT[21]             rd_clk R     8.276         8        5.092          M
+FEE_DATA_OUT[22]             rd_clk R     8.532         8        5.199          M
+FEE_DATA_OUT[23]             rd_clk R     8.304         8        5.100          M
+FEE_DATA_OUT[24]             rd_clk R     8.280         8        5.083          M
+FEE_DATA_OUT[25]             rd_clk R     8.697         8        5.287          M
+FEE_DATA_OUT[26]             rd_clk R     8.529         8        5.194          M
+FEE_DATA_OUT[27]             rd_clk R     8.687         8        5.296          M
+FEE_DATA_OUT[28]             rd_clk R     8.632         8        5.249          M
+FEE_DATA_OUT[29]             rd_clk R     8.555         8        5.214          M
+FEE_DATA_OUT[2]              rd_clk R     8.715         8        5.294          M
+FEE_DATA_OUT[30]             rd_clk R     8.514         8        5.199          M
+FEE_DATA_OUT[31]             rd_clk R     8.519         8        5.194          M
+FEE_DATA_OUT[3]              rd_clk R     8.357         8        5.108          M
+FEE_DATA_OUT[4]              rd_clk R     8.716         8        5.293          M
+FEE_DATA_OUT[5]              rd_clk R     8.884         8        5.392          M
+FEE_DATA_OUT[6]              rd_clk R     8.803         8        5.322          M
+FEE_DATA_OUT[7]              rd_clk R     8.785         8        5.315          M
+FEE_DATA_OUT[8]              rd_clk R     8.395         8        5.107          M
+FEE_DATA_OUT[9]              rd_clk R     8.309         8        5.083          M
+FEE_DATA_WRITE_OUT           rd_clk R     5.311         8        2.067          M
+FEE_TRG_RELEASE_OUT          rd_clk R     5.311         8        2.067          M
+LVL1_TRG_DATA_VALI_IN_rising rd_clk R     5.988         8        2.652          M
+burst                        rd_clk R     5.985         8        2.605          M
+discard                      rd_clk R     5.080         8        2.333          M
+fifo_data_out[0]             rd_clk R     8.408         8        5.132          M
+fifo_data_out[10]            rd_clk R     7.965         8        4.919          M
+fifo_data_out[11]            rd_clk R     8.348         8        5.096          M
+fifo_data_out[12]            rd_clk R     8.448         8        5.158          M
+fifo_data_out[13]            rd_clk R     8.654         8        5.273          M
+fifo_data_out[14]            rd_clk R     8.648         8        5.249          M
+fifo_data_out[15]            rd_clk R     7.943         8        4.904          M
+fifo_data_out[16]            rd_clk R     9.189         8        5.529          M
+fifo_data_out[17]            rd_clk R     8.779         8        5.305          M
+fifo_data_out[18]            rd_clk R     9.117         8        5.486          M
+fifo_data_out[19]            rd_clk R     8.108         8        4.987          M
+fifo_data_out[1]             rd_clk R     8.763         8        5.277          M
+fifo_data_out[20]            rd_clk R     8.873         8        5.361          M
+fifo_data_out[21]            rd_clk R     8.150         8        5.026          M
+fifo_data_out[22]            rd_clk R     8.710         8        5.292          M
+fifo_data_out[23]            rd_clk R     8.304         8        5.100          M
+fifo_data_out[24]            rd_clk R     8.545         8        5.205          M
+fifo_data_out[25]            rd_clk R     8.697         8        5.287          M
+fifo_data_out[26]            rd_clk R     8.682         8        5.269          M
+fifo_data_out[27]            rd_clk R     8.687         8        5.296          M
+fifo_data_out[28]            rd_clk R     8.785         8        5.324          M
+fifo_data_out[29]            rd_clk R     8.555         8        5.214          M
+fifo_data_out[2]             rd_clk R     8.715         8        5.294          M
+fifo_data_out[30]            rd_clk R     8.514         8        5.199          M
+fifo_data_out[31]            rd_clk R     8.672         8        5.269          M
+fifo_data_out[3]             rd_clk R     8.357         8        5.108          M
+fifo_data_out[4]             rd_clk R     8.716         8        5.293          M
+fifo_data_out[5]             rd_clk R     9.037         8        5.468          M
+fifo_data_out[6]             rd_clk R     8.957         8        5.398          M
+fifo_data_out[7]             rd_clk R     8.963         8        5.408          M
+fifo_data_out[8]             rd_clk R     8.395         8        5.107          M
+fifo_data_out[9]             rd_clk R     8.462         8        5.159          M
+fifo_empty1                  clk    R     6.338         8        3.901          M
+fifo_rden                    rd_clk R     9.015         8        4.309          M
+finished                     rd_clk R     5.699         8        2.640          M
+hades_buf_drop[1]            clk    R     4.373         8        2.516          M
+hades_buf_finished           clk    R     5.004         8        3.223          M
+hades_buf_out_valid          clk    R     4.373         8        2.516          M
+hades_buf_release            clk    R     5.056         8        3.233          M
+hades_dbg2_coarse[0]         clk    R     5.517         8        3.457          M
+hades_dbg2_coarse[1]         clk    R     5.565         8        3.485          M
+hades_dbg2_coarse[2]         clk    R     6.422         8        3.891          M
+hades_dbg2_coarse[3]         clk    R     5.749         8        3.576          M
+hades_dbg2_coarse[4]         clk    R     6.730         8        4.066          M
+hades_dbg2_coarse[5]         clk    R     6.629         8        3.989          M
+hades_dbg2_coarse[6]         clk    R     6.270         8        3.843          M
+hades_dbg2_coarse[7]         clk    R     7.034         8        4.220          M
+hades_dbg2_coarse[8]         clk    R     6.138         8        3.750          M
+hades_dbg2_out[0]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[10]           clk    R     5.455         8        3.421          M
+hades_dbg2_out[11]           clk    R     5.684         8        3.543          M
+hades_dbg2_out[12]           clk    R     5.446         8        3.434          M
+hades_dbg2_out[16]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[17]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[18]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[1]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[20]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[21]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[22]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[23]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[24]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[25]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[26]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[27]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[28]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[2]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[4]            clk    R     5.601         8        3.511          M
+hades_dbg2_out[5]            clk    R     5.147         8        3.282          M
+hades_dbg2_out[6]            clk    R     5.274         8        3.349          M
+hades_dbg2_out[7]            clk    R     5.147         8        3.282          M
+hades_dbg2_out[8]            clk    R     5.245         8        3.329          M
+hades_dbg2_out[9]            clk    R     5.236         8        3.332          M
+hades_discard                clk    R     5.876         8        3.609          M
+hades_drop_cmp_buf[0]        clk    R     4.849         8        3.145          M
+hades_drop_cmp_buf[1]        clk    R     5.102         8        3.255          M
+hades_drop_cmp_buf[2]        clk    R     5.292         8        3.360          M
+hades_drop_cmp_buf[3]        clk    R     5.275         8        3.342          M
+hades_drop_cmp_buf[4]        clk    R     5.205         8        3.328          M
+hades_drop_cmp_buf[5]        clk    R     5.149         8        3.303          M
+hades_drop_cmp_buf[6]        clk    R     4.937         8        3.174          M
+hades_drop_cmp_buf[7]        clk    R     5.330         8        3.397          M
+hades_drop_cmp_buf[8]        clk    R     5.190         8        3.317          M
+hades_drop_cmp_buf_coarse[0] clk    R     5.257         8        3.329          M
+hades_drop_cmp_buf_coarse[1] clk    R     5.665         8        3.523          M
+hades_drop_cmp_buf_coarse[2] clk    R     5.260         8        3.330          M
+hades_drop_cmp_buf_coarse[3] clk    R     5.770         8        3.582          M
+hades_drop_cmp_buf_coarse[4] clk    R     5.512         8        3.459          M
+hades_drop_cmp_buf_coarse[5] clk    R     5.675         8        3.526          M
+hades_drop_cmp_buf_coarse[6] clk    R     5.490         8        3.439          M
+hades_drop_cmp_buf_coarse[7] clk    R     5.333         8        3.360          M
+hades_drop_cmp_buf_coarse[8] clk    R     5.655         8        3.532          M
+hades_drop_cmp_buf_coarse[9] clk    R     5.740         8        3.562          M
+hades_drop_cmp_buf_valid     clk    R     5.087         8        3.238          M
+hades_hit_out_i[0]           clk    R     5.277         8        3.312          M
+hades_hit_out_i[1]           clk    R     5.091         8        3.241          M
+hades_hit_out_i[2]           clk    R     5.226         8        3.328          M
+hades_hit_out_i[3]           clk    R     5.455         8        3.423          M
+hades_hit_valid[0]           clk    R     4.969         8        3.196          M
+hades_hit_valid[1]           clk    R     4.807         8        3.119          M
+hades_hit_valid[2]           clk    R     4.969         8        3.196          M
+hades_hit_valid[3]           clk    R     4.695         8        3.062          M
+hades_invalid_dl[0]          clk    R     4.420         8        2.938          M
+hades_invalid_dl[1]          clk    R     5.004         8        3.220          M
+hades_invalid_dl[2]          clk    R     4.671         8        3.052          M
+hades_invalid_dl[3]          clk    R     4.976         8        3.211          M
+hades_offset[0]              clk    R     4.373         8        2.516          M
+hades_offset[1]              clk    R     4.373         8        2.516          M
+hades_offset[2]              clk    R     4.373         8        2.516          M
+hades_offset[3]              clk    R     4.373         8        2.516          M
+hades_offset[4]              clk    R     4.373         8        2.516          M
+hades_offset[5]              clk    R     4.373         8        2.516          M
+hades_offset[6]              clk    R     4.373         8        2.516          M
+hades_offset[7]              clk    R     4.373         8        2.516          M
+hades_offset[8]              clk    R     4.373         8        2.516          M
+hades_offset_valid           clk    R     6.416         8        3.925          M
+hades_raw_out_valid          clk    R     4.373         8        2.516          M
+hades_window_end             clk    R     6.286         8        3.867          M
+last_buf_empty               rd_clk R     7.396         8        3.504          M
+release_out                  rd_clk R     6.079         8        2.759          M
+WARNING: you must also run trce with hold speed: 8
+WARNING: you must also run trce with setup speed: M
diff --git a/impl1/s1_impl1.log b/impl1/s1_impl1.log
new file mode 100644
index 0000000..d0353b8
--- /dev/null
+++ b/impl1/s1_impl1.log
@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/impl1/s1_impl1.lpf b/impl1/s1_impl1.lpf
new file mode 100644
index 0000000..2743d95
--- /dev/null
+++ b/impl1/s1_impl1.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 200.000000 MHz;
diff --git a/impl1/s1_impl1.lsedata b/impl1/s1_impl1.lsedata
new file mode 100644
index 0000000..e16710f
--- /dev/null
+++ b/impl1/s1_impl1.lsedata
@@ -0,0 +1,120 @@
+<top name = "top"  library = "work"  arch = ""  entry = "Verilog">
+
+<clocks>
+    <clockitem name = "clk"  type = "port" />
+</clocks>
+
+<!--
+    //=============================================================
+    //  Number of Clocks processed: 1
+    //
+    //  If a clock cannot be found in the top level pins section,
+    //  that means it is an internal clock.
+    //
+    //=============================================================
+-->
+
+<library name = "work">
+
+<unit name = "top">
+
+    <!--
+        Top Level Pins: 4
+    -->
+
+    <pins>
+        <pitem  name = "clk"  direction = "in"  />
+        <pitem  name = "reset"  direction = "in"  />
+        <pitem  name = "cnt[1]"  direction = "out"  />
+        <pitem  name = "cnt[0]"  direction = "out"  />
+    </pins>
+
+    <!--
+        Instances in netlist: 3
+    -->
+
+    <instance  name = "add_3"  library = "work"  arch = ""  type = "comb">
+        <pins>
+        <pitem  name = "cin"  direction = "in"  />
+        <pitem  name = "a[1]"  direction = "in"  />
+        <pitem  name = "a[0]"  direction = "in"  />
+        <pitem  name = "b[1]"  direction = "in"  />
+        <pitem  name = "b[0]"  direction = "in"  />
+        <pitem  name = "o[1]"  direction = "out"  />
+        <pitem  name = "o[0]"  direction = "out"  />
+        </pins>
+
+        <nets>
+        <nitem  name = "gnd"  />
+        <nitem  name = "cnt[1]"  />
+        <nitem  name = "cnt[0]"  />
+        <nitem  name = "pwr"  />
+        <nitem  name = "cnt_1__N_3[1]"  />
+        <nitem  name = "cnt_1__N_3[0]"  />
+        </nets>
+    </instance>
+
+    <instance  name = "cnt_1__I_0"  library = "work"  arch = ""  type = "comb">
+        <pins>
+        <pitem  name = "d0[1]"  direction = "in"  />
+        <pitem  name = "d0[0]"  direction = "in"  />
+        <pitem  name = "d1[1]"  direction = "in"  />
+        <pitem  name = "d1[0]"  direction = "in"  />
+        <pitem  name = "cond"  direction = "in"  />
+        <pitem  name = "o[1]"  direction = "out"  />
+        <pitem  name = "o[0]"  direction = "out"  />
+        </pins>
+
+        <nets>
+        <nitem  name = "cnt_1__N_3[1]"  />
+        <nitem  name = "cnt_1__N_3[0]"  />
+        <nitem  name = "gnd"  />
+        <nitem  name = "reset"  />
+        <nitem  name = "cnt_1__N_1[1]"  />
+        <nitem  name = "cnt_1__N_1[0]"  />
+        </nets>
+    </instance>
+
+    <instance  name = "cnt"  library = "work"  arch = ""  type = "reg">
+        <pins>
+        <pitem  name = "d[1]"  direction = "in"  />
+        <pitem  name = "d[0]"  direction = "in"  />
+        <pitem  name = "set[1]"  direction = "in"  />
+        <pitem  name = "set[0]"  direction = "in"  />
+        <pitem  name = "reset[1]"  direction = "in"  />
+        <pitem  name = "reset[0]"  direction = "in"  />
+        <pitem  name = "clock"  direction = "in"  />
+        <pitem  name = "q[1]"  direction = "out"  />
+        <pitem  name = "q[0]"  direction = "out"  />
+        </pins>
+
+        <nets>
+        <nitem  name = "cnt_1__N_1[1]"  />
+        <nitem  name = "cnt_1__N_1[0]"  />
+        <nitem  name = "gnd"  />
+        <nitem  name = "clk"  />
+        <nitem  name = "cnt[1]"  />
+        <nitem  name = "cnt[0]"  />
+        </nets>
+    </instance>
+
+    <!--
+        REG instances in netlist: 1
+    -->
+
+    <regs>
+        <reg  name = "cnt"  />
+    </regs>
+
+    <!--
+        Views in design "top": 0
+    -->
+
+    <views>
+    </views>
+
+</unit>
+
+</library>
+
+</top>
diff --git a/impl1/s1_impl1.mrp b/impl1/s1_impl1.mrp
new file mode 100644
index 0000000..954bf0e
--- /dev/null
+++ b/impl1/s1_impl1.mrp
@@ -0,0 +1,12546 @@
+
+            Lattice Mapping Report File for Design Module 'top_tf'
+
+
+Design Information
+------------------
+
+Command line:   map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
+     s1_impl1.ngd -o s1_impl1_map.ncd -pr s1_impl1.prf -mp s1_impl1.mrp -lpf
+     /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf -lpf
+     /home/hadaq/mmichalek/lattice/simplified/s1.lpf -xref_sym -xref_sig -tdm
+     -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LFE5UM5G-45FCABGA381
+Target Performance:   8
+Mapper:  sa5p00g,  version:  Diamond (64-bit) 3.11.2.446
+Mapped on:  06/16/21  09:19:26
+
+Design Summary
+--------------
+
+   Number of registers:    934 out of 44457 (2%)
+      PFU registers:          899 out of 43848 (2%)
+      PIO registers:           35 out of   609 (6%)
+   Number of SLICEs:       692 out of 21924 (3%)
+      SLICEs as Logic/ROM:    692 out of 21924 (3%)
+      SLICEs as RAM:            0 out of 16443 (0%)
+      SLICEs as Carry:        121 out of 21924 (1%)
+   Number of LUT4s:        630 out of 43848 (1%)
+      Number used as logic LUTs:        388
+      Number used as distributed RAM:     0
+      Number used as ripple logic:      242
+      Number used as shift registers:     0
+   Number of PIO sites used: 187 out of 203 (92%)
+      Number of PIO sites used for single ended IOs: 185
+      Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
+     comps in NCD)
+   Number of block RAMs:  4 out of 108 (4%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   DTR used :   No
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
+   Number of DCC:  0 out of 60 (0%)
+   Number of DCS:  0 out of 2 (0%)
+   Number of PLLs:  1 out of 4 (25%)
+   Number of DDRDLLs:  0 out of 4 (0%)
+   Number of CLKDIV:  0 out of 4 (0%)
+   Number of ECLKSYNC:  0 out of 10 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Number of DCUs:  0 out of 2 (0%)
+   Number of DCU Channels:  0 out of 4 (0%)
+   Number of EXTREFs:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+
+
+                                    Page 1
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Design Summary (cont)
+---------------------
+        Number Of Mapped DSP Components:
+   --------------------------------
+   MULT18X18D          0
+   MULT9X9D            0
+   ALU54B              0
+   ALU24B              0
+   PRADD18A            0
+   PRADD9A             0
+   --------------------------------
+   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
+   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
+   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
+   Number of clocks:  6
+     Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk )
+     Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk )
+   Number of Clock Enables:  18
+     Net reset_dl[2]: 7 loads, 7 LSLICEs
+     Net N_248_i: 1 loads, 0 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs
+     Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs
+     Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6
+     LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads,
+     6 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads,
+     13 LSLICEs
+     Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10
+     loads, 1 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1
+     LSLICEs
+   Number of LSRs:  13
+     Net reset_dl[2]: 37 loads, 33 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+
+                                    Page 2
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Design Summary (cont)
+---------------------
+     loads, 1 LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+     loads, 1 LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+     loads, 1 LSLICEs
+     Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs
+     Net fifo_rden_c: 1 loads, 1 LSLICEs
+     Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sy
+     nced7_rising_i: 3 loads, 3 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced
+     7_rising_i: 4 loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4
+     loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1
+     LSLICEs
+     Net valid_fast_RNI999V: 9 loads, 0 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_risin
+     g_i: 4 loads, 4 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net reset_dl[2]: 59 loads
+     Net fifo_colector_inst/iterator[0]: 47 loads
+     Net fifo_colector_inst/iterator[1]: 23 loads
+     Net fifo_colector_inst/in_empty_pmux_i: 22 loads
+     Net un1_hit_i_2_0_a2: 20 loads
+     Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads
+
+Symbol Cross Reference
+----------------------
+
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+
+                                    Page 3
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20 (PFU) covers blocks:
+     full_cmp_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21 (PFU) covers blocks:
+     full_cmp_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22 (PFU) covers blocks:
+     full_cmp_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23 (PFU) covers blocks:
+     full_cmp_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24 (PFU) covers blocks:
+     full_cmp_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31 (PFU) covers blocks:
+
+                                    Page 4
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46 (PFU) covers blocks:
+     full_cmp_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47 (PFU) covers blocks:
+     full_cmp_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48 (PFU) covers blocks:
+     full_cmp_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49 (PFU) covers blocks:
+     full_cmp_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50 (PFU) covers blocks:
+     full_cmp_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55 (PFU) covers blocks:
+
+                                    Page 5
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72 (PFU) covers blocks:
+     full_cmp_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73 (PFU) covers blocks:
+     full_cmp_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74 (PFU) covers blocks:
+     full_cmp_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75 (PFU) covers blocks:
+     full_cmp_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76 (PFU) covers blocks:
+     full_cmp_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+fifo_colector_inst/fifo40_inst/SLICE_78 (PFU) covers blocks: w_gctr_cia
+fifo_colector_inst/fifo40_inst/SLICE_79 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_101,
+
+                                    Page 6
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/fifo40_inst/FF_100, w_gctr_0
+fifo_colector_inst/fifo40_inst/SLICE_80 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_99, fifo_colector_inst/fifo40_inst/FF_98,
+     w_gctr_1
+fifo_colector_inst/fifo40_inst/SLICE_81 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_97, fifo_colector_inst/fifo40_inst/FF_96,
+     w_gctr_2
+fifo_colector_inst/fifo40_inst/SLICE_82 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_95, fifo_colector_inst/fifo40_inst/FF_94,
+     w_gctr_3
+fifo_colector_inst/fifo40_inst/SLICE_83 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_93, fifo_colector_inst/fifo40_inst/FF_92,
+     w_gctr_4
+fifo_colector_inst/fifo40_inst/SLICE_84 (PFU) covers blocks: r_gctr_cia
+fifo_colector_inst/fifo40_inst/SLICE_85 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_71, fifo_colector_inst/fifo40_inst/FF_70,
+     r_gctr_0
+fifo_colector_inst/fifo40_inst/SLICE_86 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_69, fifo_colector_inst/fifo40_inst/FF_68,
+     r_gctr_1
+fifo_colector_inst/fifo40_inst/SLICE_87 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_67, fifo_colector_inst/fifo40_inst/FF_66,
+     r_gctr_2
+fifo_colector_inst/fifo40_inst/SLICE_88 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_65, fifo_colector_inst/fifo40_inst/FF_64,
+     r_gctr_3
+fifo_colector_inst/fifo40_inst/SLICE_89 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_63, fifo_colector_inst/fifo40_inst/FF_62,
+     r_gctr_4
+fifo_colector_inst/fifo40_inst/SLICE_90 (PFU) covers blocks: empty_cmp_ci_a
+fifo_colector_inst/fifo40_inst/SLICE_91 (PFU) covers blocks: empty_cmp_0
+fifo_colector_inst/fifo40_inst/SLICE_92 (PFU) covers blocks: empty_cmp_1
+fifo_colector_inst/fifo40_inst/SLICE_93 (PFU) covers blocks: empty_cmp_2
+fifo_colector_inst/fifo40_inst/SLICE_94 (PFU) covers blocks: empty_cmp_3
+fifo_colector_inst/fifo40_inst/SLICE_95 (PFU) covers blocks: empty_cmp_4
+fifo_colector_inst/fifo40_inst/SLICE_96 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_1, a0
+fifo_colector_inst/fifo40_inst/SLICE_97 (PFU) covers blocks: full_cmp_ci_a
+fifo_colector_inst/fifo40_inst/SLICE_98 (PFU) covers blocks: full_cmp_0
+fifo_colector_inst/fifo40_inst/SLICE_99 (PFU) covers blocks: full_cmp_1
+fifo_colector_inst/fifo40_inst/SLICE_100 (PFU) covers blocks: full_cmp_2
+fifo_colector_inst/fifo40_inst/SLICE_101 (PFU) covers blocks: full_cmp_3
+fifo_colector_inst/fifo40_inst/SLICE_102 (PFU) covers blocks: full_cmp_4
+fifo_colector_inst/fifo40_inst/SLICE_103 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_0, a1
+hades_tdc_bundle_inst/SLICE_104 (PFU) covers blocks: hit_valid25_0_I_27_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105 (PFU) covers
+     blocks: un1_coarse_1_0_I_1_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106 (PFU) covers
+     blocks: un1_coarse_1_0_I_9_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107 (PFU) covers
+     blocks: un1_coarse_1_0_I_21_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108 (PFU) covers
+     blocks: un1_coarse_1_0_I_27_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109 (PFU) covers
+     blocks: un1_buf_positive_0_I_1_0
+
+                                    Page 7
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110 (PFU) covers
+     blocks: un1_buf_positive_0_I_9_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111 (PFU) covers
+     blocks: un1_buf_positive_0_I_21_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112 (PFU) covers
+     blocks: un1_buf_positive_0_I_27_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 (PFU) covers blocks:
+     un1_window_8_cry_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 (PFU) covers blocks:
+     un1_window_8_cry_1_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115 (PFU) covers blocks:
+     un1_window_8_cry_3_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116 (PFU) covers blocks:
+     un1_window_8_cry_5_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117 (PFU) covers blocks:
+     un1_window_8_s_7_0
+hades_tdc_bundle_inst/SLICE_118 (PFU) covers blocks: hit_valid25_0_I_1_0
+hades_tdc_bundle_inst/SLICE_119 (PFU) covers blocks: hit_valid25_0_I_9_0
+hades_tdc_bundle_inst/SLICE_120 (PFU) covers blocks: hit_valid25_0_I_21_0
+hades_tdc_bundle_inst/SLICE_121 (PFU) covers blocks: hit_out_i_RNO[0],
+     buf_finished5_0_a2_0, hades_tdc_bundle_inst/hit_out_i[0]
+hades_tdc_bundle_inst/SLICE_122 (PFU) covers blocks: SUM1_1_x2, N_50_i_i,
+     hades_tdc_bundle_inst/hit_out_i[1], hades_tdc_bundle_inst/hit_out_i[3]
+hades_tdc_bundle_inst/SLICE_123 (PFU) covers blocks: hit_out_i_6_f1_0[2],
+     hit_valid_pmux_iv_0_a2_2, hades_tdc_bundle_inst/hit_out_i[2]
+trb_adapter_inst/SLICE_124 (PFU) covers blocks:
+     trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1]
+fifo_colector_inst/SLICE_125 (PFU) covers blocks: in_empty_pmux_0_RNIDRET,
+     in_empty_pmux_0, fifo_colector_inst/buffer_wr_enable
+fifo_colector_inst/SLICE_126 (PFU) covers blocks: data_buffer_3[0],
+     data_buffer_3_0[0], fifo_colector_inst/data_buffer[0]
+fifo_colector_inst/SLICE_127 (PFU) covers blocks: data_buffer_3[1],
+     data_buffer_3_0[1], fifo_colector_inst/data_buffer[1]
+fifo_colector_inst/SLICE_128 (PFU) covers blocks: data_buffer_3[2],
+     data_buffer_3_0[2], fifo_colector_inst/data_buffer[2]
+fifo_colector_inst/SLICE_129 (PFU) covers blocks: data_buffer_3[3],
+     data_buffer_3_0[3], fifo_colector_inst/data_buffer[3]
+fifo_colector_inst/SLICE_130 (PFU) covers blocks: data_buffer_3[4],
+     data_buffer_3_0[4], fifo_colector_inst/data_buffer[4]
+fifo_colector_inst/SLICE_131 (PFU) covers blocks: data_buffer_3[5],
+     data_buffer_3_0[5], fifo_colector_inst/data_buffer[5]
+fifo_colector_inst/SLICE_132 (PFU) covers blocks: data_buffer_3[6],
+     data_buffer_3_0[6], fifo_colector_inst/data_buffer[6]
+fifo_colector_inst/SLICE_133 (PFU) covers blocks: data_buffer_3[7],
+     data_buffer_3_0[7], fifo_colector_inst/data_buffer[7]
+fifo_colector_inst/SLICE_134 (PFU) covers blocks: data_buffer_3_0[8],
+     data_buffer_3_0[9], fifo_colector_inst/data_buffer[8],
+     fifo_colector_inst/data_buffer[9]
+fifo_colector_inst/SLICE_135 (PFU) covers blocks: data_buffer_3_0[10],
+     data_buffer_3_0[11], fifo_colector_inst/data_buffer[10],
+     fifo_colector_inst/data_buffer[11]
+fifo_colector_inst/SLICE_136 (PFU) covers blocks: data_buffer_3_0[12],
+     data_buffer_3_0[13], fifo_colector_inst/data_buffer[12],
+     fifo_colector_inst/data_buffer[13]
+fifo_colector_inst/SLICE_137 (PFU) covers blocks: data_buffer_3_0[14],
+     data_buffer_3_0[15], fifo_colector_inst/data_buffer[14],
+
+                                    Page 8
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/data_buffer[15]
+fifo_colector_inst/SLICE_138 (PFU) covers blocks: data_buffer_3_0[16],
+     data_buffer_3_0[17], fifo_colector_inst/data_buffer[16],
+     fifo_colector_inst/data_buffer[17]
+fifo_colector_inst/SLICE_139 (PFU) covers blocks: data_buffer_3_0[18],
+     data_buffer_3_0[19], fifo_colector_inst/data_buffer[18],
+     fifo_colector_inst/data_buffer[19]
+fifo_colector_inst/SLICE_140 (PFU) covers blocks: data_buffer_3_0[20],
+     data_buffer_3_0[21], fifo_colector_inst/data_buffer[20],
+     fifo_colector_inst/data_buffer[21]
+fifo_colector_inst/SLICE_141 (PFU) covers blocks: data_buffer_3_0[22],
+     data_buffer_3_0[23], fifo_colector_inst/data_buffer[22],
+     fifo_colector_inst/data_buffer[23]
+fifo_colector_inst/SLICE_142 (PFU) covers blocks: data_buffer_3_0[24],
+     data_buffer_3_0[25], fifo_colector_inst/data_buffer[24],
+     fifo_colector_inst/data_buffer[25]
+fifo_colector_inst/SLICE_143 (PFU) covers blocks: data_buffer_3_0[26],
+     data_buffer_3_0[27], fifo_colector_inst/data_buffer[26],
+     fifo_colector_inst/data_buffer[27]
+fifo_colector_inst/SLICE_144 (PFU) covers blocks: data_buffer_3_0[28],
+     data_buffer_3_0[29], fifo_colector_inst/data_buffer[28],
+     fifo_colector_inst/data_buffer[29]
+fifo_colector_inst/SLICE_145 (PFU) covers blocks: data_buffer_3_0[30],
+     data_buffer_3_0[31], fifo_colector_inst/data_buffer[30],
+     fifo_colector_inst/data_buffer[31]
+fifo_colector_inst/SLICE_146 (PFU) covers blocks:
+     fifo_colector_inst/data_buffer[32], fifo_colector_inst/data_buffer[33]
+fifo_colector_inst/fifo40_inst/SLICE_147 (PFU) covers blocks: XOR2_t8, XOR2_t7,
+     fifo_colector_inst/fifo40_inst/FF_61, fifo_colector_inst/fifo40_inst/FF_60
+fifo_colector_inst/fifo40_inst/SLICE_148 (PFU) covers blocks: XOR2_t6, XOR2_t5,
+     fifo_colector_inst/fifo40_inst/FF_59, fifo_colector_inst/fifo40_inst/FF_58
+fifo_colector_inst/fifo40_inst/SLICE_149 (PFU) covers blocks: XOR2_t4, XOR2_t3,
+     fifo_colector_inst/fifo40_inst/FF_57, fifo_colector_inst/fifo40_inst/FF_56
+fifo_colector_inst/fifo40_inst/SLICE_150 (PFU) covers blocks: XOR2_t2, XOR2_t1,
+     fifo_colector_inst/fifo40_inst/FF_55, fifo_colector_inst/fifo40_inst/FF_54
+fifo_colector_inst/fifo40_inst/SLICE_151 (PFU) covers blocks: XOR2_t0,
+     fifo_colector_inst/fifo40_inst/FF_53, fifo_colector_inst/fifo40_inst/FF_52
+fifo_colector_inst/fifo40_inst/SLICE_152 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_31, fifo_colector_inst/fifo40_inst/FF_30
+fifo_colector_inst/fifo40_inst/SLICE_153 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_29, fifo_colector_inst/fifo40_inst/FF_28
+fifo_colector_inst/fifo40_inst/SLICE_154 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_27, fifo_colector_inst/fifo40_inst/FF_26
+fifo_colector_inst/fifo40_inst/SLICE_155 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_25, fifo_colector_inst/fifo40_inst/FF_24
+fifo_colector_inst/fifo40_inst/SLICE_156 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_23, fifo_colector_inst/fifo40_inst/FF_22
+fifo_colector_inst/fifo40_inst/SLICE_157 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_11, fifo_colector_inst/fifo40_inst/FF_10
+fifo_colector_inst/fifo40_inst/SLICE_158 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_9, fifo_colector_inst/fifo40_inst/FF_8
+fifo_colector_inst/fifo40_inst/SLICE_159 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_7, fifo_colector_inst/fifo40_inst/FF_6
+fifo_colector_inst/fifo40_inst/SLICE_160 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_5, fifo_colector_inst/fifo40_inst/FF_4
+fifo_colector_inst/fifo40_inst/SLICE_161 (PFU) covers blocks:
+
+                                    Page 9
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/fifo40_inst/FF_3, fifo_colector_inst/fifo40_inst/FF_2
+fifo_colector_inst/fifo40_inst/SLICE_162 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_51, fifo_colector_inst/fifo40_inst/FF_50
+fifo_colector_inst/fifo40_inst/SLICE_163 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_49, fifo_colector_inst/fifo40_inst/FF_48
+fifo_colector_inst/fifo40_inst/SLICE_164 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_47, fifo_colector_inst/fifo40_inst/FF_46
+fifo_colector_inst/fifo40_inst/SLICE_165 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_45, fifo_colector_inst/fifo40_inst/FF_44
+fifo_colector_inst/fifo40_inst/SLICE_166 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_43, fifo_colector_inst/fifo40_inst/FF_42
+fifo_colector_inst/fifo40_inst/SLICE_167 (PFU) covers blocks: XOR2_t17,
+     XOR2_t16, fifo_colector_inst/fifo40_inst/FF_91,
+     fifo_colector_inst/fifo40_inst/FF_90
+fifo_colector_inst/fifo40_inst/SLICE_168 (PFU) covers blocks: XOR2_t15,
+     XOR2_t14, fifo_colector_inst/fifo40_inst/FF_89,
+     fifo_colector_inst/fifo40_inst/FF_88
+fifo_colector_inst/fifo40_inst/SLICE_169 (PFU) covers blocks: XOR2_t13,
+     XOR2_t12, fifo_colector_inst/fifo40_inst/FF_87,
+     fifo_colector_inst/fifo40_inst/FF_86
+fifo_colector_inst/fifo40_inst/SLICE_170 (PFU) covers blocks: XOR2_t11,
+     XOR2_t10, fifo_colector_inst/fifo40_inst/FF_85,
+     fifo_colector_inst/fifo40_inst/FF_84
+fifo_colector_inst/fifo40_inst/SLICE_171 (PFU) covers blocks: XOR2_t9,
+     fifo_colector_inst/fifo40_inst/FF_83, fifo_colector_inst/fifo40_inst/FF_82
+fifo_colector_inst/fifo40_inst/SLICE_172 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_41, fifo_colector_inst/fifo40_inst/FF_40
+fifo_colector_inst/fifo40_inst/SLICE_173 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_39, fifo_colector_inst/fifo40_inst/FF_38
+fifo_colector_inst/fifo40_inst/SLICE_174 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_37, fifo_colector_inst/fifo40_inst/FF_36
+fifo_colector_inst/fifo40_inst/SLICE_175 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_35, fifo_colector_inst/fifo40_inst/FF_34
+fifo_colector_inst/fifo40_inst/SLICE_176 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_33, fifo_colector_inst/fifo40_inst/FF_32
+fifo_colector_inst/fifo40_inst/SLICE_177 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_21, fifo_colector_inst/fifo40_inst/FF_20
+fifo_colector_inst/fifo40_inst/SLICE_178 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_19, fifo_colector_inst/fifo40_inst/FF_18
+fifo_colector_inst/fifo40_inst/SLICE_179 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_17, fifo_colector_inst/fifo40_inst/FF_16
+fifo_colector_inst/fifo40_inst/SLICE_180 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_15, fifo_colector_inst/fifo40_inst/FF_14
+fifo_colector_inst/fifo40_inst/SLICE_181 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_13, fifo_colector_inst/fifo40_inst/FF_12
+fifo_colector_inst/fifo40_inst/SLICE_182 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_81, fifo_colector_inst/fifo40_inst/FF_80
+fifo_colector_inst/fifo40_inst/SLICE_183 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_79, fifo_colector_inst/fifo40_inst/FF_78
+fifo_colector_inst/fifo40_inst/SLICE_184 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_77, fifo_colector_inst/fifo40_inst/FF_76
+fifo_colector_inst/fifo40_inst/SLICE_185 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_75, fifo_colector_inst/fifo40_inst/FF_74
+fifo_colector_inst/fifo40_inst/SLICE_186 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_73, fifo_colector_inst/fifo40_inst/FF_72
+fifo_colector_inst/SLICE_187 (PFU) covers blocks: un5_in_read_enable,
+
+                                   Page 10
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/iterator[0], fifo_colector_inst/iterator[1]
+trb_adapter_inst/SLICE_188 (PFU) covers blocks: buf_rden4, burst,
+     trb_adapter_inst/buf_rden
+fifo_colector_inst/SLICE_189 (PFU) covers blocks: in_read_enable_0_.fb,
+     in_read_enable_1_.fb, fifo_colector_inst/in_read_enable[0],
+     fifo_colector_inst/in_read_enable[1]
+fifo_colector_inst/SLICE_190 (PFU) covers blocks: in_read_enable_2_.fb,
+     fifo_colector_inst/in_read_enable[2]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+
+                                   Page 11
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210 (PFU) covers
+     blocks: XOR2_t0, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+
+                                   Page 12
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230 (PFU) covers
+     blocks: XOR2_t9, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+
+                                   Page 13
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[0].tdc_channel_fifo_out_inst/SLICE_246 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+
+                                   Page 14
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290 (PFU) covers
+     blocks: XOR2_t0, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291 (PFU) covers
+
+                                   Page 15
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+
+                                   Page 16
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310 (PFU) covers
+     blocks: XOR2_t9, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[1].tdc_channel_fifo_out_inst/SLICE_326 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+
+                                   Page 17
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+
+                                   Page 18
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370 (PFU) covers
+     blocks: XOR2_t0, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+
+                                   Page 19
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390 (PFU) covers
+     blocks: XOR2_t9, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+
+                                   Page 20
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[2].tdc_channel_fifo_out_inst/SLICE_406 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+
+                                   Page 21
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/SLICE_432 (PFU) covers blocks: buf_finished_RNO,
+     buf_finished5_0_a2_0, hades_tdc_bundle_inst/buf_finished
+hades_tdc_bundle_inst/SLICE_433 (PFU) covers blocks:
+     hades_tdc_bundle_inst/buf_release
+hades_tdc_bundle_inst/SLICE_434 (PFU) covers blocks: coarse_RNI8DE6[0],
+     drop_cmp_buf_coarse_2_axbxc1, hades_tdc_bundle_inst/coarse[0],
+     hades_tdc_bundle_inst/coarse[1]
+hades_tdc_bundle_inst/SLICE_435 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc2, coarse_RNI6RPP[2],
+     hades_tdc_bundle_inst/coarse[2], hades_tdc_bundle_inst/coarse[3]
+hades_tdc_bundle_inst/SLICE_436 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc4, drop_cmp_buf_coarse_2_axbxc5,
+     hades_tdc_bundle_inst/coarse[4], hades_tdc_bundle_inst/coarse[5]
+hades_tdc_bundle_inst/SLICE_437 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc6, drop_cmp_buf_coarse_2_axbxc7,
+     hades_tdc_bundle_inst/coarse[6], hades_tdc_bundle_inst/coarse[7]
+hades_tdc_bundle_inst/SLICE_438 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc8, drop_cmp_buf_coarse_2_ac0_5,
+     hades_tdc_bundle_inst/coarse[8]
+hades_tdc_bundle_inst/SLICE_439 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[3],
+     hades_tdc_bundle_inst/hitbuffer_1_[4]
+hades_tdc_bundle_inst/SLICE_440 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[5],
+     hades_tdc_bundle_inst/hitbuffer_1_[6]
+hades_tdc_bundle_inst/SLICE_441 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[7],
+     hades_tdc_bundle_inst/hitbuffer_1_[8]
+hades_tdc_bundle_inst/SLICE_442 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[9],
+     hades_tdc_bundle_inst/hitbuffer_1_[10]
+
+                                   Page 22
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/SLICE_443 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[11]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444 (PFU) covers blocks:
+     trig_dl_RNI41GL1[3], discard_en,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard
+hades_tdc_bundle_inst/SLICE_445 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[0],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[1]
+hades_tdc_bundle_inst/SLICE_446 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[2],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[3]
+hades_tdc_bundle_inst/SLICE_447 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[4],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[5]
+hades_tdc_bundle_inst/SLICE_448 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[6],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[7]
+hades_tdc_bundle_inst/SLICE_449 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[8]
+hades_tdc_bundle_inst/SLICE_450 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[0],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1]
+hades_tdc_bundle_inst/SLICE_451 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[2],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3]
+hades_tdc_bundle_inst/SLICE_452 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[4],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5]
+hades_tdc_bundle_inst/SLICE_453 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[6],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7]
+hades_tdc_bundle_inst/SLICE_454 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8]
+hades_tdc_bundle_inst/SLICE_455 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_ac0_15, drop_cmp_buf_coarse_2_ac0_9_0,
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[9]
+hades_tdc_bundle_inst/SLICE_456 (PFU) covers blocks: drop_cmp_buf_valid_4_iv_i,
+     hades_tdc_bundle_inst/drop_cmp_buf_valid
+hades_tdc_bundle_inst/SLICE_457 (PFU) covers blocks: hit_valid_1_RNO[0],
+     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[0]
+hades_tdc_bundle_inst/SLICE_458 (PFU) covers blocks: hit_valid_1_RNO[1],
+     drop_cmp_buf_valid_0_sqmuxa_0_a2, hades_tdc_bundle_inst/hit_valid_1[1]
+hades_tdc_bundle_inst/SLICE_459 (PFU) covers blocks: hit_valid_1_RNO[2],
+     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[2]
+hades_tdc_bundle_inst/SLICE_460 (PFU) covers blocks: hit_valid_1_RNO[3],
+     SUM1_0_0_o2, hades_tdc_bundle_inst/hit_valid_1[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463 (PFU) covers blocks:
+     offset_valid_RNO,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[0],
+
+                                   Page 23
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[13],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[15],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[17],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[19],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[21],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483 (PFU) covers
+     blocks:
+
+                                   Page 24
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486 (PFU) covers
+     blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487 (PFU) covers
+     blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488 (PFU) covers
+     blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489 (PFU) covers
+     blocks: valid_internal_RNO, un1_out_internal35_1_0_m3,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered1[0], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered1[1], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered1[2], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered1[3], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered1[4], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered1[5], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered1[6], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[2].in_clk_synced[6]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered1[7], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[3].in_clk_synced[7]
+
+                                   Page 25
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered[4]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered[6]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518 (PFU) covers blocks:
+     window_RNO[0], un1_reset_0_a2_2,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519 (PFU) covers blocks:
+     window_6[1], window_6[3],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 (PFU) covers blocks:
+     window_0_sqmuxadup, un1_invalid_dl,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521 (PFU) covers blocks:
+     window_6[4], window_6[5],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522 (PFU) covers blocks:
+     window_6[6], window_6[7],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[3],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[5],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[7],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8]
+
+                                   Page 26
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[9],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528 (PFU) covers
+     blocks: buf_negative_ready_RNIG7JA,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out_valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535 (PFU) covers
+     blocks: buf_negative_ready_4_f0_0_0,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541 (PFU) covers
+
+                                   Page 27
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542 (PFU) covers
+     blocks: buf_positive_ready_4_iv_i_0,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555 (PFU)
+     covers blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7, hades_
+
+                                   Page 28
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556 (PFU)
+     covers blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0, hade
+     s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557 (PFU)
+     covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1, hades_
+     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558 (PFU)
+     covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_tdc_bun
+     dle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+
+                                   Page 29
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     ec_neg_inst/in_synced[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i, out_internal_2_1_0_.m15_i, 
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inter
+     nal[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/o
+     ut_internal[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572
+     (PFU) covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_o5,
+      hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inte
+     rnal[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573
+     (PFU) covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_t
+     dc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576
+     (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577
+     (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+
+                                   Page 30
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+
+                                   Page 31
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     t/genblk1[2].out_buffered[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/SLICE_628 (PFU) covers blocks: SUM0_1_0_x2, SUM1_0_0,
+     hades_tdc_bundle_inst/hit_i[0], hades_tdc_bundle_inst/hit_i[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629 (PFU) covers blocks:
+     window_end5_0_a2, discard4_0_a2_0,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end
+trb_adapter_inst/SLICE_631 (PFU) covers blocks:
+     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1],
+     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
+trb_adapter_inst/SLICE_632 (PFU) covers blocks: trb_adapter_inst/buf_rden_prev
+trb_adapter_inst/SLICE_633 (PFU) covers blocks: trb_adapter_inst/finished_prev
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 (PFU) covers blocks:
+     offset_1_sqmuxa_i_0, offset_1_sqmuxa_i_0_o2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635 (PFU) covers blocks:
+     un1_reset_0_a2_1, discard4_0_a2_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+
+                                   Page 32
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+fifo_colector_inst/fifo40_inst/SLICE_648 (PFU) covers blocks: LUT4_6, LUT4_13
+fifo_colector_inst/fifo40_inst/SLICE_649 (PFU) covers blocks: LUT4_9, LUT4_11
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+hades_tdc_bundle_inst/SLICE_653 (PFU) covers blocks:
+     hit_valid_pmux_iv_0_a2_2_RNITDG11, hit_valid_pmux_iv_0_a2_2
+hades_tdc_bundle_inst/SLICE_654 (PFU) covers blocks: hit_valid_pmux_iv_0_0,
+     hit_valid_pmux_iv_0_a2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+
+                                   Page 33
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+fifo_colector_inst/fifo40_inst/SLICE_673 (PFU) covers blocks: LUT4_23, LUT4_14
+fifo_colector_inst/fifo40_inst/SLICE_674 (PFU) covers blocks: LUT4_22, LUT4_15
+fifo_colector_inst/fifo40_inst/SLICE_675 (PFU) covers blocks: LUT4_21, LUT4_19
+fifo_colector_inst/fifo40_inst/SLICE_676 (PFU) covers blocks: LUT4_20, LUT4_18
+fifo_colector_inst/fifo40_inst/SLICE_677 (PFU) covers blocks: LUT4_13, LUT4_4
+fifo_colector_inst/fifo40_inst/SLICE_678 (PFU) covers blocks: LUT4_12, LUT4_5
+fifo_colector_inst/fifo40_inst/SLICE_679 (PFU) covers blocks: LUT4_10, LUT4_8
+fifo_colector_inst/SLICE_680 (PFU) covers blocks: in_empty_pmux_u,
+     in_empty_pmux_0
+hades_tdc_bundle_inst/SLICE_681 (PFU) covers blocks:
+     un1_buf_positive_0_I_9_0_RNO_0, drop_cmp_buf_coarse_2_ac0_3
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682 (PFU) covers blocks:
+     un1_reset_0_a2_c, discard4_0_a2_0
+hades_tdc_bundle_inst/SLICE_683 (PFU) covers blocks: buf_out12,
+     hit_valid_pmux_iv_0_a2_2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684 (PFU) covers blocks:
+     discard4_0_a2_0_3, window_RNIOA5C[2]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+fifo_colector_inst/fifo40_inst/SLICE_691 (PFU) covers blocks: LUT4_0, LUT4_1
+fifo_colector_inst/fifo40_inst/SLICE_692 (PFU) covers blocks: LUT4_3, LUT4_2
+hades_tdc_bundle_inst/SLICE_693 (PFU) covers blocks: un1_hit_i_2_0_a2,
+     SUM1_0_0_o2_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694
+     (PFU) covers blocks: un1_out_internal35_1_0_o5, out_internal_2_1_0_.m15_i_1
+     
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695 (PFU)
+     covers blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696 (PFU)
+     covers blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697 (PFU) covers
+     blocks: un1_coarse_1_0_I_9_0_RNO, un1_buf_positive_0_I_9_0_RNO
+hades_tdc_bundle_inst/SLICE_698 (PFU) covers blocks: un1_coarse_1_0_I_9_RNO_0,
+     drop_cmp_buf_coarse_2_ac0_7
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699 (PFU) covers
+     blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700 (PFU) covers
+     blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
+hades_tdc_bundle_inst/SLICE_701 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_ac0_13_0, drop_cmp_buf_coarse_2_ac0_9_0
+fifo_colector_inst/fifo40_inst/SLICE_702 (PFU) covers blocks: LUT4_16, LUT4_17
+fifo_colector_inst/fifo40_inst/SLICE_703 (PFU) covers blocks: LUT4_7, LUT4_11
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+
+                                   Page 34
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+hades_tdc_bundle_inst/SLICE_710 (PFU) covers blocks: hit_valid_pmux_iv_0_m2,
+     drop_cmp_buf_valid_0_sqmuxa_0_a2
+genblk1[2].tdc_channel_fifo_out_inst/SLICE_711 (PFU) covers blocks: AND2_t20,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712 (PFU) covers
+     blocks: AND2_t19
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713 (PFU) covers blocks:
+     valid_internal_RNO_0
+genblk1[1].tdc_channel_fifo_out_inst/SLICE_714 (PFU) covers blocks: AND2_t20,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715 (PFU) covers
+     blocks: AND2_t19
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716 (PFU) covers blocks:
+     valid_internal_RNO_0
+genblk1[0].tdc_channel_fifo_out_inst/SLICE_717 (PFU) covers blocks: AND2_t20,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718 (PFU) covers
+     blocks: AND2_t19
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719 (PFU) covers blocks:
+     valid_internal_RNO_0
+fifo_colector_inst/fifo40_inst/SLICE_720 (PFU) covers blocks: AND2_t19
+fifo_colector_inst/fifo40_inst/SLICE_721 (PFU) covers blocks: AND2_t20
+fifo_colector_inst/SLICE_722 (PFU) covers blocks: iterator_RNI7U5I[1]
+trb_adapter_inst/SLICE_723 (PFU) covers blocks: LVL1_TRG_DATA_VALI_IN_rising
+trb_adapter_inst/SLICE_724 (PFU) covers blocks: release_out,
+     trb_adapter_inst/finished
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725
+     (PFU) covers blocks: valid_RNI97O31,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726
+     (PFU) covers blocks: in_synced_RNIT1GT[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727
+     (PFU) covers blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i_m3
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730 (PFU)
+     covers blocks: in_synced_RNIB4EQ[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731 (PFU)
+     covers blocks: valid_RNI8UMR,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732 (PFU)
+     covers blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 (PFU) covers
+     blocks: valid_fast_RNI999V
+
+                                   Page 35
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734 (PFU) covers
+     blocks: in_synced_RNI3HPF[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735 (PFU) covers
+     blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (PFU) covers
+     blocks: valid_fast_RNI5DQ71,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737 (PFU) covers blocks:
+     un1_reset_0_a2_2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 (PFU) covers blocks:
+     window_6[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739 (PFU) covers blocks:
+     window_RNICU4C[3]
+SLICE_740 (PFU) covers blocks: drop_cmp_buf_0_sqmuxa_0_a2, reset_dl[2]
+hades_tdc_bundle_inst/SLICE_741 (PFU) covers blocks: hit_out_i_6_i_a2_0[0]
+pll0inst/SLICE_742 (PFU) covers blocks: GND
+SLICE_743 (PFU) covers blocks: hades_lvl1_pad_RNINMH5
+SLICE_744 (PFU) covers blocks: trig_pad_RNII4FF[0]
+SLICE_745 (PFU) covers blocks: trig_pad_RNIJ5FF[1]
+SLICE_746 (PFU) covers blocks: trig_pad_RNIK6FF[2]
+SLICE_747 (PFU) covers blocks: hades_trig_pad_RNIE1B4
+hades_raw_valid_vect[0] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[0]
+fifo_data_out[0] (PIC/PIO) covers blocks: fifo_data_out_pad[0]
+clk (PIC/PIO) covers blocks: clk_pad
+hades_drop_cmp_buf_valid (PIC/PIO) covers blocks: hades_drop_cmp_buf_valid_pad
+hades_drop_cmp_buf_coarse[11] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[11]
+hades_drop_cmp_buf_coarse[10] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[10]
+hades_drop_cmp_buf_coarse[9] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[9]
+hades_drop_cmp_buf_coarse[8] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[8]
+hades_drop_cmp_buf_coarse[7] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[7]
+hades_drop_cmp_buf_coarse[6] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[6]
+hades_drop_cmp_buf_coarse[5] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[5]
+hades_drop_cmp_buf_coarse[4] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[4]
+hades_drop_cmp_buf_coarse[3] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[3]
+hades_drop_cmp_buf_coarse[2] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[2]
+hades_drop_cmp_buf_coarse[1] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[1]
+hades_drop_cmp_buf_coarse[0] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[0]
+hades_drop_cmp_buf[11] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[11]
+hades_drop_cmp_buf[10] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[10]
+hades_drop_cmp_buf[9] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[9]
+hades_drop_cmp_buf[8] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[8]
+hades_drop_cmp_buf[7] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[7]
+hades_drop_cmp_buf[6] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[6]
+hades_drop_cmp_buf[5] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[5]
+
+                                   Page 36
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+hades_drop_cmp_buf[4] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[4]
+hades_drop_cmp_buf[3] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[3]
+hades_drop_cmp_buf[2] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[2]
+hades_drop_cmp_buf[1] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[1]
+hades_drop_cmp_buf[0] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[0]
+hades_dbg2_coarse[8] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[8]
+hades_dbg2_coarse[7] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[7]
+hades_dbg2_coarse[6] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[6]
+hades_dbg2_coarse[5] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[5]
+hades_dbg2_coarse[4] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[4]
+hades_dbg2_coarse[3] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[3]
+hades_dbg2_coarse[2] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[2]
+hades_dbg2_coarse[1] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[1]
+hades_dbg2_coarse[0] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[0]
+hades_dbg2_out[31] (PIC/PIO) covers blocks: hades_dbg2_out_pad[31]
+hades_dbg2_out[30] (PIC/PIO) covers blocks: hades_dbg2_out_pad[30]
+hades_dbg2_out[29] (PIC/PIO) covers blocks: hades_dbg2_out_pad[29]
+hades_dbg2_out[28] (PIC/PIO) covers blocks: hades_dbg2_out_pad[28],
+     hades_tdc_bundle_inst_hitbuffer_1_io[23]
+hades_dbg2_out[27] (PIC/PIO) covers blocks: hades_dbg2_out_pad[27],
+     hades_tdc_bundle_inst_hitbuffer_1_io[22]
+hades_dbg2_out[26] (PIC/PIO) covers blocks: hades_dbg2_out_pad[26],
+     hades_tdc_bundle_inst_hitbuffer_1_io[21]
+hades_dbg2_out[25] (PIC/PIO) covers blocks: hades_dbg2_out_pad[25],
+     hades_tdc_bundle_inst_hitbuffer_1_io[20]
+hades_dbg2_out[24] (PIC/PIO) covers blocks: hades_dbg2_out_pad[24],
+     hades_tdc_bundle_inst_hitbuffer_1_io[19]
+hades_dbg2_out[23] (PIC/PIO) covers blocks: hades_dbg2_out_pad[23],
+     hades_tdc_bundle_inst_hitbuffer_1_io[18]
+hades_dbg2_out[22] (PIC/PIO) covers blocks: hades_dbg2_out_pad[22],
+     hades_tdc_bundle_inst_hitbuffer_1_io[17]
+hades_dbg2_out[21] (PIC/PIO) covers blocks: hades_dbg2_out_pad[21],
+     hades_tdc_bundle_inst_hitbuffer_1_io[16]
+hades_dbg2_out[20] (PIC/PIO) covers blocks: hades_dbg2_out_pad[20],
+     hades_tdc_bundle_inst_hitbuffer_1_io[15]
+hades_dbg2_out[19] (PIC/PIO) covers blocks: hades_dbg2_out_pad[19]
+hades_dbg2_out[18] (PIC/PIO) covers blocks: hades_dbg2_out_pad[18],
+     hades_tdc_bundle_inst_hitbuffer_1_io[14]
+hades_dbg2_out[17] (PIC/PIO) covers blocks: hades_dbg2_out_pad[17],
+     hades_tdc_bundle_inst_hitbuffer_1_io[13]
+hades_dbg2_out[16] (PIC/PIO) covers blocks: hades_dbg2_out_pad[16],
+     hades_tdc_bundle_inst_hitbuffer_1_io[12]
+hades_dbg2_out[15] (PIC/PIO) covers blocks: hades_dbg2_out_pad[15]
+hades_dbg2_out[14] (PIC/PIO) covers blocks: hades_dbg2_out_pad[14]
+hades_dbg2_out[13] (PIC/PIO) covers blocks: hades_dbg2_out_pad[13]
+hades_dbg2_out[12] (PIC/PIO) covers blocks: hades_dbg2_out_pad[12]
+hades_dbg2_out[11] (PIC/PIO) covers blocks: hades_dbg2_out_pad[11]
+hades_dbg2_out[10] (PIC/PIO) covers blocks: hades_dbg2_out_pad[10]
+hades_dbg2_out[9] (PIC/PIO) covers blocks: hades_dbg2_out_pad[9]
+hades_dbg2_out[8] (PIC/PIO) covers blocks: hades_dbg2_out_pad[8]
+hades_dbg2_out[7] (PIC/PIO) covers blocks: hades_dbg2_out_pad[7]
+hades_dbg2_out[6] (PIC/PIO) covers blocks: hades_dbg2_out_pad[6]
+hades_dbg2_out[5] (PIC/PIO) covers blocks: hades_dbg2_out_pad[5]
+hades_dbg2_out[4] (PIC/PIO) covers blocks: hades_dbg2_out_pad[4]
+hades_dbg2_out[3] (PIC/PIO) covers blocks: hades_dbg2_out_pad[3]
+hades_dbg2_out[2] (PIC/PIO) covers blocks: hades_dbg2_out_pad[2],
+
+                                   Page 37
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst_hitbuffer_1_io[2]
+hades_dbg2_out[1] (PIC/PIO) covers blocks: hades_dbg2_out_pad[1],
+     hades_tdc_bundle_inst_hitbuffer_1_io[1]
+hades_dbg2_out[0] (PIC/PIO) covers blocks: hades_dbg2_out_pad[0],
+     hades_tdc_bundle_inst_hitbuffer_1_io[0]
+hades_buf_drop[3] (PIC/PIO) covers blocks: hades_buf_drop_pad[3]
+hades_buf_drop[2] (PIC/PIO) covers blocks: hades_buf_drop_pad[2]
+hades_buf_drop[1] (PIC/PIO) covers blocks: hades_buf_drop_pad[1],
+     hades_tdc_bundle_inst_buf_drop_1io[1]
+hades_buf_drop[0] (PIC/PIO) covers blocks: hades_buf_drop_pad[0]
+hades_invalid_dl[3] (PIC/PIO) covers blocks: hades_invalid_dl_pad[3]
+hades_invalid_dl[2] (PIC/PIO) covers blocks: hades_invalid_dl_pad[2]
+hades_invalid_dl[1] (PIC/PIO) covers blocks: hades_invalid_dl_pad[1]
+hades_invalid_dl[0] (PIC/PIO) covers blocks: hades_invalid_dl_pad[0]
+hades_discard (PIC/PIO) covers blocks: hades_discard_pad
+hades_hit_valid[3] (PIC/PIO) covers blocks: hades_hit_valid_pad[3]
+hades_hit_valid[2] (PIC/PIO) covers blocks: hades_hit_valid_pad[2]
+hades_hit_valid[1] (PIC/PIO) covers blocks: hades_hit_valid_pad[1]
+hades_hit_valid[0] (PIC/PIO) covers blocks: hades_hit_valid_pad[0]
+hades_hit_out_i[3] (PIC/PIO) covers blocks: hades_hit_out_i_pad[3]
+hades_hit_out_i[2] (PIC/PIO) covers blocks: hades_hit_out_i_pad[2]
+hades_hit_out_i[1] (PIC/PIO) covers blocks: hades_hit_out_i_pad[1]
+hades_hit_out_i[0] (PIC/PIO) covers blocks: hades_hit_out_i_pad[0]
+hades_buf_finished (PIC/PIO) covers blocks: hades_buf_finished_pad
+hades_buf_release (PIC/PIO) covers blocks: hades_buf_release_pad
+hades_buf_out_valid (PIC/PIO) covers blocks: hades_buf_out_valid_pad,
+     hades_tdc_bundle_inst_buf_out_validio
+hades_window_end (PIC/PIO) covers blocks: hades_window_end_pad
+hades_offset_valid (PIC/PIO) covers blocks: hades_offset_valid_pad
+hades_offset[8] (PIC/PIO) covers blocks: hades_offset_pad[8],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8]
+hades_offset[7] (PIC/PIO) covers blocks: hades_offset_pad[7],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7]
+hades_offset[6] (PIC/PIO) covers blocks: hades_offset_pad[6],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]
+hades_offset[5] (PIC/PIO) covers blocks: hades_offset_pad[5],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]
+hades_offset[4] (PIC/PIO) covers blocks: hades_offset_pad[4],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]
+hades_offset[3] (PIC/PIO) covers blocks: hades_offset_pad[3],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]
+hades_offset[2] (PIC/PIO) covers blocks: hades_offset_pad[2],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]
+hades_offset[1] (PIC/PIO) covers blocks: hades_offset_pad[1],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]
+hades_offset[0] (PIC/PIO) covers blocks: hades_offset_pad[0],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]
+hades_lvl1_invalid (PIC/PIO) covers blocks: hades_lvl1_invalid_pad,
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0]
+hades_lvl1 (PIC/PIO) covers blocks: hades_lvl1_pad,
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0]
+hades_raw_valid_vect[1] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[1]
+hades_raw_out_valid (PIC/PIO) covers blocks: hades_raw_out_valid_pad,
+     hades_tdc_bundle_inst_referenced_out_validio
+hades_trig (PIC/PIO) covers blocks: hades_trig_pad
+release_out (PIC/PIO) covers blocks: release_out_pad
+
+                                   Page 38
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+finished (PIC/PIO) covers blocks: finished_pad
+last_buf_empty (PIC/PIO) covers blocks: last_buf_empty_pad
+discard (PIC/PIO) covers blocks: discard_pad
+burst (PIC/PIO) covers blocks: burst_pad
+LVL1_TRG_DATA_VALI_IN_rising (PIC/PIO) covers blocks:
+     LVL1_TRG_DATA_VALI_IN_rising_pad
+FEE_TRG_RELEASE_OUT (PIC/PIO) covers blocks: FEE_TRG_RELEASE_OUT_pad,
+     trb_adapter_inst_FEE_TRG_RELEASE_OUTio
+FEE_DATAFINISHED_OUT (PIC/PIO) covers blocks: FEE_DATAFINISHED_OUT_pad,
+     trb_adapter_inst_FEE_DATAFINISHED_OUTio
+FEE_DATA_WRITE_OUT (PIC/PIO) covers blocks: FEE_DATA_WRITE_OUT_pad,
+     trb_adapter_inst_FEE_DATA_WRITE_OUTio
+FEE_DATA_OUT[31] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[31]
+FEE_DATA_OUT[30] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[30]
+FEE_DATA_OUT[29] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[29]
+FEE_DATA_OUT[28] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[28]
+FEE_DATA_OUT[27] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[27]
+FEE_DATA_OUT[26] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[26]
+FEE_DATA_OUT[25] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[25]
+FEE_DATA_OUT[24] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[24]
+FEE_DATA_OUT[23] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[23]
+FEE_DATA_OUT[22] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[22]
+FEE_DATA_OUT[21] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[21]
+FEE_DATA_OUT[20] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[20]
+FEE_DATA_OUT[19] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[19]
+FEE_DATA_OUT[18] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[18]
+FEE_DATA_OUT[17] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[17]
+FEE_DATA_OUT[16] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[16]
+FEE_DATA_OUT[15] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[15]
+FEE_DATA_OUT[14] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[14]
+FEE_DATA_OUT[13] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[13]
+FEE_DATA_OUT[12] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[12]
+FEE_DATA_OUT[11] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[11]
+FEE_DATA_OUT[10] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[10]
+FEE_DATA_OUT[9] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[9]
+FEE_DATA_OUT[8] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[8]
+FEE_DATA_OUT[7] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[7]
+FEE_DATA_OUT[6] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[6]
+FEE_DATA_OUT[5] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[5]
+FEE_DATA_OUT[4] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[4]
+FEE_DATA_OUT[3] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[3]
+FEE_DATA_OUT[2] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[2]
+FEE_DATA_OUT[1] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[1]
+FEE_DATA_OUT[0] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[0]
+LVL1_INVALID_TRG_IN (PIC/PIO) covers blocks: LVL1_INVALID_TRG_IN_pad,
+     trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0]
+LVL1_TRG_DATA_VALID_IN (PIC/PIO) covers blocks: LVL1_TRG_DATA_VALID_IN_pad,
+     trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0]
+fifo_empty1 (PIC/PIO) covers blocks: fifo_empty1_pad
+fifo_rden (PIC/PIO) covers blocks: fifo_rden_pad
+fifo_data_out[31] (PIC/PIO) covers blocks: fifo_data_out_pad[31]
+fifo_data_out[30] (PIC/PIO) covers blocks: fifo_data_out_pad[30]
+fifo_data_out[29] (PIC/PIO) covers blocks: fifo_data_out_pad[29]
+fifo_data_out[28] (PIC/PIO) covers blocks: fifo_data_out_pad[28]
+fifo_data_out[27] (PIC/PIO) covers blocks: fifo_data_out_pad[27]
+fifo_data_out[26] (PIC/PIO) covers blocks: fifo_data_out_pad[26]
+
+                                   Page 39
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Symbol Cross Reference (cont)
+-----------------------------
+fifo_data_out[25] (PIC/PIO) covers blocks: fifo_data_out_pad[25]
+fifo_data_out[24] (PIC/PIO) covers blocks: fifo_data_out_pad[24]
+fifo_data_out[23] (PIC/PIO) covers blocks: fifo_data_out_pad[23]
+fifo_data_out[22] (PIC/PIO) covers blocks: fifo_data_out_pad[22]
+fifo_data_out[21] (PIC/PIO) covers blocks: fifo_data_out_pad[21]
+fifo_data_out[20] (PIC/PIO) covers blocks: fifo_data_out_pad[20]
+fifo_data_out[19] (PIC/PIO) covers blocks: fifo_data_out_pad[19]
+fifo_data_out[18] (PIC/PIO) covers blocks: fifo_data_out_pad[18]
+fifo_data_out[17] (PIC/PIO) covers blocks: fifo_data_out_pad[17]
+fifo_data_out[16] (PIC/PIO) covers blocks: fifo_data_out_pad[16]
+fifo_data_out[15] (PIC/PIO) covers blocks: fifo_data_out_pad[15]
+fifo_data_out[14] (PIC/PIO) covers blocks: fifo_data_out_pad[14]
+fifo_data_out[13] (PIC/PIO) covers blocks: fifo_data_out_pad[13]
+fifo_data_out[12] (PIC/PIO) covers blocks: fifo_data_out_pad[12]
+fifo_data_out[11] (PIC/PIO) covers blocks: fifo_data_out_pad[11]
+fifo_data_out[10] (PIC/PIO) covers blocks: fifo_data_out_pad[10]
+fifo_data_out[9] (PIC/PIO) covers blocks: fifo_data_out_pad[9]
+fifo_data_out[8] (PIC/PIO) covers blocks: fifo_data_out_pad[8]
+fifo_data_out[7] (PIC/PIO) covers blocks: fifo_data_out_pad[7]
+fifo_data_out[6] (PIC/PIO) covers blocks: fifo_data_out_pad[6]
+fifo_data_out[5] (PIC/PIO) covers blocks: fifo_data_out_pad[5]
+fifo_data_out[4] (PIC/PIO) covers blocks: fifo_data_out_pad[4]
+fifo_data_out[3] (PIC/PIO) covers blocks: fifo_data_out_pad[3]
+fifo_data_out[2] (PIC/PIO) covers blocks: fifo_data_out_pad[2]
+fifo_data_out[1] (PIC/PIO) covers blocks: fifo_data_out_pad[1]
+trig[2] (PIC/PIO) covers blocks: trig_pad[2]
+trig[1] (PIC/PIO) covers blocks: trig_pad[1]
+trig[0] (PIC/PIO) covers blocks: trig_pad[0]
+reset_dc (PIC/PIO) covers blocks: reset_dc_pad, reset_dl_0io[1]
+rd_clk (PIC/PIO) covers blocks: rd_clk_pad
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 (PDPW16KD) covers block:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
+pll0inst/PLLInst_0 (EHXPLLL) covers block: pll0inst/PLLInst_0
+
+
+Signal Cross Reference
+----------------------
+
+Signal FEE_DATA_OUT_c[0] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO18
+   Load Comps: fifo_data_out[0]:I0, FEE_DATA_OUT[0]:I0
+Signal clk_c - Driver Comp: clk:O0
+   Load Comps: pll0inst/PLLInst_0:CLKI
+Signal reset_dl[1] - Driver Comp: reset_dc_MGIOL:O2
+   Load Comps: SLICE_740:I4
+Signal pll_clks[3] - Driver Comp: pll0inst/PLLInst_0:CLKOS3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I15,
+
+                                   Page 40
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_79:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_80:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_81:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_82:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_83:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_103:I15,
+        hades_tdc_bundle_inst/SLICE_121:I15,
+        hades_tdc_bundle_inst/SLICE_122:I15,
+        hades_tdc_bundle_inst/SLICE_123:I15, fifo_colector_inst/SLICE_125:I15,
+        fifo_colector_inst/SLICE_126:I15, fifo_colector_inst/SLICE_127:I15,
+        fifo_colector_inst/SLICE_128:I15, fifo_colector_inst/SLICE_129:I15,
+        fifo_colector_inst/SLICE_130:I15, fifo_colector_inst/SLICE_131:I15,
+        fifo_colector_inst/SLICE_132:I15, fifo_colector_inst/SLICE_133:I15,
+        fifo_colector_inst/SLICE_134:I15, fifo_colector_inst/SLICE_135:I15,
+        fifo_colector_inst/SLICE_136:I15, fifo_colector_inst/SLICE_137:I15,
+        fifo_colector_inst/SLICE_138:I15, fifo_colector_inst/SLICE_139:I15,
+        fifo_colector_inst/SLICE_140:I15, fifo_colector_inst/SLICE_141:I15,
+        fifo_colector_inst/SLICE_142:I15, fifo_colector_inst/SLICE_143:I15,
+        fifo_colector_inst/SLICE_144:I15, fifo_colector_inst/SLICE_145:I15,
+        fifo_colector_inst/SLICE_146:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_152:I15,
+
+                                   Page 41
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/fifo40_inst/SLICE_153:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_154:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_155:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_156:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_157:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_158:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_159:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_160:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_161:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I15,
+        fifo_colector_inst/SLICE_187:I15, fifo_colector_inst/SLICE_189:I15,
+        fifo_colector_inst/SLICE_190:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I15,
+
+                                   Page 42
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I15,
+
+                                   Page 43
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I15,
+
+                                   Page 44
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I15,
+        hades_tdc_bundle_inst/SLICE_432:I15,
+        hades_tdc_bundle_inst/SLICE_433:I15,
+        hades_tdc_bundle_inst/SLICE_434:I15,
+        hades_tdc_bundle_inst/SLICE_435:I15,
+        hades_tdc_bundle_inst/SLICE_436:I15,
+        hades_tdc_bundle_inst/SLICE_437:I15,
+        hades_tdc_bundle_inst/SLICE_438:I15,
+        hades_tdc_bundle_inst/SLICE_439:I15,
+        hades_tdc_bundle_inst/SLICE_440:I15,
+        hades_tdc_bundle_inst/SLICE_441:I15,
+        hades_tdc_bundle_inst/SLICE_442:I15,
+        hades_tdc_bundle_inst/SLICE_443:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I15,
+        hades_tdc_bundle_inst/SLICE_445:I15,
+        hades_tdc_bundle_inst/SLICE_446:I15,
+        hades_tdc_bundle_inst/SLICE_447:I15,
+        hades_tdc_bundle_inst/SLICE_448:I15,
+        hades_tdc_bundle_inst/SLICE_449:I15,
+        hades_tdc_bundle_inst/SLICE_450:I15,
+        hades_tdc_bundle_inst/SLICE_451:I15,
+        hades_tdc_bundle_inst/SLICE_452:I15,
+        hades_tdc_bundle_inst/SLICE_453:I15,
+        hades_tdc_bundle_inst/SLICE_454:I15,
+        hades_tdc_bundle_inst/SLICE_455:I15,
+        hades_tdc_bundle_inst/SLICE_456:I15,
+        hades_tdc_bundle_inst/SLICE_457:I15,
+
+                                   Page 45
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/SLICE_458:I15,
+        hades_tdc_bundle_inst/SLICE_459:I15,
+        hades_tdc_bundle_inst/SLICE_460:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I15,
+
+                                   Page 46
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I15, hade
+        s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:I15,
+         hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544
+        :I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLIC
+        E_545:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_546:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
+        _inst/SLICE_547:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+        t/dec_inst/SLICE_548:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/dec_inst/SLICE_549:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_inst/SLICE_550:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/dec_inst/SLICE_551:I15, hades_tdc_bundle_inst/hades_tdc
+        _channel_raw_out_inst/dec_inst/SLICE_552:I15, hades_tdc_bundle_inst/hade
+        s_tdc_channel_raw_out_inst/dec_inst/SLICE_553:I15, hades_tdc_bundle_inst
+        /hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:I15, hades_tdc_bundle
+        _inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:I15, hades_
+        tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:I15, h
+        ades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:I
+        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
+        ICE_559:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
+        g_inst/SLICE_560:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_neg_inst/SLICE_561:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_562:I15, hades_tdc_bundle_inst/hades_tdc_
+        channel_raw_out_inst/dec_neg_inst/SLICE_563:I15, hades_tdc_bundle_inst/h
+        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564:I15, hades_tdc_bund
+        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565:I15, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566:I
+        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
+        ICE_567:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
+        g_inst/SLICE_568:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_neg_inst/SLICE_569:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_570:I15, hades_tdc_bundle_inst/hades_tdc_
+        channel_raw_out_inst/dec_neg_inst/SLICE_571:I15, hades_tdc_bundle_inst/h
+        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572:I15, hades_tdc_bund
+        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573:I15, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:I15, 
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:
+        I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/S
+        LICE_576:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_n
+        eg_inst/SLICE_577:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_inst/SLICE_591:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_
+        out_inst/tdc_inst/SLICE_595:I15, hades_tdc_bundle_inst/hades_tdc_channel
+        _raw_out_inst/tdc_neg_inst/SLICE_607:I15, hades_tdc_bundle_inst/hades_td
+        c_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I15, hades_tdc_bundle_inst
+        /hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:I15, hades_tdc_bundle
+        _inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_62
+        7:I15, hades_tdc_bundle_inst/SLICE_628:I15,
+
+                                   Page 47
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I15, hades_tdc_bundle_ins
+        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I15,
+        SLICE_740:I15, hades_dbg2_out[28]_MGIOL:I6, hades_dbg2_out[27]_MGIOL:I6,
+        hades_dbg2_out[26]_MGIOL:I6, hades_dbg2_out[25]_MGIOL:I6,
+        hades_dbg2_out[24]_MGIOL:I6, hades_dbg2_out[23]_MGIOL:I6,
+        hades_dbg2_out[22]_MGIOL:I6, hades_dbg2_out[21]_MGIOL:I6,
+        hades_dbg2_out[20]_MGIOL:I6, hades_dbg2_out[18]_MGIOL:I6,
+        hades_dbg2_out[17]_MGIOL:I6, hades_dbg2_out[16]_MGIOL:I6,
+        hades_dbg2_out[2]_MGIOL:I6, hades_dbg2_out[1]_MGIOL:I6,
+        hades_dbg2_out[0]_MGIOL:I6, hades_buf_drop[1]_MGIOL:I6,
+        hades_buf_out_valid_MGIOL:I6, hades_offset[8]_MGIOL:I6,
+        hades_offset[7]_MGIOL:I6, hades_offset[6]_MGIOL:I6,
+        hades_offset[5]_MGIOL:I6, hades_offset[4]_MGIOL:I6,
+        hades_offset[3]_MGIOL:I6, hades_offset[2]_MGIOL:I6,
+        hades_offset[1]_MGIOL:I6, hades_offset[0]_MGIOL:I6,
+        hades_lvl1_invalid_MGIOL:I6, hades_lvl1_MGIOL:I6,
+        hades_raw_out_valid_MGIOL:I6, reset_dc_MGIOL:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKW
+Signal reset_dl[2] - Driver Comp: SLICE_740:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I16,
+        hades_tdc_bundle_inst/SLICE_122:I16,
+        hades_tdc_bundle_inst/SLICE_123:I16,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I16,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I16,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I16,
+        hades_tdc_bundle_inst/SLICE_432:I16,
+        hades_tdc_bundle_inst/SLICE_433:I16,
+        hades_tdc_bundle_inst/SLICE_434:I16,
+        hades_tdc_bundle_inst/SLICE_435:I16,
+        hades_tdc_bundle_inst/SLICE_436:I16,
+        hades_tdc_bundle_inst/SLICE_437:I16,
+        hades_tdc_bundle_inst/SLICE_438:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I16,
+        hades_tdc_bundle_inst/SLICE_456:I14,
+        hades_tdc_bundle_inst/SLICE_457:I14,
+        hades_tdc_bundle_inst/SLICE_458:I14,
+        hades_tdc_bundle_inst/SLICE_459:I14,
+        hades_tdc_bundle_inst/SLICE_460:I14,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I16,
+
+                                   Page 48
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I14,
+        hades_tdc_bundle_inst/SLICE_628:I16, hades_tdc_bundle_inst/SLICE_653:I4,
+        hades_tdc_bundle_inst/SLICE_693:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I16,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I16,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I16, hades_tdc_bundle_ins
+        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I2, hades_tdc_bu
+        ndle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I3,
+        SLICE_740:I1, hades_buf_drop[1]_MGIOL:I9, FEE_TRG_RELEASE_OUT_MGIOL:I9,
+        FEE_DATAFINISHED_OUT_MGIOL:I9, FEE_DATA_WRITE_OUT_MGIOL:I9
+Signal hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_710:O1
+   Load Comps: hades_buf_drop[1]_MGIOL:I10
+Signal hades_buf_drop_c[1] - Driver Comp: hades_buf_drop[1]_MGIOL:O0
+   Load Comps: hades_buf_drop[1]:I1
+Signal hades_tdc_bundle_inst.buf_out12 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_683:O0
+   Load Comps: hades_buf_out_valid_MGIOL:I10
+Signal N_248_i - Driver Comp: hades_tdc_bundle_inst/SLICE_653:O2
+   Load Comps: hades_buf_out_valid_MGIOL:I8
+Signal hades_buf_out_valid_c - Driver Comp: hades_buf_out_valid_MGIOL:O0
+   Load Comps: hades_buf_out_valid:I1
+Signal hades_lvl1_invalid_c - Driver Comp: hades_lvl1_invalid:O0
+   Load Comps: hades_lvl1_invalid_MGIOL:I5
+Signal hades_invalid_dl_c[0] - Driver Comp: hades_lvl1_invalid_MGIOL:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I4,
+        hades_invalid_dl[0]:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I6,
+
+                                   Page 49
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I8,
+
+                                   Page 50
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I2,
+
+                                   Page 51
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O1
+
+                                   Page 52
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I7
+
+                                   Page 53
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I7,
+
+                                   Page 54
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I7,
+
+                                   Page 55
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_128:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_129:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_130:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_131:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_132:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_133:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_138:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_138:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_139:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_139:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_140:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_140:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_141:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_141:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+
+                                   Page 56
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/SLICE_142:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_142:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_143:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_143:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_144:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_144:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_145:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_145:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_126:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_127:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I0,
+
+                                   Page 57
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O3
+
+                                   Page 58
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I5
+
+                                   Page 59
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I7,
+
+                                   Page 60
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O4
+
+                                   Page 61
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+
+                                   Page 62
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I12
+Signal fifo_empty[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I6, fifo_colector_inst/SLICE_680:I2,
+
+                                   Page 63
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I1,
+        fifo_colector_inst/SLICE_722:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I17
+
+                                   Page 64
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I0
+Signal fifo_read[2] - Driver Comp: fifo_colector_inst/SLICE_190:O3
+   Load Comps: fifo_colector_inst/SLICE_190:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I16
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I4
+
+                                   Page 65
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I9
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I4
+
+                                   Page 66
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I4
+Signal trig_c_i[2] - Driver Comp: SLICE_746:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I4
+Signal pll_clks[2] - Driver Comp: pll0inst/PLLInst_0:CLKOS2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I15,
+
+                                   Page 67
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        94:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+        t/SLICE_606:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_610:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_614:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_618:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_622:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:I15
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I4
+Signal pll_clks[1] - Driver Comp: pll0inst/PLLInst_0:CLKOS
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        93:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+
+                                   Page 68
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        t/SLICE_605:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_609:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_613:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_617:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_621:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:I15
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I4
+Signal pll_clks[0] - Driver Comp: pll0inst/PLLInst_0:CLKOP
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        92:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+        t/SLICE_604:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_608:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_612:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_616:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_620:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:I15,
+        pll0inst/PLLInst_0:CLKFB
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O0
+
+                                   Page 69
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+
+                                   Page 70
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+
+                                   Page 71
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+
+                                   Page 72
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I1,
+
+                                   Page 73
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O3
+
+                                   Page 74
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O3
+
+                                   Page 75
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_135:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_135:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_136:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_136:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_137:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_137:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_142:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_142:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_143:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_143:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_144:I1
+
+                                   Page 76
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_144:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_145:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_145:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+   Load Comps: fifo_colector_inst/SLICE_126:I2, fifo_colector_inst/SLICE_126:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_127:I2, fifo_colector_inst/SLICE_127:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_128:I2, fifo_colector_inst/SLICE_128:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_129:I2, fifo_colector_inst/SLICE_129:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_130:I2, fifo_colector_inst/SLICE_130:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_131:I2, fifo_colector_inst/SLICE_131:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_132:I2, fifo_colector_inst/SLICE_132:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_133:I2, fifo_colector_inst/SLICE_133:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_134:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_134:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I1,
+
+                                   Page 77
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+
+                                   Page 78
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+
+                                   Page 79
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I6,
+
+                                   Page 80
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I13
+
+                                   Page 81
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O4
+
+                                   Page 82
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+
+                                   Page 83
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I12
+Signal fifo_empty[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I2, fifo_colector_inst/SLICE_680:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:O6
+
+                                   Page 84
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I0
+Signal fifo_read[1] - Driver Comp: fifo_colector_inst/SLICE_189:O4
+   Load Comps: fifo_colector_inst/SLICE_189:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I16
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I5
+
+                                   Page 85
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I9
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O4
+
+                                   Page 86
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I4
+Signal trig_c_i[1] - Driver Comp: SLICE_745:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I5,
+
+                                   Page 87
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+
+                                   Page 88
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+
+                                   Page 89
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I2,
+
+                                   Page 90
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+
+                                   Page 91
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O3
+
+                                   Page 92
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I14,
+
+                                   Page 93
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I14,
+
+                                   Page 94
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_139:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_139:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_140:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_140:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_141:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_141:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_126:I1, fifo_colector_inst/SLICE_126:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_127:I1, fifo_colector_inst/SLICE_127:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_128:I1, fifo_colector_inst/SLICE_128:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_129:I1, fifo_colector_inst/SLICE_129:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_130:I1, fifo_colector_inst/SLICE_130:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_131:I1, fifo_colector_inst/SLICE_131:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_132:I1, fifo_colector_inst/SLICE_132:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_133:I1, fifo_colector_inst/SLICE_133:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+   Load Comps: fifo_colector_inst/SLICE_134:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+
+                                   Page 95
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_134:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_135:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_135:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_136:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_136:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_137:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_137:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_138:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_138:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+
+                                   Page 96
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I0,
+
+                                   Page 97
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O0
+
+                                   Page 98
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I4
+
+                                   Page 99
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+
+                                   Page 100
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I5
+
+                                   Page 101
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I12
+Signal fifo_empty1_c - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I1, fifo_colector_inst/SLICE_680:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I1,
+        fifo_empty1:I0
+
+                                   Page 102
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:O6
+
+                                   Page 103
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I0
+Signal fifo_read[0] - Driver Comp: fifo_colector_inst/SLICE_189:O3
+   Load Comps: fifo_colector_inst/SLICE_189:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I16
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O4
+
+                                   Page 104
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I9
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O4
+
+                                   Page 105
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I4
+Signal trig_c_i[0] - Driver Comp: SLICE_744:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+
+                                   Page 106
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I12
+Signal fifo_colector_inst/data_buffer_3[31] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O1
+   Load Comps: fifo_colector_inst/SLICE_145:I13
+Signal fifo_colector_inst/in_empty_pmux_i - Driver Comp:
+     fifo_colector_inst/SLICE_125:O2
+   Load Comps: fifo_colector_inst/SLICE_125:I12,
+        fifo_colector_inst/SLICE_126:I14, fifo_colector_inst/SLICE_127:I14,
+        fifo_colector_inst/SLICE_128:I14, fifo_colector_inst/SLICE_129:I14,
+        fifo_colector_inst/SLICE_130:I14, fifo_colector_inst/SLICE_131:I14,
+        fifo_colector_inst/SLICE_132:I14, fifo_colector_inst/SLICE_133:I14,
+        fifo_colector_inst/SLICE_134:I14, fifo_colector_inst/SLICE_135:I14,
+        fifo_colector_inst/SLICE_136:I14, fifo_colector_inst/SLICE_137:I14,
+        fifo_colector_inst/SLICE_138:I14, fifo_colector_inst/SLICE_139:I14,
+        fifo_colector_inst/SLICE_140:I14, fifo_colector_inst/SLICE_141:I14,
+        fifo_colector_inst/SLICE_142:I14, fifo_colector_inst/SLICE_143:I14,
+        fifo_colector_inst/SLICE_144:I14, fifo_colector_inst/SLICE_145:I14,
+        fifo_colector_inst/SLICE_146:I14
+Signal fifo_colector_inst/iterator_RNI7U5I[1] - Driver Comp:
+     fifo_colector_inst/SLICE_722:O0
+   Load Comps: fifo_colector_inst/SLICE_134:I16,
+        fifo_colector_inst/SLICE_135:I16, fifo_colector_inst/SLICE_136:I16,
+        fifo_colector_inst/SLICE_137:I16, fifo_colector_inst/SLICE_138:I16,
+        fifo_colector_inst/SLICE_139:I16, fifo_colector_inst/SLICE_140:I16,
+        fifo_colector_inst/SLICE_141:I16, fifo_colector_inst/SLICE_142:I16,
+
+                                   Page 107
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/SLICE_143:I16, fifo_colector_inst/SLICE_144:I16,
+        fifo_colector_inst/SLICE_145:I16
+Signal fifo_colector_inst/data_buffer[31] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI31
+Signal fifo_colector_inst/data_buffer[0] - Driver Comp:
+     fifo_colector_inst/SLICE_126:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI0
+Signal fifo_colector_inst/data_buffer[1] - Driver Comp:
+     fifo_colector_inst/SLICE_127:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI1
+Signal fifo_colector_inst/data_buffer[2] - Driver Comp:
+     fifo_colector_inst/SLICE_128:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI2
+Signal fifo_colector_inst/data_buffer[3] - Driver Comp:
+     fifo_colector_inst/SLICE_129:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI3
+Signal fifo_colector_inst/data_buffer[4] - Driver Comp:
+     fifo_colector_inst/SLICE_130:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI4
+Signal fifo_colector_inst/data_buffer[5] - Driver Comp:
+     fifo_colector_inst/SLICE_131:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI5
+Signal fifo_colector_inst/data_buffer[6] - Driver Comp:
+     fifo_colector_inst/SLICE_132:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI6
+Signal fifo_colector_inst/data_buffer[7] - Driver Comp:
+     fifo_colector_inst/SLICE_133:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI7
+Signal fifo_colector_inst/data_buffer[8] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI8
+Signal fifo_colector_inst/data_buffer[9] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI9
+Signal fifo_colector_inst/data_buffer[10] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI10
+Signal fifo_colector_inst/data_buffer[11] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI11
+Signal fifo_colector_inst/data_buffer[12] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI12
+Signal fifo_colector_inst/data_buffer[13] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI13
+Signal fifo_colector_inst/data_buffer[14] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI14
+Signal fifo_colector_inst/data_buffer[15] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI15
+Signal fifo_colector_inst/data_buffer[16] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI16
+
+                                   Page 108
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal fifo_colector_inst/data_buffer[17] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI17
+Signal fifo_colector_inst/data_buffer[18] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI18
+Signal fifo_colector_inst/data_buffer[19] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI19
+Signal fifo_colector_inst/data_buffer[20] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI20
+Signal fifo_colector_inst/data_buffer[21] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI21
+Signal fifo_colector_inst/data_buffer[22] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI22
+Signal fifo_colector_inst/data_buffer[23] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI23
+Signal fifo_colector_inst/data_buffer[24] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI24
+Signal fifo_colector_inst/data_buffer[25] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI25
+Signal fifo_colector_inst/data_buffer[26] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI26
+Signal fifo_colector_inst/data_buffer[27] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI27
+Signal fifo_colector_inst/data_buffer[28] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI28
+Signal fifo_colector_inst/data_buffer[29] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI29
+Signal fifo_colector_inst/data_buffer[30] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI30
+Signal fifo_colector_inst/data_buffer[32] - Driver Comp:
+     fifo_colector_inst/SLICE_146:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI32
+Signal fifo_colector_inst/data_buffer[33] - Driver Comp:
+     fifo_colector_inst/SLICE_146:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI33
+Signal fifo_colector_inst/fifo40_inst/wptr_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_182:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW0
+Signal fifo_colector_inst/fifo40_inst/wptr_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_182:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW1
+Signal fifo_colector_inst/fifo40_inst/wptr_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_183:O3
+
+                                   Page 109
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW2
+Signal fifo_colector_inst/fifo40_inst/wptr_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_183:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW3
+Signal fifo_colector_inst/fifo40_inst/wptr_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_184:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW4
+Signal fifo_colector_inst/fifo40_inst/wptr_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_184:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW5
+Signal fifo_colector_inst/fifo40_inst/wptr_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_185:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW6
+Signal fifo_colector_inst/fifo40_inst/wptr_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_185:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW7
+Signal fifo_colector_inst/fifo40_inst/wptr_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_186:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW8
+Signal fifo_colector_inst/fifo40_inst/wren_i - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_721:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_80:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_81:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_82:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_83:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_97:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_97:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I14,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CEW
+Signal fifo_colector_inst/fifo40_inst/rptr_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_162:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR5
+Signal fifo_colector_inst/fifo40_inst/rptr_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_162:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR6
+Signal fifo_colector_inst/fifo40_inst/rptr_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_163:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR7
+Signal fifo_colector_inst/fifo40_inst/rptr_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_163:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR8
+Signal fifo_colector_inst/fifo40_inst/rptr_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_164:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR9
+Signal fifo_colector_inst/fifo40_inst/rptr_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_164:O4
+
+                                   Page 110
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR10
+Signal fifo_colector_inst/fifo40_inst/rptr_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_165:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR11
+Signal fifo_colector_inst/fifo40_inst/rptr_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_165:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR12
+Signal fifo_colector_inst/fifo40_inst/rptr_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_166:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR13
+Signal fifo_colector_inst/fifo40_inst/rden_i - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_720:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_86:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_87:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_88:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_89:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_90:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_90:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I14,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CER,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:OCER
+Signal rd_clk_c - Driver Comp: rd_clk:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_86:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_87:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_88:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_89:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_96:I15,
+        trb_adapter_inst/SLICE_124:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_172:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_173:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_174:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_175:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_176:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_177:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_178:I15,
+
+                                   Page 111
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/fifo40_inst/SLICE_179:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_180:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_181:I15,
+        trb_adapter_inst/SLICE_188:I15, trb_adapter_inst/SLICE_631:I15,
+        trb_adapter_inst/SLICE_632:I15, trb_adapter_inst/SLICE_633:I15,
+        trb_adapter_inst/SLICE_724:I15, FEE_TRG_RELEASE_OUT_MGIOL:I6,
+        FEE_DATAFINISHED_OUT_MGIOL:I6, FEE_DATA_WRITE_OUT_MGIOL:I6,
+        LVL1_INVALID_TRG_IN_MGIOL:I6, LVL1_TRG_DATA_VALID_IN_MGIOL:I6,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKR
+Signal FEE_DATA_OUT_c[18] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO0
+   Load Comps: FEE_DATA_OUT[18]:I0, fifo_data_out[18]:I0
+Signal FEE_DATA_OUT_c[19] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO1
+   Load Comps: FEE_DATA_OUT[19]:I0, fifo_data_out[19]:I0
+Signal FEE_DATA_OUT_c[20] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO2
+   Load Comps: FEE_DATA_OUT[20]:I0, fifo_data_out[20]:I0
+Signal FEE_DATA_OUT_c[21] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO3
+   Load Comps: FEE_DATA_OUT[21]:I0, fifo_data_out[21]:I0
+Signal FEE_DATA_OUT_c[22] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO4
+   Load Comps: FEE_DATA_OUT[22]:I0, fifo_data_out[22]:I0
+Signal FEE_DATA_OUT_c[23] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO5
+   Load Comps: FEE_DATA_OUT[23]:I0, fifo_data_out[23]:I0
+Signal FEE_DATA_OUT_c[24] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO6
+   Load Comps: FEE_DATA_OUT[24]:I0, fifo_data_out[24]:I0
+Signal FEE_DATA_OUT_c[25] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO7
+   Load Comps: FEE_DATA_OUT[25]:I0, fifo_data_out[25]:I0
+Signal FEE_DATA_OUT_c[26] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO8
+   Load Comps: FEE_DATA_OUT[26]:I0, fifo_data_out[26]:I0
+Signal FEE_DATA_OUT_c[27] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO9
+   Load Comps: FEE_DATA_OUT[27]:I0, fifo_data_out[27]:I0
+Signal FEE_DATA_OUT_c[28] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO10
+   Load Comps: FEE_DATA_OUT[28]:I0, fifo_data_out[28]:I0
+Signal FEE_DATA_OUT_c[29] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO11
+   Load Comps: FEE_DATA_OUT[29]:I0, fifo_data_out[29]:I0
+Signal FEE_DATA_OUT_c[30] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO12
+   Load Comps: FEE_DATA_OUT[30]:I0, fifo_data_out[30]:I0
+Signal FEE_DATA_OUT_c[31] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO13
+   Load Comps: FEE_DATA_OUT[31]:I0, fifo_data_out[31]:I0
+Signal FEE_DATA_OUT_c[1] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO19
+   Load Comps: FEE_DATA_OUT[1]:I0, fifo_data_out[1]:I0
+Signal FEE_DATA_OUT_c[2] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO20
+
+                                   Page 112
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: FEE_DATA_OUT[2]:I0, fifo_data_out[2]:I0
+Signal FEE_DATA_OUT_c[3] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO21
+   Load Comps: FEE_DATA_OUT[3]:I0, fifo_data_out[3]:I0
+Signal FEE_DATA_OUT_c[4] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO22
+   Load Comps: FEE_DATA_OUT[4]:I0, fifo_data_out[4]:I0
+Signal FEE_DATA_OUT_c[5] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO23
+   Load Comps: FEE_DATA_OUT[5]:I0, fifo_data_out[5]:I0
+Signal FEE_DATA_OUT_c[6] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO24
+   Load Comps: FEE_DATA_OUT[6]:I0, fifo_data_out[6]:I0
+Signal FEE_DATA_OUT_c[7] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO25
+   Load Comps: FEE_DATA_OUT[7]:I0, fifo_data_out[7]:I0
+Signal FEE_DATA_OUT_c[8] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO26
+   Load Comps: FEE_DATA_OUT[8]:I0, fifo_data_out[8]:I0
+Signal FEE_DATA_OUT_c[9] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO27
+   Load Comps: FEE_DATA_OUT[9]:I0, fifo_data_out[9]:I0
+Signal FEE_DATA_OUT_c[10] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO28
+   Load Comps: FEE_DATA_OUT[10]:I0, fifo_data_out[10]:I0
+Signal FEE_DATA_OUT_c[11] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO29
+   Load Comps: FEE_DATA_OUT[11]:I0, fifo_data_out[11]:I0
+Signal FEE_DATA_OUT_c[12] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO30
+   Load Comps: FEE_DATA_OUT[12]:I0, fifo_data_out[12]:I0
+Signal FEE_DATA_OUT_c[13] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO31
+   Load Comps: FEE_DATA_OUT[13]:I0, fifo_data_out[13]:I0
+Signal FEE_DATA_OUT_c[14] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO32
+   Load Comps: FEE_DATA_OUT[14]:I0, fifo_data_out[14]:I0
+Signal FEE_DATA_OUT_c[15] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO33
+   Load Comps: FEE_DATA_OUT[15]:I0, fifo_data_out[15]:I0
+Signal FEE_DATA_OUT_c[16] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO34
+   Load Comps: FEE_DATA_OUT[16]:I0, fifo_data_out[16]:I0
+Signal FEE_DATA_OUT_c[17] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO35
+   Load Comps: FEE_DATA_OUT[17]:I0, fifo_data_out[17]:I0
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w29 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_161:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I6,
+
+                                   Page 113
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/fifo40_inst/SLICE_703:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I7
+Signal fifo_colector_inst/fifo40_inst/wptr_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_186:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_691:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I8
+Signal fifo_colector_inst/fifo40_inst/full_cmp_clr - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_691:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I7
+Signal fifo_colector_inst/fifo40_inst/full_d - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_103:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I12
+Signal fifo_colector_inst/fifo40_inst/Full - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_103:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I1
+Signal fifo_colector_inst/fifo40_inst/empty_d - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_96:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I12
+Signal last_buf_empty_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_96:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_720:I1, last_buf_empty:I0
+Signal fifo_colector_inst/fifo40_inst/rcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I7
+Signal fifo_colector_inst/fifo40_inst/rptr_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_166:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_692:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I8
+Signal fifo_colector_inst/fifo40_inst/ircount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_91:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r29 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_181:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I0,
+
+                                   Page 114
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/fifo40_inst/SLICE_692:I6
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r28 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_181:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I1
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r27 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_180:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I2
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r26 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_180:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I7
+Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_673:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_673:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I6
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r25 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_179:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I7
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r24 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_179:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I8
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r23 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_178:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I9
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r22 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_178:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I3
+Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_674:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I0
+Signal fifo_colector_inst/fifo40_inst/wcount_r8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_675:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_676:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_675:O1
+
+                                   Page 115
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_676:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I1
+Signal fifo_colector_inst/fifo40_inst/wcount_r3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_702:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_702:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I1
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r21 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_177:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_674:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I7
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r20 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_177:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_673:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w28 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_161:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I7
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w27 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_160:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I2
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w26 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_160:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I7
+Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_677:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I0
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w25 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_159:O4
+
+                                   Page 116
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_649:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w24 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_159:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I2
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w23 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_158:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I3
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w22 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_158:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I3
+Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_678:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_703:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I1
+Signal fifo_colector_inst/fifo40_inst/rcount_w7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_679:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I6
+Signal fifo_colector_inst/fifo40_inst/rcount_w5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_649:O2
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_679:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I1
+Signal fifo_colector_inst/fifo40_inst/rcount_w3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_703:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_648:O2
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w21 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_157:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I6
+Signal fifo_colector_inst/fifo40_inst/rcount_w1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_678:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I7
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w20 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_157:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_677:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I1
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_set - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_692:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I6
+
+                                   Page 117
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_clr - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_692:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I7
+Signal fifo_colector_inst/fifo40_inst/full_cmp_set - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_691:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I6
+Signal fifo_colector_inst/fifo40_inst/iwcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_98:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_98:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_99:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_99:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_100:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_5 - Driver Comp:
+
+                                   Page 118
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/fifo40_inst/SLICE_81:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_100:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_101:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_101:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_102:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I13
+Signal fifo_colector_inst/fifo40_inst/w_gdata_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O0
+
+                                   Page 119
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_171:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_91:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I12
+
+                                   Page 120
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal fifo_colector_inst/fifo40_inst/rcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_92:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_92:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_93:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_93:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_94:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_94:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I6,
+
+                                   Page 121
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/fifo40_inst/SLICE_165:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_95:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I13
+Signal fifo_colector_inst/fifo40_inst/r_gdata_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I4
+
+                                   Page 122
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal fifo_colector_inst/fifo40_inst/r_gdata_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_151:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_172:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_172:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_173:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_173:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_174:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_174:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_175:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_175:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_176:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_176:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_152:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_152:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_153:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_153:O4
+
+                                   Page 123
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_154:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_154:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_155:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_155:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_156:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_156:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I5
+Signal fifo_colector_inst/fifo40_inst/w_gctr_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_78:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I17
+Signal fifo_colector_inst/fifo40_inst/co0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I17
+Signal fifo_colector_inst/fifo40_inst/co1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I17
+Signal fifo_colector_inst/fifo40_inst/co2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I17
+Signal fifo_colector_inst/fifo40_inst/co3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I17
+Signal fifo_colector_inst/fifo40_inst/r_gctr_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_84:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I17
+Signal fifo_colector_inst/fifo40_inst/co0_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I17
+Signal fifo_colector_inst/fifo40_inst/co1_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I17
+Signal fifo_colector_inst/fifo40_inst/co2_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I17
+Signal fifo_colector_inst/fifo40_inst/co3_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I17
+Signal fifo_colector_inst/fifo40_inst/cmp_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_90:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I17
+Signal fifo_colector_inst/fifo40_inst/co0_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_91:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I17
+Signal fifo_colector_inst/fifo40_inst/co1_2 - Driver Comp:
+
+                                   Page 124
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/fifo40_inst/SLICE_92:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I17
+Signal fifo_colector_inst/fifo40_inst/co2_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_93:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I17
+Signal fifo_colector_inst/fifo40_inst/co3_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_94:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I17
+Signal fifo_colector_inst/fifo40_inst/empty_d_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_95:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I17
+Signal fifo_colector_inst/fifo40_inst/cmp_ci_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_97:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I17
+Signal fifo_colector_inst/fifo40_inst/co0_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_98:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I17
+Signal fifo_colector_inst/fifo40_inst/co1_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_99:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I17
+Signal fifo_colector_inst/fifo40_inst/co2_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_100:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I17
+Signal fifo_colector_inst/fifo40_inst/co3_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_101:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I17
+Signal fifo_colector_inst/fifo40_inst/full_d_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_102:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I17
+Signal fifo_rden_c - Driver Comp: trb_adapter_inst/SLICE_188:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I1, trb_adapter_inst/SLICE_632:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_720:I0,
+        trb_adapter_inst/SLICE_724:I16, FEE_DATA_WRITE_OUT_MGIOL:I10,
+        fifo_rden:I0
+Signal fifo_colector_inst/buffer_wr_enable - Driver Comp:
+     fifo_colector_inst/SLICE_125:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I0
+Signal fifo_colector_inst/iterator[1] - Driver Comp:
+     fifo_colector_inst/SLICE_187:O4
+   Load Comps: fifo_colector_inst/SLICE_125:I4, fifo_colector_inst/SLICE_126:I3,
+        fifo_colector_inst/SLICE_126:I9, fifo_colector_inst/SLICE_127:I3,
+        fifo_colector_inst/SLICE_127:I9, fifo_colector_inst/SLICE_128:I3,
+        fifo_colector_inst/SLICE_128:I9, fifo_colector_inst/SLICE_129:I3,
+        fifo_colector_inst/SLICE_129:I9, fifo_colector_inst/SLICE_130:I3,
+        fifo_colector_inst/SLICE_130:I9, fifo_colector_inst/SLICE_131:I3,
+        fifo_colector_inst/SLICE_131:I9, fifo_colector_inst/SLICE_132:I3,
+        fifo_colector_inst/SLICE_132:I9, fifo_colector_inst/SLICE_133:I3,
+        fifo_colector_inst/SLICE_133:I9, fifo_colector_inst/SLICE_146:I5,
+        fifo_colector_inst/SLICE_187:I1, fifo_colector_inst/SLICE_189:I1,
+        fifo_colector_inst/SLICE_190:I0, fifo_colector_inst/SLICE_680:I1,
+        fifo_colector_inst/SLICE_722:I0
+Signal fifo_colector_inst/iterator[0] - Driver Comp:
+     fifo_colector_inst/SLICE_187:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I0, fifo_colector_inst/SLICE_126:I0,
+        fifo_colector_inst/SLICE_126:I6, fifo_colector_inst/SLICE_127:I0,
+        fifo_colector_inst/SLICE_127:I6, fifo_colector_inst/SLICE_128:I0,
+
+                                   Page 125
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        fifo_colector_inst/SLICE_128:I6, fifo_colector_inst/SLICE_129:I0,
+        fifo_colector_inst/SLICE_129:I6, fifo_colector_inst/SLICE_130:I0,
+        fifo_colector_inst/SLICE_130:I6, fifo_colector_inst/SLICE_131:I0,
+        fifo_colector_inst/SLICE_131:I6, fifo_colector_inst/SLICE_132:I0,
+        fifo_colector_inst/SLICE_132:I6, fifo_colector_inst/SLICE_133:I0,
+        fifo_colector_inst/SLICE_133:I6, fifo_colector_inst/SLICE_134:I0,
+        fifo_colector_inst/SLICE_134:I6, fifo_colector_inst/SLICE_135:I0,
+        fifo_colector_inst/SLICE_135:I6, fifo_colector_inst/SLICE_136:I0,
+        fifo_colector_inst/SLICE_136:I6, fifo_colector_inst/SLICE_137:I0,
+        fifo_colector_inst/SLICE_137:I6, fifo_colector_inst/SLICE_138:I0,
+        fifo_colector_inst/SLICE_138:I6, fifo_colector_inst/SLICE_139:I0,
+        fifo_colector_inst/SLICE_139:I6, fifo_colector_inst/SLICE_140:I0,
+        fifo_colector_inst/SLICE_140:I6, fifo_colector_inst/SLICE_141:I0,
+        fifo_colector_inst/SLICE_141:I6, fifo_colector_inst/SLICE_142:I0,
+        fifo_colector_inst/SLICE_142:I6, fifo_colector_inst/SLICE_143:I0,
+        fifo_colector_inst/SLICE_143:I6, fifo_colector_inst/SLICE_144:I0,
+        fifo_colector_inst/SLICE_144:I6, fifo_colector_inst/SLICE_145:I0,
+        fifo_colector_inst/SLICE_145:I6, fifo_colector_inst/SLICE_146:I4,
+        fifo_colector_inst/SLICE_187:I0, fifo_colector_inst/SLICE_187:I5,
+        fifo_colector_inst/SLICE_189:I2, fifo_colector_inst/SLICE_189:I6,
+        fifo_colector_inst/SLICE_680:I6
+Signal fifo_colector_inst/fb_0 - Driver Comp: fifo_colector_inst/SLICE_189:O0
+   Load Comps: fifo_colector_inst/SLICE_189:I12
+Signal fifo_colector_inst/in_empty_pmux_0 - Driver Comp:
+     fifo_colector_inst/SLICE_680:O1
+   Load Comps: fifo_colector_inst/SLICE_680:I0
+Signal fifo_colector_inst/fb_0_0 - Driver Comp: fifo_colector_inst/SLICE_190:O0
+   Load Comps: fifo_colector_inst/SLICE_190:I12
+Signal fifo_colector_inst/fb_0_1 - Driver Comp: fifo_colector_inst/SLICE_189:O1
+   Load Comps: fifo_colector_inst/SLICE_189:I13
+Signal fifo_colector_inst/un5_in_read_enable - Driver Comp:
+     fifo_colector_inst/SLICE_187:O0
+   Load Comps: fifo_colector_inst/SLICE_187:I12
+Signal fifo_colector_inst/in_empty_pmux - Driver Comp:
+     fifo_colector_inst/SLICE_680:O0
+   Load Comps: fifo_colector_inst/SLICE_189:I16,
+        fifo_colector_inst/SLICE_190:I16
+Signal fifo_colector_inst/data_buffer_3[0] - Driver Comp:
+     fifo_colector_inst/SLICE_126:O2
+   Load Comps: fifo_colector_inst/SLICE_126:I12
+Signal fifo_colector_inst/data_buffer_3[1] - Driver Comp:
+     fifo_colector_inst/SLICE_127:O2
+   Load Comps: fifo_colector_inst/SLICE_127:I12
+Signal fifo_colector_inst/data_buffer_3[2] - Driver Comp:
+     fifo_colector_inst/SLICE_128:O2
+   Load Comps: fifo_colector_inst/SLICE_128:I12
+Signal fifo_colector_inst/data_buffer_3[3] - Driver Comp:
+     fifo_colector_inst/SLICE_129:O2
+   Load Comps: fifo_colector_inst/SLICE_129:I12
+Signal fifo_colector_inst/data_buffer_3[4] - Driver Comp:
+     fifo_colector_inst/SLICE_130:O2
+   Load Comps: fifo_colector_inst/SLICE_130:I12
+Signal fifo_colector_inst/data_buffer_3[5] - Driver Comp:
+     fifo_colector_inst/SLICE_131:O2
+   Load Comps: fifo_colector_inst/SLICE_131:I12
+Signal fifo_colector_inst/data_buffer_3[6] - Driver Comp:
+
+                                   Page 126
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     fifo_colector_inst/SLICE_132:O2
+   Load Comps: fifo_colector_inst/SLICE_132:I12
+Signal fifo_colector_inst/data_buffer_3[7] - Driver Comp:
+     fifo_colector_inst/SLICE_133:O2
+   Load Comps: fifo_colector_inst/SLICE_133:I12
+Signal fifo_colector_inst/data_buffer_3[8] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O0
+   Load Comps: fifo_colector_inst/SLICE_134:I12
+Signal fifo_colector_inst/data_buffer_3[9] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O1
+   Load Comps: fifo_colector_inst/SLICE_134:I13
+Signal fifo_colector_inst/data_buffer_3[10] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O0
+   Load Comps: fifo_colector_inst/SLICE_135:I12
+Signal fifo_colector_inst/data_buffer_3[11] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O1
+   Load Comps: fifo_colector_inst/SLICE_135:I13
+Signal fifo_colector_inst/data_buffer_3[12] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O0
+   Load Comps: fifo_colector_inst/SLICE_136:I12
+Signal fifo_colector_inst/data_buffer_3[13] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O1
+   Load Comps: fifo_colector_inst/SLICE_136:I13
+Signal fifo_colector_inst/data_buffer_3[14] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O0
+   Load Comps: fifo_colector_inst/SLICE_137:I12
+Signal fifo_colector_inst/data_buffer_3[15] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O1
+   Load Comps: fifo_colector_inst/SLICE_137:I13
+Signal fifo_colector_inst/data_buffer_3[16] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O0
+   Load Comps: fifo_colector_inst/SLICE_138:I12
+Signal fifo_colector_inst/data_buffer_3[17] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O1
+   Load Comps: fifo_colector_inst/SLICE_138:I13
+Signal fifo_colector_inst/data_buffer_3[18] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O0
+   Load Comps: fifo_colector_inst/SLICE_139:I12
+Signal fifo_colector_inst/data_buffer_3[19] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O1
+   Load Comps: fifo_colector_inst/SLICE_139:I13
+Signal fifo_colector_inst/data_buffer_3[20] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O0
+   Load Comps: fifo_colector_inst/SLICE_140:I12
+Signal fifo_colector_inst/data_buffer_3[21] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O1
+   Load Comps: fifo_colector_inst/SLICE_140:I13
+Signal fifo_colector_inst/data_buffer_3[22] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O0
+   Load Comps: fifo_colector_inst/SLICE_141:I12
+Signal fifo_colector_inst/data_buffer_3[23] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O1
+   Load Comps: fifo_colector_inst/SLICE_141:I13
+Signal fifo_colector_inst/data_buffer_3[24] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O0
+   Load Comps: fifo_colector_inst/SLICE_142:I12
+
+                                   Page 127
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal fifo_colector_inst/data_buffer_3[25] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O1
+   Load Comps: fifo_colector_inst/SLICE_142:I13
+Signal fifo_colector_inst/data_buffer_3[26] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O0
+   Load Comps: fifo_colector_inst/SLICE_143:I12
+Signal fifo_colector_inst/data_buffer_3[27] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O1
+   Load Comps: fifo_colector_inst/SLICE_143:I13
+Signal fifo_colector_inst/data_buffer_3[28] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O0
+   Load Comps: fifo_colector_inst/SLICE_144:I12
+Signal fifo_colector_inst/data_buffer_3[29] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O1
+   Load Comps: fifo_colector_inst/SLICE_144:I13
+Signal fifo_colector_inst/data_buffer_3[30] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O0
+   Load Comps: fifo_colector_inst/SLICE_145:I12
+Signal finished_c - Driver Comp: trb_adapter_inst/SLICE_724:O3
+   Load Comps: trb_adapter_inst/SLICE_633:I4, trb_adapter_inst/SLICE_724:I0,
+        finished:I0, FEE_DATAFINISHED_OUT_MGIOL:I10
+Signal trb_adapter_inst/finished_prev - Driver Comp:
+     trb_adapter_inst/SLICE_633:O3
+   Load Comps: trb_adapter_inst/SLICE_724:I1
+Signal trb_adapter_inst/buf_rden_prev - Driver Comp:
+     trb_adapter_inst/SLICE_632:O3
+   Load Comps: trb_adapter_inst/SLICE_724:I4
+Signal trb_adapter_inst/buf_rden4 - Driver Comp: trb_adapter_inst/SLICE_188:O0
+   Load Comps: trb_adapter_inst/SLICE_188:I12
+Signal trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - Driver Comp:
+     LVL1_TRG_DATA_VALID_IN_MGIOL:O2
+   Load Comps: trb_adapter_inst/SLICE_631:I4
+Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - Driver Comp:
+     trb_adapter_inst/SLICE_631:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I8, trb_adapter_inst/SLICE_631:I5,
+        trb_adapter_inst/SLICE_723:I0
+Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - Driver Comp:
+     trb_adapter_inst/SLICE_631:O4
+   Load Comps: trb_adapter_inst/SLICE_188:I7, trb_adapter_inst/SLICE_723:I1
+Signal trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - Driver Comp:
+     LVL1_INVALID_TRG_IN_MGIOL:O2
+   Load Comps: trb_adapter_inst/SLICE_124:I4
+Signal discard_c - Driver Comp: trb_adapter_inst/SLICE_124:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I6, discard:I0
+Signal burst_c - Driver Comp: trb_adapter_inst/SLICE_188:O1
+   Load Comps: trb_adapter_inst/SLICE_188:I0, burst:I0
+Signal LVL1_TRG_DATA_VALI_IN_rising_c - Driver Comp:
+     trb_adapter_inst/SLICE_723:O0
+   Load Comps: LVL1_TRG_DATA_VALI_IN_rising:I0
+Signal release_out_c - Driver Comp: trb_adapter_inst/SLICE_724:O0
+   Load Comps: release_out:I0, FEE_TRG_RELEASE_OUT_MGIOL:I10
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_120:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_104:I17
+Signal hades_tdc_bundle_inst/hit_valid25 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_104:O0
+
+                                   Page 128
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I2,
+        hades_tdc_bundle_inst/SLICE_458:I1, hades_tdc_bundle_inst/SLICE_458:I7,
+        hades_tdc_bundle_inst/SLICE_710:I7
+Signal hades_tdc_bundle_inst/buf_finished5 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_432:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_432:I12
+Signal hades_buf_finished_c - Driver Comp: hades_tdc_bundle_inst/SLICE_432:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_433:I4, hades_buf_finished:I0
+Signal hades_dbg2_out_c[12] - Driver Comp: hades_tdc_bundle_inst/SLICE_443:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_449:I4, hades_dbg2_out[12]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - Driver Comp: SLICE_740:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I14,
+        hades_tdc_bundle_inst/SLICE_446:I14,
+        hades_tdc_bundle_inst/SLICE_447:I14,
+        hades_tdc_bundle_inst/SLICE_448:I14,
+        hades_tdc_bundle_inst/SLICE_449:I14,
+        hades_tdc_bundle_inst/SLICE_450:I14,
+        hades_tdc_bundle_inst/SLICE_451:I14,
+        hades_tdc_bundle_inst/SLICE_452:I14,
+        hades_tdc_bundle_inst/SLICE_453:I14,
+        hades_tdc_bundle_inst/SLICE_454:I14, hades_tdc_bundle_inst/SLICE_455:I14
+        
+Signal hades_drop_cmp_buf_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_449:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I8, hades_drop_cmp_buf[8]:I0
+Signal hades_tdc_bundle_inst/hades_raw_out_valid - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I0,
+        hades_tdc_bundle_inst/SLICE_459:I6, hades_tdc_bundle_inst/SLICE_460:I6,
+        hades_tdc_bundle_inst/SLICE_628:I0, hades_tdc_bundle_inst/SLICE_628:I8,
+        hades_tdc_bundle_inst/SLICE_693:I1, hades_tdc_bundle_inst/SLICE_693:I8
+Signal hades_tdc_bundle_inst/hit_i[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I1,
+        hades_tdc_bundle_inst/SLICE_459:I7, hades_tdc_bundle_inst/SLICE_460:I7,
+        hades_tdc_bundle_inst/SLICE_628:I1, hades_tdc_bundle_inst/SLICE_628:I7,
+        hades_tdc_bundle_inst/SLICE_693:I2, hades_tdc_bundle_inst/SLICE_693:I7
+Signal hades_tdc_bundle_inst/hit_i[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I4,
+        hades_tdc_bundle_inst/SLICE_459:I4, hades_tdc_bundle_inst/SLICE_460:I4,
+        hades_tdc_bundle_inst/SLICE_628:I6, hades_tdc_bundle_inst/SLICE_693:I3,
+        hades_tdc_bundle_inst/SLICE_693:I6
+Signal un1_hit_i_2_0_a2 - Driver Comp: hades_tdc_bundle_inst/SLICE_693:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I14,
+        hades_tdc_bundle_inst/SLICE_440:I14,
+        hades_tdc_bundle_inst/SLICE_441:I14,
+        hades_tdc_bundle_inst/SLICE_442:I14,
+        hades_tdc_bundle_inst/SLICE_443:I14, hades_dbg2_out[28]_MGIOL:I8,
+        hades_dbg2_out[27]_MGIOL:I8, hades_dbg2_out[26]_MGIOL:I8,
+        hades_dbg2_out[25]_MGIOL:I8, hades_dbg2_out[24]_MGIOL:I8,
+        hades_dbg2_out[23]_MGIOL:I8, hades_dbg2_out[22]_MGIOL:I8,
+        hades_dbg2_out[21]_MGIOL:I8, hades_dbg2_out[20]_MGIOL:I8,
+        hades_dbg2_out[18]_MGIOL:I8, hades_dbg2_out[17]_MGIOL:I8,
+        hades_dbg2_out[16]_MGIOL:I8, hades_dbg2_out[2]_MGIOL:I8,
+        hades_dbg2_out[1]_MGIOL:I8, hades_dbg2_out[0]_MGIOL:I8
+
+                                   Page 129
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/dec_neg_inst/SLICE_573:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_573:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed7_rising_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out
+     _inst/dec_neg_inst/SLICE_726:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
+        _neg_inst/SLICE_572:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out
+        _inst/dec_neg_inst/SLICE_573:I16
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_i
+     nternal - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst
+     /dec_neg_inst/SLICE_573:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_725:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_725:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I2, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
+        1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+     t/dec_neg_inst/SLICE_571:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_576:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_576:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_571:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+     t/dec_neg_inst/SLICE_571:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_576:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_576:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I5
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_571:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I13
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+
+                                   Page 130
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     t/dec_neg_inst/SLICE_572:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_577:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_577:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_572:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I12
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_563:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_567:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_567:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_728:I0
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_563:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_567:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_567:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I6, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_728:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_564:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_568:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_568:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I0, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_694:I7, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I0
+Signal
+
+                                   Page 131
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_564:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_568:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_568:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_694:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I8, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I0, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_565:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_569:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_569:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_694:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I9, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I1, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I2
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_565:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_569:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_569:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_572:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I3, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I2, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I3, hades_tdc_bundle_inst/had
+        es_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729:I2
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_566:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_570:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_570:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+
+                                   Page 132
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        neg_inst/SLICE_727:I3
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_566:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_570:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_726:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_570:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_726:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_559:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_563:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_559:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_563:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_560:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_564:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_560:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_564:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_561:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_565:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_561:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_565:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_562:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_566:I4
+Signal
+
+                                   Page 133
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_562:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_566:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_620:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_559:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_621:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_559:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_622:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_560:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_623:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_560:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_624:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_561:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_625:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_561:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_626:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_562:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_627:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_562:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_r
+     aw_out_inst/dec_neg_inst/SLICE_694:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_0_0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_ra
+     w_out_inst/dec_neg_inst/SLICE_727:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_573:I4
+
+                                   Page 134
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_729:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal31_1_i_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel
+     _raw_out_inst/dec_neg_inst/SLICE_572:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_571:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_572:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_728:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I1, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
+        0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLI
+     CE_725:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I14
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
+     _0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+     neg_inst/SLICE_694:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal35_1_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_
+     rising_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+        t/SLICE_556:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/de
+        c_inst/SLICE_557:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_inst/SLICE_558:I16
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_inter
+
+                                   Page 135
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     nal - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_731:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I2, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_574:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_574:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I5
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_575:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal31_1_i_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_557:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] -
+
+                                   Page 136
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_551:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_558:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_696:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_696:I6
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_551:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_695:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_696:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_696:I7
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_552:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_558:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_695:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/dec_inst/SLICE_696:I2, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_inst/SLICE_696:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_552:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_557:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+
+                                   Page 137
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        inst/SLICE_695:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_732:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_553:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_557:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_695:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_732:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_553:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_557:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_696:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/dec_inst/SLICE_732:I2
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_554:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_557:I4, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_732:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_554:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_730:I0
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+
+                                   Page 138
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_730:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_547:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_547:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_548:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_548:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_549:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_549:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_550:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_550:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_543:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_543:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - Driver
+     Comp:
+
+                                   Page 139
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_544:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_544:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_545:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_545:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_546:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_546:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_557:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_558:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal35_1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I14,
+
+                                   Page 140
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I14
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I2
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_607:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_607:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_607:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_623:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_611:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_627:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_611:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_611:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_606:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_606:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_606:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_622:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_610:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_626:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_610:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_610:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_605:O3
+
+                                   Page 141
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_621:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_605:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_605:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_609:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_625:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_609:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_609:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_604:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_620:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_604:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_604:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_608:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_624:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_608:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_608:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_591:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_615:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_619:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+
+                                   Page 142
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        CE_595:I4
+Signal hades_trig_c_i - Driver Comp: SLICE_747:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_588:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst
+        /SLICE_589:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
+        inst/SLICE_590:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        tdc_inst/SLICE_591:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_inst/SLICE_592:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/tdc_inst/SLICE_593:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_594:I5, hades_tdc_bundle_inst/hades_tdc_chann
+        el_raw_out_inst/tdc_inst/SLICE_595:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_614:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_590:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_594:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_618:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_589:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_613:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_617:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_593:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_588:I4
+
+                                   Page 143
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_612:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_592:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_616:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I0
+Signal hades_dbg2_coarse_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I2,
+        hades_tdc_bundle_inst/SLICE_435:I7, hades_tdc_bundle_inst/SLICE_438:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I5,
+        hades_tdc_bundle_inst/SLICE_681:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I7,
+        hades_dbg2_coarse[2]:I0, hades_offset[5]_MGIOL:I10
+Signal hades_dbg2_coarse_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I9,
+        hades_tdc_bundle_inst/SLICE_434:I7, hades_tdc_bundle_inst/SLICE_435:I1,
+        hades_tdc_bundle_inst/SLICE_435:I8, hades_tdc_bundle_inst/SLICE_438:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I4,
+        hades_tdc_bundle_inst/SLICE_681:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I8,
+        hades_dbg2_coarse[1]:I0, hades_offset[4]_MGIOL:I10
+Signal hades_dbg2_coarse_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I8,
+        hades_tdc_bundle_inst/SLICE_434:I0, hades_tdc_bundle_inst/SLICE_434:I6,
+        hades_tdc_bundle_inst/SLICE_435:I0, hades_tdc_bundle_inst/SLICE_435:I9,
+        hades_tdc_bundle_inst/SLICE_438:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I5,
+        hades_tdc_bundle_inst/SLICE_681:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I9,
+        hades_dbg2_coarse[0]:I0, hades_offset[3]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19
+
+                                   Page 144
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I0
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I6
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
+     _19 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I0
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O3
+   Load Comps: hades_dbg2_out[0]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O4
+   Load Comps: hades_dbg2_out[1]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O3
+   Load Comps: hades_dbg2_out[2]_MGIOL:I10
+
+                                   Page 145
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I4
+Signal hades_tdc_bundle_inst/hades_raw_out[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_440:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_440:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I4,
+        hades_tdc_bundle_inst/SLICE_681:I3
+Signal hades_tdc_bundle_inst/hades_raw_out[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_441:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[8] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_441:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I4
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[9] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_442:I4
+
+                                   Page 146
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I5
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[10] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_442:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I4
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[11] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_443:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[12] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O4
+   Load Comps: hades_dbg2_out[16]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[13] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O3
+   Load Comps: hades_dbg2_out[17]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[14] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O4
+   Load Comps: hades_dbg2_out[18]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I4
+Signal hades_tdc_bundle_inst.hades_raw_out[15] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O3
+   Load Comps: hades_dbg2_out[20]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[16] - Driver Comp:
+
+                                   Page 147
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O4
+   Load Comps: hades_dbg2_out[21]_MGIOL:I10
+Signal hades_tdc_bundle_inst.hades_raw_out[17] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O3
+   Load Comps: hades_dbg2_out[22]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[18] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O4
+   Load Comps: hades_dbg2_out[23]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I4,
+        hades_tdc_bundle_inst/SLICE_698:I3
+Signal hades_tdc_bundle_inst.hades_raw_out[19] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O3
+   Load Comps: hades_dbg2_out[24]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[20] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O4
+   Load Comps: hades_dbg2_out[25]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[21] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O3
+   Load Comps: hades_dbg2_out[26]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[22] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O4
+   Load Comps: hades_dbg2_out[27]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[23] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:O3
+   Load Comps: hades_dbg2_out[28]_MGIOL:I10
+
+                                   Page 148
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I12
+Signal hades_dbg2_coarse_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I3,
+        hades_tdc_bundle_inst/SLICE_435:I6, hades_tdc_bundle_inst/SLICE_436:I0,
+        hades_tdc_bundle_inst/SLICE_436:I6, hades_tdc_bundle_inst/SLICE_437:I0,
+        hades_tdc_bundle_inst/SLICE_438:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I4,
+        hades_tdc_bundle_inst/SLICE_681:I0, hades_tdc_bundle_inst/SLICE_698:I0,
+        hades_tdc_bundle_inst/SLICE_698:I6, hades_dbg2_coarse[3]:I0,
+        hades_offset[6]_MGIOL:I10
+Signal hades_dbg2_coarse_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I1,
+        hades_tdc_bundle_inst/SLICE_436:I7, hades_tdc_bundle_inst/SLICE_455:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I5,
+        hades_tdc_bundle_inst/SLICE_681:I1, hades_tdc_bundle_inst/SLICE_698:I1,
+        hades_tdc_bundle_inst/SLICE_698:I7, hades_tdc_bundle_inst/SLICE_701:I6,
+        hades_dbg2_coarse[4]:I0, hades_offset[7]_MGIOL:I10
+Signal hades_dbg2_coarse_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I9,
+        hades_tdc_bundle_inst/SLICE_436:I8, hades_tdc_bundle_inst/SLICE_455:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I4,
+        hades_tdc_bundle_inst/SLICE_701:I7, hades_dbg2_coarse[5]:I0,
+        hades_offset[8]_MGIOL:I10
+Signal hades_dbg2_coarse_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I0,
+        hades_tdc_bundle_inst/SLICE_437:I1, hades_tdc_bundle_inst/SLICE_437:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I5,
+        hades_tdc_bundle_inst/SLICE_701:I0, hades_dbg2_coarse[6]:I0
+Signal hades_dbg2_coarse_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I1,
+        hades_tdc_bundle_inst/SLICE_437:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I4,
+        hades_tdc_bundle_inst/SLICE_701:I1, hades_dbg2_coarse[7]:I0
+Signal hades_dbg2_coarse_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_438:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I6,
+        hades_tdc_bundle_inst/SLICE_438:I0, hades_tdc_bundle_inst/SLICE_455:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I5,
+
+                                   Page 149
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_dbg2_coarse[8]:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_681:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I2,
+        hades_tdc_bundle_inst/SLICE_436:I2, hades_tdc_bundle_inst/SLICE_436:I9,
+        hades_tdc_bundle_inst/SLICE_437:I3, hades_tdc_bundle_inst/SLICE_681:I2,
+        hades_tdc_bundle_inst/SLICE_698:I2, hades_tdc_bundle_inst/SLICE_698:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
+     _14 - Driver Comp: hades_tdc_bundle_inst/SLICE_681:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I6
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14
+     - Driver Comp: hades_tdc_bundle_inst/SLICE_698:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I6
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I3
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I3
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
+     tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_698:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
+     tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_701:O1
+
+                                   Page 150
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I8,
+        hades_tdc_bundle_inst/SLICE_437:I2, hades_tdc_bundle_inst/SLICE_437:I8,
+        hades_tdc_bundle_inst/SLICE_438:I1
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_438:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I9,
+        hades_tdc_bundle_inst/SLICE_437:I9, hades_tdc_bundle_inst/SLICE_438:I3,
+        hades_tdc_bundle_inst/SLICE_455:I4
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_701:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I7,
+        hades_tdc_bundle_inst/SLICE_438:I2, hades_tdc_bundle_inst/SLICE_455:I9
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     cry - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
+     ata_tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
+     ata_tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_cry - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I12,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I16
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I16
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I0,
+
+                                   Page 151
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I6
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I14,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I1,
+        hades_offset[8]_MGIOL:I8, hades_offset[7]_MGIOL:I8,
+        hades_offset[6]_MGIOL:I8, hades_offset[5]_MGIOL:I8,
+        hades_offset[4]_MGIOL:I8, hades_offset[3]_MGIOL:I8,
+        hades_offset[2]_MGIOL:I8, hades_offset[1]_MGIOL:I8,
+        hades_offset[0]_MGIOL:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I2
+Signal hades_discard_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_123:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I0,
+        hades_tdc_bundle_inst/SLICE_741:I0, hades_discard:I0
+Signal valid_fast_RNI999V - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:O0
+   Load Comps: hades_offset[8]_MGIOL:I9, hades_offset[7]_MGIOL:I9,
+        hades_offset[6]_MGIOL:I9, hades_offset[5]_MGIOL:I9,
+        hades_offset[4]_MGIOL:I9, hades_offset[3]_MGIOL:I9,
+        hades_offset[2]_MGIOL:I9, hades_offset[1]_MGIOL:I9,
+        hades_offset[0]_MGIOL:I9
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
+     _1_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I12
+Signal
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I16
+
+                                   Page 152
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I4
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O3
+   Load Comps: hades_offset[0]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I5
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O4
+   Load Comps: hades_offset[1]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31
+     _1_i_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I4
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:O3
+   Load Comps: hades_offset[2]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O3
+   Load Comps:
+
+                                   Page 153
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I6
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I7
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O3
+
+                                   Page 154
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O4
+
+                                   Page 155
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O1
+
+                                   Page 156
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
+     _1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] -
+
+                                   Page 157
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I4
+Signal hades_lvl1_c_i - Driver Comp: SLICE_743:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] -
+     Driver Comp:
+
+                                   Page 158
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I2
+Signal hades_invalid_dl_c[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I1,
+        hades_invalid_dl[3]:I0
+Signal hades_invalid_dl_c[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I0,
+        hades_invalid_dl[2]:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - Driver
+
+                                   Page 159
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I12
+Signal hades_tdc_bundle_inst/SUM1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_628:I13
+Signal ANB3 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I7,
+        hades_tdc_bundle_inst/SLICE_122:I6, hades_tdc_bundle_inst/SLICE_123:I1,
+        hades_tdc_bundle_inst/SLICE_432:I2, hades_tdc_bundle_inst/SLICE_432:I7,
+        hades_tdc_bundle_inst/SLICE_653:I1, hades_tdc_bundle_inst/SLICE_654:I8,
+        hades_tdc_bundle_inst/SLICE_683:I7, hades_hit_out_i[3]:I0
+Signal ANB2 - Driver Comp: hades_tdc_bundle_inst/SLICE_123:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I9,
+        hades_tdc_bundle_inst/SLICE_122:I7, hades_tdc_bundle_inst/SLICE_123:I3,
+        hades_tdc_bundle_inst/SLICE_123:I7, hades_tdc_bundle_inst/SLICE_432:I0,
+        hades_tdc_bundle_inst/SLICE_653:I3, hades_tdc_bundle_inst/SLICE_654:I0,
+        hades_tdc_bundle_inst/SLICE_654:I7, hades_hit_out_i[2]:I0
+Signal ANB1 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I6,
+        hades_tdc_bundle_inst/SLICE_122:I1, hades_tdc_bundle_inst/SLICE_122:I8,
+        hades_tdc_bundle_inst/SLICE_123:I2, hades_tdc_bundle_inst/SLICE_123:I6,
+        hades_tdc_bundle_inst/SLICE_432:I3, hades_tdc_bundle_inst/SLICE_432:I6,
+        hades_tdc_bundle_inst/SLICE_653:I2, hades_tdc_bundle_inst/SLICE_654:I6,
+        hades_tdc_bundle_inst/SLICE_683:I8, hades_hit_out_i[1]:I0
+Signal ANB0 - Driver Comp: hades_tdc_bundle_inst/SLICE_121:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I0,
+        hades_tdc_bundle_inst/SLICE_121:I8, hades_tdc_bundle_inst/SLICE_122:I0,
+        hades_tdc_bundle_inst/SLICE_122:I9, hades_tdc_bundle_inst/SLICE_123:I4,
+        hades_tdc_bundle_inst/SLICE_432:I1, hades_tdc_bundle_inst/SLICE_653:I0,
+        hades_tdc_bundle_inst/SLICE_683:I6, hades_tdc_bundle_inst/SLICE_710:I0,
+        hades_hit_out_i[0]:I0
+Signal hades_tdc_bundle_inst/N_50_i_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_122:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_122:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I12
+Signal hades_window_end_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_741:I1, hades_window_end:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I13
+
+                                   Page 160
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I7
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I9
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - Driver Comp:
+     hades_lvl1_MGIOL:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I12
+Signal hades_offset_valid_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O3
+   Load Comps: hades_offset_valid:I0, hades_raw_out_valid_MGIOL:I10
+Signal hades_invalid_dl_c[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I5,
+
+                                   Page 161
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        hades_invalid_dl[1]:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I14
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I6
+Signal hades_tdc_bundle_inst/N_59_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_628:I12
+Signal hades_tdc_bundle_inst/N_46_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_122:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_122:I12
+Signal hades_tdc_bundle_inst/N_44 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_693:O1
+
+                                   Page 162
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: hades_tdc_bundle_inst/SLICE_458:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_435:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I13,
+        hades_tdc_bundle_inst/SLICE_451:I5
+Signal hades_dbg2_out_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I4, hades_dbg2_out[4]:I0
+Signal hades_dbg2_out_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I5, hades_dbg2_out[5]:I0
+Signal hades_dbg2_out_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_446:I4, hades_dbg2_out[6]:I0
+Signal hades_dbg2_out_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_446:I5, hades_dbg2_out[7]:I0
+Signal hades_dbg2_out_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_447:I4, hades_dbg2_out[8]:I0
+Signal hades_dbg2_out_c[9] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_447:I5, hades_dbg2_out[9]:I0
+Signal hades_dbg2_out_c[10] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_448:I4, hades_dbg2_out[10]:I0
+Signal hades_dbg2_out_c[11] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_448:I5, hades_dbg2_out[11]:I0
+Signal hades_tdc_bundle_inst/N_246_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_457:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I12
+Signal hades_hit_valid_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_457:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I3,
+        hades_tdc_bundle_inst/SLICE_457:I7, hades_tdc_bundle_inst/SLICE_654:I3,
+        hades_hit_valid[0]:I0
+Signal hades_tdc_bundle_inst/N_243_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_458:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_458:I12
+Signal hades_hit_valid_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_458:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I1,
+        hades_tdc_bundle_inst/SLICE_458:I4, hades_tdc_bundle_inst/SLICE_710:I1,
+        SLICE_740:I0, hades_hit_valid[1]:I0
+Signal hades_tdc_bundle_inst/N_245_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_459:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_459:I12
+Signal hades_hit_valid_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_459:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_459:I1,
+        hades_tdc_bundle_inst/SLICE_459:I9, hades_tdc_bundle_inst/SLICE_710:I2,
+        hades_hit_valid[2]:I0
+Signal hades_tdc_bundle_inst/N_244_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_460:O2
+
+                                   Page 163
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+   Load Comps: hades_tdc_bundle_inst/SLICE_460:I12
+Signal hades_hit_valid_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_460:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_460:I1,
+        hades_tdc_bundle_inst/SLICE_460:I9, hades_tdc_bundle_inst/SLICE_683:I1,
+        hades_hit_valid[3]:I0
+Signal hades_tdc_bundle_inst/N_247_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_121:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I12
+Signal hades_tdc_bundle_inst/hit_out_i_6[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_123:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_123:I12
+Signal hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_456:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I12
+Signal hades_drop_cmp_buf_valid_c - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_456:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I0,
+        hades_tdc_bundle_inst/SLICE_458:I0, hades_tdc_bundle_inst/SLICE_458:I6,
+        hades_tdc_bundle_inst/SLICE_710:I6, hades_drop_cmp_buf_valid:I0
+Signal hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_434:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_434:I12,
+        hades_tdc_bundle_inst/SLICE_450:I4
+Signal hades_drop_cmp_buf_coarse_c[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_450:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I8,
+        hades_drop_cmp_buf_coarse[0]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_434:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_434:I13,
+        hades_tdc_bundle_inst/SLICE_450:I5
+Signal hades_drop_cmp_buf_coarse_c[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_450:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I6,
+        hades_drop_cmp_buf_coarse[1]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_435:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I12,
+        hades_tdc_bundle_inst/SLICE_451:I4
+Signal hades_drop_cmp_buf_coarse_c[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_451:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I2,
+        hades_drop_cmp_buf_coarse[2]:I0
+Signal hades_drop_cmp_buf_coarse_c[3] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_451:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I0,
+        hades_drop_cmp_buf_coarse[3]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_436:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I12,
+        hades_tdc_bundle_inst/SLICE_452:I4
+Signal hades_drop_cmp_buf_coarse_c[4] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_452:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I8,
+        hades_drop_cmp_buf_coarse[4]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - Driver Comp:
+
+                                   Page 164
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+     hades_tdc_bundle_inst/SLICE_436:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I13,
+        hades_tdc_bundle_inst/SLICE_452:I5
+Signal hades_drop_cmp_buf_coarse_c[5] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_452:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I6,
+        hades_drop_cmp_buf_coarse[5]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_437:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_437:I12,
+        hades_tdc_bundle_inst/SLICE_453:I4
+Signal hades_drop_cmp_buf_coarse_c[6] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_453:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I2,
+        hades_drop_cmp_buf_coarse[6]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_437:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_437:I13,
+        hades_tdc_bundle_inst/SLICE_453:I5
+Signal hades_drop_cmp_buf_coarse_c[7] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_453:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I0,
+        hades_drop_cmp_buf_coarse[7]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_438:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_438:I12,
+        hades_tdc_bundle_inst/SLICE_454:I4
+Signal hades_drop_cmp_buf_coarse_c[8] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_454:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I7,
+        hades_drop_cmp_buf_coarse[8]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_455:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_455:I12
+Signal hades_drop_cmp_buf_coarse_c[9] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_455:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I6,
+        hades_drop_cmp_buf_coarse[9]:I0
+Signal hades_drop_cmp_buf_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I9, hades_drop_cmp_buf[0]:I0
+Signal hades_drop_cmp_buf_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I7, hades_drop_cmp_buf[1]:I0
+Signal hades_drop_cmp_buf_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I3, hades_drop_cmp_buf[2]:I0
+Signal hades_drop_cmp_buf_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I1, hades_drop_cmp_buf[3]:I0
+Signal hades_drop_cmp_buf_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I9, hades_drop_cmp_buf[4]:I0
+Signal hades_drop_cmp_buf_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I7, hades_drop_cmp_buf[5]:I0
+
+                                   Page 165
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_drop_cmp_buf_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I3, hades_drop_cmp_buf[6]:I0
+Signal hades_drop_cmp_buf_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I1, hades_drop_cmp_buf[7]:I0
+Signal hades_buf_release_c - Driver Comp: hades_tdc_bundle_inst/SLICE_433:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I2,
+        hades_tdc_bundle_inst/SLICE_457:I6, hades_tdc_bundle_inst/SLICE_458:I3,
+        hades_tdc_bundle_inst/SLICE_458:I8, hades_tdc_bundle_inst/SLICE_459:I0,
+        hades_tdc_bundle_inst/SLICE_459:I8, hades_tdc_bundle_inst/SLICE_460:I0,
+        hades_tdc_bundle_inst/SLICE_460:I8, hades_buf_release:I0
+Signal hades_tdc_bundle_inst/N_90 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_683:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_683:I0
+Signal hades_tdc_bundle_inst/N_80 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_432:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I2
+Signal hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_741:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I4
+Signal hades_tdc_bundle_inst/N_66 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_654:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I1
+Signal hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_654:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_683:I2
+Signal hades_tdc_bundle_inst/N_45 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_710:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I9
+Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_118:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I17
+Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_119:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I17
+Signal pll0inst/GND - Driver Comp: pll0inst/SLICE_742:O0
+   Load Comps: pll0inst/PLLInst_0:STDBY
+Signal LVL1_TRG_DATA_VALID_IN_c - Driver Comp: LVL1_TRG_DATA_VALID_IN:O0
+   Load Comps: LVL1_TRG_DATA_VALID_IN_MGIOL:I5
+Signal LVL1_INVALID_TRG_IN_c - Driver Comp: LVL1_INVALID_TRG_IN:O0
+   Load Comps: LVL1_INVALID_TRG_IN_MGIOL:I5
+Signal reset_dc_c - Driver Comp: reset_dc:O0
+   Load Comps: reset_dc_MGIOL:I5
+Signal hades_lvl1_c - Driver Comp: hades_lvl1:O0
+   Load Comps: SLICE_743:I0, hades_lvl1_MGIOL:I5
+Signal FEE_TRG_RELEASE_OUT_c - Driver Comp: FEE_TRG_RELEASE_OUT_MGIOL:O0
+   Load Comps: FEE_TRG_RELEASE_OUT:I1
+Signal FEE_DATA_WRITE_OUT_c - Driver Comp: FEE_DATA_WRITE_OUT_MGIOL:O0
+   Load Comps: FEE_DATA_WRITE_OUT:I1
+Signal FEE_DATAFINISHED_OUT_c - Driver Comp: FEE_DATAFINISHED_OUT_MGIOL:O0
+   Load Comps: FEE_DATAFINISHED_OUT:I1
+Signal hades_raw_out_valid_c - Driver Comp: hades_raw_out_valid_MGIOL:O0
+   Load Comps: hades_raw_out_valid:I1
+Signal hades_dbg2_out_c[0] - Driver Comp: hades_dbg2_out[0]_MGIOL:O0
+   Load Comps: hades_dbg2_out[0]:I1
+
+                                   Page 166
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+Signal hades_dbg2_out_c[1] - Driver Comp: hades_dbg2_out[1]_MGIOL:O0
+   Load Comps: hades_dbg2_out[1]:I1
+Signal hades_dbg2_out_c[2] - Driver Comp: hades_dbg2_out[2]_MGIOL:O0
+   Load Comps: hades_dbg2_out[2]:I1
+Signal hades_dbg2_out_c[16] - Driver Comp: hades_dbg2_out[16]_MGIOL:O0
+   Load Comps: hades_dbg2_out[16]:I1
+Signal hades_dbg2_out_c[17] - Driver Comp: hades_dbg2_out[17]_MGIOL:O0
+   Load Comps: hades_dbg2_out[17]:I1
+Signal hades_dbg2_out_c[18] - Driver Comp: hades_dbg2_out[18]_MGIOL:O0
+   Load Comps: hades_dbg2_out[18]:I1
+Signal hades_dbg2_out_c[20] - Driver Comp: hades_dbg2_out[20]_MGIOL:O0
+   Load Comps: hades_dbg2_out[20]:I1
+Signal hades_dbg2_out_c[21] - Driver Comp: hades_dbg2_out[21]_MGIOL:O0
+   Load Comps: hades_dbg2_out[21]:I1
+Signal hades_dbg2_out_c[22] - Driver Comp: hades_dbg2_out[22]_MGIOL:O0
+   Load Comps: hades_dbg2_out[22]:I1
+Signal hades_dbg2_out_c[23] - Driver Comp: hades_dbg2_out[23]_MGIOL:O0
+   Load Comps: hades_dbg2_out[23]:I1
+Signal hades_dbg2_out_c[24] - Driver Comp: hades_dbg2_out[24]_MGIOL:O0
+   Load Comps: hades_dbg2_out[24]:I1
+Signal hades_dbg2_out_c[25] - Driver Comp: hades_dbg2_out[25]_MGIOL:O0
+   Load Comps: hades_dbg2_out[25]:I1
+Signal hades_dbg2_out_c[26] - Driver Comp: hades_dbg2_out[26]_MGIOL:O0
+   Load Comps: hades_dbg2_out[26]:I1
+Signal hades_dbg2_out_c[27] - Driver Comp: hades_dbg2_out[27]_MGIOL:O0
+   Load Comps: hades_dbg2_out[27]:I1
+Signal hades_dbg2_out_c[28] - Driver Comp: hades_dbg2_out[28]_MGIOL:O0
+   Load Comps: hades_dbg2_out[28]:I1
+Signal hades_offset_c[0] - Driver Comp: hades_offset[0]_MGIOL:O0
+   Load Comps: hades_offset[0]:I1
+Signal hades_offset_c[1] - Driver Comp: hades_offset[1]_MGIOL:O0
+   Load Comps: hades_offset[1]:I1
+Signal hades_offset_c[2] - Driver Comp: hades_offset[2]_MGIOL:O0
+   Load Comps: hades_offset[2]:I1
+Signal hades_offset_c[3] - Driver Comp: hades_offset[3]_MGIOL:O0
+   Load Comps: hades_offset[3]:I1
+Signal hades_offset_c[4] - Driver Comp: hades_offset[4]_MGIOL:O0
+   Load Comps: hades_offset[4]:I1
+Signal hades_offset_c[5] - Driver Comp: hades_offset[5]_MGIOL:O0
+   Load Comps: hades_offset[5]:I1
+Signal hades_offset_c[6] - Driver Comp: hades_offset[6]_MGIOL:O0
+   Load Comps: hades_offset[6]:I1
+Signal hades_offset_c[7] - Driver Comp: hades_offset[7]_MGIOL:O0
+   Load Comps: hades_offset[7]:I1
+Signal hades_offset_c[8] - Driver Comp: hades_offset[8]_MGIOL:O0
+   Load Comps: hades_offset[8]:I1
+Signal hades_trig_c - Driver Comp: hades_trig:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_604:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
+        neg_inst/SLICE_605:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_neg_inst/SLICE_606:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_neg_inst/SLICE_607:I5, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/tdc_neg_inst/SLICE_608:I5, hades_tdc_bundle_inst/had
+        es_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:I5, hades_tdc_bundle_
+        inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:I5, hades_tdc
+        _bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I5,
+
+                                   Page 167
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Signal Cross Reference (cont)
+-----------------------------
+        SLICE_747:I0
+Signal trig_c[2] - Driver Comp: trig[2]:O0
+   Load Comps: SLICE_746:I0
+Signal trig_c[1] - Driver Comp: trig[1]:O0
+   Load Comps: SLICE_745:I0
+Signal trig_c[0] - Driver Comp: trig[0]:O0
+   Load Comps: SLICE_744:I0
+
+
+
+
+
+   Number of warnings:  13
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic
+     error in "BLOCK NET "tdc_out*" ;": tdc_out* does not match any nets in the
+     design. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic
+     error in "LOCATE COMP "reset" SITE "D11" ;": COMP "reset" cannot be found
+     in design. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic
+     error in "UGROUP "trig_gate0" BBOX 1 1 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO
+     	BLKNAME trig_pad_RNII4FF[0];": Block
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO" of UGROUP
+     "trig_gate0" not found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic
+     error in "LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;": UGROUP "trig_gate0"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic
+     error in "UGROUP "tdc_ch0" BBOX 1 6 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de   ....
+     _inst/dec_inst/out_internal[2]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;":
+     Block "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP
+     "tdc_ch0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc_ch0"
+     not found in designBlock
+
+                                   Page 168
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Design Errors/Warnings (cont)
+-----------------------------
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]" of UGROUP "tdc_ch0"
+     not found in designBlock "genblk1[0].tdc_cha   ....   out_internal[1]" of
+     UGROUP "tdc_ch0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]" of UGROUP
+     "tdc_ch0" not found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic
+     error in "LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;": UGROUP "tdc_ch0"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic
+     error in "UGROUP "tdc2" BBOX 1 6 
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_   ....
+     st/dec_inst/valid
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+     	BLKNAME
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
+     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]" of
+     UGROUP "tdc2" not found in designBlock
+     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc2" not
+     found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]"
+     of UGROUP "tdc2" not found in designBlock "genblk1[1].td   ....
+     ternal[2]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channe
+     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "tdc2" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic
+     error in "LOCATE UGROUP "tdc2" SITE "R65C41D" ;": UGROUP "tdc2" cannot be
+     found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic
+     error in "UGROUP "dec3" BBOX 1 6 
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_   ....
+     st/dec_inst/valid
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+     	BLKNAME
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
+     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]" of
+     UGROUP "dec3" not found in designBlock
+     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "dec3" not
+     found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]"
+     of UGROUP "dec3" not found in designBlock "genblk1[2].td   ....
+     ternal[2]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channe
+     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "dec3" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic
+     error in "LOCATE UGROUP "dec3" SITE "R65C49D" ;": UGROUP "dec3" cannot be
+     found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic
+     error in "UGROUP "tdc0_neg" BBOX 1 4 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_cl
+     k_synced[0]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b
+     uffered1[0]
+
+                                   Page 169
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Design Errors/Warnings (cont)
+-----------------------------
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_   ....   enblk1[0].tdc_c
+     hannel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_b
+     uffered[7];": Block "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genb
+     lk1[0].in_clk_synced[0]" of UGROUP "tdc0_neg" not found in designBlock "gen
+     blk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]"
+     of UGROUP "tdc0_neg" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b   ....
+     of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_
+     out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]" of UGROUP "tdc0_neg" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic
+     error in "LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;": UGROUP "tdc0_neg"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: Semantic error in "PGROUP "lvl1_dec" BBOX 1 6  DEVSIZE
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_ins   ....
+     inst/SLICE_734"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";":
+     Group lvl1_dec is invalid because BBOX size is too small to accommodate all
+     the components. This preference has been disabled.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| hades_raw_valid_vect[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[0]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| clk                 | INPUT     | LVDS      |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_valid| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[11]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[10]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[9]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+                                   Page 170
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| hades_drop_cmp_buf_coarse[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[11]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[10]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[9]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[31]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[30]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[29]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+                                   Page 171
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| hades_dbg2_out[28]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[27]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[26]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[25]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[24]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[23]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[22]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[21]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[20]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[19]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[18]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[17]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[16]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[15]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[14]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[13]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[12]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[11]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[10]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[9]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[8]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[7]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[6]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[5]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[4]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[3]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[2]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[1]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+
+                                   Page 172
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| hades_dbg2_out[0]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[3]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[2]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[1]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[0]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[3] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[2] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[1] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[0] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_discard       | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[3]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[2]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[1]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[0]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[3]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[2]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[1]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[0]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_finished  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_release   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_out_valid | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_window_end    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_offset_valid  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_offset[8]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[7]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[6]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[5]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[4]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+
+                                   Page 173
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| hades_offset[3]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[2]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[1]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[0]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_lvl1_invalid  | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| hades_lvl1          | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| hades_raw_valid_vect[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_raw_out_valid | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_trig          | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| release_out         | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| finished            | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| last_buf_empty      | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| discard             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| burst               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LVL1_TRG_DATA_VALI_IN_rising| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_TRG_RELEASE_OUT | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATAFINISHED_OUT| OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_WRITE_OUT  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[31]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[30]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[29]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[28]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[27]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[26]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[25]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[24]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[23]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[22]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+                                   Page 174
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| FEE_DATA_OUT[21]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[20]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[19]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[18]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[17]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[16]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[15]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[14]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[13]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[12]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[11]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[10]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[9]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[8]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[7]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[6]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[5]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[4]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[3]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[2]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[1]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[0]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LVL1_INVALID_TRG_IN | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| LVL1_TRG_DATA_VALID_IN| INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| fifo_empty1         | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_rden           | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[31]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[30]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+                                   Page 175
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| fifo_data_out[29]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[28]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[27]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[26]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[25]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[24]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[23]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[22]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[21]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[20]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[19]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[18]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[17]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[16]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[15]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[14]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[13]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[12]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[11]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[10]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[9]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[8]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[7]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[6]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[5]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[4]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[3]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[2]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+                                   Page 176
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+IO (PIO) Attributes (cont)
+--------------------------
+| fifo_data_out[1]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| reset_dc            | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| rd_clk              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/VCC undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/VCC undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/VCC undriven
+     or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/VCC
+     undriven or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/VCC undriven
+     or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/VCC
+     undriven or does not drive anything - clipped.
+Block trb_adapter_inst/VCC undriven or does not drive anything - clipped.
+Block fifo_colector_inst/VCC undriven or does not drive anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg was
+     merged into signal hades_trig_c
+Signal reset_dl_i[2] was merged into signal reset_dl[2]
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.
+     CN was merged into signal pll_clks[0]
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.
+     CN was merged into signal pll_clks[1]
+
+                                   Page 177
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.
+     CN was merged into signal pll_clks[2]
+Signal genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN was merged into signal
+     pll_clks[3]
+Signal fifo_colector_inst/fifo40_inst/invout_0 was merged into signal
+     last_buf_empty_c
+Signal fifo_colector_inst/fifo40_inst/invout_1 was merged into signal
+     fifo_colector_inst/fifo40_inst/Full
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty1_c
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty[1]
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty[2]
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal GND undriven or does not drive anything - clipped.
+Signal VCC undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/VCC undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/VCC undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/rRst undriven or does not drive anything -
+     clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal pll0inst/CLKINTFB undriven or does not drive anything - clipped.
+Signal pll0inst/REFCLK undriven or does not drive anything - clipped.
+Signal pll0inst/INTLOCK undriven or does not drive anything - clipped.
+Signal pll0inst/LOCK undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1 undriven or does not drive
+
+                                   Page 178
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/N_73 undriven or does not drive anything - clipped.
+     
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1 undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_0_COUT undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _21_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _21_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _9_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _9_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _1_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _1_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1 undriven or does
+     not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     0_COUT undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
+     0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
+     0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
+     _S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
+     _S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
+     _S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
+     _S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2 undriven or does
+     not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a1_S1_2 undriven or does not drive
+
+                                   Page 179
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a1_COUT_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/a0_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a0_COUT_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2 undriven or does not
+
+                                   Page 180
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_0 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/co4_1 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_1 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/co4 undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_2 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[35] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[34] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[33] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[32] undriven or does not drive
+     anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+
+                                   Page 181
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+
+                                   Page 182
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_0
+
+                                   Page 183
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+
+                                   Page 184
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1
+
+                                   Page 185
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1/out_RN
+     O was optimized away.
+Block reset_dl_RNISCAF[2] was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buff
+     ered1_4_.CN was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buff
+     ered1_5_.CN was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buff
+     ered1_6_.CN was optimized away.
+
+                                   Page 186
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Removed logic (cont)
+--------------------
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_7_.CN was
+     optimized away.
+Block fifo_colector_inst/fifo40_inst/INV_0 was optimized away.
+Block fifo_colector_inst/fifo40_inst/INV_1 was optimized away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block GND was optimized away.
+Block VCC was optimized away.
+Block hades_tdc_bundle_inst/VCC was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC was optimized away.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC was optimized
+     away.
+Block fifo_colector_inst/fifo40_inst/VCC was optimized away.
+Block fifo_colector_inst/fifo40_inst/OR2_t18 was optimized away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+
+Memory Usage
+------------
+
+/fifo_colector_inst/fifo40_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_1:  TYPE= PDPW16KD,  Width= 32,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo40_dc.lpc
+/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+
+                                   Page 187
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+Memory Usage (cont)
+-------------------
+/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+
+     
+
+PLL/DLL Summary
+---------------
+
+PLL 1:                                     Pin/Node Value
+  PLL Instance Name:                                pll0inst/PLLInst_0
+  PLL Type:                                         EHXPLLL
+  Input Clock:                             PIN      clk_c
+  Input Clock2:                                     NONE
+  Input Clock select:                               NONE
+  Output Clock(P):                         NODE     pll_clks[0]
+  Output Clock(S):                         NODE     pll_clks[1]
+  Output Clock(S2):                        NODE     pll_clks[2]
+  Output Clock(S3):                        NODE     pll_clks[3]
+  Feedback Signal:                         NODE     pll_clks[0]
+  Reset Signal:                                     NONE
+  Standby Signal:                          NODE     pll0inst/GND
+  PLL LOCK signal:                                  NONE
+  PLL Internal LOCK Signal:                         NONE
+  Input Clock Frequency (MHz):                      100.0000
+  Output Clock(P) Frequency (MHz):                  300.0000
+  Output Clock(S) Frequency (MHz):                  300.0000
+  Output Clock(S2) Frequency (MHz):                 300.0000
+  Output Clock(S3) Frequency (MHz):                 300.0000
+  CLKOP Post Divider A Input:                       DIVA
+  CLKOS Post Divider B Input:                       DIVB
+  CLKOS2 Post Divider C Input:                      DIVC
+  CLKOS3 Post Divider D Input:                      DIVD
+  Pre Divider A Input:                              NONE
+  Pre Divider B Input:                              NONE
+  Pre Divider C Input:                              NONE
+  Pre Divider D Input:                              NONE
+  FB_MODE:                                          CLKOP
+  CLKI Divider:                                     1
+  CLKFB Divider:                                    3
+  CLKOP Divider:                                    2
+  CLKOS Divider:                                    2
+  CLKOS2 Divider:                                   2
+
+                                   Page 188
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+PLL/DLL Summary (cont)
+----------------------
+  CLKOS3 Divider:                                   2
+  Fractional N Divider:                             NONE
+  CLKOP Desired Phase Shift(degree):                0
+  CLKOP Trim Option Rising/Falling:                 FALLING
+  CLKOP Trim Option Delay:                          0
+  CLKOS Desired Phase Shift(degree):                45
+  CLKOS Trim Option Rising/Falling:                 FALLING
+  CLKOS Trim Option Delay:                          0
+  CLKOS2 Desired Phase Shift(degree):               90
+  CLKOS2 Trim Option Rising/Falling:                NONE
+  CLKOS2 Trim Option Delay:                         NONE
+  CLKOS3 Desired Phase Shift(degree):               135
+  CLKOS3 Trim Option Rising/Falling:                NONE
+  CLKOS3 Trim Option Delay:                         NONE
+
+ASIC Components
+---------------
+
+Instance Name: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
+         Type: PDPW16KD
+Instance Name: pll0inst/PLLInst_0
+         Type: EHXPLLL
+
+PGROUP Utilization
+------------------
+
+PGROUP "tdc0":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "tdc22":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "tdc3":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "lvl1_tdc":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_dec_pos":
+   Logic contained: 23 SLICEs, 6 PFUs
+   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_dec_neg":
+   Logic contained: 23 SLICEs, 6 PFUs
+   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_tdc_pos":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_tdc_neg":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+
+                                   Page 189
+
+
+
+
+Design:  top_tf                                        Date:  06/16/21  09:19:26
+
+PGROUP Utilization (cont)
+-------------------------
+PGROUP "lvl1_pad":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "gate2":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "trig3":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 4 secs  
+   Total REAL Time: 5 secs  
+   Peak Memory Usage: 361 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                   Page 190
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/impl1/s1_impl1.mt b/impl1/s1_impl1.mt
new file mode 100644
index 0000000..ade4de5
--- /dev/null
+++ b/impl1/s1_impl1.mt
@@ -0,0 +1,9 @@
+-v
+1
+
+
+-gt
+
+-fullname
+-mapchkpnt 0
+-sethld
diff --git a/impl1/s1_impl1.ncd b/impl1/s1_impl1.ncd
new file mode 100644
index 0000000..eb6d8aa
Binary files /dev/null and b/impl1/s1_impl1.ncd differ
diff --git a/impl1/s1_impl1.ngd b/impl1/s1_impl1.ngd
new file mode 100644
index 0000000..517dcbc
Binary files /dev/null and b/impl1/s1_impl1.ngd differ
diff --git a/impl1/s1_impl1.ngo b/impl1/s1_impl1.ngo
new file mode 100644
index 0000000..e848d47
Binary files /dev/null and b/impl1/s1_impl1.ngo differ
diff --git a/impl1/s1_impl1.p2t b/impl1/s1_impl1.p2t
new file mode 100644
index 0000000..de0af6f
--- /dev/null
+++ b/impl1/s1_impl1.p2t
@@ -0,0 +1,10 @@
+-w
+-l 5
+-i 6
+-y
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF
diff --git a/impl1/s1_impl1.p3t b/impl1/s1_impl1.p3t
new file mode 100644
index 0000000..3d2e48b
--- /dev/null
+++ b/impl1/s1_impl1.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "s1_impl1.log"
+-o "s1_impl1.csv"
+-pr "s1_impl1.prf"
diff --git a/impl1/s1_impl1.pad b/impl1/s1_impl1.pad
new file mode 100644
index 0000000..9c4860c
--- /dev/null
+++ b/impl1/s1_impl1.pad
@@ -0,0 +1,702 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LFE5UM5G-45F
+Performance Grade:      8
+PACKAGE:          CABGA381
+Package Status:                     Final          Version 1.38
+
+Wed Jun 16 09:20:00 2021
+
+Pinout by Port Name:
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| Port Name                     | Pin/Bank | Buffer Type  | Site  | BC Enable | Properties                        |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| FEE_DATAFINISHED_OUT          | D13/1    | LVCMOS25_OUT | PT53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[0]               | R17/3    | LVCMOS25_OUT | PR44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[10]              | J19/2    | LVCMOS25_OUT | PR32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[11]              | R3/8     | LVCMOS25_OUT | PB15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[12]              | N5/6     | LVCMOS25_OUT | PL59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[13]              | G16/2    | LVCMOS25_OUT | PR17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[14]              | P5/6     | LVCMOS25_OUT | PL59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[15]              | M19/3    | LVCMOS25_OUT | PR35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[16]              | N19/3    | LVCMOS25_OUT | PR59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[17]              | B15/1    | LVCMOS25_OUT | PT69A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[18]              | A15/1    | LVCMOS25_OUT | PT67A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[19]              | K5/6     | LVCMOS25_OUT | PL44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[1]               | N3/6     | LVCMOS25_OUT | PL62A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[20]              | V1/8     | LVCMOS25_OUT | PB6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[21]              | G19/2    | LVCMOS25_OUT | PR29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[22]              | T2/8     | LVCMOS25_OUT | PB13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[23]              | H20/2    | LVCMOS25_OUT | PR29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[24]              | K19/2    | LVCMOS25_OUT | PR32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[25]              | H17/2    | LVCMOS25_OUT | PR20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[26]              | L19/3    | LVCMOS25_OUT | PR35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[27]              | C20/2    | LVCMOS25_OUT | PR23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[28]              | F19/2    | LVCMOS25_OUT | PR26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[29]              | U1/8     | LVCMOS25_OUT | PB6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[2]               | G18/2    | LVCMOS25_OUT | PR17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[30]              | D20/2    | LVCMOS25_OUT | PR23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[31]              | H18/2    | LVCMOS25_OUT | PR20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[3]               | M17/3    | LVCMOS25_OUT | PR41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[4]               | E18/2    | LVCMOS25_OUT | PR14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[5]               | F16/2    | LVCMOS25_OUT | PR11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[6]               | A16/1    | LVCMOS25_OUT | PT74A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[7]               | L3/6     | LVCMOS25_OUT | PL62C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[8]               | L16/3    | LVCMOS25_OUT | PR38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[9]               | F20/2    | LVCMOS25_OUT | PR26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_WRITE_OUT            | C13/1    | LVCMOS25_OUT | PT51B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_TRG_RELEASE_OUT           | E13/1    | LVCMOS25_OUT | PT53B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| LVL1_INVALID_TRG_IN           | R16/3    | LVCMOS25_IN  | PR44C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALID_IN        | A9/0     | LVCMOS25_IN  | PT33A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALI_IN_rising  | N18/3    | LVCMOS25_OUT | PR41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| burst                         | N16/3    | LVCMOS25_OUT | PR41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| clk                           | P3/6     | LVDS_IN      | PL68C |           | CLAMP:ON                          |
+| discard                       | P16/3    | LVCMOS25_OUT | PR44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[0]              | P17/3    | LVCMOS25_OUT | PR41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[10]             | K20/2    | LVCMOS25_OUT | PR32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[11]             | U2/8     | LVCMOS25_OUT | PB13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[12]             | N4/6     | LVCMOS25_OUT | PL59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[13]             | J16/2    | LVCMOS25_OUT | PR20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[14]             | M4/6     | LVCMOS25_OUT | PL59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[15]             | J20/2    | LVCMOS25_OUT | PR32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[16]             | P18/3    | LVCMOS25_OUT | PR59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[17]             | C15/1    | LVCMOS25_OUT | PT69B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[18]             | E14/1    | LVCMOS25_OUT | PT58B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[19]             | L4/6     | LVCMOS25_OUT | PL44C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[1]              | M3/6     | LVCMOS25_OUT | PL62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[20]             | Y2/8     | LVCMOS25_OUT | PB9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[21]             | K18/2    | LVCMOS25_OUT | PR29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[22]             | W1/8     | LVCMOS25_OUT | PB9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[23]             | J18/2    | LVCMOS25_OUT | PR29C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[24]             | M20/3    | LVCMOS25_OUT | PR35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[25]             | J17/2    | LVCMOS25_OUT | PR20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[26]             | L20/3    | LVCMOS25_OUT | PR35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[27]             | D19/2    | LVCMOS25_OUT | PR23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[28]             | G20/2    | LVCMOS25_OUT | PR26D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[29]             | T1/8     | LVCMOS25_OUT | PB4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[2]              | F17/2    | LVCMOS25_OUT | PR17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[30]             | E19/2    | LVCMOS25_OUT | PR23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[31]             | H16/2    | LVCMOS25_OUT | PR17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[3]              | L17/3    | LVCMOS25_OUT | PR38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[4]              | F18/2    | LVCMOS25_OUT | PR14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[5]              | D17/2    | LVCMOS25_OUT | PR11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[6]              | B16/1    | LVCMOS25_OUT | PT74B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[7]              | N1/6     | LVCMOS25_OUT | PL65D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[8]              | M18/3    | LVCMOS25_OUT | PR38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[9]              | E20/2    | LVCMOS25_OUT | PR26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_empty1                   | N17/3    | LVCMOS25_OUT | PR44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_rden                     | A19/1    | LVCMOS25_OUT | PT85A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| finished                      | D14/1    | LVCMOS25_OUT | PT58A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[0]             | N20/3    | LVCMOS25_OUT | PR59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[1]             | A10/0    | LVCMOS25_OUT | PT36A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[2]             | R20/3    | LVCMOS25_OUT | PR62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[3]             | U16/3    | LVCMOS25_OUT | PR68C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_finished            | A4/7     | LVCMOS25_OUT | PL11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_out_valid           | C9/0     | LVCMOS25_OUT | PT27A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_release             | E7/0     | LVCMOS25_OUT | PT9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[0]          | G5/7     | LVCMOS25_OUT | PL29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[1]          | H3/7     | LVCMOS25_OUT | PL29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[2]          | E3/7     | LVCMOS25_OUT | PL20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[3]          | C2/7     | LVCMOS25_OUT | PL23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[4]          | B6/0     | LVCMOS25_OUT | PT4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[5]          | B1/7     | LVCMOS25_OUT | PL23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[6]          | E5/7     | LVCMOS25_OUT | PL20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[7]          | M5/6     | LVCMOS25_OUT | PL53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[8]          | F1/6     | LVCMOS25_OUT | PL35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[0]             | J3/6     | LVCMOS25_OUT | PL38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[10]            | A8/0     | LVCMOS25_OUT | PT18B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[11]            | D6/0     | LVCMOS25_OUT | PT6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[12]            | B8/0     | LVCMOS25_OUT | PT15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[13]            | P19/3    | LVCMOS25_OUT | PR59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[14]            | P1/6     | LVCMOS25_OUT | PL68A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[15]            | C17/1    | LVCMOS25_OUT | PT78B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[16]            | G3/7     | LVCMOS25_OUT | PL32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[17]            | G1/6     | LVCMOS25_OUT | PL35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[18]            | J5/6     | LVCMOS25_OUT | PL38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[19]            | R1/8     | LVCMOS25_OUT | PB4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[1]             | E2/7     | LVCMOS25_OUT | PL32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[20]            | K3/6     | LVCMOS25_OUT | PL38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[21]            | G2/6     | LVCMOS25_OUT | PL35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[22]            | H4/7     | LVCMOS25_OUT | PL29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[23]            | J4/6     | LVCMOS25_OUT | PL38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[24]            | H1/6     | LVCMOS25_OUT | PL41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[25]            | J1/6     | LVCMOS25_OUT | PL41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[26]            | K1/6     | LVCMOS25_OUT | PL41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[27]            | F2/7     | LVCMOS25_OUT | PL32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[28]            | H2/6     | LVCMOS25_OUT | PL35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[29]            | A17/1    | LVCMOS25_OUT | PT80A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[2]             | F3/7     | LVCMOS25_OUT | PL32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[30]            | E16/2    | LVCMOS25_OUT | PR11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[31]            | R18/3    | LVCMOS25_OUT | PR65B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[3]             | C16/1    | LVCMOS25_OUT | PT76A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[4]             | E4/7     | LVCMOS25_OUT | PL17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[5]             | C3/7     | LVCMOS25_OUT | PL17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[6]             | F4/7     | LVCMOS25_OUT | PL20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[7]             | B3/7     | LVCMOS25_OUT | PL14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[8]             | E8/0     | LVCMOS25_OUT | PT13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[9]             | C7/0     | LVCMOS25_OUT | PT11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_discard                 | B11/0    | LVCMOS25_OUT | PT38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[0]         | D3/7     | LVCMOS25_OUT | PL17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[10]        | B17/1    | LVCMOS25_OUT | PT78A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[11]        | U17/3    | LVCMOS25_OUT | PR68B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[1]         | D9/0     | LVCMOS25_OUT | PT20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[2]         | A6/0     | LVCMOS25_OUT | PT4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[3]         | C6/0     | LVCMOS25_OUT | PT11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[4]         | F5/7     | LVCMOS25_OUT | PL20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[5]         | C4/7     | LVCMOS25_OUT | PL14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[6]         | D8/0     | LVCMOS25_OUT | PT13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[7]         | D5/7     | LVCMOS25_OUT | PL17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[8]         | B4/7     | LVCMOS25_OUT | PL14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[9]         | B20/1    | LVCMOS25_OUT | PT85B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[0]  | A11/0    | LVCMOS25_OUT | PT36B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[10] | T17/3    | LVCMOS25_OUT | PR68D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[11] | D18/2    | LVCMOS25_OUT | PR14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[1]  | A13/1    | LVCMOS25_OUT | PT49B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[2]  | B10/0    | LVCMOS25_OUT | PT33B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[3]  | C12/1    | LVCMOS25_OUT | PT44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[4]  | E12/1    | LVCMOS25_OUT | PT47B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[5]  | D12/1    | LVCMOS25_OUT | PT47A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[6]  | E11/1    | LVCMOS25_OUT | PT42B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[7]  | D11/1    | LVCMOS25_OUT | PT42A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[8]  | B13/1    | LVCMOS25_OUT | PT51A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[9]  | A12/1    | LVCMOS25_OUT | PT49A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_valid      | A7/0     | LVCMOS25_OUT | PT18A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[0]            | E9/0     | LVCMOS25_OUT | PT20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[1]            | C11/0    | LVCMOS25_OUT | PT38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[2]            | E6/0     | LVCMOS25_OUT | PT6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[3]            | D7/0     | LVCMOS25_OUT | PT9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[0]            | A3/7     | LVCMOS25_OUT | PL14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[1]            | B5/7     | LVCMOS25_OUT | PL11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[2]            | A5/7     | LVCMOS25_OUT | PL11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[3]            | C5/7     | LVCMOS25_OUT | PL11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[0]           | V2/8     | LVCMOS25_OUT | PB11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[1]           | L5/6     | LVCMOS25_OUT | PL44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[2]           | K2/6     | LVCMOS25_OUT | PL41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[3]           | K4/6     | LVCMOS25_OUT | PL44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_lvl1                    | E1/7     | LVCMOS25_IN  | PL26D |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_lvl1_invalid            | W2/8     | LVCMOS25_IN  | PB11B |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_offset[0]               | D10/0    | LVCMOS25_OUT | PT29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[1]               | C10/0    | LVCMOS25_OUT | PT31B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[2]               | E10/0    | LVCMOS25_OUT | PT29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[3]               | D1/7     | LVCMOS25_OUT | PL26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[4]               | C1/7     | LVCMOS25_OUT | PL26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[5]               | D2/7     | LVCMOS25_OUT | PL26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[6]               | A2/7     | LVCMOS25_OUT | PL23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[7]               | B9/0     | LVCMOS25_OUT | PT31A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[8]               | B2/7     | LVCMOS25_OUT | PL23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset_valid            | D15/1    | LVCMOS25_OUT | PT71A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_out_valid           | E15/1    | LVCMOS25_OUT | PT71B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[0]       | U20/3    | LVCMOS25_OUT | PR62D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[1]       | E17/2    | LVCMOS25_OUT | PR14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_trig                    | H5/7     | LVCMOS25_IN  | PL29C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_window_end              | C14/1    | LVCMOS25_OUT | PT56B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| last_buf_empty                | L18/3    | LVCMOS25_OUT | PR38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| rd_clk                        | B12/1    | LVCMOS25_IN  | PT44A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| release_out                   | A14/1    | LVCMOS25_OUT | PT56A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| reset_dc                      | C8/0     | LVCMOS25_IN  | PT15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[0]                       | R2/8     | LVCMOS25_IN  | PB15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[1]                       | T3/8     | LVCMOS25_IN  | PB18A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[2]                       | T19/3    | LVCMOS25_IN  | PR65A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
+| 6    | 2.5V  |
+| 7    | 2.5V  |
+| 8    | 2.5V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| Pin/Bank | Pin Info                      | Preference | Buffer Type  | Site         | Dual Function            | BC Enable |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| A2/7     | hades_offset[6]               |            | LVCMOS25_OUT | PL23A        | LDQ29                    |           |
+| A3/7     | hades_hit_valid[0]            |            | LVCMOS25_OUT | PL14C        | LDQ17                    |           |
+| A4/7     | hades_buf_finished            |            | LVCMOS25_OUT | PL11A        | ULC_GPLL0T_IN/LDQ17      |           |
+| A5/7     | hades_hit_valid[2]            |            | LVCMOS25_OUT | PL11B        | ULC_GPLL0C_IN/LDQ17      |           |
+| A6/0     | hades_drop_cmp_buf[2]         |            | LVCMOS25_OUT | PT4A         | ULC_GPLL1T_IN            |           |
+| A7/0     | hades_drop_cmp_buf_valid      |            | LVCMOS25_OUT | PT18A        |                          |           |
+| A8/0     | hades_dbg2_out[10]            |            | LVCMOS25_OUT | PT18B        |                          |           |
+| A9/0     | LVL1_TRG_DATA_VALID_IN        | LOCATED    | LVCMOS25_IN  | PT33A        | GR_PCLK0_1               |           |
+| A10/0    | hades_buf_drop[1]             |            | LVCMOS25_OUT | PT36A        | PCLKT0_1                 |           |
+| A11/0    | hades_drop_cmp_buf_coarse[0]  |            | LVCMOS25_OUT | PT36B        |                          |           |
+| A12/1    | hades_drop_cmp_buf_coarse[9]  |            | LVCMOS25_OUT | PT49A        |                          |           |
+| A13/1    | hades_drop_cmp_buf_coarse[1]  |            | LVCMOS25_OUT | PT49B        |                          |           |
+| A14/1    | release_out                   |            | LVCMOS25_OUT | PT56A        |                          |           |
+| A15/1    | FEE_DATA_OUT[18]              |            | LVCMOS25_OUT | PT67A        |                          |           |
+| A16/1    | FEE_DATA_OUT[6]               |            | LVCMOS25_OUT | PT74A        |                          |           |
+| A17/1    | hades_dbg2_out[29]            |            | LVCMOS25_OUT | PT80A        |                          |           |
+| A18/1    |     unused, PULL:DOWN         |            |              | PT83A        |                          |           |
+| A19/1    | fifo_rden                     |            | LVCMOS25_OUT | PT85A        | URC_GPLL1T_IN            |           |
+| B1/7     | hades_dbg2_coarse[5]          |            | LVCMOS25_OUT | PL23B        | LDQ29                    |           |
+| B2/7     | hades_offset[8]               |            | LVCMOS25_OUT | PL23C        | VREF1_7/LDQ29            |           |
+| B3/7     | hades_dbg2_out[7]             |            | LVCMOS25_OUT | PL14D        | LDQ17                    |           |
+| B4/7     | hades_drop_cmp_buf[8]         |            | LVCMOS25_OUT | PL14B        | LDQ17                    |           |
+| B5/7     | hades_hit_valid[1]            |            | LVCMOS25_OUT | PL11C        | LDQ17                    |           |
+| B6/0     | hades_dbg2_coarse[4]          |            | LVCMOS25_OUT | PT4B         | ULC_GPLL1C_IN            |           |
+| B8/0     | hades_dbg2_out[12]            |            | LVCMOS25_OUT | PT15B        |                          |           |
+| B9/0     | hades_offset[7]               |            | LVCMOS25_OUT | PT31A        |                          |           |
+| B10/0    | hades_drop_cmp_buf_coarse[2]  |            | LVCMOS25_OUT | PT33B        | GR_PCLK0_0               |           |
+| B11/0    | hades_discard                 |            | LVCMOS25_OUT | PT38A        | PCLKT0_0                 |           |
+| B12/1    | rd_clk                        |            | LVCMOS25_IN  | PT44A        | PCLKT1_0                 |           |
+| B13/1    | hades_drop_cmp_buf_coarse[8]  |            | LVCMOS25_OUT | PT51A        |                          |           |
+| B15/1    | FEE_DATA_OUT[17]              |            | LVCMOS25_OUT | PT69A        |                          |           |
+| B16/1    | fifo_data_out[6]              |            | LVCMOS25_OUT | PT74B        |                          |           |
+| B17/1    | hades_drop_cmp_buf[10]        |            | LVCMOS25_OUT | PT78A        |                          |           |
+| B18/1    |     unused, PULL:DOWN         |            |              | PT80B        |                          |           |
+| B19/1    |     unused, PULL:DOWN         |            |              | PT83B        |                          |           |
+| B20/1    | hades_drop_cmp_buf[9]         |            | LVCMOS25_OUT | PT85B        | URC_GPLL1C_IN            |           |
+| C1/7     | hades_offset[4]               |            | LVCMOS25_OUT | PL26A        | LDQ29                    |           |
+| C2/7     | hades_dbg2_coarse[3]          |            | LVCMOS25_OUT | PL23D        | LDQ29                    |           |
+| C3/7     | hades_dbg2_out[5]             |            | LVCMOS25_OUT | PL17C        | LDQ17                    |           |
+| C4/7     | hades_drop_cmp_buf[5]         |            | LVCMOS25_OUT | PL14A        | LDQ17                    |           |
+| C5/7     | hades_hit_valid[3]            |            | LVCMOS25_OUT | PL11D        | LDQ17                    |           |
+| C6/0     | hades_drop_cmp_buf[3]         |            | LVCMOS25_OUT | PT11A        |                          |           |
+| C7/0     | hades_dbg2_out[9]             |            | LVCMOS25_OUT | PT11B        |                          |           |
+| C8/0     | reset_dc                      |            | LVCMOS25_IN  | PT15A        |                          |           |
+| C9/0     | hades_buf_out_valid           |            | LVCMOS25_OUT | PT27A        |                          |           |
+| C10/0    | hades_offset[1]               |            | LVCMOS25_OUT | PT31B        |                          |           |
+| C11/0    | hades_hit_out_i[1]            |            | LVCMOS25_OUT | PT38B        |                          |           |
+| C12/1    | hades_drop_cmp_buf_coarse[3]  |            | LVCMOS25_OUT | PT44B        |                          |           |
+| C13/1    | FEE_DATA_WRITE_OUT            |            | LVCMOS25_OUT | PT51B        |                          |           |
+| C14/1    | hades_window_end              |            | LVCMOS25_OUT | PT56B        |                          |           |
+| C15/1    | fifo_data_out[17]             |            | LVCMOS25_OUT | PT69B        |                          |           |
+| C16/1    | hades_dbg2_out[3]             |            | LVCMOS25_OUT | PT76A        |                          |           |
+| C17/1    | hades_dbg2_out[15]            |            | LVCMOS25_OUT | PT78B        |                          |           |
+| C18/2    |     unused, PULL:DOWN         |            |              | PR11A        | URC_GPLL0T_IN/RDQ17      |           |
+| C20/2    | FEE_DATA_OUT[27]              |            | LVCMOS25_OUT | PR23A        | RDQ29                    |           |
+| CCLK/8   |                               |            |              | CCLK         | MCLK/SCK                 |           |
+| D1/7     | hades_offset[3]               |            | LVCMOS25_OUT | PL26B        | LDQ29                    |           |
+| D2/7     | hades_offset[5]               |            | LVCMOS25_OUT | PL26C        | LDQ29                    |           |
+| D3/7     | hades_drop_cmp_buf[0]         |            | LVCMOS25_OUT | PL17D        | LDQ17                    |           |
+| D5/7     | hades_drop_cmp_buf[7]         |            | LVCMOS25_OUT | PL17B        | LDQSN17                  |           |
+| D6/0     | hades_dbg2_out[11]            |            | LVCMOS25_OUT | PT6B         |                          |           |
+| D7/0     | hades_hit_out_i[3]            |            | LVCMOS25_OUT | PT9B         |                          |           |
+| D8/0     | hades_drop_cmp_buf[6]         |            | LVCMOS25_OUT | PT13B        |                          |           |
+| D9/0     | hades_drop_cmp_buf[1]         |            | LVCMOS25_OUT | PT20A        |                          |           |
+| D10/0    | hades_offset[0]               |            | LVCMOS25_OUT | PT29A        |                          |           |
+| D11/1    | hades_drop_cmp_buf_coarse[7]  |            | LVCMOS25_OUT | PT42A        | PCLKT1_1                 |           |
+| D12/1    | hades_drop_cmp_buf_coarse[5]  |            | LVCMOS25_OUT | PT47A        | GR_PCLK1_0               |           |
+| D13/1    | FEE_DATAFINISHED_OUT          |            | LVCMOS25_OUT | PT53A        |                          |           |
+| D14/1    | finished                      |            | LVCMOS25_OUT | PT58A        |                          |           |
+| D15/1    | hades_offset_valid            |            | LVCMOS25_OUT | PT71A        |                          |           |
+| D16/1    |     unused, PULL:DOWN         |            |              | PT76B        |                          |           |
+| D17/2    | fifo_data_out[5]              |            | LVCMOS25_OUT | PR11B        | URC_GPLL0C_IN/RDQ17      |           |
+| D18/2    | hades_drop_cmp_buf_coarse[11] |            | LVCMOS25_OUT | PR14A        | RDQ17                    |           |
+| D19/2    | fifo_data_out[27]             |            | LVCMOS25_OUT | PR23B        | RDQ29                    |           |
+| D20/2    | FEE_DATA_OUT[30]              |            | LVCMOS25_OUT | PR23C        | VREF1_2/RDQ29            |           |
+| E1/7     | hades_lvl1                    | LOCATED    | LVCMOS25_IN  | PL26D        | LDQ29                    |           |
+| E2/7     | hades_dbg2_out[1]             |            | LVCMOS25_OUT | PL32D        | PCLKC7_0/LDQ29           |           |
+| E3/7     | hades_dbg2_coarse[2]          |            | LVCMOS25_OUT | PL20B        | LDQ17                    |           |
+| E4/7     | hades_dbg2_out[4]             |            | LVCMOS25_OUT | PL17A        | LDQS17                   |           |
+| E5/7     | hades_dbg2_coarse[6]          |            | LVCMOS25_OUT | PL20C        | LDQ17                    |           |
+| E6/0     | hades_hit_out_i[2]            |            | LVCMOS25_OUT | PT6A         |                          |           |
+| E7/0     | hades_buf_release             |            | LVCMOS25_OUT | PT9A         |                          |           |
+| E8/0     | hades_dbg2_out[8]             |            | LVCMOS25_OUT | PT13A        |                          |           |
+| E9/0     | hades_hit_out_i[0]            |            | LVCMOS25_OUT | PT20B        |                          |           |
+| E10/0    | hades_offset[2]               |            | LVCMOS25_OUT | PT29B        |                          |           |
+| E11/1    | hades_drop_cmp_buf_coarse[6]  |            | LVCMOS25_OUT | PT42B        |                          |           |
+| E12/1    | hades_drop_cmp_buf_coarse[4]  |            | LVCMOS25_OUT | PT47B        | GR_PCLK1_1               |           |
+| E13/1    | FEE_TRG_RELEASE_OUT           |            | LVCMOS25_OUT | PT53B        |                          |           |
+| E14/1    | fifo_data_out[18]             |            | LVCMOS25_OUT | PT58B        |                          |           |
+| E15/1    | hades_raw_out_valid           |            | LVCMOS25_OUT | PT71B        |                          |           |
+| E16/2    | hades_dbg2_out[30]            |            | LVCMOS25_OUT | PR11C        | RDQ17                    |           |
+| E17/2    | hades_raw_valid_vect[1]       |            | LVCMOS25_OUT | PR14B        | RDQ17                    |           |
+| E18/2    | FEE_DATA_OUT[4]               |            | LVCMOS25_OUT | PR14C        | RDQ17                    |           |
+| E19/2    | fifo_data_out[30]             |            | LVCMOS25_OUT | PR23D        | RDQ29                    |           |
+| E20/2    | fifo_data_out[9]              |            | LVCMOS25_OUT | PR26A        | RDQ29                    |           |
+| F1/6     | hades_dbg2_coarse[8]          |            | LVCMOS25_OUT | PL35B        | PCLKC6_1/LDQ41           |           |
+| F2/7     | hades_dbg2_out[27]            |            | LVCMOS25_OUT | PL32C        | PCLKT7_0/LDQ29           |           |
+| F3/7     | hades_dbg2_out[2]             |            | LVCMOS25_OUT | PL32B        | PCLKC7_1/LDQ29           |           |
+| F4/7     | hades_dbg2_out[6]             |            | LVCMOS25_OUT | PL20A        | LDQ17                    |           |
+| F5/7     | hades_drop_cmp_buf[4]         |            | LVCMOS25_OUT | PL20D        | LDQ17                    |           |
+| F16/2    | FEE_DATA_OUT[5]               |            | LVCMOS25_OUT | PR11D        | RDQ17                    |           |
+| F17/2    | fifo_data_out[2]              |            | LVCMOS25_OUT | PR17A        | RDQS17                   |           |
+| F18/2    | fifo_data_out[4]              |            | LVCMOS25_OUT | PR14D        | RDQ17                    |           |
+| F19/2    | FEE_DATA_OUT[28]              |            | LVCMOS25_OUT | PR26B        | RDQ29                    |           |
+| F20/2    | FEE_DATA_OUT[9]               |            | LVCMOS25_OUT | PR26C        | RDQ29                    |           |
+| G1/6     | hades_dbg2_out[17]            |            | LVCMOS25_OUT | PL35D        | PCLKC6_0/LDQ41           |           |
+| G2/6     | hades_dbg2_out[21]            |            | LVCMOS25_OUT | PL35A        | PCLKT6_1/LDQ41           |           |
+| G3/7     | hades_dbg2_out[16]            |            | LVCMOS25_OUT | PL32A        | PCLKT7_1/LDQ29           |           |
+| G5/7     | hades_dbg2_coarse[0]          |            | LVCMOS25_OUT | PL29B        | LDQSN29                  |           |
+| G16/2    | FEE_DATA_OUT[13]              |            | LVCMOS25_OUT | PR17C        | RDQ17                    |           |
+| G18/2    | FEE_DATA_OUT[2]               |            | LVCMOS25_OUT | PR17B        | RDQSN17                  |           |
+| G19/2    | FEE_DATA_OUT[21]              |            | LVCMOS25_OUT | PR29A        | GR_PCLK2_1/RDQS29        |           |
+| G20/2    | fifo_data_out[28]             |            | LVCMOS25_OUT | PR26D        | RDQ29                    |           |
+| H1/6     | hades_dbg2_out[24]            |            | LVCMOS25_OUT | PL41C        | LDQ41                    |           |
+| H2/6     | hades_dbg2_out[28]            |            | LVCMOS25_OUT | PL35C        | PCLKT6_0/LDQ41           |           |
+| H3/7     | hades_dbg2_coarse[1]          |            | LVCMOS25_OUT | PL29D        | LDQ29                    |           |
+| H4/7     | hades_dbg2_out[22]            |            | LVCMOS25_OUT | PL29A        | GR_PCLK7_1/LDQS29        |           |
+| H5/7     | hades_trig                    | LOCATED    | LVCMOS25_IN  | PL29C        | GR_PCLK7_0/LDQ29         |           |
+| H16/2    | fifo_data_out[31]             |            | LVCMOS25_OUT | PR17D        | RDQ17                    |           |
+| H17/2    | FEE_DATA_OUT[25]              |            | LVCMOS25_OUT | PR20B        | RDQ17                    |           |
+| H18/2    | FEE_DATA_OUT[31]              |            | LVCMOS25_OUT | PR20A        | RDQ17                    |           |
+| H20/2    | FEE_DATA_OUT[23]              |            | LVCMOS25_OUT | PR29B        | RDQSN29                  |           |
+| J1/6     | hades_dbg2_out[25]            |            | LVCMOS25_OUT | PL41B        | LDQSN41                  |           |
+| J3/6     | hades_dbg2_out[0]             |            | LVCMOS25_OUT | PL38C        | GR_PCLK6_1/LDQ41         |           |
+| J4/6     | hades_dbg2_out[23]            |            | LVCMOS25_OUT | PL38A        | GR_PCLK6_0/LDQ41         |           |
+| J5/6     | hades_dbg2_out[18]            |            | LVCMOS25_OUT | PL38B        | LDQ41                    |           |
+| J16/2    | fifo_data_out[13]             |            | LVCMOS25_OUT | PR20D        | RDQ17                    |           |
+| J17/2    | fifo_data_out[25]             |            | LVCMOS25_OUT | PR20C        | RDQ17                    |           |
+| J18/2    | fifo_data_out[23]             |            | LVCMOS25_OUT | PR29C        | GR_PCLK2_0/RDQ29         |           |
+| J19/2    | FEE_DATA_OUT[10]              |            | LVCMOS25_OUT | PR32A        | PCLKT2_1/RDQ29           |           |
+| J20/2    | fifo_data_out[15]             |            | LVCMOS25_OUT | PR32C        | PCLKT2_0/RDQ29           |           |
+| K1/6     | hades_dbg2_out[26]            |            | LVCMOS25_OUT | PL41D        | LDQ41                    |           |
+| K2/6     | hades_invalid_dl[2]           |            | LVCMOS25_OUT | PL41A        | LDQS41                   |           |
+| K3/6     | hades_dbg2_out[20]            |            | LVCMOS25_OUT | PL38D        | LDQ41                    |           |
+| K4/6     | hades_invalid_dl[3]           |            | LVCMOS25_OUT | PL44A        | LDQ41                    |           |
+| K5/6     | FEE_DATA_OUT[19]              |            | LVCMOS25_OUT | PL44B        | VREF1_6/LDQ41            |           |
+| K18/2    | fifo_data_out[21]             |            | LVCMOS25_OUT | PR29D        | RDQ29                    |           |
+| K19/2    | FEE_DATA_OUT[24]              |            | LVCMOS25_OUT | PR32B        | PCLKC2_1/RDQ29           |           |
+| K20/2    | fifo_data_out[10]             |            | LVCMOS25_OUT | PR32D        | PCLKC2_0/RDQ29           |           |
+| L1/6     |     unused, PULL:DOWN         |            |              | PL65C        | LDQ65                    |           |
+| L2/6     |     unused, PULL:DOWN         |            |              | PL62D        | LDQ65                    |           |
+| L3/6     | FEE_DATA_OUT[7]               |            | LVCMOS25_OUT | PL62C        | LDQ65                    |           |
+| L4/6     | fifo_data_out[19]             |            | LVCMOS25_OUT | PL44C        | LDQ41                    |           |
+| L5/6     | hades_invalid_dl[1]           |            | LVCMOS25_OUT | PL44D        | LDQ41                    |           |
+| L16/3    | FEE_DATA_OUT[8]               |            | LVCMOS25_OUT | PR38A        | GR_PCLK3_0/RDQ41         |           |
+| L17/3    | fifo_data_out[3]              |            | LVCMOS25_OUT | PR38B        | RDQ41                    |           |
+| L18/3    | last_buf_empty                |            | LVCMOS25_OUT | PR38C        | GR_PCLK3_1/RDQ41         |           |
+| L19/3    | FEE_DATA_OUT[26]              |            | LVCMOS25_OUT | PR35C        | PCLKT3_0/RDQ41           |           |
+| L20/3    | fifo_data_out[26]             |            | LVCMOS25_OUT | PR35A        | PCLKT3_1/RDQ41           |           |
+| M1/6     |     unused, PULL:DOWN         |            |              | PL65B        | LDQSN65                  |           |
+| M3/6     | fifo_data_out[1]              |            | LVCMOS25_OUT | PL62B        | LDQ65                    |           |
+| M4/6     | fifo_data_out[14]             |            | LVCMOS25_OUT | PL59A        | LDQ65                    |           |
+| M5/6     | hades_dbg2_coarse[7]          |            | LVCMOS25_OUT | PL53A        | LDQS53                   |           |
+| M17/3    | FEE_DATA_OUT[3]               |            | LVCMOS25_OUT | PR41B        | RDQSN41                  |           |
+| M18/3    | fifo_data_out[8]              |            | LVCMOS25_OUT | PR38D        | RDQ41                    |           |
+| M19/3    | FEE_DATA_OUT[15]              |            | LVCMOS25_OUT | PR35D        | PCLKC3_0/RDQ41           |           |
+| M20/3    | fifo_data_out[24]             |            | LVCMOS25_OUT | PR35B        | PCLKC3_1/RDQ41           |           |
+| N1/6     | fifo_data_out[7]              |            | LVCMOS25_OUT | PL65D        | LDQ65                    |           |
+| N2/6     |     unused, PULL:DOWN         |            |              | PL65A        | LDQS65                   |           |
+| N3/6     | FEE_DATA_OUT[1]               |            | LVCMOS25_OUT | PL62A        | LDQ65                    |           |
+| N4/6     | fifo_data_out[12]             |            | LVCMOS25_OUT | PL59C        | LDQ65                    |           |
+| N5/6     | FEE_DATA_OUT[12]              |            | LVCMOS25_OUT | PL59B        | LDQ65                    |           |
+| N16/3    | burst                         |            | LVCMOS25_OUT | PR41A        | RDQS41                   |           |
+| N17/3    | fifo_empty1                   |            | LVCMOS25_OUT | PR44A        | RDQ41                    |           |
+| N18/3    | LVL1_TRG_DATA_VALI_IN_rising  |            | LVCMOS25_OUT | PR41C        | RDQ41                    |           |
+| N19/3    | FEE_DATA_OUT[16]              |            | LVCMOS25_OUT | PR59A        | RDQ65                    |           |
+| N20/3    | hades_buf_drop[0]             |            | LVCMOS25_OUT | PR59B        | RDQ65                    |           |
+| P1/6     | hades_dbg2_out[14]            |            | LVCMOS25_OUT | PL68A        | LDQ65                    |           |
+| P2/6     |     unused, PULL:DOWN         |            |              | PL68B        | LDQ65                    |           |
+| P3/6     | clk+                          | LOCATED    | LVDS_IN      | PL68C        | LLC_GPLL0T_IN/LDQ65      |           |
+| P4/6     | clk-                          |            | LVDS_IN      | PL68D        | LLC_GPLL0C_IN/LDQ65      |           |
+| P5/6     | FEE_DATA_OUT[14]              |            | LVCMOS25_OUT | PL59D        | LDQ65                    |           |
+| P16/3    | discard                       |            | LVCMOS25_OUT | PR44B        | VREF1_3/RDQ41            |           |
+| P17/3    | fifo_data_out[0]              |            | LVCMOS25_OUT | PR41D        | RDQ41                    |           |
+| P18/3    | fifo_data_out[16]             |            | LVCMOS25_OUT | PR59D        | RDQ65                    |           |
+| P19/3    | hades_dbg2_out[13]            |            | LVCMOS25_OUT | PR59C        | RDQ65                    |           |
+| P20/3    |     unused, PULL:DOWN         |            |              | PR62A        | RDQ65                    |           |
+| PL47A/6  |     unused, PULL:DOWN         |            |              | PL47A        | LDQ53                    |           |
+| PL47B/6  |     unused, PULL:DOWN         |            |              | PL47B        | LDQ53                    |           |
+| PL47C/6  |     unused, PULL:DOWN         |            |              | PL47C        | LDQ53                    |           |
+| PL47D/6  |     unused, PULL:DOWN         |            |              | PL47D        | LDQ53                    |           |
+| PL50A/6  |     unused, PULL:DOWN         |            |              | PL50A        | LDQ53                    |           |
+| PL50B/6  |     unused, PULL:DOWN         |            |              | PL50B        | LDQ53                    |           |
+| PL50C/6  |     unused, PULL:DOWN         |            |              | PL50C        | LDQ53                    |           |
+| PL50D/6  |     unused, PULL:DOWN         |            |              | PL50D        | LDQ53                    |           |
+| PL53B/6  |     unused, PULL:DOWN         |            |              | PL53B        | LDQSN53                  |           |
+| PL53C/6  |     unused, PULL:DOWN         |            |              | PL53C        | LDQ53                    |           |
+| PL53D/6  |     unused, PULL:DOWN         |            |              | PL53D        | LDQ53                    |           |
+| PL56A/6  |     unused, PULL:DOWN         |            |              | PL56A        | LDQ53                    |           |
+| PL56B/6  |     unused, PULL:DOWN         |            |              | PL56B        | LDQ53                    |           |
+| PL56C/6  |     unused, PULL:DOWN         |            |              | PL56C        | LDQ53                    |           |
+| PL56D/6  |     unused, PULL:DOWN         |            |              | PL56D        | LDQ53                    |           |
+| PR47A/3  |     unused, PULL:DOWN         |            |              | PR47A        | RDQ53                    |           |
+| PR47B/3  |     unused, PULL:DOWN         |            |              | PR47B        | RDQ53                    |           |
+| PR47C/3  |     unused, PULL:DOWN         |            |              | PR47C        | RDQ53                    |           |
+| PR47D/3  |     unused, PULL:DOWN         |            |              | PR47D        | RDQ53                    |           |
+| PR50A/3  |     unused, PULL:DOWN         |            |              | PR50A        | RDQ53                    |           |
+| PR50B/3  |     unused, PULL:DOWN         |            |              | PR50B        | RDQ53                    |           |
+| PR50C/3  |     unused, PULL:DOWN         |            |              | PR50C        | RDQ53                    |           |
+| PR50D/3  |     unused, PULL:DOWN         |            |              | PR50D        | RDQ53                    |           |
+| PR53B/3  |     unused, PULL:DOWN         |            |              | PR53B        | RDQSN53                  |           |
+| PR53C/3  |     unused, PULL:DOWN         |            |              | PR53C        | RDQ53                    |           |
+| PR53D/3  |     unused, PULL:DOWN         |            |              | PR53D        | RDQ53                    |           |
+| PR56A/3  |     unused, PULL:DOWN         |            |              | PR56A        | RDQ53                    |           |
+| PR56B/3  |     unused, PULL:DOWN         |            |              | PR56B        | RDQ53                    |           |
+| PR56C/3  |     unused, PULL:DOWN         |            |              | PR56C        | RDQ53                    |           |
+| PR56D/3  |     unused, PULL:DOWN         |            |              | PR56D        | RDQ53                    |           |
+| PT22A/0  |     unused, PULL:DOWN         |            |              | PT22A        |                          |           |
+| PT22B/0  |     unused, PULL:DOWN         |            |              | PT22B        |                          |           |
+| PT24A/0  |     unused, PULL:DOWN         |            |              | PT24A        |                          |           |
+| PT24B/0  |     unused, PULL:DOWN         |            |              | PT24B        |                          |           |
+| PT27B/0  |     unused, PULL:DOWN         |            |              | PT27B        |                          |           |
+| PT60A/1  |     unused, PULL:DOWN         |            |              | PT60A        |                          |           |
+| PT60B/1  |     unused, PULL:DOWN         |            |              | PT60B        |                          |           |
+| PT62A/1  |     unused, PULL:DOWN         |            |              | PT62A        |                          |           |
+| PT62B/1  |     unused, PULL:DOWN         |            |              | PT62B        |                          |           |
+| PT65A/1  |     unused, PULL:DOWN         |            |              | PT65A        |                          |           |
+| PT65B/1  |     unused, PULL:DOWN         |            |              | PT65B        |                          |           |
+| PT67B/1  |     unused, PULL:DOWN         |            |              | PT67B        |                          |           |
+| R1/8     | hades_dbg2_out[19]            |            | LVCMOS25_OUT | PB4A         | D7/IO7                   |           |
+| R2/8     | trig[0]                       | LOCATED    | LVCMOS25_IN  | PB15A        | HOLDN/DI/BUSY/CSSPIN/CEN |           |
+| R3/8     | FEE_DATA_OUT[11]              |            | LVCMOS25_OUT | PB15B        | DOUT/CSON                |           |
+| R16/3    | LVL1_INVALID_TRG_IN           |            | LVCMOS25_IN  | PR44C        | RDQ41                    |           |
+| R17/3    | FEE_DATA_OUT[0]               |            | LVCMOS25_OUT | PR44D        | RDQ41                    |           |
+| R18/3    | hades_dbg2_out[31]            |            | LVCMOS25_OUT | PR65B        | RDQSN65                  |           |
+| R20/3    | hades_buf_drop[2]             |            | LVCMOS25_OUT | PR62B        | RDQ65                    |           |
+| T1/8     | fifo_data_out[29]             |            | LVCMOS25_OUT | PB4B         | D6/IO6                   |           |
+| T2/8     | FEE_DATA_OUT[22]              |            | LVCMOS25_OUT | PB13A        | SN/CSN                   |           |
+| T3/8     | trig[1]                       | LOCATED    | LVCMOS25_IN  | PB18A        | WRITEN                   |           |
+| T16/3    |     unused, PULL:DOWN         |            |              | PR53A        | RDQS53                   |           |
+| T17/3    | hades_drop_cmp_buf_coarse[10] |            | LVCMOS25_OUT | PR68D        | LRC_GPLL0C_IN/RDQ65      |           |
+| T18/3    |     unused, PULL:DOWN         |            |              | PR65D        | RDQ65                    |           |
+| T19/3    | trig[2]                       | LOCATED    | LVCMOS25_IN  | PR65A        | RDQS65                   |           |
+| T20/3    |     unused, PULL:DOWN         |            |              | PR62C        | RDQ65                    |           |
+| TCK/40   |                               |            |              | TCK          |                          |           |
+| TDI/40   |                               |            |              | TDI          |                          |           |
+| TDO/40   |                               |            |              | TDO          |                          |           |
+| TMS/40   |                               |            |              | TMS          |                          |           |
+| U1/8     | FEE_DATA_OUT[29]              |            | LVCMOS25_OUT | PB6A         | D5/MISO2/IO5             |           |
+| U2/8     | fifo_data_out[11]             |            | LVCMOS25_OUT | PB13B        | CS1N                     |           |
+| U16/3    | hades_buf_drop[3]             |            | LVCMOS25_OUT | PR68C        | LRC_GPLL0T_IN/RDQ65      |           |
+| U17/3    | hades_drop_cmp_buf[11]        |            | LVCMOS25_OUT | PR68B        | RDQ65                    |           |
+| U18/3    |     unused, PULL:DOWN         |            |              | PR68A        | RDQ65                    |           |
+| U19/3    |     unused, PULL:DOWN         |            |              | PR65C        | RDQ65                    |           |
+| U20/3    | hades_raw_valid_vect[0]       |            | LVCMOS25_OUT | PR62D        | RDQ65                    |           |
+| V1/8     | FEE_DATA_OUT[20]              |            | LVCMOS25_OUT | PB6B         | D4/MOSI2/IO4             |           |
+| V2/8     | hades_invalid_dl[0]           |            | LVCMOS25_OUT | PB11A        | D1/MISO/IO1              |           |
+| W1/8     | fifo_data_out[22]             |            | LVCMOS25_OUT | PB9A         | D3/IO3                   |           |
+| W2/8     | hades_lvl1_invalid            |            | LVCMOS25_IN  | PB11B        | D0/MOSI/IO0              |           |
+| W4/50    |                               |            |              | HDTXP0_D0CH0 |                          |           |
+| W5/50    |                               |            |              | HDTXN0_D0CH0 |                          |           |
+| W8/50    |                               |            |              | HDTXP0_D0CH1 |                          |           |
+| W9/50    |                               |            |              | HDTXN0_D0CH1 |                          |           |
+| W13/51   |                               |            |              | HDTXP0_D1CH0 |                          |           |
+| W14/51   |                               |            |              | HDTXN0_D1CH0 |                          |           |
+| W17/51   |                               |            |              | HDTXP0_D1CH1 |                          |           |
+| W18/51   |                               |            |              | HDTXN0_D1CH1 |                          |           |
+| W20/51   |                               |            |              | REFCLKN_D1   |                          |           |
+| Y2/8     | fifo_data_out[20]             |            | LVCMOS25_OUT | PB9B         | D2/IO2                   |           |
+| Y5/50    |                               |            |              | HDRXP0_D0CH0 |                          |           |
+| Y6/50    |                               |            |              | HDRXN0_D0CH0 |                          |           |
+| Y7/50    |                               |            |              | HDRXP0_D0CH1 |                          |           |
+| Y8/50    |                               |            |              | HDRXN0_D0CH1 |                          |           |
+| Y11/50   |                               |            |              | REFCLKP_D0   |                          |           |
+| Y12/50   |                               |            |              | REFCLKN_D0   |                          |           |
+| Y14/51   |                               |            |              | HDRXP0_D1CH0 |                          |           |
+| Y15/51   |                               |            |              | HDRXN0_D1CH0 |                          |           |
+| Y16/51   |                               |            |              | HDRXP0_D1CH1 |                          |           |
+| Y17/51   |                               |            |              | HDRXN0_D1CH1 |                          |           |
+| Y19/51   |                               |            |              | REFCLKP_D1   |                          |           |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "FEE_DATAFINISHED_OUT"  SITE  "D13";
+LOCATE  COMP  "FEE_DATA_OUT[0]"  SITE  "R17";
+LOCATE  COMP  "FEE_DATA_OUT[10]"  SITE  "J19";
+LOCATE  COMP  "FEE_DATA_OUT[11]"  SITE  "R3";
+LOCATE  COMP  "FEE_DATA_OUT[12]"  SITE  "N5";
+LOCATE  COMP  "FEE_DATA_OUT[13]"  SITE  "G16";
+LOCATE  COMP  "FEE_DATA_OUT[14]"  SITE  "P5";
+LOCATE  COMP  "FEE_DATA_OUT[15]"  SITE  "M19";
+LOCATE  COMP  "FEE_DATA_OUT[16]"  SITE  "N19";
+LOCATE  COMP  "FEE_DATA_OUT[17]"  SITE  "B15";
+LOCATE  COMP  "FEE_DATA_OUT[18]"  SITE  "A15";
+LOCATE  COMP  "FEE_DATA_OUT[19]"  SITE  "K5";
+LOCATE  COMP  "FEE_DATA_OUT[1]"  SITE  "N3";
+LOCATE  COMP  "FEE_DATA_OUT[20]"  SITE  "V1";
+LOCATE  COMP  "FEE_DATA_OUT[21]"  SITE  "G19";
+LOCATE  COMP  "FEE_DATA_OUT[22]"  SITE  "T2";
+LOCATE  COMP  "FEE_DATA_OUT[23]"  SITE  "H20";
+LOCATE  COMP  "FEE_DATA_OUT[24]"  SITE  "K19";
+LOCATE  COMP  "FEE_DATA_OUT[25]"  SITE  "H17";
+LOCATE  COMP  "FEE_DATA_OUT[26]"  SITE  "L19";
+LOCATE  COMP  "FEE_DATA_OUT[27]"  SITE  "C20";
+LOCATE  COMP  "FEE_DATA_OUT[28]"  SITE  "F19";
+LOCATE  COMP  "FEE_DATA_OUT[29]"  SITE  "U1";
+LOCATE  COMP  "FEE_DATA_OUT[2]"  SITE  "G18";
+LOCATE  COMP  "FEE_DATA_OUT[30]"  SITE  "D20";
+LOCATE  COMP  "FEE_DATA_OUT[31]"  SITE  "H18";
+LOCATE  COMP  "FEE_DATA_OUT[3]"  SITE  "M17";
+LOCATE  COMP  "FEE_DATA_OUT[4]"  SITE  "E18";
+LOCATE  COMP  "FEE_DATA_OUT[5]"  SITE  "F16";
+LOCATE  COMP  "FEE_DATA_OUT[6]"  SITE  "A16";
+LOCATE  COMP  "FEE_DATA_OUT[7]"  SITE  "L3";
+LOCATE  COMP  "FEE_DATA_OUT[8]"  SITE  "L16";
+LOCATE  COMP  "FEE_DATA_OUT[9]"  SITE  "F20";
+LOCATE  COMP  "FEE_DATA_WRITE_OUT"  SITE  "C13";
+LOCATE  COMP  "FEE_TRG_RELEASE_OUT"  SITE  "E13";
+LOCATE  COMP  "LVL1_INVALID_TRG_IN"  SITE  "R16";
+LOCATE  COMP  "LVL1_TRG_DATA_VALID_IN"  SITE  "A9";
+LOCATE  COMP  "LVL1_TRG_DATA_VALI_IN_rising"  SITE  "N18";
+LOCATE  COMP  "burst"  SITE  "N16";
+LOCATE  COMP  "clk"  SITE  "P3";
+LOCATE  COMP  "discard"  SITE  "P16";
+LOCATE  COMP  "fifo_data_out[0]"  SITE  "P17";
+LOCATE  COMP  "fifo_data_out[10]"  SITE  "K20";
+LOCATE  COMP  "fifo_data_out[11]"  SITE  "U2";
+LOCATE  COMP  "fifo_data_out[12]"  SITE  "N4";
+LOCATE  COMP  "fifo_data_out[13]"  SITE  "J16";
+LOCATE  COMP  "fifo_data_out[14]"  SITE  "M4";
+LOCATE  COMP  "fifo_data_out[15]"  SITE  "J20";
+LOCATE  COMP  "fifo_data_out[16]"  SITE  "P18";
+LOCATE  COMP  "fifo_data_out[17]"  SITE  "C15";
+LOCATE  COMP  "fifo_data_out[18]"  SITE  "E14";
+LOCATE  COMP  "fifo_data_out[19]"  SITE  "L4";
+LOCATE  COMP  "fifo_data_out[1]"  SITE  "M3";
+LOCATE  COMP  "fifo_data_out[20]"  SITE  "Y2";
+LOCATE  COMP  "fifo_data_out[21]"  SITE  "K18";
+LOCATE  COMP  "fifo_data_out[22]"  SITE  "W1";
+LOCATE  COMP  "fifo_data_out[23]"  SITE  "J18";
+LOCATE  COMP  "fifo_data_out[24]"  SITE  "M20";
+LOCATE  COMP  "fifo_data_out[25]"  SITE  "J17";
+LOCATE  COMP  "fifo_data_out[26]"  SITE  "L20";
+LOCATE  COMP  "fifo_data_out[27]"  SITE  "D19";
+LOCATE  COMP  "fifo_data_out[28]"  SITE  "G20";
+LOCATE  COMP  "fifo_data_out[29]"  SITE  "T1";
+LOCATE  COMP  "fifo_data_out[2]"  SITE  "F17";
+LOCATE  COMP  "fifo_data_out[30]"  SITE  "E19";
+LOCATE  COMP  "fifo_data_out[31]"  SITE  "H16";
+LOCATE  COMP  "fifo_data_out[3]"  SITE  "L17";
+LOCATE  COMP  "fifo_data_out[4]"  SITE  "F18";
+LOCATE  COMP  "fifo_data_out[5]"  SITE  "D17";
+LOCATE  COMP  "fifo_data_out[6]"  SITE  "B16";
+LOCATE  COMP  "fifo_data_out[7]"  SITE  "N1";
+LOCATE  COMP  "fifo_data_out[8]"  SITE  "M18";
+LOCATE  COMP  "fifo_data_out[9]"  SITE  "E20";
+LOCATE  COMP  "fifo_empty1"  SITE  "N17";
+LOCATE  COMP  "fifo_rden"  SITE  "A19";
+LOCATE  COMP  "finished"  SITE  "D14";
+LOCATE  COMP  "hades_buf_drop[0]"  SITE  "N20";
+LOCATE  COMP  "hades_buf_drop[1]"  SITE  "A10";
+LOCATE  COMP  "hades_buf_drop[2]"  SITE  "R20";
+LOCATE  COMP  "hades_buf_drop[3]"  SITE  "U16";
+LOCATE  COMP  "hades_buf_finished"  SITE  "A4";
+LOCATE  COMP  "hades_buf_out_valid"  SITE  "C9";
+LOCATE  COMP  "hades_buf_release"  SITE  "E7";
+LOCATE  COMP  "hades_dbg2_coarse[0]"  SITE  "G5";
+LOCATE  COMP  "hades_dbg2_coarse[1]"  SITE  "H3";
+LOCATE  COMP  "hades_dbg2_coarse[2]"  SITE  "E3";
+LOCATE  COMP  "hades_dbg2_coarse[3]"  SITE  "C2";
+LOCATE  COMP  "hades_dbg2_coarse[4]"  SITE  "B6";
+LOCATE  COMP  "hades_dbg2_coarse[5]"  SITE  "B1";
+LOCATE  COMP  "hades_dbg2_coarse[6]"  SITE  "E5";
+LOCATE  COMP  "hades_dbg2_coarse[7]"  SITE  "M5";
+LOCATE  COMP  "hades_dbg2_coarse[8]"  SITE  "F1";
+LOCATE  COMP  "hades_dbg2_out[0]"  SITE  "J3";
+LOCATE  COMP  "hades_dbg2_out[10]"  SITE  "A8";
+LOCATE  COMP  "hades_dbg2_out[11]"  SITE  "D6";
+LOCATE  COMP  "hades_dbg2_out[12]"  SITE  "B8";
+LOCATE  COMP  "hades_dbg2_out[13]"  SITE  "P19";
+LOCATE  COMP  "hades_dbg2_out[14]"  SITE  "P1";
+LOCATE  COMP  "hades_dbg2_out[15]"  SITE  "C17";
+LOCATE  COMP  "hades_dbg2_out[16]"  SITE  "G3";
+LOCATE  COMP  "hades_dbg2_out[17]"  SITE  "G1";
+LOCATE  COMP  "hades_dbg2_out[18]"  SITE  "J5";
+LOCATE  COMP  "hades_dbg2_out[19]"  SITE  "R1";
+LOCATE  COMP  "hades_dbg2_out[1]"  SITE  "E2";
+LOCATE  COMP  "hades_dbg2_out[20]"  SITE  "K3";
+LOCATE  COMP  "hades_dbg2_out[21]"  SITE  "G2";
+LOCATE  COMP  "hades_dbg2_out[22]"  SITE  "H4";
+LOCATE  COMP  "hades_dbg2_out[23]"  SITE  "J4";
+LOCATE  COMP  "hades_dbg2_out[24]"  SITE  "H1";
+LOCATE  COMP  "hades_dbg2_out[25]"  SITE  "J1";
+LOCATE  COMP  "hades_dbg2_out[26]"  SITE  "K1";
+LOCATE  COMP  "hades_dbg2_out[27]"  SITE  "F2";
+LOCATE  COMP  "hades_dbg2_out[28]"  SITE  "H2";
+LOCATE  COMP  "hades_dbg2_out[29]"  SITE  "A17";
+LOCATE  COMP  "hades_dbg2_out[2]"  SITE  "F3";
+LOCATE  COMP  "hades_dbg2_out[30]"  SITE  "E16";
+LOCATE  COMP  "hades_dbg2_out[31]"  SITE  "R18";
+LOCATE  COMP  "hades_dbg2_out[3]"  SITE  "C16";
+LOCATE  COMP  "hades_dbg2_out[4]"  SITE  "E4";
+LOCATE  COMP  "hades_dbg2_out[5]"  SITE  "C3";
+LOCATE  COMP  "hades_dbg2_out[6]"  SITE  "F4";
+LOCATE  COMP  "hades_dbg2_out[7]"  SITE  "B3";
+LOCATE  COMP  "hades_dbg2_out[8]"  SITE  "E8";
+LOCATE  COMP  "hades_dbg2_out[9]"  SITE  "C7";
+LOCATE  COMP  "hades_discard"  SITE  "B11";
+LOCATE  COMP  "hades_drop_cmp_buf[0]"  SITE  "D3";
+LOCATE  COMP  "hades_drop_cmp_buf[10]"  SITE  "B17";
+LOCATE  COMP  "hades_drop_cmp_buf[11]"  SITE  "U17";
+LOCATE  COMP  "hades_drop_cmp_buf[1]"  SITE  "D9";
+LOCATE  COMP  "hades_drop_cmp_buf[2]"  SITE  "A6";
+LOCATE  COMP  "hades_drop_cmp_buf[3]"  SITE  "C6";
+LOCATE  COMP  "hades_drop_cmp_buf[4]"  SITE  "F5";
+LOCATE  COMP  "hades_drop_cmp_buf[5]"  SITE  "C4";
+LOCATE  COMP  "hades_drop_cmp_buf[6]"  SITE  "D8";
+LOCATE  COMP  "hades_drop_cmp_buf[7]"  SITE  "D5";
+LOCATE  COMP  "hades_drop_cmp_buf[8]"  SITE  "B4";
+LOCATE  COMP  "hades_drop_cmp_buf[9]"  SITE  "B20";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[0]"  SITE  "A11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[10]"  SITE  "T17";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[11]"  SITE  "D18";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[1]"  SITE  "A13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[2]"  SITE  "B10";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[3]"  SITE  "C12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[4]"  SITE  "E12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[5]"  SITE  "D12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[6]"  SITE  "E11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[7]"  SITE  "D11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[8]"  SITE  "B13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[9]"  SITE  "A12";
+LOCATE  COMP  "hades_drop_cmp_buf_valid"  SITE  "A7";
+LOCATE  COMP  "hades_hit_out_i[0]"  SITE  "E9";
+LOCATE  COMP  "hades_hit_out_i[1]"  SITE  "C11";
+LOCATE  COMP  "hades_hit_out_i[2]"  SITE  "E6";
+LOCATE  COMP  "hades_hit_out_i[3]"  SITE  "D7";
+LOCATE  COMP  "hades_hit_valid[0]"  SITE  "A3";
+LOCATE  COMP  "hades_hit_valid[1]"  SITE  "B5";
+LOCATE  COMP  "hades_hit_valid[2]"  SITE  "A5";
+LOCATE  COMP  "hades_hit_valid[3]"  SITE  "C5";
+LOCATE  COMP  "hades_invalid_dl[0]"  SITE  "V2";
+LOCATE  COMP  "hades_invalid_dl[1]"  SITE  "L5";
+LOCATE  COMP  "hades_invalid_dl[2]"  SITE  "K2";
+LOCATE  COMP  "hades_invalid_dl[3]"  SITE  "K4";
+LOCATE  COMP  "hades_lvl1"  SITE  "E1";
+LOCATE  COMP  "hades_lvl1_invalid"  SITE  "W2";
+LOCATE  COMP  "hades_offset[0]"  SITE  "D10";
+LOCATE  COMP  "hades_offset[1]"  SITE  "C10";
+LOCATE  COMP  "hades_offset[2]"  SITE  "E10";
+LOCATE  COMP  "hades_offset[3]"  SITE  "D1";
+LOCATE  COMP  "hades_offset[4]"  SITE  "C1";
+LOCATE  COMP  "hades_offset[5]"  SITE  "D2";
+LOCATE  COMP  "hades_offset[6]"  SITE  "A2";
+LOCATE  COMP  "hades_offset[7]"  SITE  "B9";
+LOCATE  COMP  "hades_offset[8]"  SITE  "B2";
+LOCATE  COMP  "hades_offset_valid"  SITE  "D15";
+LOCATE  COMP  "hades_raw_out_valid"  SITE  "E15";
+LOCATE  COMP  "hades_raw_valid_vect[0]"  SITE  "U20";
+LOCATE  COMP  "hades_raw_valid_vect[1]"  SITE  "E17";
+LOCATE  COMP  "hades_trig"  SITE  "H5";
+LOCATE  COMP  "hades_window_end"  SITE  "C14";
+LOCATE  COMP  "last_buf_empty"  SITE  "L18";
+LOCATE  COMP  "rd_clk"  SITE  "B12";
+LOCATE  COMP  "release_out"  SITE  "A14";
+LOCATE  COMP  "reset_dc"  SITE  "C8";
+LOCATE  COMP  "trig[0]"  SITE  "R2";
+LOCATE  COMP  "trig[1]"  SITE  "T3";
+LOCATE  COMP  "trig[2]"  SITE  "T19";
+
+#PLL
+LOCATE  COMP  "pll0inst/PLLInst_0"  SITE  "PLL_BL0" ;
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:20:03 2021
+
diff --git a/impl1/s1_impl1.par b/impl1/s1_impl1.par
new file mode 100644
index 0000000..ffbb001
--- /dev/null
+++ b/impl1/s1_impl1.par
@@ -0,0 +1,323 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:19:35 2021
+
+/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t
+s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset
+/home/hadaq/mmichalek/lattice/simplified/promote.xml
+
+
+Preference file: s1_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -2.994       209210       -1.015       9647         48           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 48 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "s1_impl1_map.ncd"
+Wed Jun 16 09:19:35 2021
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf
+Preference file: s1_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)     187/245          76% used
+                    187/203          92% bonded
+   IOLOGIC           35/245          14% used
+
+   SLICE            692/21924         3% used
+
+   EBR                4/108           3% used
+   PLL                1/4            25% used
+
+
+Number of Signals: 1594
+Number of Connections: 3725
+
+Pin Constraint Summary:
+   7 out of 186 pins locked (3% locked).
+
+The following 5 signals are selected to use the primary clock routing resources:
+    pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
+    pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+    pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0)
+    rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0)
+    pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+
+
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 8 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 788909.
+Finished Placer Phase 1.  REAL time: 24 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  774601
+Finished Placer Phase 2.  REAL time: 25 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 12 (8%)
+  GR_PCLK    : 0 out of 12 (0%)
+  PLL        : 1 out of 4 (25%)
+  DCS        : 0 out of 2 (0%)
+  DCC        : 0 out of 60 (0%)
+  CLKDIV     : 0 out of 4 (0%)
+
+Quadrant TL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant TR Clocks:
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8
+
+  PRIMARY  : 2 out of 16 (12%)
+
+Quadrant BL Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant BR Clocks:
+  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115
+  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9
+  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Edge Clocks:
+
+  No edge clock selected.
+
+
+--------------- End of Clock Report ---------------
+
+
++
+I/O Usage Summary (final):
+   187 out of 245 (76.3%) PIO sites used.
+   187 out of 203 (92.1%) bonded PIO sites used.
+   Number of PIO comps: 186; differential: 1.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 27 / 27 (100%) | 2.5V       | -          | -          |
+| 1        | 29 / 33 ( 87%) | 2.5V       | -          | -          |
+| 2        | 31 / 32 ( 96%) | 2.5V       | -          | -          |
+| 3        | 27 / 33 ( 81%) | 2.5V       | -          | -          |
+| 6        | 28 / 33 ( 84%) | 2.5V       | -          | -          |
+| 7        | 32 / 32 (100%) | 2.5V       | -          | -          |
+| 8        | 13 / 13 (100%) | 2.5V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 24 secs 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+0 connections routed; 3725 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 39 secs 
+
+Start NBR router at Wed Jun 16 09:20:14 CEST 2021
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021
+
+Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021
+Level 1, iteration 1
+21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.876ns/-158.654ns; real time: 41 secs 
+Level 2, iteration 1
+46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-159.217ns; real time: 41 secs 
+Level 3, iteration 1
+167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.962ns/-163.305ns; real time: 42 secs 
+Level 4, iteration 1
+81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-177.384ns; real time: 42 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021
+Level 1, iteration 1
+53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-171.398ns; real time: 43 secs 
+Level 4, iteration 1
+54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 2
+35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 3
+24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 4
+12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 5
+8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 43 secs 
+Level 4, iteration 6
+5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 44 secs 
+Level 4, iteration 7
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 8
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 9
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -2.994ns/-172.896ns; real time: 44 secs 
+
+Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 156 (4.19%)
+  Estimated worst slack<setup> : -2.994ns
+  Timing score<setup> : 209210
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 46 secs 
+Total REAL time: 47 secs 
+Completely routed.
+End of route.  3725 routed (100.00%); 0 unrouted.
+
+Generating "par" statistics.
+
+
+   The Delay Summary Report
+
+   The SCORE FOR THIS DESIGN is: 284326
+
+
+   The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
+
+   The AVERAGE CONNECTION DELAY for this design is:          0.79 (  0.79)
+   The AVERAGE CONNECTION DELAY on CRITICAL NETS is:         0.00 (  0.00)
+   The CLOCK SKEW AVERAGE for this design is:                0.03
+   The MAXIMUM PIN DELAY IS:                                 4.32 (  4.32)
+   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:     3.37 (  3.37)
+
+   Listing Pin Delays by value: (nsec)
+
+    d <= 10    < d <= 20   < d <= 30   < d <= 40   < d <= 50    d > 50
+   ---------   ---------   ---------   ---------   ---------   ---------
+        3725           0           0           0           0           0
+
+Hold time timing score: 9, hold timing errors: 18
+
+
+Timing score: 209210 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -2.994
+PAR_SUMMARY::Timing score<setup/<ns>> = 209.210
+PAR_SUMMARY::Worst  slack<hold /<ns>> = -1.015
+PAR_SUMMARY::Timing score<hold /<ns>> = 9.647
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 48 secs 
+Total REAL time to completion: 48 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/impl1/s1_impl1.prf b/impl1/s1_impl1.prf
new file mode 100644
index 0000000..7f26db5
--- /dev/null
+++ b/impl1/s1_impl1.prf
@@ -0,0 +1,196 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.11.2.446 -- WARNING: Map write only section -- Wed Jun 16 09:19:31 2021
+
+SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG INBUF=OFF ;
+PGROUP "tdc0" BBOX 1 4  DEVSIZE
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271";
+LOCATE PGROUP "tdc0" SITE "R68C14D" ;
+PGROUP "tdc22" BBOX 1 4  DEVSIZE
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351";
+LOCATE PGROUP "tdc22" SITE "R66C41D" ;
+PGROUP "tdc3" BBOX 1 4  DEVSIZE
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431";
+LOCATE PGROUP "tdc3" SITE "R66C49D" ;
+PGROUP "lvl1_tdc" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514";
+LOCATE PGROUP "lvl1_tdc" SITE "R25C3D" ;
+PGROUP "hades_dec_pos" BBOX 1 6  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732";
+LOCATE PGROUP "hades_dec_pos" SITE "R27C2D" ;
+PGROUP "hades_dec_neg" BBOX 1 6  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729";
+LOCATE PGROUP "hades_dec_neg" SITE "R30C2D" ;
+PGROUP "hades_tdc_pos" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619";
+LOCATE PGROUP "hades_tdc_pos" SITE "R28C3D" ;
+PGROUP "hades_tdc_neg" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627";
+LOCATE PGROUP "hades_tdc_neg" SITE "R29C3D" ;
+PGROUP "lvl1_pad" BBOX 1 1  DEVSIZE
+	COMP "SLICE_743";
+LOCATE PGROUP "lvl1_pad" SITE "R25C2D" ;
+PGROUP "gate2" BBOX 1 1  DEVSIZE
+	COMP "SLICE_745";
+LOCATE PGROUP "gate2" SITE "R67C41D" ;
+PGROUP "trig3" BBOX 1 1  DEVSIZE
+	COMP "SLICE_746";
+LOCATE PGROUP "trig3" SITE "R67C49D" ;
+LOCATE COMP "clk" SITE "P3" ;
+LOCATE COMP "hades_lvl1" SITE "E1" ;
+LOCATE COMP "hades_trig" SITE "H5" ;
+LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9" ;
+LOCATE COMP "trig[2]" SITE "T19" ;
+LOCATE COMP "trig[1]" SITE "T3" ;
+LOCATE COMP "trig[0]" SITE "R2" ;
+FREQUENCY NET "clk_c" 100.000000 MHz ;
+FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+FREQUENCY PORT "clk" 100.000000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK NET "trig*" ;
+BLOCK NET "reset*" ;
+FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+PROHIBIT SITE "IOL_B18A" ;
+PROHIBIT SITE "IOL_B15A" ;
+PROHIBIT SITE "IOL_L29C" ;
+PROHIBIT SITE "IOL_L29B" ;
+PROHIBIT SITE "IOL_L29D" ;
+COMMERCIAL ;
diff --git a/impl1/s1_impl1.pt b/impl1/s1_impl1.pt
new file mode 100644
index 0000000..7850c7d
--- /dev/null
+++ b/impl1/s1_impl1.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+-fullname
+-gt
+-sethld
+-sp 8
+-sphld m
diff --git a/impl1/s1_impl1.srd b/impl1/s1_impl1.srd
new file mode 100644
index 0000000..36d89c3
Binary files /dev/null and b/impl1/s1_impl1.srd differ
diff --git a/impl1/s1_impl1.srf b/impl1/s1_impl1.srf
new file mode 100644
index 0000000..140bf93
--- /dev/null
+++ b/impl1/s1_impl1.srf
@@ -0,0 +1,1747 @@
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Jun 16 09:19:13 2021
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
+Premap Report
+
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Jun 16 09:19:25 2021
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS2_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS3_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: top_tf|rd_clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
diff --git a/impl1/s1_impl1.srm b/impl1/s1_impl1.srm
new file mode 100644
index 0000000..febdd83
Binary files /dev/null and b/impl1/s1_impl1.srm differ
diff --git a/impl1/s1_impl1.srr b/impl1/s1_impl1.srr
new file mode 100644
index 0000000..140bf93
--- /dev/null
+++ b/impl1/s1_impl1.srr
@@ -0,0 +1,1747 @@
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Jun 16 09:19:13 2021
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
+Premap Report
+
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Jun 16 09:19:25 2021
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS2_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS3_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: top_tf|rd_clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
diff --git a/impl1/s1_impl1.srr.db b/impl1/s1_impl1.srr.db
new file mode 100644
index 0000000..de14016
Binary files /dev/null and b/impl1/s1_impl1.srr.db differ
diff --git a/impl1/s1_impl1.srs b/impl1/s1_impl1.srs
new file mode 100644
index 0000000..2946e25
Binary files /dev/null and b/impl1/s1_impl1.srs differ
diff --git a/impl1/s1_impl1.t2b b/impl1/s1_impl1.t2b
new file mode 100644
index 0000000..f783761
--- /dev/null
+++ b/impl1/s1_impl1.t2b
@@ -0,0 +1,8 @@
+
+
+
+
+-g CfgMode:Disable
+-g RamCfg:Reset
+-g DisableUES:FALSE
+-g ES:No
diff --git a/impl1/s1_impl1.tw1 b/impl1/s1_impl1.tw1
new file mode 100644
index 0000000..324cec7
--- /dev/null
+++ b/impl1/s1_impl1.tw1
@@ -0,0 +1,639 @@
+
+Loading design for application trce from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 78 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.095ns (weighted slack = -2.190ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.537ns  (44.3% logic, 55.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      2.537ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.095ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.CLK to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5   e 0.156 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+C1TOFCO_DE  ---     0.278 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
+ROUTE         1   e 0.001 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
+FCITOF1_DE  ---     0.273 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.537   (44.3% logic, 55.7% route), 5 logic levels.
+
+Warning: 181.028MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.298ns
+         The internal maximum frequency of the following component is 370.096 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
+
+   Delay:               2.702ns -- based on Minimum Pulse Width
+
+Report:  370.096MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  181.028 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/valid_fast                        |       5|      48|     61.54%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_2_0                |      10|      46|     58.97%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_1_0_S1           |       1|      33|     42.31%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window_6[2]                       |       1|      33|     42.31%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_0                |       1|      21|     26.92%
+                                        |        |        |
+valid_fast_RNI999V                      |       9|      18|     23.08%
+                                        |        |        |
+hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
+_inst.offset_1_sqmuxa_i_0               |      11|      18|     23.08%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_4                |       1|      15|     19.23%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_2                |       1|      15|     19.23%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_c                  |       7|      14|     17.95%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/N_97                              |       3|      14|     17.95%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/discard4_0_a2_0_3                 |       3|      12|     15.38%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_s_7_0_S0             |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window_6[7]                       |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/G_25_0_a3_5_0                     |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/G_25_0_a3_4_0                     |       1|       8|     10.26%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 78  Score: 41485
+Cumulative negative slack: 24538
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]  (from pll_clks[3] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]  (to pll_clks[3] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (from pll_clks[3])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] (to pll_clks[3])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 78 (setup), 0 (hold)
+Score: 41485 (setup), 0 (hold)
+Cumulative negative slack: 24538 (24538+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/impl1/s1_impl1.twr b/impl1/s1_impl1.twr
new file mode 100644
index 0000000..b3d8a86
--- /dev/null
+++ b/impl1/s1_impl1.twr
@@ -0,0 +1,4135 @@
+
+Loading design for application trce from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 280 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.497ns (weighted slack = -2.994ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.939ns  (38.2% logic, 61.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      2.939ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.000ns skew and
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.497ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10     0.731     R29C37C.F0 to     R31C37A.A1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+C1TOFCO_DE  ---     0.278     R31C37A.A1 to    R31C37A.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
+ROUTE         1     0.000    R31C37A.FCO to    R31C37B.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
+FCITOF1_DE  ---     0.273    R31C37B.FCI to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.939   (38.2% logic, 61.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.396ns (weighted slack = -2.792ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
+
+   Delay:               3.050ns  (22.0% logic, 78.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.050ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.396ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.050   (22.0% logic, 78.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.387ns (weighted slack = -2.774ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
+
+   Delay:               3.041ns  (22.0% logic, 78.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.041ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.387ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.041   (22.0% logic, 78.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
+
+   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
+
+   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.354ns (weighted slack = -2.708ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
+
+   Delay:               3.008ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.008ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.354ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.008   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
+
+   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
+
+   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.345ns (weighted slack = -2.690ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
+
+   Delay:               2.999ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      2.999ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.345ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    2.999   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.337ns (weighted slack = -2.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.779ns  (34.7% logic, 65.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      2.779ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.000ns skew and
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.337ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10     0.730     R29C37C.F0 to     R31C37B.B0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+CTOF1_DEL   ---     0.392     R31C37B.B0 to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.779   (34.7% logic, 65.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 158.003MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.251      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.251     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C6B.CLK to      R28C6B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (from pll_clks[2])
+ROUTE         1     0.251      R28C6B.Q0 to      R28C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.251     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C51D.CLK to     R66C51D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (from pll_clks[2])
+ROUTE         1     0.251     R66C51D.Q0 to     R66C51A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C14B.CLK to     R68C14B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (from pll_clks[2])
+ROUTE         1     0.251     R68C14B.Q0 to     R68C14A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R25C5D.CLK to      R25C5D.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (from pll_clks[2])
+ROUTE         1     0.251      R25C5D.Q0 to      R25C5A.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.251     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C41B.CLK to     R66C41B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (from pll_clks[2])
+ROUTE         1     0.251     R66C41B.Q0 to     R66C41A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C3D.CLK to      R29C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 (from pll_clks[2])
+ROUTE         1     0.251      R29C3D.Q0 to      R29C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.685ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.765ns  (40.4% logic, 59.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.765ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.685ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C16C.CLK to     R68C16C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1     0.456     R68C16C.Q0 to     R68C16A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.765   (40.4% logic, 59.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.840ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.610ns  (50.5% logic, 49.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.610ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.840ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.308    R68C16C.CLK to     R68C16C.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1     0.302     R68C16C.Q1 to     R68C16C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.610   (50.5% logic, 49.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.251      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.251     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C6D.CLK to      R29C6D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 (from pll_clks[1])
+ROUTE         1     0.251      R29C6D.Q0 to      R29C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C14D.CLK to     R68C14D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (from pll_clks[1])
+ROUTE         1     0.251     R68C14D.Q0 to     R68C14C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C50C.CLK to     R66C50C.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (from pll_clks[1])
+ROUTE         1     0.251     R66C50C.Q0 to     R66C50B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.251      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C5C.CLK to      R28C5C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (from pll_clks[1])
+ROUTE         1     0.251      R28C5C.Q0 to      R28C5A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.251     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.251      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.251     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C4D.CLK to      R28C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (from pll_clks[0])
+ROUTE         1     0.251      R28C4D.Q0 to      R28C4C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.251     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C52D.CLK to     R66C52D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (from pll_clks[0])
+ROUTE         1     0.251     R66C52D.Q0 to     R66C52A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C15C.CLK to     R68C15C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (from pll_clks[0])
+ROUTE         1     0.251     R68C15C.Q0 to     R68C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R25C5B.CLK to      R25C5B.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (from pll_clks[0])
+ROUTE         1     0.251      R25C5B.Q0 to      R25C5C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.251     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C43D.CLK to     R66C43D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (from pll_clks[0])
+ROUTE         1     0.251     R66C43D.Q0 to     R66C43A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C3B.CLK to      R29C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 (from pll_clks[0])
+ROUTE         1     0.251      R29C3B.Q0 to      R29C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.298ns
+         The internal maximum frequency of the following component is 370.096 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
+
+   Delay:               2.702ns -- based on Minimum Pulse Width
+
+Report:  370.096MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  158.003 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/N_97                              |       3|     141|     50.36%
+                                        |        |        |
+hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
+_inst.offset_1_sqmuxa_i_0               |      11|     130|     46.43%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/discard4_0_a2_0_3                 |       3|     122|     43.57%
+                                        |        |        |
+valid_fast_RNI999V                      |       9|      82|     29.29%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/valid_fast                        |       5|      82|     29.29%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_2_0                |      10|      66|     23.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_c                  |       7|      52|     18.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window[7]                         |       3|      45|     16.07%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window[5]                         |       3|      45|     16.07%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_4                |       1|      44|     15.71%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window_6[2]                       |       1|      44|     15.71%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_1_0_S1           |       1|      43|     15.36%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_2                |       1|      38|     13.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_0                |       1|      33|     11.79%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 280  Score: 209210
+Cumulative negative slack: 139580
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 18 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.328ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R29C3C.CLK to      R29C3C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 (from pll_clks[0])
+ROUTE         1     0.195      R29C3C.Q0 to      R30C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] (to pll_clks[3])
+                  --------
+                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R30C3B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 1.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.328ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R68C15A.CLK to     R68C15A.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (from pll_clks[0])
+ROUTE         1     0.195     R68C15A.Q0 to     R66C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 1.000ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.343ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.000ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R25C5C.CLK to      R25C5C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (from pll_clks[0])
+ROUTE         1     0.210      R25C5C.Q0 to      R25C8C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.939ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.404ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.939ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R28C4C.CLK to      R28C4C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (from pll_clks[0])
+ROUTE         1     0.271      R28C4C.Q0 to      R27C6B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R27C6B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.928ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.415ns  (32.0% logic, 68.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.415ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.928ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C52A.CLK to     R66C52A.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (from pll_clks[0])
+ROUTE         1     0.282     R66C52A.Q0 to     R66C47D.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.415   (32.0% logic, 68.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.914ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.429ns  (31.0% logic, 69.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.429ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.914ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C43A.CLK to     R66C43A.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (from pll_clks[0])
+ROUTE         1     0.296     R66C43A.Q0 to     R66C39B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.429   (31.0% logic, 69.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.588ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.340ns  (39.1% logic, 60.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.340ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.588ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C41C.CLK to     R66C41C.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (from pll_clks[1])
+ROUTE         1     0.207     R66C41C.Q0 to     R66C39B.M1 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.340   (39.1% logic, 60.9% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C41C.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.585ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.343ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.585ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C50B.CLK to     R66C50B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (from pll_clks[1])
+ROUTE         1     0.210     R66C50B.Q0 to     R66C47D.M1 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.353ns  (37.7% logic, 62.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.353ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.575ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R25C4A.CLK to      R25C4A.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (from pll_clks[1])
+ROUTE         1     0.220      R25C4A.Q0 to      R25C8C.M1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.353   (37.7% logic, 62.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C4A.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.524ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.404ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.524ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R68C14C.CLK to     R68C14C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (from pll_clks[1])
+ROUTE         1     0.271     R68C14C.Q0 to     R66C15A.M1 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C52B.CLK to     R66C52B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.119     R66C52B.Q1 to     R66C52B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R68C15B.CLK to     R68C15B.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.119     R68C15B.Q1 to     R68C15B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C3B.CLK to      R28C3B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.119      R28C3B.Q1 to      R28C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C42D.CLK to     R66C42D.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.119     R66C42D.Q1 to     R66C42D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C4B.CLK to      R25C4B.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (from pll_clks[2])
+ROUTE         1     0.119      R25C4B.Q1 to      R25C4B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C5B.CLK to      R29C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 (from pll_clks[2])
+ROUTE         1     0.119      R29C5B.Q1 to      R29C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.119     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.119      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.119     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.119     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C3C.CLK to      R25C3C.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.119      R25C3C.Q1 to      R25C3C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C44B.CLK to     R66C44B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.119     R66C44B.Q1 to     R66C44B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C4D.CLK to      R29C4D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
+ROUTE         1     0.119      R29C4D.Q1 to      R29C4D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C51B.CLK to     R66C51B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.119     R66C51B.Q1 to     R66C51B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C3D.CLK to      R28C3D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.119      R28C3D.Q1 to      R28C3D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.119     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.119      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.119      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R29C4D.CLK to      R29C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
+ROUTE         1     0.119      R29C4D.Q0 to      R29C4A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4A.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.119     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C49B.CLK to     R66C49B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.119     R66C49B.Q1 to     R66C49B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R68C16D.CLK to     R68C16D.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.119     R68C16D.Q1 to     R68C16D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C5B.CLK to      R28C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.119      R28C5B.Q1 to      R28C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C43B.CLK to     R66C43B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.119     R66C43B.Q1 to     R66C43B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C6D.CLK to      R25C6D.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (from pll_clks[0])
+ROUTE         1     0.119      R25C6D.Q1 to      R25C6D.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C4B.CLK to      R29C4B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 (from pll_clks[0])
+ROUTE         1     0.119      R29C4B.Q1 to      R29C4B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.119     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.119      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.119     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.119     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|    -1.015 ns|   1 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+No net is responsible for more than 10% of the timing errors.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 18  Score: 9647
+Cumulative negative slack: 9647
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 280 (setup), 18 (hold)
+Score: 209210 (setup), 9647 (hold)
+Cumulative negative slack: 149227 (139580+9647)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/impl1/s1_impl1_bgn.html b/impl1/s1_impl1_bgn.html
new file mode 100644
index 0000000..f66e157
--- /dev/null
+++ b/impl1/s1_impl1_bgn.html
@@ -0,0 +1,146 @@
+<HTML>
+<HEAD><TITLE>Bitgen Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.2.446
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed May 26 19:56:50 2021
+
+
+Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s /home/hadaq/mmichalek/lattice/simplified/s1.sec -k /home/hadaq/mmichalek/lattice/simplified/s1.bek -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+
+Loading design for application Bitgen from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application Bitgen from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from s1_impl1.prf.
+
+<A name="bgn_ps"></A>
+<B><U><big>Preference Summary:</big></U></B>
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                        CfgMode  |                      Disable**  |
++---------------------------------+---------------------------------+
+|                        DONE_EX  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                        DONE_OD  |                           ON**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                          2.4**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                    CONFIG_MODE  |                         JTAG**  |
++---------------------------------+---------------------------------+
+|                        WAKE_UP  |                           21**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                     DisableUES  |                        FALSE**  |
++---------------------------------+---------------------------------+
+|            SLAVE_PARALLEL_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                      DONE_PULL  |                           ON**  |
++---------------------------------+---------------------------------+
+|               CONFIG_IOVOLTAGE  |                          2.5**  |
++---------------------------------+---------------------------------+
+|                        TRANSFR  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 10.27.
+ 
+Saving bit stream in "s1_impl1.bit".
+Total CPU Time: 11 secs 
+Total REAL Time: 12 secs 
+Peak Memory Usage: 576 MB
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_cck.rpt b/impl1/s1_impl1_cck.rpt
new file mode 100644
index 0000000..298f602
--- /dev/null
+++ b/impl1/s1_impl1_cck.rpt
@@ -0,0 +1,274 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+
+# Written on Wed Jun 16 09:19:18 2021
+
+##### DESIGN INFO #######################################################
+
+Top View:                "top_tf"
+Constraint File(s):      (none)
+
+
+
+
+##### SUMMARY ############################################################
+
+Found 0 issues in 0 out of 0 constraints
+
+
+##### DETAILS ############################################################
+
+
+
+Clock Relationships
+*******************
+
+Starting                       Ending                         |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         pll0|CLKOS3_inferred_clock     |     5.000            |     No paths         |     No paths         |     No paths                         
+System                         top_tf|rd_clk                  |     5.000            |     No paths         |     No paths         |     No paths                         
+pll0|CLKOS3_inferred_clock     System                         |     5.000            |     No paths         |     No paths         |     5.000                            
+pll0|CLKOS3_inferred_clock     pll0|CLKOS3_inferred_clock     |     5.000            |     5.000            |     2.500            |     2.500                            
+pll0|CLKOS3_inferred_clock     top_tf|rd_clk                  |     Diff grp         |     No paths         |     No paths         |     No paths                         
+pll0|CLKOP_inferred_clock      pll0|CLKOS3_inferred_clock     |     No paths         |     Diff grp         |     Diff grp         |     No paths                         
+pll0|CLKOP_inferred_clock      pll0|CLKOP_inferred_clock      |     5.000            |     5.000            |     No paths         |     No paths                         
+pll0|CLKOS_inferred_clock      pll0|CLKOS3_inferred_clock     |     No paths         |     Diff grp         |     Diff grp         |     No paths                         
+pll0|CLKOS_inferred_clock      pll0|CLKOS_inferred_clock      |     5.000            |     5.000            |     No paths         |     No paths                         
+pll0|CLKOS2_inferred_clock     pll0|CLKOS3_inferred_clock     |     No paths         |     Diff grp         |     Diff grp         |     No paths                         
+pll0|CLKOS2_inferred_clock     pll0|CLKOS2_inferred_clock     |     5.000            |     5.000            |     No paths         |     No paths                         
+top_tf|rd_clk                  System                         |     5.000            |     No paths         |     No paths         |     No paths                         
+top_tf|rd_clk                  pll0|CLKOS3_inferred_clock     |     Diff grp         |     No paths         |     No paths         |     No paths                         
+top_tf|rd_clk                  top_tf|rd_clk                  |     5.000            |     No paths         |     No paths         |     No paths                         
+=========================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+Unconstrained Start/End Points
+******************************
+
+p:FEE_DATAFINISHED_OUT
+p:FEE_DATA_OUT[0]
+p:FEE_DATA_OUT[1]
+p:FEE_DATA_OUT[2]
+p:FEE_DATA_OUT[3]
+p:FEE_DATA_OUT[4]
+p:FEE_DATA_OUT[5]
+p:FEE_DATA_OUT[6]
+p:FEE_DATA_OUT[7]
+p:FEE_DATA_OUT[8]
+p:FEE_DATA_OUT[9]
+p:FEE_DATA_OUT[10]
+p:FEE_DATA_OUT[11]
+p:FEE_DATA_OUT[12]
+p:FEE_DATA_OUT[13]
+p:FEE_DATA_OUT[14]
+p:FEE_DATA_OUT[15]
+p:FEE_DATA_OUT[16]
+p:FEE_DATA_OUT[17]
+p:FEE_DATA_OUT[18]
+p:FEE_DATA_OUT[19]
+p:FEE_DATA_OUT[20]
+p:FEE_DATA_OUT[21]
+p:FEE_DATA_OUT[22]
+p:FEE_DATA_OUT[23]
+p:FEE_DATA_OUT[24]
+p:FEE_DATA_OUT[25]
+p:FEE_DATA_OUT[26]
+p:FEE_DATA_OUT[27]
+p:FEE_DATA_OUT[28]
+p:FEE_DATA_OUT[29]
+p:FEE_DATA_OUT[30]
+p:FEE_DATA_OUT[31]
+p:FEE_DATA_WRITE_OUT
+p:FEE_TRG_RELEASE_OUT
+p:LVL1_INVALID_TRG_IN
+p:LVL1_TRG_DATA_VALID_IN
+p:LVL1_TRG_DATA_VALI_IN_rising
+p:burst
+p:clk
+p:discard
+p:fifo_data_out[0]
+p:fifo_data_out[1]
+p:fifo_data_out[2]
+p:fifo_data_out[3]
+p:fifo_data_out[4]
+p:fifo_data_out[5]
+p:fifo_data_out[6]
+p:fifo_data_out[7]
+p:fifo_data_out[8]
+p:fifo_data_out[9]
+p:fifo_data_out[10]
+p:fifo_data_out[11]
+p:fifo_data_out[12]
+p:fifo_data_out[13]
+p:fifo_data_out[14]
+p:fifo_data_out[15]
+p:fifo_data_out[16]
+p:fifo_data_out[17]
+p:fifo_data_out[18]
+p:fifo_data_out[19]
+p:fifo_data_out[20]
+p:fifo_data_out[21]
+p:fifo_data_out[22]
+p:fifo_data_out[23]
+p:fifo_data_out[24]
+p:fifo_data_out[25]
+p:fifo_data_out[26]
+p:fifo_data_out[27]
+p:fifo_data_out[28]
+p:fifo_data_out[29]
+p:fifo_data_out[30]
+p:fifo_data_out[31]
+p:fifo_empty1
+p:fifo_rden
+p:finished
+p:hades_buf_drop[0]
+p:hades_buf_drop[1]
+p:hades_buf_drop[2]
+p:hades_buf_drop[3]
+p:hades_buf_finished
+p:hades_buf_out_valid
+p:hades_buf_release
+p:hades_dbg2_coarse[0]
+p:hades_dbg2_coarse[1]
+p:hades_dbg2_coarse[2]
+p:hades_dbg2_coarse[3]
+p:hades_dbg2_coarse[4]
+p:hades_dbg2_coarse[5]
+p:hades_dbg2_coarse[6]
+p:hades_dbg2_coarse[7]
+p:hades_dbg2_coarse[8]
+p:hades_dbg2_out[0]
+p:hades_dbg2_out[1]
+p:hades_dbg2_out[2]
+p:hades_dbg2_out[3]
+p:hades_dbg2_out[4]
+p:hades_dbg2_out[5]
+p:hades_dbg2_out[6]
+p:hades_dbg2_out[7]
+p:hades_dbg2_out[8]
+p:hades_dbg2_out[9]
+p:hades_dbg2_out[10]
+p:hades_dbg2_out[11]
+p:hades_dbg2_out[12]
+p:hades_dbg2_out[13]
+p:hades_dbg2_out[14]
+p:hades_dbg2_out[15]
+p:hades_dbg2_out[16]
+p:hades_dbg2_out[17]
+p:hades_dbg2_out[18]
+p:hades_dbg2_out[19]
+p:hades_dbg2_out[20]
+p:hades_dbg2_out[21]
+p:hades_dbg2_out[22]
+p:hades_dbg2_out[23]
+p:hades_dbg2_out[24]
+p:hades_dbg2_out[25]
+p:hades_dbg2_out[26]
+p:hades_dbg2_out[27]
+p:hades_dbg2_out[28]
+p:hades_dbg2_out[29]
+p:hades_dbg2_out[30]
+p:hades_dbg2_out[31]
+p:hades_discard
+p:hades_drop_cmp_buf[0]
+p:hades_drop_cmp_buf[1]
+p:hades_drop_cmp_buf[2]
+p:hades_drop_cmp_buf[3]
+p:hades_drop_cmp_buf[4]
+p:hades_drop_cmp_buf[5]
+p:hades_drop_cmp_buf[6]
+p:hades_drop_cmp_buf[7]
+p:hades_drop_cmp_buf[8]
+p:hades_drop_cmp_buf[9]
+p:hades_drop_cmp_buf[10]
+p:hades_drop_cmp_buf[11]
+p:hades_drop_cmp_buf_coarse[0]
+p:hades_drop_cmp_buf_coarse[1]
+p:hades_drop_cmp_buf_coarse[2]
+p:hades_drop_cmp_buf_coarse[3]
+p:hades_drop_cmp_buf_coarse[4]
+p:hades_drop_cmp_buf_coarse[5]
+p:hades_drop_cmp_buf_coarse[6]
+p:hades_drop_cmp_buf_coarse[7]
+p:hades_drop_cmp_buf_coarse[8]
+p:hades_drop_cmp_buf_coarse[9]
+p:hades_drop_cmp_buf_coarse[10]
+p:hades_drop_cmp_buf_coarse[11]
+p:hades_drop_cmp_buf_valid
+p:hades_hit_out_i[0]
+p:hades_hit_out_i[1]
+p:hades_hit_out_i[2]
+p:hades_hit_out_i[3]
+p:hades_hit_valid[0]
+p:hades_hit_valid[1]
+p:hades_hit_valid[2]
+p:hades_hit_valid[3]
+p:hades_invalid_dl[0]
+p:hades_invalid_dl[1]
+p:hades_invalid_dl[2]
+p:hades_invalid_dl[3]
+p:hades_lvl1
+p:hades_lvl1_invalid
+p:hades_offset[0]
+p:hades_offset[1]
+p:hades_offset[2]
+p:hades_offset[3]
+p:hades_offset[4]
+p:hades_offset[5]
+p:hades_offset[6]
+p:hades_offset[7]
+p:hades_offset[8]
+p:hades_offset_valid
+p:hades_raw_out_valid
+p:hades_raw_valid_vect[0]
+p:hades_raw_valid_vect[1]
+p:hades_trig
+p:hades_window_end
+p:last_buf_empty
+p:release_out
+p:reset_dc
+p:trig[0]
+p:trig[1]
+p:trig[2]
+
+
+Inapplicable constraints
+************************
+
+(none)
+
+
+Applicable constraints with issues
+**********************************
+
+(none)
+
+
+Constraints with matching wildcard expressions
+**********************************************
+
+(none)
+
+
+Library Report
+**************
+
+
+# End of Constraint Checker Report
diff --git a/impl1/s1_impl1_cck.rpt.db b/impl1/s1_impl1_cck.rpt.db
new file mode 100644
index 0000000..33612a2
Binary files /dev/null and b/impl1/s1_impl1_cck.rpt.db differ
diff --git a/impl1/s1_impl1_iotiming.html b/impl1/s1_impl1_iotiming.html
new file mode 100644
index 0000000..c3584bb
--- /dev/null
+++ b/impl1/s1_impl1_iotiming.html
@@ -0,0 +1,269 @@
+<HTML>
+<HEAD><TITLE>I/O Timing Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
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a:visited {
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background-color: #00ff00;
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.comment
{
    font-size: 90%;
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+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 9
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Loading design for application iotiming from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: M
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+// Design: top_tf
+// Package: CABGA381
+// ncd File: s1_impl1.ncd
+// Version: Diamond (64-bit) 3.11.2.446
+// Written on Wed Jun 16 09:20:37 2021
+// M: Minimum Performance Grade
+// iotiming s1_impl1.ncd s1_impl1.prf -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 9, 8):
+
+// Input Setup and Hold Times
+
+Port                   Clock  Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+LVL1_INVALID_TRG_IN    rd_clk R    -0.242      M       2.049     8
+LVL1_TRG_DATA_VALID_IN rd_clk R    -0.242      M       2.049     8
+hades_lvl1             clk    F     2.162      8       1.169     M
+hades_lvl1_invalid     clk    R    -0.529      8       1.138     M
+hades_trig             clk    F     2.282      8       0.712     M
+
+
+// Clock to Output Delay
+
+Port                         Clock  Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+FEE_DATAFINISHED_OUT         rd_clk R     5.311         8        2.067          M
+FEE_DATA_OUT[0]              rd_clk R     8.637         8        5.249          M
+FEE_DATA_OUT[10]             rd_clk R     7.965         8        4.919          M
+FEE_DATA_OUT[11]             rd_clk R     8.348         8        5.096          M
+FEE_DATA_OUT[12]             rd_clk R     8.295         8        5.082          M
+FEE_DATA_OUT[13]             rd_clk R     8.705         8        5.299          M
+FEE_DATA_OUT[14]             rd_clk R     8.495         8        5.173          M
+FEE_DATA_OUT[15]             rd_clk R     8.386         8        5.119          M
+FEE_DATA_OUT[16]             rd_clk R     9.036         8        5.453          M
+FEE_DATA_OUT[17]             rd_clk R     8.626         8        5.229          M
+FEE_DATA_OUT[18]             rd_clk R     8.622         8        5.246          M
+FEE_DATA_OUT[19]             rd_clk R     8.108         8        4.987          M
+FEE_DATA_OUT[1]              rd_clk R     8.763         8        5.277          M
+FEE_DATA_OUT[20]             rd_clk R     8.695         8        5.268          M
+FEE_DATA_OUT[21]             rd_clk R     8.276         8        5.092          M
+FEE_DATA_OUT[22]             rd_clk R     8.532         8        5.199          M
+FEE_DATA_OUT[23]             rd_clk R     8.304         8        5.100          M
+FEE_DATA_OUT[24]             rd_clk R     8.280         8        5.083          M
+FEE_DATA_OUT[25]             rd_clk R     8.697         8        5.287          M
+FEE_DATA_OUT[26]             rd_clk R     8.529         8        5.194          M
+FEE_DATA_OUT[27]             rd_clk R     8.687         8        5.296          M
+FEE_DATA_OUT[28]             rd_clk R     8.632         8        5.249          M
+FEE_DATA_OUT[29]             rd_clk R     8.555         8        5.214          M
+FEE_DATA_OUT[2]              rd_clk R     8.715         8        5.294          M
+FEE_DATA_OUT[30]             rd_clk R     8.514         8        5.199          M
+FEE_DATA_OUT[31]             rd_clk R     8.519         8        5.194          M
+FEE_DATA_OUT[3]              rd_clk R     8.357         8        5.108          M
+FEE_DATA_OUT[4]              rd_clk R     8.716         8        5.293          M
+FEE_DATA_OUT[5]              rd_clk R     8.884         8        5.392          M
+FEE_DATA_OUT[6]              rd_clk R     8.803         8        5.322          M
+FEE_DATA_OUT[7]              rd_clk R     8.785         8        5.315          M
+FEE_DATA_OUT[8]              rd_clk R     8.395         8        5.107          M
+FEE_DATA_OUT[9]              rd_clk R     8.309         8        5.083          M
+FEE_DATA_WRITE_OUT           rd_clk R     5.311         8        2.067          M
+FEE_TRG_RELEASE_OUT          rd_clk R     5.311         8        2.067          M
+LVL1_TRG_DATA_VALI_IN_rising rd_clk R     5.988         8        2.652          M
+burst                        rd_clk R     5.985         8        2.605          M
+discard                      rd_clk R     5.080         8        2.333          M
+fifo_data_out[0]             rd_clk R     8.408         8        5.132          M
+fifo_data_out[10]            rd_clk R     7.965         8        4.919          M
+fifo_data_out[11]            rd_clk R     8.348         8        5.096          M
+fifo_data_out[12]            rd_clk R     8.448         8        5.158          M
+fifo_data_out[13]            rd_clk R     8.654         8        5.273          M
+fifo_data_out[14]            rd_clk R     8.648         8        5.249          M
+fifo_data_out[15]            rd_clk R     7.943         8        4.904          M
+fifo_data_out[16]            rd_clk R     9.189         8        5.529          M
+fifo_data_out[17]            rd_clk R     8.779         8        5.305          M
+fifo_data_out[18]            rd_clk R     9.117         8        5.486          M
+fifo_data_out[19]            rd_clk R     8.108         8        4.987          M
+fifo_data_out[1]             rd_clk R     8.763         8        5.277          M
+fifo_data_out[20]            rd_clk R     8.873         8        5.361          M
+fifo_data_out[21]            rd_clk R     8.150         8        5.026          M
+fifo_data_out[22]            rd_clk R     8.710         8        5.292          M
+fifo_data_out[23]            rd_clk R     8.304         8        5.100          M
+fifo_data_out[24]            rd_clk R     8.545         8        5.205          M
+fifo_data_out[25]            rd_clk R     8.697         8        5.287          M
+fifo_data_out[26]            rd_clk R     8.682         8        5.269          M
+fifo_data_out[27]            rd_clk R     8.687         8        5.296          M
+fifo_data_out[28]            rd_clk R     8.785         8        5.324          M
+fifo_data_out[29]            rd_clk R     8.555         8        5.214          M
+fifo_data_out[2]             rd_clk R     8.715         8        5.294          M
+fifo_data_out[30]            rd_clk R     8.514         8        5.199          M
+fifo_data_out[31]            rd_clk R     8.672         8        5.269          M
+fifo_data_out[3]             rd_clk R     8.357         8        5.108          M
+fifo_data_out[4]             rd_clk R     8.716         8        5.293          M
+fifo_data_out[5]             rd_clk R     9.037         8        5.468          M
+fifo_data_out[6]             rd_clk R     8.957         8        5.398          M
+fifo_data_out[7]             rd_clk R     8.963         8        5.408          M
+fifo_data_out[8]             rd_clk R     8.395         8        5.107          M
+fifo_data_out[9]             rd_clk R     8.462         8        5.159          M
+fifo_empty1                  clk    R     6.338         8        3.901          M
+fifo_rden                    rd_clk R     9.015         8        4.309          M
+finished                     rd_clk R     5.699         8        2.640          M
+hades_buf_drop[1]            clk    R     4.373         8        2.516          M
+hades_buf_finished           clk    R     5.004         8        3.223          M
+hades_buf_out_valid          clk    R     4.373         8        2.516          M
+hades_buf_release            clk    R     5.056         8        3.233          M
+hades_dbg2_coarse[0]         clk    R     5.517         8        3.457          M
+hades_dbg2_coarse[1]         clk    R     5.565         8        3.485          M
+hades_dbg2_coarse[2]         clk    R     6.422         8        3.891          M
+hades_dbg2_coarse[3]         clk    R     5.749         8        3.576          M
+hades_dbg2_coarse[4]         clk    R     6.730         8        4.066          M
+hades_dbg2_coarse[5]         clk    R     6.629         8        3.989          M
+hades_dbg2_coarse[6]         clk    R     6.270         8        3.843          M
+hades_dbg2_coarse[7]         clk    R     7.034         8        4.220          M
+hades_dbg2_coarse[8]         clk    R     6.138         8        3.750          M
+hades_dbg2_out[0]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[10]           clk    R     5.455         8        3.421          M
+hades_dbg2_out[11]           clk    R     5.684         8        3.543          M
+hades_dbg2_out[12]           clk    R     5.446         8        3.434          M
+hades_dbg2_out[16]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[17]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[18]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[1]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[20]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[21]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[22]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[23]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[24]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[25]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[26]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[27]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[28]           clk    R     4.373         8        2.516          M
+hades_dbg2_out[2]            clk    R     4.373         8        2.516          M
+hades_dbg2_out[4]            clk    R     5.601         8        3.511          M
+hades_dbg2_out[5]            clk    R     5.147         8        3.282          M
+hades_dbg2_out[6]            clk    R     5.274         8        3.349          M
+hades_dbg2_out[7]            clk    R     5.147         8        3.282          M
+hades_dbg2_out[8]            clk    R     5.245         8        3.329          M
+hades_dbg2_out[9]            clk    R     5.236         8        3.332          M
+hades_discard                clk    R     5.876         8        3.609          M
+hades_drop_cmp_buf[0]        clk    R     4.849         8        3.145          M
+hades_drop_cmp_buf[1]        clk    R     5.102         8        3.255          M
+hades_drop_cmp_buf[2]        clk    R     5.292         8        3.360          M
+hades_drop_cmp_buf[3]        clk    R     5.275         8        3.342          M
+hades_drop_cmp_buf[4]        clk    R     5.205         8        3.328          M
+hades_drop_cmp_buf[5]        clk    R     5.149         8        3.303          M
+hades_drop_cmp_buf[6]        clk    R     4.937         8        3.174          M
+hades_drop_cmp_buf[7]        clk    R     5.330         8        3.397          M
+hades_drop_cmp_buf[8]        clk    R     5.190         8        3.317          M
+hades_drop_cmp_buf_coarse[0] clk    R     5.257         8        3.329          M
+hades_drop_cmp_buf_coarse[1] clk    R     5.665         8        3.523          M
+hades_drop_cmp_buf_coarse[2] clk    R     5.260         8        3.330          M
+hades_drop_cmp_buf_coarse[3] clk    R     5.770         8        3.582          M
+hades_drop_cmp_buf_coarse[4] clk    R     5.512         8        3.459          M
+hades_drop_cmp_buf_coarse[5] clk    R     5.675         8        3.526          M
+hades_drop_cmp_buf_coarse[6] clk    R     5.490         8        3.439          M
+hades_drop_cmp_buf_coarse[7] clk    R     5.333         8        3.360          M
+hades_drop_cmp_buf_coarse[8] clk    R     5.655         8        3.532          M
+hades_drop_cmp_buf_coarse[9] clk    R     5.740         8        3.562          M
+hades_drop_cmp_buf_valid     clk    R     5.087         8        3.238          M
+hades_hit_out_i[0]           clk    R     5.277         8        3.312          M
+hades_hit_out_i[1]           clk    R     5.091         8        3.241          M
+hades_hit_out_i[2]           clk    R     5.226         8        3.328          M
+hades_hit_out_i[3]           clk    R     5.455         8        3.423          M
+hades_hit_valid[0]           clk    R     4.969         8        3.196          M
+hades_hit_valid[1]           clk    R     4.807         8        3.119          M
+hades_hit_valid[2]           clk    R     4.969         8        3.196          M
+hades_hit_valid[3]           clk    R     4.695         8        3.062          M
+hades_invalid_dl[0]          clk    R     4.420         8        2.938          M
+hades_invalid_dl[1]          clk    R     5.004         8        3.220          M
+hades_invalid_dl[2]          clk    R     4.671         8        3.052          M
+hades_invalid_dl[3]          clk    R     4.976         8        3.211          M
+hades_offset[0]              clk    R     4.373         8        2.516          M
+hades_offset[1]              clk    R     4.373         8        2.516          M
+hades_offset[2]              clk    R     4.373         8        2.516          M
+hades_offset[3]              clk    R     4.373         8        2.516          M
+hades_offset[4]              clk    R     4.373         8        2.516          M
+hades_offset[5]              clk    R     4.373         8        2.516          M
+hades_offset[6]              clk    R     4.373         8        2.516          M
+hades_offset[7]              clk    R     4.373         8        2.516          M
+hades_offset[8]              clk    R     4.373         8        2.516          M
+hades_offset_valid           clk    R     6.416         8        3.925          M
+hades_raw_out_valid          clk    R     4.373         8        2.516          M
+hades_window_end             clk    R     6.286         8        3.867          M
+last_buf_empty               rd_clk R     7.396         8        3.504          M
+release_out                  rd_clk R     6.079         8        2.759          M
+WARNING: you must also run trce with hold speed: 8
+WARNING: you must also run trce with setup speed: M
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
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diff --git a/impl1/s1_impl1_lattice.synproj b/impl1/s1_impl1_lattice.synproj
new file mode 100644
index 0000000..fa95682
--- /dev/null
+++ b/impl1/s1_impl1_lattice.synproj
@@ -0,0 +1,41 @@
+-a "ECP5UM5G"
+-d LFE5UM5G-45F
+-t CABGA381
+-s 8
+-frequency 200
+-optimization_goal Timing
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 0
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+-ifd
+-lpf 1
+-p "/home/hadaq/mmichalek/lattice/simplified"
+-ver "/home/hadaq/mmichalek/lattice/simplified/top.v"
+-top top
+
+
+-p "/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data" "/home/hadaq/mmichalek/lattice/simplified/impl1" "/home/hadaq/mmichalek/lattice/simplified"
+
+-ngd "s1_impl1.ngd"
+
diff --git a/impl1/s1_impl1_map.asd b/impl1/s1_impl1_map.asd
new file mode 100644
index 0000000..d2dd4e1
--- /dev/null
+++ b/impl1/s1_impl1_map.asd
@@ -0,0 +1,96 @@
+[ActiveSupport MAP]
+Device = LFE5UM5G-45F;
+Package = CABGA381;
+Performance = 8;
+LUTS_avail = 43848;
+LUTS_used = 630;
+FF_avail = 44051;
+FF_used = 934;
+INPUT_LVCMOS25 = 10;
+INPUT_LVDS = 1;
+OUTPUT_LVCMOS25 = 175;
+IO_avail = 203;
+IO_used = 187;
+EBR_avail = 108;
+EBR_used = 4;
+;
+; start of DSP statistics
+MULT18X18D = 0;
+MULT9X9D = 0;
+ALU54B = 0;
+ALU24B = 0;
+PRADD18A = 0;
+PRADD9A = 0;
+DSP_MULT_avail = 144;
+DSP_MULT_used = 0;
+DSP_ALU_avail = 72;
+DSP_ALU_used = 0;
+DSP_PRADD_avail = 144;
+DSP_PRADD_used = 0;
+; end of DSP statistics
+;
+; Begin EBR Section
+Instance_Name = fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1;
+Type = PDPW16KD;
+Width = 32;
+Depth_R = 512;
+Depth_W = 512;
+REGMODE = NOREG;
+RESETMODE = ASYNC;
+ASYNC_RESET_RELEASE = SYNC;
+GSR = DISABLED;
+MEM_LPC_FILE = fifo40_dc.lpc;
+Instance_Name = genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0;
+Type = PDPW16KD;
+Width = 24;
+Depth_R = 512;
+Depth_W = 512;
+REGMODE = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+GSR = DISABLED;
+MEM_LPC_FILE = fifo32dc.lpc;
+Instance_Name = genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0;
+Type = PDPW16KD;
+Width = 24;
+Depth_R = 512;
+Depth_W = 512;
+REGMODE = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+GSR = DISABLED;
+MEM_LPC_FILE = fifo32dc.lpc;
+Instance_Name = genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0;
+Type = PDPW16KD;
+Width = 24;
+Depth_R = 512;
+Depth_W = 512;
+REGMODE = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+GSR = DISABLED;
+MEM_LPC_FILE = fifo32dc.lpc;
+; End EBR Section
+; Begin PLL Section
+Instance_Name = pll0inst/PLLInst_0;
+Type = EHXPLLL;
+CLKOP_Post_Divider_A_Input = DIVA;
+CLKOS_Post_Divider_B_Input = DIVB;
+CLKOS2_Post_Divider_C_Input = DIVC;
+CLKOS3_Post_Divider_D_Input = DIVD;
+FB_MODE = CLKOP;
+CLKI_Divider = 1;
+CLKFB_Divider = 3;
+CLKOP_Divider = 2;
+CLKOS_Divider = 2;
+CLKOS2_Divider = 2;
+CLKOS3_Divider = 2;
+CLKOP_Desired_Phase_Shift(degree) = 0;
+CLKOP_Trim_Option_Rising/Falling = FALLING;
+CLKOP_Trim_Option_Delay = 0;
+CLKOS_Desired_Phase_Shift(degree) = 45;
+CLKOS_Trim_Option_Rising/Falling = FALLING;
+CLKOS_Trim_Option_Delay = 0;
+CLKOS2_Desired_Phase_Shift(degree) = 90;
+CLKOS3_Desired_Phase_Shift(degree) = 135;
+; End PLL Section
diff --git a/impl1/s1_impl1_map.cam b/impl1/s1_impl1_map.cam
new file mode 100644
index 0000000..439d2ae
--- /dev/null
+++ b/impl1/s1_impl1_map.cam
@@ -0,0 +1,473 @@
+[ START MERGED ]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty[2]
+genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN pll_clks[3]
+genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.CN pll_clks[2]
+genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.CN pll_clks[1]
+genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.CN pll_clks[0]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty[1]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty1_c
+fifo_colector_inst/fifo40_inst/invout_0 last_buf_empty_c
+fifo_colector_inst/fifo40_inst/invout_1 fifo_colector_inst/fifo40_inst/Full
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg hades_trig_c
+reset_dl_i[2] reset_dl[2]
+[ END MERGED ]
+[ START CLIPPED ]
+GND
+VCC
+hades_tdc_bundle_inst/VCC
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC
+fifo_colector_inst/fifo40_inst/VCC
+fifo_colector_inst/fifo40_inst/rRst
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst
+pll0inst/CLKINTFB
+pll0inst/REFCLK
+pll0inst/INTLOCK
+pll0inst/LOCK
+hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1
+hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0
+hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1
+hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0
+hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1
+hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0
+hades_tdc_bundle_inst/N_73
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0_COUT
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0_COUT
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0_S1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0_S0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2
+hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1
+hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT
+fifo_colector_inst/fifo40_inst/a1_S1_2
+fifo_colector_inst/fifo40_inst/a1_COUT_2
+fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2
+fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2
+fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2
+fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2
+fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2
+fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2
+fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2
+fifo_colector_inst/fifo40_inst/CIN
+fifo_colector_inst/fifo40_inst/a0_S1_2
+fifo_colector_inst/fifo40_inst/a0_COUT_2
+fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2
+fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2
+fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2
+fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2
+fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2
+fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2
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+fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2
+fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2
+fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2
+fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2
+fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2
+fifo_colector_inst/fifo40_inst/CIN_0
+fifo_colector_inst/fifo40_inst/co4_1
+fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2
+fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2
+fifo_colector_inst/fifo40_inst/CIN_1
+fifo_colector_inst/fifo40_inst/co4
+fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2
+fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2
+fifo_colector_inst/fifo40_inst/CIN_2
+fifo_colector_inst/fifo40_inst/Q_1[35]
+fifo_colector_inst/fifo40_inst/Q_1[34]
+fifo_colector_inst/fifo40_inst/Q_1[33]
+fifo_colector_inst/fifo40_inst/Q_1[32]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1
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+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25]
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0
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+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0
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+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN
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+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0
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+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25]
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24]
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.11.2.446 -- WARNING: Map write only section -- Wed Jun 16 09:19:31 2021
+
+SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG INBUF=OFF ;
+PGROUP "tdc0" BBOX 1 4  DEVSIZE
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270"
+	COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271";
+LOCATE PGROUP "tdc0" SITE "R68C14D" ;
+PGROUP "tdc22" BBOX 1 4  DEVSIZE
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350"
+	COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351";
+LOCATE PGROUP "tdc22" SITE "R66C41D" ;
+PGROUP "tdc3" BBOX 1 4  DEVSIZE
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430"
+	COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431";
+LOCATE PGROUP "tdc3" SITE "R66C49D" ;
+PGROUP "lvl1_dec" BBOX 1 6  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";
+LOCATE PGROUP "lvl1_dec" SITE "R26C2D" ;
+PGROUP "lvl1_tdc" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513"
+	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514";
+LOCATE PGROUP "lvl1_tdc" SITE "R25C3D" ;
+PGROUP "hades_dec_pos" BBOX 1 6  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732";
+LOCATE PGROUP "hades_dec_pos" SITE "R27C2D" ;
+PGROUP "hades_dec_neg" BBOX 1 6  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729";
+LOCATE PGROUP "hades_dec_neg" SITE "R30C2D" ;
+PGROUP "hades_tdc_pos" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619";
+LOCATE PGROUP "hades_tdc_pos" SITE "R28C3D" ;
+PGROUP "hades_tdc_neg" BBOX 1 4  DEVSIZE
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626"
+	COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627";
+LOCATE PGROUP "hades_tdc_neg" SITE "R29C3D" ;
+PGROUP "lvl1_pad" BBOX 1 1  DEVSIZE
+	COMP "SLICE_743";
+LOCATE PGROUP "lvl1_pad" SITE "R25C2D" ;
+PGROUP "gate2" BBOX 1 1  DEVSIZE
+	COMP "SLICE_745";
+LOCATE PGROUP "gate2" SITE "R67C41D" ;
+PGROUP "trig3" BBOX 1 1  DEVSIZE
+	COMP "SLICE_746";
+LOCATE PGROUP "trig3" SITE "R67C49D" ;
+LOCATE COMP "clk" SITE "P3" ;
+LOCATE COMP "hades_lvl1" SITE "E1" ;
+LOCATE COMP "hades_trig" SITE "H5" ;
+LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9" ;
+LOCATE COMP "trig[2]" SITE "T19" ;
+LOCATE COMP "trig[1]" SITE "T3" ;
+LOCATE COMP "trig[0]" SITE "R2" ;
+FREQUENCY NET "clk_c" 100.000000 MHz ;
+FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+FREQUENCY PORT "clk" 100.000000 MHz ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/impl1/s1_impl1_map.hrr b/impl1/s1_impl1_map.hrr
new file mode 100644
index 0000000..9d8b8ea
--- /dev/null
+++ b/impl1/s1_impl1_map.hrr
@@ -0,0 +1,272 @@
+---------------------------------------------------
+Report for cell top_tf
+   Instance path: top_tf
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     692.00        100.0
+                                 IOLGC	      35.00        100.0
+                                  LUT4	     388.00        100.0
+                                 IOREG	         35        100.0
+                                 IOBUF	        186        100.0
+                                PFUREG	        899        100.0
+                                RIPPLE	        121        100.0
+                                   EBR	          4        100.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                           trb_adapter	          1         1.0
+                tdc_channel_fifo_out_2	          1        16.6
+                tdc_channel_fifo_out_3	          1        16.6
+                  tdc_channel_fifo_out	          1        16.6
+                                  pll0	          1         0.1
+                      hades_tdc_bundle	          1        32.6
+                         fifo_colector	          1        15.6
+---------------------------------------------------
+Report for cell tdc_channel_fifo_out_3
+   Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     115.00        16.6
+                                  LUT4	      53.00        13.7
+                                PFUREG	        154        17.1
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                       tdc4ddr_short_4	          1         2.3
+                   output_decoder8_2_1	          1         2.3
+                            fifo32dc_1	          1        11.8
+---------------------------------------------------
+Report for cell fifo32dc_1
+   Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      81.50        11.8
+                                  LUT4	      48.00        12.4
+                                PFUREG	        102        11.3
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+---------------------------------------------------
+Report for cell output_decoder8_2_1
+   Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/dec_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                  LUT4	       4.00         1.0
+                                PFUREG	         26         2.9
+---------------------------------------------------
+Report for cell tdc4ddr_short_4
+   Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/tdc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell tdc_channel_fifo_out_2
+   Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     115.00        16.6
+                                  LUT4	      53.00        13.7
+                                PFUREG	        154        17.1
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                       tdc4ddr_short_3	          1         2.3
+                   output_decoder8_2_0	          1         2.3
+                            fifo32dc_0	          1        11.8
+---------------------------------------------------
+Report for cell fifo32dc_0
+   Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      81.50        11.8
+                                  LUT4	      48.00        12.4
+                                PFUREG	        102        11.3
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+---------------------------------------------------
+Report for cell output_decoder8_2_0
+   Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/dec_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                  LUT4	       4.00         1.0
+                                PFUREG	         26         2.9
+---------------------------------------------------
+Report for cell tdc4ddr_short_3
+   Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/tdc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell tdc_channel_fifo_out
+   Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     115.00        16.6
+                                  LUT4	      53.00        13.7
+                                PFUREG	        154        17.1
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                       tdc4ddr_short_2	          1         2.3
+                     output_decoder8_2	          1         2.3
+                              fifo32dc	          1        11.8
+---------------------------------------------------
+Report for cell fifo32dc
+   Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      81.50        11.8
+                                  LUT4	      48.00        12.4
+                                PFUREG	        102        11.3
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+---------------------------------------------------
+Report for cell output_decoder8_2
+   Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/dec_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                  LUT4	       4.00         1.0
+                                PFUREG	         26         2.9
+---------------------------------------------------
+Report for cell tdc4ddr_short_2
+   Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/tdc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell fifo_colector
+   Instance path: top_tf/fifo_colector_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     108.00        15.6
+                                  LUT4	      95.00        24.5
+                                PFUREG	        142        15.8
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                             fifo40_dc	          1        11.7
+---------------------------------------------------
+Report for cell fifo40_dc
+   Instance path: top_tf/fifo_colector_inst/fifo40_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      81.00        11.7
+                                  LUT4	      46.00        11.9
+                                PFUREG	        102        11.3
+                                RIPPLE	         26        21.5
+                                   EBR	          1        25.0
+---------------------------------------------------
+Report for cell trb_adapter
+   Instance path: top_tf/trb_adapter_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	       7.00         1.0
+                                  LUT4	       4.00         1.0
+                                PFUREG	          7         0.8
+---------------------------------------------------
+Report for cell hades_tdc_bundle
+   Instance path: top_tf/hades_tdc_bundle_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     225.50        32.6
+                                  LUT4	     124.00        32.0
+                                PFUREG	        287        31.9
+                                RIPPLE	         17        14.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+             hades_tdc_channel_raw_out	          1        16.8
+                    hades_LVL1_raw_out	          1         9.7
+---------------------------------------------------
+Report for cell hades_tdc_channel_raw_out
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     116.00        16.8
+                                  LUT4	      35.00         9.0
+                                PFUREG	        163        18.1
+                                RIPPLE	          8         6.6
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                              trig_inv	          1         0.0
+                       tdc4ddr_short_0	          1         2.3
+                       tdc4ddr_short_1	          1         2.3
+                   output_decoder8_0_1	          1         3.3
+                   output_decoder8_0_0	          1         3.3
+---------------------------------------------------
+Report for cell output_decoder8_0_1
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      23.00         3.3
+                                  LUT4	      13.00         3.4
+                                PFUREG	         32         3.6
+---------------------------------------------------
+Report for cell output_decoder8_0_0
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      23.00         3.3
+                                  LUT4	      15.00         3.9
+                                PFUREG	         32         3.6
+---------------------------------------------------
+Report for cell tdc4ddr_short_1
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell tdc4ddr_short_0
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell trig_inv
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+---------------------------------------------------
+Report for cell hades_LVL1_raw_out
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      66.83         9.7
+                                  LUT4	      48.00        12.4
+                                PFUREG	         74         8.2
+                                RIPPLE	          5         4.1
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                         tdc4ddr_short	          1         2.3
+                     output_decoder8_0	          1         3.6
+---------------------------------------------------
+Report for cell output_decoder8_0
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      25.00         3.6
+                                  LUT4	      16.00         4.1
+                                PFUREG	         33         3.7
+---------------------------------------------------
+Report for cell tdc4ddr_short
+   Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      16.00         2.3
+                                PFUREG	         24         2.7
+---------------------------------------------------
+Report for cell pll0
+   Instance path: top_tf/pll0inst
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	       1.00         0.1
+                                  LUT4	       1.00         0.3
diff --git a/impl1/s1_impl1_map.ncd b/impl1/s1_impl1_map.ncd
new file mode 100644
index 0000000..a83bac3
Binary files /dev/null and b/impl1/s1_impl1_map.ncd differ
diff --git a/impl1/s1_impl1_map_trce.asd b/impl1/s1_impl1_map_trce.asd
new file mode 100644
index 0000000..d3aa255
--- /dev/null
+++ b/impl1/s1_impl1_map_trce.asd
@@ -0,0 +1,7 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Other_0 = - (-);
+Other_1 = - (-);
+Failed = 0 (Total 2);
+Clock_ports = 0;
+Clock_nets = 0;
diff --git a/impl1/s1_impl1_mrp.html b/impl1/s1_impl1_mrp.html
new file mode 100644
index 0000000..f71d338
--- /dev/null
+++ b/impl1/s1_impl1_mrp.html
@@ -0,0 +1,10746 @@
+<HTML>
+<HEAD><TITLE>Project Summary</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
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    margin-top: 18px;
    margin-bottom: 5px;
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}
p {
    font-size:78%;
}
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    margin-bottom: 4px;
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    margin-left: 4px;
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table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
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    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
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a {
    color:#013C9A;
    text-decoration:none;
}

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    color:#013C9A;
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    text-decoration:underline;
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background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Mrp"></A>
+            Lattice Mapping Report File for Design Module 'top_tf'
+
+
+
+<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
+
+Command line:   map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
+     s1_impl1.ngd -o s1_impl1_map.ncd -pr s1_impl1.prf -mp s1_impl1.mrp -lpf
+     /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf -lpf
+     /home/hadaq/mmichalek/lattice/simplified/s1.lpf -xref_sym -xref_sig -tdm
+     -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LFE5UM5G-45FCABGA381
+Target Performance:   8
+Mapper:  sa5p00g,  version:  Diamond (64-bit) 3.11.2.446
+Mapped on:  06/16/21  09:19:26
+
+
+<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
+   Number of registers:    934 out of 44457 (2%)
+      PFU registers:          899 out of 43848 (2%)
+      PIO registers:           35 out of   609 (6%)
+   Number of SLICEs:       692 out of 21924 (3%)
+      SLICEs as Logic/ROM:    692 out of 21924 (3%)
+      SLICEs as RAM:            0 out of 16443 (0%)
+      SLICEs as Carry:        121 out of 21924 (1%)
+   Number of LUT4s:        630 out of 43848 (1%)
+      Number used as logic LUTs:        388
+      Number used as distributed RAM:     0
+      Number used as ripple logic:      242
+      Number used as shift registers:     0
+   Number of PIO sites used: 187 out of 203 (92%)
+      Number of PIO sites used for single ended IOs: 185
+      Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
+     comps in NCD)
+   Number of block RAMs:  4 out of 108 (4%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   DTR used :   No
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
+   Number of DCC:  0 out of 60 (0%)
+   Number of DCS:  0 out of 2 (0%)
+   Number of PLLs:  1 out of 4 (25%)
+   Number of DDRDLLs:  0 out of 4 (0%)
+   Number of CLKDIV:  0 out of 4 (0%)
+   Number of ECLKSYNC:  0 out of 10 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Number of DCUs:  0 out of 2 (0%)
+   Number of DCU Channels:  0 out of 4 (0%)
+   Number of EXTREFs:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+
+
+        Number Of Mapped DSP Components:
+   --------------------------------
+   MULT18X18D          0
+   MULT9X9D            0
+   ALU54B              0
+   ALU24B              0
+   PRADD18A            0
+   PRADD9A             0
+   --------------------------------
+   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
+   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
+   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
+   Number of clocks:  6
+     Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk )
+     Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver:
+     pll0inst/PLLInst_0 )
+     Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk )
+   Number of Clock Enables:  18
+     Net reset_dl[2]: 7 loads, 7 LSLICEs
+     Net N_248_i: 1 loads, 0 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
+     LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
+     LSLICEs
+     Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs
+     Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs
+     Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs
+     Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6
+     LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads,
+     6 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads,
+     13 LSLICEs
+     Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10
+     loads, 1 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1
+     LSLICEs
+   Number of LSRs:  13
+     Net reset_dl[2]: 37 loads, 33 LSLICEs
+     Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+
+     loads, 1 LSLICEs
+     Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+     loads, 1 LSLICEs
+     Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
+     loads, 1 LSLICEs
+     Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs
+     Net fifo_rden_c: 1 loads, 1 LSLICEs
+     Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sy
+     nced7_rising_i: 3 loads, 3 LSLICEs
+     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced
+     7_rising_i: 4 loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4
+     loads, 4 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1
+     LSLICEs
+     Net valid_fast_RNI999V: 9 loads, 0 LSLICEs
+     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_risin
+     g_i: 4 loads, 4 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net reset_dl[2]: 59 loads
+     Net fifo_colector_inst/iterator[0]: 47 loads
+     Net fifo_colector_inst/iterator[1]: 23 loads
+     Net fifo_colector_inst/in_empty_pmux_i: 22 loads
+     Net un1_hit_i_2_0_a2: 20 loads
+     Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads
+     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
+     Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads
+
+
+
+
+<A name="mrp_sym"></A><B><U><big>Symbol Cross Reference</big></U></B>
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20 (PFU) covers blocks:
+     full_cmp_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21 (PFU) covers blocks:
+     full_cmp_1
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22 (PFU) covers blocks:
+     full_cmp_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23 (PFU) covers blocks:
+     full_cmp_3
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24 (PFU) covers blocks:
+     full_cmp_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46 (PFU) covers blocks:
+     full_cmp_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47 (PFU) covers blocks:
+     full_cmp_1
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48 (PFU) covers blocks:
+     full_cmp_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49 (PFU) covers blocks:
+     full_cmp_3
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50 (PFU) covers blocks:
+     full_cmp_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52 (PFU) covers blocks:
+     w_gctr_cia
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58 (PFU) covers blocks:
+     r_gctr_cia
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64 (PFU) covers blocks:
+     empty_cmp_ci_a
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65 (PFU) covers blocks:
+     empty_cmp_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66 (PFU) covers blocks:
+     empty_cmp_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67 (PFU) covers blocks:
+     empty_cmp_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68 (PFU) covers blocks:
+     empty_cmp_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69 (PFU) covers blocks:
+     empty_cmp_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71 (PFU) covers blocks:
+     full_cmp_ci_a
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72 (PFU) covers blocks:
+     full_cmp_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73 (PFU) covers blocks:
+     full_cmp_1
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74 (PFU) covers blocks:
+     full_cmp_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75 (PFU) covers blocks:
+     full_cmp_3
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76 (PFU) covers blocks:
+     full_cmp_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
+fifo_colector_inst/fifo40_inst/SLICE_78 (PFU) covers blocks: w_gctr_cia
+fifo_colector_inst/fifo40_inst/SLICE_79 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_101,
+     fifo_colector_inst/fifo40_inst/FF_100, w_gctr_0
+fifo_colector_inst/fifo40_inst/SLICE_80 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_99, fifo_colector_inst/fifo40_inst/FF_98,
+     w_gctr_1
+fifo_colector_inst/fifo40_inst/SLICE_81 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_97, fifo_colector_inst/fifo40_inst/FF_96,
+     w_gctr_2
+fifo_colector_inst/fifo40_inst/SLICE_82 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_95, fifo_colector_inst/fifo40_inst/FF_94,
+     w_gctr_3
+fifo_colector_inst/fifo40_inst/SLICE_83 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_93, fifo_colector_inst/fifo40_inst/FF_92,
+     w_gctr_4
+fifo_colector_inst/fifo40_inst/SLICE_84 (PFU) covers blocks: r_gctr_cia
+fifo_colector_inst/fifo40_inst/SLICE_85 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_71, fifo_colector_inst/fifo40_inst/FF_70,
+     r_gctr_0
+fifo_colector_inst/fifo40_inst/SLICE_86 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_69, fifo_colector_inst/fifo40_inst/FF_68,
+     r_gctr_1
+fifo_colector_inst/fifo40_inst/SLICE_87 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_67, fifo_colector_inst/fifo40_inst/FF_66,
+     r_gctr_2
+fifo_colector_inst/fifo40_inst/SLICE_88 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_65, fifo_colector_inst/fifo40_inst/FF_64,
+     r_gctr_3
+fifo_colector_inst/fifo40_inst/SLICE_89 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_63, fifo_colector_inst/fifo40_inst/FF_62,
+     r_gctr_4
+fifo_colector_inst/fifo40_inst/SLICE_90 (PFU) covers blocks: empty_cmp_ci_a
+fifo_colector_inst/fifo40_inst/SLICE_91 (PFU) covers blocks: empty_cmp_0
+fifo_colector_inst/fifo40_inst/SLICE_92 (PFU) covers blocks: empty_cmp_1
+fifo_colector_inst/fifo40_inst/SLICE_93 (PFU) covers blocks: empty_cmp_2
+fifo_colector_inst/fifo40_inst/SLICE_94 (PFU) covers blocks: empty_cmp_3
+fifo_colector_inst/fifo40_inst/SLICE_95 (PFU) covers blocks: empty_cmp_4
+fifo_colector_inst/fifo40_inst/SLICE_96 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_1, a0
+fifo_colector_inst/fifo40_inst/SLICE_97 (PFU) covers blocks: full_cmp_ci_a
+fifo_colector_inst/fifo40_inst/SLICE_98 (PFU) covers blocks: full_cmp_0
+fifo_colector_inst/fifo40_inst/SLICE_99 (PFU) covers blocks: full_cmp_1
+fifo_colector_inst/fifo40_inst/SLICE_100 (PFU) covers blocks: full_cmp_2
+fifo_colector_inst/fifo40_inst/SLICE_101 (PFU) covers blocks: full_cmp_3
+fifo_colector_inst/fifo40_inst/SLICE_102 (PFU) covers blocks: full_cmp_4
+fifo_colector_inst/fifo40_inst/SLICE_103 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_0, a1
+hades_tdc_bundle_inst/SLICE_104 (PFU) covers blocks: hit_valid25_0_I_27_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105 (PFU) covers
+     blocks: un1_coarse_1_0_I_1_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106 (PFU) covers
+     blocks: un1_coarse_1_0_I_9_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107 (PFU) covers
+     blocks: un1_coarse_1_0_I_21_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108 (PFU) covers
+     blocks: un1_coarse_1_0_I_27_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109 (PFU) covers
+     blocks: un1_buf_positive_0_I_1_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110 (PFU) covers
+     blocks: un1_buf_positive_0_I_9_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111 (PFU) covers
+     blocks: un1_buf_positive_0_I_21_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112 (PFU) covers
+     blocks: un1_buf_positive_0_I_27_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 (PFU) covers blocks:
+     un1_window_8_cry_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 (PFU) covers blocks:
+     un1_window_8_cry_1_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115 (PFU) covers blocks:
+     un1_window_8_cry_3_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116 (PFU) covers blocks:
+     un1_window_8_cry_5_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117 (PFU) covers blocks:
+     un1_window_8_s_7_0
+hades_tdc_bundle_inst/SLICE_118 (PFU) covers blocks: hit_valid25_0_I_1_0
+hades_tdc_bundle_inst/SLICE_119 (PFU) covers blocks: hit_valid25_0_I_9_0
+hades_tdc_bundle_inst/SLICE_120 (PFU) covers blocks: hit_valid25_0_I_21_0
+hades_tdc_bundle_inst/SLICE_121 (PFU) covers blocks: hit_out_i_RNO[0],
+     buf_finished5_0_a2_0, hades_tdc_bundle_inst/hit_out_i[0]
+hades_tdc_bundle_inst/SLICE_122 (PFU) covers blocks: SUM1_1_x2, N_50_i_i,
+     hades_tdc_bundle_inst/hit_out_i[1], hades_tdc_bundle_inst/hit_out_i[3]
+hades_tdc_bundle_inst/SLICE_123 (PFU) covers blocks: hit_out_i_6_f1_0[2],
+     hit_valid_pmux_iv_0_a2_2, hades_tdc_bundle_inst/hit_out_i[2]
+trb_adapter_inst/SLICE_124 (PFU) covers blocks:
+     trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1]
+fifo_colector_inst/SLICE_125 (PFU) covers blocks: in_empty_pmux_0_RNIDRET,
+     in_empty_pmux_0, fifo_colector_inst/buffer_wr_enable
+fifo_colector_inst/SLICE_126 (PFU) covers blocks: data_buffer_3[0],
+     data_buffer_3_0[0], fifo_colector_inst/data_buffer[0]
+fifo_colector_inst/SLICE_127 (PFU) covers blocks: data_buffer_3[1],
+     data_buffer_3_0[1], fifo_colector_inst/data_buffer[1]
+fifo_colector_inst/SLICE_128 (PFU) covers blocks: data_buffer_3[2],
+     data_buffer_3_0[2], fifo_colector_inst/data_buffer[2]
+fifo_colector_inst/SLICE_129 (PFU) covers blocks: data_buffer_3[3],
+     data_buffer_3_0[3], fifo_colector_inst/data_buffer[3]
+fifo_colector_inst/SLICE_130 (PFU) covers blocks: data_buffer_3[4],
+     data_buffer_3_0[4], fifo_colector_inst/data_buffer[4]
+fifo_colector_inst/SLICE_131 (PFU) covers blocks: data_buffer_3[5],
+     data_buffer_3_0[5], fifo_colector_inst/data_buffer[5]
+fifo_colector_inst/SLICE_132 (PFU) covers blocks: data_buffer_3[6],
+     data_buffer_3_0[6], fifo_colector_inst/data_buffer[6]
+fifo_colector_inst/SLICE_133 (PFU) covers blocks: data_buffer_3[7],
+     data_buffer_3_0[7], fifo_colector_inst/data_buffer[7]
+fifo_colector_inst/SLICE_134 (PFU) covers blocks: data_buffer_3_0[8],
+     data_buffer_3_0[9], fifo_colector_inst/data_buffer[8],
+     fifo_colector_inst/data_buffer[9]
+fifo_colector_inst/SLICE_135 (PFU) covers blocks: data_buffer_3_0[10],
+     data_buffer_3_0[11], fifo_colector_inst/data_buffer[10],
+     fifo_colector_inst/data_buffer[11]
+fifo_colector_inst/SLICE_136 (PFU) covers blocks: data_buffer_3_0[12],
+     data_buffer_3_0[13], fifo_colector_inst/data_buffer[12],
+     fifo_colector_inst/data_buffer[13]
+fifo_colector_inst/SLICE_137 (PFU) covers blocks: data_buffer_3_0[14],
+     data_buffer_3_0[15], fifo_colector_inst/data_buffer[14],
+     fifo_colector_inst/data_buffer[15]
+fifo_colector_inst/SLICE_138 (PFU) covers blocks: data_buffer_3_0[16],
+     data_buffer_3_0[17], fifo_colector_inst/data_buffer[16],
+     fifo_colector_inst/data_buffer[17]
+fifo_colector_inst/SLICE_139 (PFU) covers blocks: data_buffer_3_0[18],
+     data_buffer_3_0[19], fifo_colector_inst/data_buffer[18],
+     fifo_colector_inst/data_buffer[19]
+fifo_colector_inst/SLICE_140 (PFU) covers blocks: data_buffer_3_0[20],
+     data_buffer_3_0[21], fifo_colector_inst/data_buffer[20],
+     fifo_colector_inst/data_buffer[21]
+fifo_colector_inst/SLICE_141 (PFU) covers blocks: data_buffer_3_0[22],
+     data_buffer_3_0[23], fifo_colector_inst/data_buffer[22],
+     fifo_colector_inst/data_buffer[23]
+fifo_colector_inst/SLICE_142 (PFU) covers blocks: data_buffer_3_0[24],
+     data_buffer_3_0[25], fifo_colector_inst/data_buffer[24],
+     fifo_colector_inst/data_buffer[25]
+fifo_colector_inst/SLICE_143 (PFU) covers blocks: data_buffer_3_0[26],
+     data_buffer_3_0[27], fifo_colector_inst/data_buffer[26],
+     fifo_colector_inst/data_buffer[27]
+fifo_colector_inst/SLICE_144 (PFU) covers blocks: data_buffer_3_0[28],
+     data_buffer_3_0[29], fifo_colector_inst/data_buffer[28],
+     fifo_colector_inst/data_buffer[29]
+fifo_colector_inst/SLICE_145 (PFU) covers blocks: data_buffer_3_0[30],
+     data_buffer_3_0[31], fifo_colector_inst/data_buffer[30],
+     fifo_colector_inst/data_buffer[31]
+fifo_colector_inst/SLICE_146 (PFU) covers blocks:
+     fifo_colector_inst/data_buffer[32], fifo_colector_inst/data_buffer[33]
+fifo_colector_inst/fifo40_inst/SLICE_147 (PFU) covers blocks: XOR2_t8, XOR2_t7,
+     fifo_colector_inst/fifo40_inst/FF_61, fifo_colector_inst/fifo40_inst/FF_60
+fifo_colector_inst/fifo40_inst/SLICE_148 (PFU) covers blocks: XOR2_t6, XOR2_t5,
+     fifo_colector_inst/fifo40_inst/FF_59, fifo_colector_inst/fifo40_inst/FF_58
+fifo_colector_inst/fifo40_inst/SLICE_149 (PFU) covers blocks: XOR2_t4, XOR2_t3,
+     fifo_colector_inst/fifo40_inst/FF_57, fifo_colector_inst/fifo40_inst/FF_56
+fifo_colector_inst/fifo40_inst/SLICE_150 (PFU) covers blocks: XOR2_t2, XOR2_t1,
+     fifo_colector_inst/fifo40_inst/FF_55, fifo_colector_inst/fifo40_inst/FF_54
+fifo_colector_inst/fifo40_inst/SLICE_151 (PFU) covers blocks: XOR2_t0,
+     fifo_colector_inst/fifo40_inst/FF_53, fifo_colector_inst/fifo40_inst/FF_52
+fifo_colector_inst/fifo40_inst/SLICE_152 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_31, fifo_colector_inst/fifo40_inst/FF_30
+fifo_colector_inst/fifo40_inst/SLICE_153 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_29, fifo_colector_inst/fifo40_inst/FF_28
+fifo_colector_inst/fifo40_inst/SLICE_154 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_27, fifo_colector_inst/fifo40_inst/FF_26
+fifo_colector_inst/fifo40_inst/SLICE_155 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_25, fifo_colector_inst/fifo40_inst/FF_24
+fifo_colector_inst/fifo40_inst/SLICE_156 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_23, fifo_colector_inst/fifo40_inst/FF_22
+fifo_colector_inst/fifo40_inst/SLICE_157 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_11, fifo_colector_inst/fifo40_inst/FF_10
+fifo_colector_inst/fifo40_inst/SLICE_158 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_9, fifo_colector_inst/fifo40_inst/FF_8
+fifo_colector_inst/fifo40_inst/SLICE_159 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_7, fifo_colector_inst/fifo40_inst/FF_6
+fifo_colector_inst/fifo40_inst/SLICE_160 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_5, fifo_colector_inst/fifo40_inst/FF_4
+fifo_colector_inst/fifo40_inst/SLICE_161 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_3, fifo_colector_inst/fifo40_inst/FF_2
+fifo_colector_inst/fifo40_inst/SLICE_162 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_51, fifo_colector_inst/fifo40_inst/FF_50
+fifo_colector_inst/fifo40_inst/SLICE_163 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_49, fifo_colector_inst/fifo40_inst/FF_48
+fifo_colector_inst/fifo40_inst/SLICE_164 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_47, fifo_colector_inst/fifo40_inst/FF_46
+fifo_colector_inst/fifo40_inst/SLICE_165 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_45, fifo_colector_inst/fifo40_inst/FF_44
+fifo_colector_inst/fifo40_inst/SLICE_166 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_43, fifo_colector_inst/fifo40_inst/FF_42
+fifo_colector_inst/fifo40_inst/SLICE_167 (PFU) covers blocks: XOR2_t17,
+     XOR2_t16, fifo_colector_inst/fifo40_inst/FF_91,
+     fifo_colector_inst/fifo40_inst/FF_90
+fifo_colector_inst/fifo40_inst/SLICE_168 (PFU) covers blocks: XOR2_t15,
+     XOR2_t14, fifo_colector_inst/fifo40_inst/FF_89,
+     fifo_colector_inst/fifo40_inst/FF_88
+fifo_colector_inst/fifo40_inst/SLICE_169 (PFU) covers blocks: XOR2_t13,
+     XOR2_t12, fifo_colector_inst/fifo40_inst/FF_87,
+     fifo_colector_inst/fifo40_inst/FF_86
+fifo_colector_inst/fifo40_inst/SLICE_170 (PFU) covers blocks: XOR2_t11,
+     XOR2_t10, fifo_colector_inst/fifo40_inst/FF_85,
+     fifo_colector_inst/fifo40_inst/FF_84
+fifo_colector_inst/fifo40_inst/SLICE_171 (PFU) covers blocks: XOR2_t9,
+     fifo_colector_inst/fifo40_inst/FF_83, fifo_colector_inst/fifo40_inst/FF_82
+fifo_colector_inst/fifo40_inst/SLICE_172 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_41, fifo_colector_inst/fifo40_inst/FF_40
+fifo_colector_inst/fifo40_inst/SLICE_173 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_39, fifo_colector_inst/fifo40_inst/FF_38
+fifo_colector_inst/fifo40_inst/SLICE_174 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_37, fifo_colector_inst/fifo40_inst/FF_36
+fifo_colector_inst/fifo40_inst/SLICE_175 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_35, fifo_colector_inst/fifo40_inst/FF_34
+fifo_colector_inst/fifo40_inst/SLICE_176 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_33, fifo_colector_inst/fifo40_inst/FF_32
+fifo_colector_inst/fifo40_inst/SLICE_177 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_21, fifo_colector_inst/fifo40_inst/FF_20
+fifo_colector_inst/fifo40_inst/SLICE_178 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_19, fifo_colector_inst/fifo40_inst/FF_18
+fifo_colector_inst/fifo40_inst/SLICE_179 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_17, fifo_colector_inst/fifo40_inst/FF_16
+fifo_colector_inst/fifo40_inst/SLICE_180 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_15, fifo_colector_inst/fifo40_inst/FF_14
+fifo_colector_inst/fifo40_inst/SLICE_181 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_13, fifo_colector_inst/fifo40_inst/FF_12
+fifo_colector_inst/fifo40_inst/SLICE_182 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_81, fifo_colector_inst/fifo40_inst/FF_80
+fifo_colector_inst/fifo40_inst/SLICE_183 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_79, fifo_colector_inst/fifo40_inst/FF_78
+fifo_colector_inst/fifo40_inst/SLICE_184 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_77, fifo_colector_inst/fifo40_inst/FF_76
+fifo_colector_inst/fifo40_inst/SLICE_185 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_75, fifo_colector_inst/fifo40_inst/FF_74
+fifo_colector_inst/fifo40_inst/SLICE_186 (PFU) covers blocks:
+     fifo_colector_inst/fifo40_inst/FF_73, fifo_colector_inst/fifo40_inst/FF_72
+fifo_colector_inst/SLICE_187 (PFU) covers blocks: un5_in_read_enable,
+     fifo_colector_inst/iterator[0], fifo_colector_inst/iterator[1]
+trb_adapter_inst/SLICE_188 (PFU) covers blocks: buf_rden4, burst,
+     trb_adapter_inst/buf_rden
+fifo_colector_inst/SLICE_189 (PFU) covers blocks: in_read_enable_0_.fb,
+     in_read_enable_1_.fb, fifo_colector_inst/in_read_enable[0],
+     fifo_colector_inst/in_read_enable[1]
+fifo_colector_inst/SLICE_190 (PFU) covers blocks: in_read_enable_2_.fb,
+     fifo_colector_inst/in_read_enable[2]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210 (PFU) covers
+     blocks: XOR2_t0, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230 (PFU) covers
+     blocks: XOR2_t9, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245 (PFU) covers
+     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[0].tdc_channel_fifo_out_inst/SLICE_246 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271 (PFU) covers blocks:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290 (PFU) covers
+     blocks: XOR2_t0, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310 (PFU) covers
+     blocks: XOR2_t9, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325 (PFU) covers
+     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[1].tdc_channel_fifo_out_inst/SLICE_326 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351 (PFU) covers blocks:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364 (PFU) covers blocks:
+     valid_internal_RNO,
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366 (PFU) covers
+     blocks: XOR2_t8, XOR2_t7,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367 (PFU) covers
+     blocks: XOR2_t6, XOR2_t5,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368 (PFU) covers
+     blocks: XOR2_t4, XOR2_t3,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369 (PFU) covers
+     blocks: XOR2_t2, XOR2_t1,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370 (PFU) covers
+     blocks: XOR2_t0, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386 (PFU) covers
+     blocks: XOR2_t17, XOR2_t16,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387 (PFU) covers
+     blocks: XOR2_t15, XOR2_t14,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388 (PFU) covers
+     blocks: XOR2_t13, XOR2_t12,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389 (PFU) covers
+     blocks: XOR2_t11, XOR2_t10,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390 (PFU) covers
+     blocks: XOR2_t9, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405 (PFU) covers
+     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
+genblk1[2].tdc_channel_fifo_out_inst/SLICE_406 (PFU) covers blocks:
+     fifo_in_data_11_.fb, genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[11]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431 (PFU) covers blocks:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/SLICE_432 (PFU) covers blocks: buf_finished_RNO,
+     buf_finished5_0_a2_0, hades_tdc_bundle_inst/buf_finished
+hades_tdc_bundle_inst/SLICE_433 (PFU) covers blocks:
+     hades_tdc_bundle_inst/buf_release
+hades_tdc_bundle_inst/SLICE_434 (PFU) covers blocks: coarse_RNI8DE6[0],
+     drop_cmp_buf_coarse_2_axbxc1, hades_tdc_bundle_inst/coarse[0],
+     hades_tdc_bundle_inst/coarse[1]
+hades_tdc_bundle_inst/SLICE_435 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc2, coarse_RNI6RPP[2],
+     hades_tdc_bundle_inst/coarse[2], hades_tdc_bundle_inst/coarse[3]
+hades_tdc_bundle_inst/SLICE_436 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc4, drop_cmp_buf_coarse_2_axbxc5,
+     hades_tdc_bundle_inst/coarse[4], hades_tdc_bundle_inst/coarse[5]
+hades_tdc_bundle_inst/SLICE_437 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc6, drop_cmp_buf_coarse_2_axbxc7,
+     hades_tdc_bundle_inst/coarse[6], hades_tdc_bundle_inst/coarse[7]
+hades_tdc_bundle_inst/SLICE_438 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_axbxc8, drop_cmp_buf_coarse_2_ac0_5,
+     hades_tdc_bundle_inst/coarse[8]
+hades_tdc_bundle_inst/SLICE_439 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[3],
+     hades_tdc_bundle_inst/hitbuffer_1_[4]
+hades_tdc_bundle_inst/SLICE_440 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[5],
+     hades_tdc_bundle_inst/hitbuffer_1_[6]
+hades_tdc_bundle_inst/SLICE_441 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[7],
+     hades_tdc_bundle_inst/hitbuffer_1_[8]
+hades_tdc_bundle_inst/SLICE_442 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[9],
+     hades_tdc_bundle_inst/hitbuffer_1_[10]
+hades_tdc_bundle_inst/SLICE_443 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hitbuffer_1_[11]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444 (PFU) covers blocks:
+     trig_dl_RNI41GL1[3], discard_en,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard
+hades_tdc_bundle_inst/SLICE_445 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[0],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[1]
+hades_tdc_bundle_inst/SLICE_446 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[2],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[3]
+hades_tdc_bundle_inst/SLICE_447 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[4],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[5]
+hades_tdc_bundle_inst/SLICE_448 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[6],
+     hades_tdc_bundle_inst/drop_cmp_buf_1[7]
+hades_tdc_bundle_inst/SLICE_449 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_1[8]
+hades_tdc_bundle_inst/SLICE_450 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[0],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1]
+hades_tdc_bundle_inst/SLICE_451 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[2],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3]
+hades_tdc_bundle_inst/SLICE_452 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[4],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5]
+hades_tdc_bundle_inst/SLICE_453 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[6],
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7]
+hades_tdc_bundle_inst/SLICE_454 (PFU) covers blocks:
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8]
+hades_tdc_bundle_inst/SLICE_455 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_ac0_15, drop_cmp_buf_coarse_2_ac0_9_0,
+     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[9]
+hades_tdc_bundle_inst/SLICE_456 (PFU) covers blocks: drop_cmp_buf_valid_4_iv_i,
+     hades_tdc_bundle_inst/drop_cmp_buf_valid
+hades_tdc_bundle_inst/SLICE_457 (PFU) covers blocks: hit_valid_1_RNO[0],
+     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[0]
+hades_tdc_bundle_inst/SLICE_458 (PFU) covers blocks: hit_valid_1_RNO[1],
+     drop_cmp_buf_valid_0_sqmuxa_0_a2, hades_tdc_bundle_inst/hit_valid_1[1]
+hades_tdc_bundle_inst/SLICE_459 (PFU) covers blocks: hit_valid_1_RNO[2],
+     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[2]
+hades_tdc_bundle_inst/SLICE_460 (PFU) covers blocks: hit_valid_1_RNO[3],
+     SUM1_0_0_o2, hades_tdc_bundle_inst/hit_valid_1[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463 (PFU) covers blocks:
+     offset_valid_RNO,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[13],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[15],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[17],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[19],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[21],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486 (PFU) covers
+     blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487 (PFU) covers
+     blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488 (PFU) covers
+     blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489 (PFU) covers
+     blocks: valid_internal_RNO, un1_out_internal35_1_0_m3,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered1[0], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered1[1], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered1[2], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered1[3], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered1[4], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered1[5], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered1[6], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[2].in_clk_synced[6]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered1[7], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
+     blk1[3].in_clk_synced[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
+     ut_buffered[4]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
+     ut_buffered[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
+     ut_buffered[6]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
+     ut_buffered[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516 (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518 (PFU) covers blocks:
+     window_RNO[0], un1_reset_0_a2_2,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519 (PFU) covers blocks:
+     window_6[1], window_6[3],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 (PFU) covers blocks:
+     window_0_sqmuxadup, un1_invalid_dl,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521 (PFU) covers blocks:
+     window_6[4], window_6[5],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522 (PFU) covers blocks:
+     window_6[6], window_6[7],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6],
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[3],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[5],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[7],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[9],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527 (PFU) covers
+     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528 (PFU) covers
+     blocks: buf_negative_ready_RNIG7JA,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out_valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535 (PFU) covers
+     blocks: buf_negative_ready_4_f0_0_0,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541 (PFU) covers
+     blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542 (PFU) covers
+     blocks: buf_positive_ready_4_iv_i_0,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+     t/in_synced[6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555 (PFU)
+     covers blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7, hades_
+     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556 (PFU)
+     covers blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0, hade
+     s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557 (PFU)
+     covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1, hades_
+     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558 (PFU)
+     covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_tdc_bun
+     dle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[0][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][2],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][4],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/dl[1][6],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/in_synced[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+     nst/dec_neg_inst/in_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i, out_internal_2_1_0_.m15_i, 
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inter
+     nal[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/o
+     ut_internal[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572
+     (PFU) covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_o5,
+      hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inte
+     rnal[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573
+     (PFU) covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_t
+     dc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575 (PFU)
+     covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576
+     (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[0],
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577
+     (PFU) covers blocks:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_ch
+     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[0].out_buffered[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[1].out_buffered[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[2].out_buffered[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619 (PFU)
+     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
+     t/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered[0]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered[1]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered[2]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered[3]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[0].out_buffered[4]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[1].out_buffered[5]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[2].out_buffered[6]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627
+     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
+     dc_neg_inst/genblk1[3].out_buffered[7]
+hades_tdc_bundle_inst/SLICE_628 (PFU) covers blocks: SUM0_1_0_x2, SUM1_0_0,
+     hades_tdc_bundle_inst/hit_i[0], hades_tdc_bundle_inst/hit_i[1]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629 (PFU) covers blocks:
+     window_end5_0_a2, discard4_0_a2_0,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end
+trb_adapter_inst/SLICE_631 (PFU) covers blocks:
+     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1],
+     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
+trb_adapter_inst/SLICE_632 (PFU) covers blocks: trb_adapter_inst/buf_rden_prev
+trb_adapter_inst/SLICE_633 (PFU) covers blocks: trb_adapter_inst/finished_prev
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 (PFU) covers blocks:
+     offset_1_sqmuxa_i_0, offset_1_sqmuxa_i_0_o2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635 (PFU) covers blocks:
+     un1_reset_0_a2_1, discard4_0_a2_0
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644 (PFU) covers
+     blocks: LUT4_16, LUT4_23
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645 (PFU) covers
+     blocks: LUT4_19, LUT4_21
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646 (PFU) covers
+     blocks: LUT4_6, LUT4_13
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647 (PFU) covers
+     blocks: LUT4_9, LUT4_11
+fifo_colector_inst/fifo40_inst/SLICE_648 (PFU) covers blocks: LUT4_6, LUT4_13
+fifo_colector_inst/fifo40_inst/SLICE_649 (PFU) covers blocks: LUT4_9, LUT4_11
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652 (PFU) covers blocks:
+     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
+hades_tdc_bundle_inst/SLICE_653 (PFU) covers blocks:
+     hit_valid_pmux_iv_0_a2_2_RNITDG11, hit_valid_pmux_iv_0_a2_2
+hades_tdc_bundle_inst/SLICE_654 (PFU) covers blocks: hit_valid_pmux_iv_0_0,
+     hit_valid_pmux_iv_0_a2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667 (PFU) covers
+     blocks: LUT4_23, LUT4_14
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668 (PFU) covers
+     blocks: LUT4_22, LUT4_15
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669 (PFU) covers
+     blocks: LUT4_20, LUT4_18
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670 (PFU) covers
+     blocks: LUT4_13, LUT4_4
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671 (PFU) covers
+     blocks: LUT4_12, LUT4_5
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672 (PFU) covers
+     blocks: LUT4_10, LUT4_8
+fifo_colector_inst/fifo40_inst/SLICE_673 (PFU) covers blocks: LUT4_23, LUT4_14
+fifo_colector_inst/fifo40_inst/SLICE_674 (PFU) covers blocks: LUT4_22, LUT4_15
+fifo_colector_inst/fifo40_inst/SLICE_675 (PFU) covers blocks: LUT4_21, LUT4_19
+fifo_colector_inst/fifo40_inst/SLICE_676 (PFU) covers blocks: LUT4_20, LUT4_18
+fifo_colector_inst/fifo40_inst/SLICE_677 (PFU) covers blocks: LUT4_13, LUT4_4
+fifo_colector_inst/fifo40_inst/SLICE_678 (PFU) covers blocks: LUT4_12, LUT4_5
+fifo_colector_inst/fifo40_inst/SLICE_679 (PFU) covers blocks: LUT4_10, LUT4_8
+fifo_colector_inst/SLICE_680 (PFU) covers blocks: in_empty_pmux_u,
+     in_empty_pmux_0
+hades_tdc_bundle_inst/SLICE_681 (PFU) covers blocks:
+     un1_buf_positive_0_I_9_0_RNO_0, drop_cmp_buf_coarse_2_ac0_3
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682 (PFU) covers blocks:
+     un1_reset_0_a2_c, discard4_0_a2_0
+hades_tdc_bundle_inst/SLICE_683 (PFU) covers blocks: buf_out12,
+     hit_valid_pmux_iv_0_a2_2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684 (PFU) covers blocks:
+     discard4_0_a2_0_3, window_RNIOA5C[2]
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689 (PFU) covers
+     blocks: LUT4_3, LUT4_2
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690 (PFU) covers
+     blocks: LUT4_1, LUT4_0
+fifo_colector_inst/fifo40_inst/SLICE_691 (PFU) covers blocks: LUT4_0, LUT4_1
+fifo_colector_inst/fifo40_inst/SLICE_692 (PFU) covers blocks: LUT4_3, LUT4_2
+hades_tdc_bundle_inst/SLICE_693 (PFU) covers blocks: un1_hit_i_2_0_a2,
+     SUM1_0_0_o2_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694
+     (PFU) covers blocks: un1_out_internal35_1_0_o5, out_internal_2_1_0_.m15_i_1
+     
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695 (PFU)
+     covers blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696 (PFU)
+     covers blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697 (PFU) covers
+     blocks: un1_coarse_1_0_I_9_0_RNO, un1_buf_positive_0_I_9_0_RNO
+hades_tdc_bundle_inst/SLICE_698 (PFU) covers blocks: un1_coarse_1_0_I_9_RNO_0,
+     drop_cmp_buf_coarse_2_ac0_7
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699 (PFU) covers
+     blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700 (PFU) covers
+     blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
+hades_tdc_bundle_inst/SLICE_701 (PFU) covers blocks:
+     drop_cmp_buf_coarse_2_ac0_13_0, drop_cmp_buf_coarse_2_ac0_9_0
+fifo_colector_inst/fifo40_inst/SLICE_702 (PFU) covers blocks: LUT4_16, LUT4_17
+fifo_colector_inst/fifo40_inst/SLICE_703 (PFU) covers blocks: LUT4_7, LUT4_11
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708 (PFU) covers
+     blocks: LUT4_7, LUT4_11
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709 (PFU) covers
+     blocks: LUT4_17, LUT4_21
+hades_tdc_bundle_inst/SLICE_710 (PFU) covers blocks: hit_valid_pmux_iv_0_m2,
+     drop_cmp_buf_valid_0_sqmuxa_0_a2
+genblk1[2].tdc_channel_fifo_out_inst/SLICE_711 (PFU) covers blocks: AND2_t20,
+     genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712 (PFU) covers
+     blocks: AND2_t19
+genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713 (PFU) covers blocks:
+     valid_internal_RNO_0
+genblk1[1].tdc_channel_fifo_out_inst/SLICE_714 (PFU) covers blocks: AND2_t20,
+     genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715 (PFU) covers
+     blocks: AND2_t19
+genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716 (PFU) covers blocks:
+     valid_internal_RNO_0
+genblk1[0].tdc_channel_fifo_out_inst/SLICE_717 (PFU) covers blocks: AND2_t20,
+     genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718 (PFU) covers
+     blocks: AND2_t19
+genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719 (PFU) covers blocks:
+     valid_internal_RNO_0
+fifo_colector_inst/fifo40_inst/SLICE_720 (PFU) covers blocks: AND2_t19
+fifo_colector_inst/fifo40_inst/SLICE_721 (PFU) covers blocks: AND2_t20
+fifo_colector_inst/SLICE_722 (PFU) covers blocks: iterator_RNI7U5I[1]
+trb_adapter_inst/SLICE_723 (PFU) covers blocks: LVL1_TRG_DATA_VALI_IN_rising
+trb_adapter_inst/SLICE_724 (PFU) covers blocks: release_out,
+     trb_adapter_inst/finished
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725
+     (PFU) covers blocks: valid_RNI97O31,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726
+     (PFU) covers blocks: in_synced_RNIT1GT[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727
+     (PFU) covers blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i_0
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729
+     (PFU) covers blocks: out_internal_2_1_0_.m11_i_m3
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730 (PFU)
+     covers blocks: in_synced_RNIB4EQ[7]
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731 (PFU)
+     covers blocks: valid_RNI8UMR,
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid
+hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732 (PFU)
+     covers blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 (PFU) covers
+     blocks: valid_fast_RNI999V
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734 (PFU) covers
+     blocks: in_synced_RNI3HPF[7]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735 (PFU) covers
+     blocks: un1_out_internal35_1_0_0
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (PFU) covers
+     blocks: valid_fast_RNI5DQ71,
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737 (PFU) covers blocks:
+     un1_reset_0_a2_2
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 (PFU) covers blocks:
+     window_6[2]
+hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739 (PFU) covers blocks:
+     window_RNICU4C[3]
+SLICE_740 (PFU) covers blocks: drop_cmp_buf_0_sqmuxa_0_a2, reset_dl[2]
+hades_tdc_bundle_inst/SLICE_741 (PFU) covers blocks: hit_out_i_6_i_a2_0[0]
+pll0inst/SLICE_742 (PFU) covers blocks: GND
+SLICE_743 (PFU) covers blocks: hades_lvl1_pad_RNINMH5
+SLICE_744 (PFU) covers blocks: trig_pad_RNII4FF[0]
+SLICE_745 (PFU) covers blocks: trig_pad_RNIJ5FF[1]
+SLICE_746 (PFU) covers blocks: trig_pad_RNIK6FF[2]
+SLICE_747 (PFU) covers blocks: hades_trig_pad_RNIE1B4
+hades_raw_valid_vect[0] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[0]
+fifo_data_out[0] (PIC/PIO) covers blocks: fifo_data_out_pad[0]
+clk (PIC/PIO) covers blocks: clk_pad
+hades_drop_cmp_buf_valid (PIC/PIO) covers blocks: hades_drop_cmp_buf_valid_pad
+hades_drop_cmp_buf_coarse[11] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[11]
+hades_drop_cmp_buf_coarse[10] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[10]
+hades_drop_cmp_buf_coarse[9] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[9]
+hades_drop_cmp_buf_coarse[8] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[8]
+hades_drop_cmp_buf_coarse[7] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[7]
+hades_drop_cmp_buf_coarse[6] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[6]
+hades_drop_cmp_buf_coarse[5] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[5]
+hades_drop_cmp_buf_coarse[4] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[4]
+hades_drop_cmp_buf_coarse[3] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[3]
+hades_drop_cmp_buf_coarse[2] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[2]
+hades_drop_cmp_buf_coarse[1] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[1]
+hades_drop_cmp_buf_coarse[0] (PIC/PIO) covers blocks:
+     hades_drop_cmp_buf_coarse_pad[0]
+hades_drop_cmp_buf[11] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[11]
+hades_drop_cmp_buf[10] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[10]
+hades_drop_cmp_buf[9] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[9]
+hades_drop_cmp_buf[8] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[8]
+hades_drop_cmp_buf[7] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[7]
+hades_drop_cmp_buf[6] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[6]
+hades_drop_cmp_buf[5] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[5]
+hades_drop_cmp_buf[4] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[4]
+hades_drop_cmp_buf[3] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[3]
+hades_drop_cmp_buf[2] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[2]
+hades_drop_cmp_buf[1] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[1]
+hades_drop_cmp_buf[0] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[0]
+hades_dbg2_coarse[8] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[8]
+hades_dbg2_coarse[7] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[7]
+hades_dbg2_coarse[6] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[6]
+hades_dbg2_coarse[5] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[5]
+hades_dbg2_coarse[4] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[4]
+hades_dbg2_coarse[3] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[3]
+hades_dbg2_coarse[2] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[2]
+hades_dbg2_coarse[1] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[1]
+hades_dbg2_coarse[0] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[0]
+hades_dbg2_out[31] (PIC/PIO) covers blocks: hades_dbg2_out_pad[31]
+hades_dbg2_out[30] (PIC/PIO) covers blocks: hades_dbg2_out_pad[30]
+hades_dbg2_out[29] (PIC/PIO) covers blocks: hades_dbg2_out_pad[29]
+hades_dbg2_out[28] (PIC/PIO) covers blocks: hades_dbg2_out_pad[28],
+     hades_tdc_bundle_inst_hitbuffer_1_io[23]
+hades_dbg2_out[27] (PIC/PIO) covers blocks: hades_dbg2_out_pad[27],
+     hades_tdc_bundle_inst_hitbuffer_1_io[22]
+hades_dbg2_out[26] (PIC/PIO) covers blocks: hades_dbg2_out_pad[26],
+     hades_tdc_bundle_inst_hitbuffer_1_io[21]
+hades_dbg2_out[25] (PIC/PIO) covers blocks: hades_dbg2_out_pad[25],
+     hades_tdc_bundle_inst_hitbuffer_1_io[20]
+hades_dbg2_out[24] (PIC/PIO) covers blocks: hades_dbg2_out_pad[24],
+     hades_tdc_bundle_inst_hitbuffer_1_io[19]
+hades_dbg2_out[23] (PIC/PIO) covers blocks: hades_dbg2_out_pad[23],
+     hades_tdc_bundle_inst_hitbuffer_1_io[18]
+hades_dbg2_out[22] (PIC/PIO) covers blocks: hades_dbg2_out_pad[22],
+     hades_tdc_bundle_inst_hitbuffer_1_io[17]
+hades_dbg2_out[21] (PIC/PIO) covers blocks: hades_dbg2_out_pad[21],
+     hades_tdc_bundle_inst_hitbuffer_1_io[16]
+hades_dbg2_out[20] (PIC/PIO) covers blocks: hades_dbg2_out_pad[20],
+     hades_tdc_bundle_inst_hitbuffer_1_io[15]
+hades_dbg2_out[19] (PIC/PIO) covers blocks: hades_dbg2_out_pad[19]
+hades_dbg2_out[18] (PIC/PIO) covers blocks: hades_dbg2_out_pad[18],
+     hades_tdc_bundle_inst_hitbuffer_1_io[14]
+hades_dbg2_out[17] (PIC/PIO) covers blocks: hades_dbg2_out_pad[17],
+     hades_tdc_bundle_inst_hitbuffer_1_io[13]
+hades_dbg2_out[16] (PIC/PIO) covers blocks: hades_dbg2_out_pad[16],
+     hades_tdc_bundle_inst_hitbuffer_1_io[12]
+hades_dbg2_out[15] (PIC/PIO) covers blocks: hades_dbg2_out_pad[15]
+hades_dbg2_out[14] (PIC/PIO) covers blocks: hades_dbg2_out_pad[14]
+hades_dbg2_out[13] (PIC/PIO) covers blocks: hades_dbg2_out_pad[13]
+hades_dbg2_out[12] (PIC/PIO) covers blocks: hades_dbg2_out_pad[12]
+hades_dbg2_out[11] (PIC/PIO) covers blocks: hades_dbg2_out_pad[11]
+hades_dbg2_out[10] (PIC/PIO) covers blocks: hades_dbg2_out_pad[10]
+hades_dbg2_out[9] (PIC/PIO) covers blocks: hades_dbg2_out_pad[9]
+hades_dbg2_out[8] (PIC/PIO) covers blocks: hades_dbg2_out_pad[8]
+hades_dbg2_out[7] (PIC/PIO) covers blocks: hades_dbg2_out_pad[7]
+hades_dbg2_out[6] (PIC/PIO) covers blocks: hades_dbg2_out_pad[6]
+hades_dbg2_out[5] (PIC/PIO) covers blocks: hades_dbg2_out_pad[5]
+hades_dbg2_out[4] (PIC/PIO) covers blocks: hades_dbg2_out_pad[4]
+hades_dbg2_out[3] (PIC/PIO) covers blocks: hades_dbg2_out_pad[3]
+hades_dbg2_out[2] (PIC/PIO) covers blocks: hades_dbg2_out_pad[2],
+     hades_tdc_bundle_inst_hitbuffer_1_io[2]
+hades_dbg2_out[1] (PIC/PIO) covers blocks: hades_dbg2_out_pad[1],
+     hades_tdc_bundle_inst_hitbuffer_1_io[1]
+hades_dbg2_out[0] (PIC/PIO) covers blocks: hades_dbg2_out_pad[0],
+     hades_tdc_bundle_inst_hitbuffer_1_io[0]
+hades_buf_drop[3] (PIC/PIO) covers blocks: hades_buf_drop_pad[3]
+hades_buf_drop[2] (PIC/PIO) covers blocks: hades_buf_drop_pad[2]
+hades_buf_drop[1] (PIC/PIO) covers blocks: hades_buf_drop_pad[1],
+     hades_tdc_bundle_inst_buf_drop_1io[1]
+hades_buf_drop[0] (PIC/PIO) covers blocks: hades_buf_drop_pad[0]
+hades_invalid_dl[3] (PIC/PIO) covers blocks: hades_invalid_dl_pad[3]
+hades_invalid_dl[2] (PIC/PIO) covers blocks: hades_invalid_dl_pad[2]
+hades_invalid_dl[1] (PIC/PIO) covers blocks: hades_invalid_dl_pad[1]
+hades_invalid_dl[0] (PIC/PIO) covers blocks: hades_invalid_dl_pad[0]
+hades_discard (PIC/PIO) covers blocks: hades_discard_pad
+hades_hit_valid[3] (PIC/PIO) covers blocks: hades_hit_valid_pad[3]
+hades_hit_valid[2] (PIC/PIO) covers blocks: hades_hit_valid_pad[2]
+hades_hit_valid[1] (PIC/PIO) covers blocks: hades_hit_valid_pad[1]
+hades_hit_valid[0] (PIC/PIO) covers blocks: hades_hit_valid_pad[0]
+hades_hit_out_i[3] (PIC/PIO) covers blocks: hades_hit_out_i_pad[3]
+hades_hit_out_i[2] (PIC/PIO) covers blocks: hades_hit_out_i_pad[2]
+hades_hit_out_i[1] (PIC/PIO) covers blocks: hades_hit_out_i_pad[1]
+hades_hit_out_i[0] (PIC/PIO) covers blocks: hades_hit_out_i_pad[0]
+hades_buf_finished (PIC/PIO) covers blocks: hades_buf_finished_pad
+hades_buf_release (PIC/PIO) covers blocks: hades_buf_release_pad
+hades_buf_out_valid (PIC/PIO) covers blocks: hades_buf_out_valid_pad,
+     hades_tdc_bundle_inst_buf_out_validio
+hades_window_end (PIC/PIO) covers blocks: hades_window_end_pad
+hades_offset_valid (PIC/PIO) covers blocks: hades_offset_valid_pad
+hades_offset[8] (PIC/PIO) covers blocks: hades_offset_pad[8],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8]
+hades_offset[7] (PIC/PIO) covers blocks: hades_offset_pad[7],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7]
+hades_offset[6] (PIC/PIO) covers blocks: hades_offset_pad[6],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]
+hades_offset[5] (PIC/PIO) covers blocks: hades_offset_pad[5],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]
+hades_offset[4] (PIC/PIO) covers blocks: hades_offset_pad[4],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]
+hades_offset[3] (PIC/PIO) covers blocks: hades_offset_pad[3],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]
+hades_offset[2] (PIC/PIO) covers blocks: hades_offset_pad[2],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]
+hades_offset[1] (PIC/PIO) covers blocks: hades_offset_pad[1],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]
+hades_offset[0] (PIC/PIO) covers blocks: hades_offset_pad[0],
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]
+hades_lvl1_invalid (PIC/PIO) covers blocks: hades_lvl1_invalid_pad,
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0]
+hades_lvl1 (PIC/PIO) covers blocks: hades_lvl1_pad,
+     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0]
+hades_raw_valid_vect[1] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[1]
+hades_raw_out_valid (PIC/PIO) covers blocks: hades_raw_out_valid_pad,
+     hades_tdc_bundle_inst_referenced_out_validio
+hades_trig (PIC/PIO) covers blocks: hades_trig_pad
+release_out (PIC/PIO) covers blocks: release_out_pad
+finished (PIC/PIO) covers blocks: finished_pad
+last_buf_empty (PIC/PIO) covers blocks: last_buf_empty_pad
+discard (PIC/PIO) covers blocks: discard_pad
+burst (PIC/PIO) covers blocks: burst_pad
+LVL1_TRG_DATA_VALI_IN_rising (PIC/PIO) covers blocks:
+     LVL1_TRG_DATA_VALI_IN_rising_pad
+FEE_TRG_RELEASE_OUT (PIC/PIO) covers blocks: FEE_TRG_RELEASE_OUT_pad,
+     trb_adapter_inst_FEE_TRG_RELEASE_OUTio
+FEE_DATAFINISHED_OUT (PIC/PIO) covers blocks: FEE_DATAFINISHED_OUT_pad,
+     trb_adapter_inst_FEE_DATAFINISHED_OUTio
+FEE_DATA_WRITE_OUT (PIC/PIO) covers blocks: FEE_DATA_WRITE_OUT_pad,
+     trb_adapter_inst_FEE_DATA_WRITE_OUTio
+FEE_DATA_OUT[31] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[31]
+FEE_DATA_OUT[30] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[30]
+FEE_DATA_OUT[29] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[29]
+FEE_DATA_OUT[28] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[28]
+FEE_DATA_OUT[27] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[27]
+FEE_DATA_OUT[26] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[26]
+FEE_DATA_OUT[25] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[25]
+FEE_DATA_OUT[24] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[24]
+FEE_DATA_OUT[23] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[23]
+FEE_DATA_OUT[22] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[22]
+FEE_DATA_OUT[21] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[21]
+FEE_DATA_OUT[20] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[20]
+FEE_DATA_OUT[19] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[19]
+FEE_DATA_OUT[18] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[18]
+FEE_DATA_OUT[17] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[17]
+FEE_DATA_OUT[16] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[16]
+FEE_DATA_OUT[15] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[15]
+FEE_DATA_OUT[14] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[14]
+FEE_DATA_OUT[13] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[13]
+FEE_DATA_OUT[12] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[12]
+FEE_DATA_OUT[11] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[11]
+FEE_DATA_OUT[10] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[10]
+FEE_DATA_OUT[9] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[9]
+FEE_DATA_OUT[8] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[8]
+FEE_DATA_OUT[7] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[7]
+FEE_DATA_OUT[6] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[6]
+FEE_DATA_OUT[5] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[5]
+FEE_DATA_OUT[4] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[4]
+FEE_DATA_OUT[3] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[3]
+FEE_DATA_OUT[2] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[2]
+FEE_DATA_OUT[1] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[1]
+FEE_DATA_OUT[0] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[0]
+LVL1_INVALID_TRG_IN (PIC/PIO) covers blocks: LVL1_INVALID_TRG_IN_pad,
+     trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0]
+LVL1_TRG_DATA_VALID_IN (PIC/PIO) covers blocks: LVL1_TRG_DATA_VALID_IN_pad,
+     trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0]
+fifo_empty1 (PIC/PIO) covers blocks: fifo_empty1_pad
+fifo_rden (PIC/PIO) covers blocks: fifo_rden_pad
+fifo_data_out[31] (PIC/PIO) covers blocks: fifo_data_out_pad[31]
+fifo_data_out[30] (PIC/PIO) covers blocks: fifo_data_out_pad[30]
+fifo_data_out[29] (PIC/PIO) covers blocks: fifo_data_out_pad[29]
+fifo_data_out[28] (PIC/PIO) covers blocks: fifo_data_out_pad[28]
+fifo_data_out[27] (PIC/PIO) covers blocks: fifo_data_out_pad[27]
+fifo_data_out[26] (PIC/PIO) covers blocks: fifo_data_out_pad[26]
+fifo_data_out[25] (PIC/PIO) covers blocks: fifo_data_out_pad[25]
+fifo_data_out[24] (PIC/PIO) covers blocks: fifo_data_out_pad[24]
+fifo_data_out[23] (PIC/PIO) covers blocks: fifo_data_out_pad[23]
+fifo_data_out[22] (PIC/PIO) covers blocks: fifo_data_out_pad[22]
+fifo_data_out[21] (PIC/PIO) covers blocks: fifo_data_out_pad[21]
+fifo_data_out[20] (PIC/PIO) covers blocks: fifo_data_out_pad[20]
+fifo_data_out[19] (PIC/PIO) covers blocks: fifo_data_out_pad[19]
+fifo_data_out[18] (PIC/PIO) covers blocks: fifo_data_out_pad[18]
+fifo_data_out[17] (PIC/PIO) covers blocks: fifo_data_out_pad[17]
+fifo_data_out[16] (PIC/PIO) covers blocks: fifo_data_out_pad[16]
+fifo_data_out[15] (PIC/PIO) covers blocks: fifo_data_out_pad[15]
+fifo_data_out[14] (PIC/PIO) covers blocks: fifo_data_out_pad[14]
+fifo_data_out[13] (PIC/PIO) covers blocks: fifo_data_out_pad[13]
+fifo_data_out[12] (PIC/PIO) covers blocks: fifo_data_out_pad[12]
+fifo_data_out[11] (PIC/PIO) covers blocks: fifo_data_out_pad[11]
+fifo_data_out[10] (PIC/PIO) covers blocks: fifo_data_out_pad[10]
+fifo_data_out[9] (PIC/PIO) covers blocks: fifo_data_out_pad[9]
+fifo_data_out[8] (PIC/PIO) covers blocks: fifo_data_out_pad[8]
+fifo_data_out[7] (PIC/PIO) covers blocks: fifo_data_out_pad[7]
+fifo_data_out[6] (PIC/PIO) covers blocks: fifo_data_out_pad[6]
+fifo_data_out[5] (PIC/PIO) covers blocks: fifo_data_out_pad[5]
+fifo_data_out[4] (PIC/PIO) covers blocks: fifo_data_out_pad[4]
+fifo_data_out[3] (PIC/PIO) covers blocks: fifo_data_out_pad[3]
+fifo_data_out[2] (PIC/PIO) covers blocks: fifo_data_out_pad[2]
+fifo_data_out[1] (PIC/PIO) covers blocks: fifo_data_out_pad[1]
+trig[2] (PIC/PIO) covers blocks: trig_pad[2]
+trig[1] (PIC/PIO) covers blocks: trig_pad[1]
+trig[0] (PIC/PIO) covers blocks: trig_pad[0]
+reset_dc (PIC/PIO) covers blocks: reset_dc_pad, reset_dl_0io[1]
+rd_clk (PIC/PIO) covers blocks: rd_clk_pad
+genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
+     covers block:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 (PDPW16KD) covers block:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
+pll0inst/PLLInst_0 (EHXPLLL) covers block: pll0inst/PLLInst_0
+
+
+<A name="mrp_sig"></A><B><U><big>Signal Cross Reference</big></U></B>
+Signal FEE_DATA_OUT_c[0] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO18
+   Load Comps: fifo_data_out[0]:I0, FEE_DATA_OUT[0]:I0
+Signal clk_c - Driver Comp: clk:O0
+   Load Comps: pll0inst/PLLInst_0:CLKI
+Signal reset_dl[1] - Driver Comp: reset_dc_MGIOL:O2
+   Load Comps: SLICE_740:I4
+Signal pll_clks[3] - Driver Comp: pll0inst/PLLInst_0:CLKOS3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_79:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_80:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_81:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_82:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_83:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_103:I15,
+        hades_tdc_bundle_inst/SLICE_121:I15,
+        hades_tdc_bundle_inst/SLICE_122:I15,
+        hades_tdc_bundle_inst/SLICE_123:I15, fifo_colector_inst/SLICE_125:I15,
+        fifo_colector_inst/SLICE_126:I15, fifo_colector_inst/SLICE_127:I15,
+        fifo_colector_inst/SLICE_128:I15, fifo_colector_inst/SLICE_129:I15,
+        fifo_colector_inst/SLICE_130:I15, fifo_colector_inst/SLICE_131:I15,
+        fifo_colector_inst/SLICE_132:I15, fifo_colector_inst/SLICE_133:I15,
+        fifo_colector_inst/SLICE_134:I15, fifo_colector_inst/SLICE_135:I15,
+        fifo_colector_inst/SLICE_136:I15, fifo_colector_inst/SLICE_137:I15,
+        fifo_colector_inst/SLICE_138:I15, fifo_colector_inst/SLICE_139:I15,
+        fifo_colector_inst/SLICE_140:I15, fifo_colector_inst/SLICE_141:I15,
+        fifo_colector_inst/SLICE_142:I15, fifo_colector_inst/SLICE_143:I15,
+        fifo_colector_inst/SLICE_144:I15, fifo_colector_inst/SLICE_145:I15,
+        fifo_colector_inst/SLICE_146:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_152:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_153:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_154:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_155:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_156:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_157:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_158:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_159:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_160:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_161:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I15,
+        fifo_colector_inst/SLICE_187:I15, fifo_colector_inst/SLICE_189:I15,
+        fifo_colector_inst/SLICE_190:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I15,
+        hades_tdc_bundle_inst/SLICE_432:I15,
+        hades_tdc_bundle_inst/SLICE_433:I15,
+        hades_tdc_bundle_inst/SLICE_434:I15,
+        hades_tdc_bundle_inst/SLICE_435:I15,
+        hades_tdc_bundle_inst/SLICE_436:I15,
+        hades_tdc_bundle_inst/SLICE_437:I15,
+        hades_tdc_bundle_inst/SLICE_438:I15,
+        hades_tdc_bundle_inst/SLICE_439:I15,
+        hades_tdc_bundle_inst/SLICE_440:I15,
+        hades_tdc_bundle_inst/SLICE_441:I15,
+        hades_tdc_bundle_inst/SLICE_442:I15,
+        hades_tdc_bundle_inst/SLICE_443:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I15,
+        hades_tdc_bundle_inst/SLICE_445:I15,
+        hades_tdc_bundle_inst/SLICE_446:I15,
+        hades_tdc_bundle_inst/SLICE_447:I15,
+        hades_tdc_bundle_inst/SLICE_448:I15,
+        hades_tdc_bundle_inst/SLICE_449:I15,
+        hades_tdc_bundle_inst/SLICE_450:I15,
+        hades_tdc_bundle_inst/SLICE_451:I15,
+        hades_tdc_bundle_inst/SLICE_452:I15,
+        hades_tdc_bundle_inst/SLICE_453:I15,
+        hades_tdc_bundle_inst/SLICE_454:I15,
+        hades_tdc_bundle_inst/SLICE_455:I15,
+        hades_tdc_bundle_inst/SLICE_456:I15,
+        hades_tdc_bundle_inst/SLICE_457:I15,
+        hades_tdc_bundle_inst/SLICE_458:I15,
+        hades_tdc_bundle_inst/SLICE_459:I15,
+        hades_tdc_bundle_inst/SLICE_460:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I15,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I15, hade
+        s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:I15,
+         hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544
+        :I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLIC
+        E_545:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_546:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
+        _inst/SLICE_547:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+        t/dec_inst/SLICE_548:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/dec_inst/SLICE_549:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_inst/SLICE_550:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/dec_inst/SLICE_551:I15, hades_tdc_bundle_inst/hades_tdc
+        _channel_raw_out_inst/dec_inst/SLICE_552:I15, hades_tdc_bundle_inst/hade
+        s_tdc_channel_raw_out_inst/dec_inst/SLICE_553:I15, hades_tdc_bundle_inst
+        /hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:I15, hades_tdc_bundle
+        _inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:I15, hades_
+        tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:I15, h
+        ades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:I
+        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
+        ICE_559:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
+        g_inst/SLICE_560:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_neg_inst/SLICE_561:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_562:I15, hades_tdc_bundle_inst/hades_tdc_
+        channel_raw_out_inst/dec_neg_inst/SLICE_563:I15, hades_tdc_bundle_inst/h
+        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564:I15, hades_tdc_bund
+        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565:I15, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566:I
+        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
+        ICE_567:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
+        g_inst/SLICE_568:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_neg_inst/SLICE_569:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_570:I15, hades_tdc_bundle_inst/hades_tdc_
+        channel_raw_out_inst/dec_neg_inst/SLICE_571:I15, hades_tdc_bundle_inst/h
+        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572:I15, hades_tdc_bund
+        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573:I15, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:I15, 
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:
+        I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/S
+        LICE_576:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_n
+        eg_inst/SLICE_577:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_inst/SLICE_591:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_
+        out_inst/tdc_inst/SLICE_595:I15, hades_tdc_bundle_inst/hades_tdc_channel
+        _raw_out_inst/tdc_neg_inst/SLICE_607:I15, hades_tdc_bundle_inst/hades_td
+        c_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I15, hades_tdc_bundle_inst
+        /hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:I15, hades_tdc_bundle
+        _inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_62
+        7:I15, hades_tdc_bundle_inst/SLICE_628:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I15, hades_tdc_bundle_ins
+        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I15, hades_tdc_b
+        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I15,
+        SLICE_740:I15, hades_dbg2_out[28]_MGIOL:I6, hades_dbg2_out[27]_MGIOL:I6,
+        hades_dbg2_out[26]_MGIOL:I6, hades_dbg2_out[25]_MGIOL:I6,
+        hades_dbg2_out[24]_MGIOL:I6, hades_dbg2_out[23]_MGIOL:I6,
+        hades_dbg2_out[22]_MGIOL:I6, hades_dbg2_out[21]_MGIOL:I6,
+        hades_dbg2_out[20]_MGIOL:I6, hades_dbg2_out[18]_MGIOL:I6,
+        hades_dbg2_out[17]_MGIOL:I6, hades_dbg2_out[16]_MGIOL:I6,
+        hades_dbg2_out[2]_MGIOL:I6, hades_dbg2_out[1]_MGIOL:I6,
+        hades_dbg2_out[0]_MGIOL:I6, hades_buf_drop[1]_MGIOL:I6,
+        hades_buf_out_valid_MGIOL:I6, hades_offset[8]_MGIOL:I6,
+        hades_offset[7]_MGIOL:I6, hades_offset[6]_MGIOL:I6,
+        hades_offset[5]_MGIOL:I6, hades_offset[4]_MGIOL:I6,
+        hades_offset[3]_MGIOL:I6, hades_offset[2]_MGIOL:I6,
+        hades_offset[1]_MGIOL:I6, hades_offset[0]_MGIOL:I6,
+        hades_lvl1_invalid_MGIOL:I6, hades_lvl1_MGIOL:I6,
+        hades_raw_out_valid_MGIOL:I6, reset_dc_MGIOL:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKW
+Signal reset_dl[2] - Driver Comp: SLICE_740:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I16,
+        hades_tdc_bundle_inst/SLICE_122:I16,
+        hades_tdc_bundle_inst/SLICE_123:I16,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I16,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I16,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I16,
+        hades_tdc_bundle_inst/SLICE_432:I16,
+        hades_tdc_bundle_inst/SLICE_433:I16,
+        hades_tdc_bundle_inst/SLICE_434:I16,
+        hades_tdc_bundle_inst/SLICE_435:I16,
+        hades_tdc_bundle_inst/SLICE_436:I16,
+        hades_tdc_bundle_inst/SLICE_437:I16,
+        hades_tdc_bundle_inst/SLICE_438:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I16,
+        hades_tdc_bundle_inst/SLICE_456:I14,
+        hades_tdc_bundle_inst/SLICE_457:I14,
+        hades_tdc_bundle_inst/SLICE_458:I14,
+        hades_tdc_bundle_inst/SLICE_459:I14,
+        hades_tdc_bundle_inst/SLICE_460:I14,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I16,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I14,
+        hades_tdc_bundle_inst/SLICE_628:I16, hades_tdc_bundle_inst/SLICE_653:I4,
+        hades_tdc_bundle_inst/SLICE_693:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I16,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I16,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I16, hades_tdc_bundle_ins
+        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I2, hades_tdc_bu
+        ndle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I3,
+        SLICE_740:I1, hades_buf_drop[1]_MGIOL:I9, FEE_TRG_RELEASE_OUT_MGIOL:I9,
+        FEE_DATAFINISHED_OUT_MGIOL:I9, FEE_DATA_WRITE_OUT_MGIOL:I9
+Signal hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_710:O1
+   Load Comps: hades_buf_drop[1]_MGIOL:I10
+Signal hades_buf_drop_c[1] - Driver Comp: hades_buf_drop[1]_MGIOL:O0
+   Load Comps: hades_buf_drop[1]:I1
+Signal hades_tdc_bundle_inst.buf_out12 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_683:O0
+   Load Comps: hades_buf_out_valid_MGIOL:I10
+Signal N_248_i - Driver Comp: hades_tdc_bundle_inst/SLICE_653:O2
+   Load Comps: hades_buf_out_valid_MGIOL:I8
+Signal hades_buf_out_valid_c - Driver Comp: hades_buf_out_valid_MGIOL:O0
+   Load Comps: hades_buf_out_valid:I1
+Signal hades_lvl1_invalid_c - Driver Comp: hades_lvl1_invalid:O0
+   Load Comps: hades_lvl1_invalid_MGIOL:I5
+Signal hades_invalid_dl_c[0] - Driver Comp: hades_lvl1_invalid_MGIOL:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I4,
+        hades_invalid_dl[0]:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I4,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I8,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O4
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O3
+   Load Comps:
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I14,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_128:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_129:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_130:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_131:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_132:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_133:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_138:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_138:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_139:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_139:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_140:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_140:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_141:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_141:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+   Load Comps: fifo_colector_inst/SLICE_142:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_142:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_143:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_143:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_144:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_144:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_145:I2
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_145:I8
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_126:I4
+Signal genblk1[2].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_127:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I6,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I7,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O1
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I13
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I12
+Signal fifo_empty[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I6, fifo_colector_inst/SLICE_680:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I1,
+        fifo_colector_inst/SLICE_722:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:O6
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I17
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I0
+Signal fifo_read[2] - Driver Comp: fifo_colector_inst/SLICE_190:O3
+   Load Comps: fifo_colector_inst/SLICE_190:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I12
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I16
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I1,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I7
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I2,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I8
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I3,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I9
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I0,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I6
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I0
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I1
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:O2
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I3
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I4
+Signal trig_c_i[2] - Driver Comp: SLICE_746:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I5,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I5
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I4
+Signal pll_clks[2] - Driver Comp: pll0inst/PLLInst_0:CLKOS2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        94:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+        t/SLICE_606:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_610:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_614:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_618:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_622:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:I15
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I4
+Signal pll_clks[1] - Driver Comp: pll0inst/PLLInst_0:CLKOS
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        93:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+        t/SLICE_605:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_609:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_613:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_617:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_621:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:I15
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I4
+Signal pll_clks[0] - Driver Comp: pll0inst/PLLInst_0:CLKOP
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I15,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I15,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I15,
+        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I15,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I15, ha
+        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:I1
+        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
+        92:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
+        t/SLICE_604:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
+        c_neg_inst/SLICE_608:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
+        t_inst/tdc_inst/SLICE_612:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_616:I15, hades_tdc_bundle_inst/hades_tdc_chan
+        nel_raw_out_inst/tdc_neg_inst/SLICE_620:I15, hades_tdc_bundle_inst/hades
+        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:I15,
+        pll0inst/PLLInst_0:CLKFB
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O4
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O3
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I4
+Signal genblk1[2].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O0
+   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I4,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O4
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O3
+   Load Comps:
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I14,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_135:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_135:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_136:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_136:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_137:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_137:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_142:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_142:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_143:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_143:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_144:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_144:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_145:I1
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_145:I7
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+   Load Comps: fifo_colector_inst/SLICE_126:I2, fifo_colector_inst/SLICE_126:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_127:I2, fifo_colector_inst/SLICE_127:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_128:I2, fifo_colector_inst/SLICE_128:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_129:I2, fifo_colector_inst/SLICE_129:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_130:I2, fifo_colector_inst/SLICE_130:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_131:I2, fifo_colector_inst/SLICE_131:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_132:I2, fifo_colector_inst/SLICE_132:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_133:I2, fifo_colector_inst/SLICE_133:I8
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_134:I2
+Signal genblk1[1].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_134:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I6,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O1
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I13
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I12
+Signal fifo_empty[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I2, fifo_colector_inst/SLICE_680:I8,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:O6
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I17
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I0
+Signal fifo_read[1] - Driver Comp: fifo_colector_inst/SLICE_189:O4
+   Load Comps: fifo_colector_inst/SLICE_189:I7,
+        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I12
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I16
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I1,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I7
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I2,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I8
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I3,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I9
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I0,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I6
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I0
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I1
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:O2
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I3
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I4
+Signal trig_c_i[1] - Driver Comp: SLICE_745:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I5,
+        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I5
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O4
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O3
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I4
+Signal genblk1[1].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O0
+   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
+     Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I4,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I8,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O4
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O3
+   Load Comps:
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I14,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
+   Load Comps: fifo_colector_inst/SLICE_139:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
+   Load Comps: fifo_colector_inst/SLICE_139:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
+   Load Comps: fifo_colector_inst/SLICE_140:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
+   Load Comps: fifo_colector_inst/SLICE_140:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
+   Load Comps: fifo_colector_inst/SLICE_141:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
+   Load Comps: fifo_colector_inst/SLICE_141:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
+   Load Comps: fifo_colector_inst/SLICE_126:I1, fifo_colector_inst/SLICE_126:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
+   Load Comps: fifo_colector_inst/SLICE_127:I1, fifo_colector_inst/SLICE_127:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
+   Load Comps: fifo_colector_inst/SLICE_128:I1, fifo_colector_inst/SLICE_128:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
+   Load Comps: fifo_colector_inst/SLICE_129:I1, fifo_colector_inst/SLICE_129:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
+   Load Comps: fifo_colector_inst/SLICE_130:I1, fifo_colector_inst/SLICE_130:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
+   Load Comps: fifo_colector_inst/SLICE_131:I1, fifo_colector_inst/SLICE_131:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
+   Load Comps: fifo_colector_inst/SLICE_132:I1, fifo_colector_inst/SLICE_132:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
+   Load Comps: fifo_colector_inst/SLICE_133:I1, fifo_colector_inst/SLICE_133:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
+   Load Comps: fifo_colector_inst/SLICE_134:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
+   Load Comps: fifo_colector_inst/SLICE_134:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
+   Load Comps: fifo_colector_inst/SLICE_135:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
+   Load Comps: fifo_colector_inst/SLICE_135:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
+   Load Comps: fifo_colector_inst/SLICE_136:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
+   Load Comps: fifo_colector_inst/SLICE_136:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
+   Load Comps: fifo_colector_inst/SLICE_137:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
+   Load Comps: fifo_colector_inst/SLICE_137:I7
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
+   Load Comps: fifo_colector_inst/SLICE_138:I1
+Signal genblk1[0].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
+   Load Comps: fifo_colector_inst/SLICE_138:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I6,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O1
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I13
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I12
+Signal fifo_empty1_c - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I1, fifo_colector_inst/SLICE_680:I7,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I1,
+        fifo_empty1:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:O6
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I17
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I0
+Signal fifo_read[0] - Driver Comp: fifo_colector_inst/SLICE_189:O3
+   Load Comps: fifo_colector_inst/SLICE_189:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I12
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
+     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I16
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I1,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I7
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I2,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I8
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I3,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I9
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I0,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I6
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I0
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I1
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
+     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:O2
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I3
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I4
+Signal trig_c_i[0] - Driver Comp: SLICE_744:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I5,
+        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I5
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O4
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
+     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O3
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I4
+Signal genblk1[0].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
+     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O0
+   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I12
+Signal fifo_colector_inst/data_buffer_3[31] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O1
+   Load Comps: fifo_colector_inst/SLICE_145:I13
+Signal fifo_colector_inst/in_empty_pmux_i - Driver Comp:
+     fifo_colector_inst/SLICE_125:O2
+   Load Comps: fifo_colector_inst/SLICE_125:I12,
+        fifo_colector_inst/SLICE_126:I14, fifo_colector_inst/SLICE_127:I14,
+        fifo_colector_inst/SLICE_128:I14, fifo_colector_inst/SLICE_129:I14,
+        fifo_colector_inst/SLICE_130:I14, fifo_colector_inst/SLICE_131:I14,
+        fifo_colector_inst/SLICE_132:I14, fifo_colector_inst/SLICE_133:I14,
+        fifo_colector_inst/SLICE_134:I14, fifo_colector_inst/SLICE_135:I14,
+        fifo_colector_inst/SLICE_136:I14, fifo_colector_inst/SLICE_137:I14,
+        fifo_colector_inst/SLICE_138:I14, fifo_colector_inst/SLICE_139:I14,
+        fifo_colector_inst/SLICE_140:I14, fifo_colector_inst/SLICE_141:I14,
+        fifo_colector_inst/SLICE_142:I14, fifo_colector_inst/SLICE_143:I14,
+        fifo_colector_inst/SLICE_144:I14, fifo_colector_inst/SLICE_145:I14,
+        fifo_colector_inst/SLICE_146:I14
+Signal fifo_colector_inst/iterator_RNI7U5I[1] - Driver Comp:
+     fifo_colector_inst/SLICE_722:O0
+   Load Comps: fifo_colector_inst/SLICE_134:I16,
+        fifo_colector_inst/SLICE_135:I16, fifo_colector_inst/SLICE_136:I16,
+        fifo_colector_inst/SLICE_137:I16, fifo_colector_inst/SLICE_138:I16,
+        fifo_colector_inst/SLICE_139:I16, fifo_colector_inst/SLICE_140:I16,
+        fifo_colector_inst/SLICE_141:I16, fifo_colector_inst/SLICE_142:I16,
+        fifo_colector_inst/SLICE_143:I16, fifo_colector_inst/SLICE_144:I16,
+        fifo_colector_inst/SLICE_145:I16
+Signal fifo_colector_inst/data_buffer[31] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI31
+Signal fifo_colector_inst/data_buffer[0] - Driver Comp:
+     fifo_colector_inst/SLICE_126:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI0
+Signal fifo_colector_inst/data_buffer[1] - Driver Comp:
+     fifo_colector_inst/SLICE_127:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI1
+Signal fifo_colector_inst/data_buffer[2] - Driver Comp:
+     fifo_colector_inst/SLICE_128:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI2
+Signal fifo_colector_inst/data_buffer[3] - Driver Comp:
+     fifo_colector_inst/SLICE_129:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI3
+Signal fifo_colector_inst/data_buffer[4] - Driver Comp:
+     fifo_colector_inst/SLICE_130:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI4
+Signal fifo_colector_inst/data_buffer[5] - Driver Comp:
+     fifo_colector_inst/SLICE_131:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI5
+Signal fifo_colector_inst/data_buffer[6] - Driver Comp:
+     fifo_colector_inst/SLICE_132:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI6
+Signal fifo_colector_inst/data_buffer[7] - Driver Comp:
+     fifo_colector_inst/SLICE_133:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI7
+Signal fifo_colector_inst/data_buffer[8] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI8
+Signal fifo_colector_inst/data_buffer[9] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI9
+Signal fifo_colector_inst/data_buffer[10] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI10
+Signal fifo_colector_inst/data_buffer[11] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI11
+Signal fifo_colector_inst/data_buffer[12] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI12
+Signal fifo_colector_inst/data_buffer[13] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI13
+Signal fifo_colector_inst/data_buffer[14] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI14
+Signal fifo_colector_inst/data_buffer[15] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI15
+Signal fifo_colector_inst/data_buffer[16] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI16
+Signal fifo_colector_inst/data_buffer[17] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI17
+Signal fifo_colector_inst/data_buffer[18] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI18
+Signal fifo_colector_inst/data_buffer[19] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI19
+Signal fifo_colector_inst/data_buffer[20] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI20
+Signal fifo_colector_inst/data_buffer[21] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI21
+Signal fifo_colector_inst/data_buffer[22] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI22
+Signal fifo_colector_inst/data_buffer[23] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI23
+Signal fifo_colector_inst/data_buffer[24] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI24
+Signal fifo_colector_inst/data_buffer[25] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI25
+Signal fifo_colector_inst/data_buffer[26] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI26
+Signal fifo_colector_inst/data_buffer[27] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI27
+Signal fifo_colector_inst/data_buffer[28] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI28
+Signal fifo_colector_inst/data_buffer[29] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI29
+Signal fifo_colector_inst/data_buffer[30] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI30
+Signal fifo_colector_inst/data_buffer[32] - Driver Comp:
+     fifo_colector_inst/SLICE_146:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI32
+Signal fifo_colector_inst/data_buffer[33] - Driver Comp:
+     fifo_colector_inst/SLICE_146:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI33
+Signal fifo_colector_inst/fifo40_inst/wptr_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_182:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW0
+Signal fifo_colector_inst/fifo40_inst/wptr_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_182:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW1
+Signal fifo_colector_inst/fifo40_inst/wptr_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_183:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW2
+Signal fifo_colector_inst/fifo40_inst/wptr_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_183:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW3
+Signal fifo_colector_inst/fifo40_inst/wptr_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_184:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW4
+Signal fifo_colector_inst/fifo40_inst/wptr_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_184:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW5
+Signal fifo_colector_inst/fifo40_inst/wptr_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_185:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW6
+Signal fifo_colector_inst/fifo40_inst/wptr_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_185:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW7
+Signal fifo_colector_inst/fifo40_inst/wptr_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_186:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW8
+Signal fifo_colector_inst/fifo40_inst/wren_i - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_721:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_80:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_81:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_82:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_83:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_97:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_97:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I14,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CEW
+Signal fifo_colector_inst/fifo40_inst/rptr_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_162:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR5
+Signal fifo_colector_inst/fifo40_inst/rptr_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_162:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR6
+Signal fifo_colector_inst/fifo40_inst/rptr_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_163:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR7
+Signal fifo_colector_inst/fifo40_inst/rptr_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_163:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR8
+Signal fifo_colector_inst/fifo40_inst/rptr_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_164:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR9
+Signal fifo_colector_inst/fifo40_inst/rptr_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_164:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR10
+Signal fifo_colector_inst/fifo40_inst/rptr_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_165:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR11
+Signal fifo_colector_inst/fifo40_inst/rptr_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_165:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR12
+Signal fifo_colector_inst/fifo40_inst/rptr_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_166:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR13
+Signal fifo_colector_inst/fifo40_inst/rden_i - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_720:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_86:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_87:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_88:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_89:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_90:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_90:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I14,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I14,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CER,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:OCER
+Signal rd_clk_c - Driver Comp: rd_clk:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_86:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_87:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_88:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_89:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_96:I15,
+        trb_adapter_inst/SLICE_124:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_172:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_173:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_174:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_175:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_176:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_177:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_178:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_179:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_180:I15,
+        fifo_colector_inst/fifo40_inst/SLICE_181:I15,
+        trb_adapter_inst/SLICE_188:I15, trb_adapter_inst/SLICE_631:I15,
+        trb_adapter_inst/SLICE_632:I15, trb_adapter_inst/SLICE_633:I15,
+        trb_adapter_inst/SLICE_724:I15, FEE_TRG_RELEASE_OUT_MGIOL:I6,
+        FEE_DATAFINISHED_OUT_MGIOL:I6, FEE_DATA_WRITE_OUT_MGIOL:I6,
+        LVL1_INVALID_TRG_IN_MGIOL:I6, LVL1_TRG_DATA_VALID_IN_MGIOL:I6,
+        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKR
+Signal FEE_DATA_OUT_c[18] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO0
+   Load Comps: FEE_DATA_OUT[18]:I0, fifo_data_out[18]:I0
+Signal FEE_DATA_OUT_c[19] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO1
+   Load Comps: FEE_DATA_OUT[19]:I0, fifo_data_out[19]:I0
+Signal FEE_DATA_OUT_c[20] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO2
+   Load Comps: FEE_DATA_OUT[20]:I0, fifo_data_out[20]:I0
+Signal FEE_DATA_OUT_c[21] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO3
+   Load Comps: FEE_DATA_OUT[21]:I0, fifo_data_out[21]:I0
+Signal FEE_DATA_OUT_c[22] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO4
+   Load Comps: FEE_DATA_OUT[22]:I0, fifo_data_out[22]:I0
+Signal FEE_DATA_OUT_c[23] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO5
+   Load Comps: FEE_DATA_OUT[23]:I0, fifo_data_out[23]:I0
+Signal FEE_DATA_OUT_c[24] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO6
+   Load Comps: FEE_DATA_OUT[24]:I0, fifo_data_out[24]:I0
+Signal FEE_DATA_OUT_c[25] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO7
+   Load Comps: FEE_DATA_OUT[25]:I0, fifo_data_out[25]:I0
+Signal FEE_DATA_OUT_c[26] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO8
+   Load Comps: FEE_DATA_OUT[26]:I0, fifo_data_out[26]:I0
+Signal FEE_DATA_OUT_c[27] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO9
+   Load Comps: FEE_DATA_OUT[27]:I0, fifo_data_out[27]:I0
+Signal FEE_DATA_OUT_c[28] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO10
+   Load Comps: FEE_DATA_OUT[28]:I0, fifo_data_out[28]:I0
+Signal FEE_DATA_OUT_c[29] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO11
+   Load Comps: FEE_DATA_OUT[29]:I0, fifo_data_out[29]:I0
+Signal FEE_DATA_OUT_c[30] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO12
+   Load Comps: FEE_DATA_OUT[30]:I0, fifo_data_out[30]:I0
+Signal FEE_DATA_OUT_c[31] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO13
+   Load Comps: FEE_DATA_OUT[31]:I0, fifo_data_out[31]:I0
+Signal FEE_DATA_OUT_c[1] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO19
+   Load Comps: FEE_DATA_OUT[1]:I0, fifo_data_out[1]:I0
+Signal FEE_DATA_OUT_c[2] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO20
+   Load Comps: FEE_DATA_OUT[2]:I0, fifo_data_out[2]:I0
+Signal FEE_DATA_OUT_c[3] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO21
+   Load Comps: FEE_DATA_OUT[3]:I0, fifo_data_out[3]:I0
+Signal FEE_DATA_OUT_c[4] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO22
+   Load Comps: FEE_DATA_OUT[4]:I0, fifo_data_out[4]:I0
+Signal FEE_DATA_OUT_c[5] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO23
+   Load Comps: FEE_DATA_OUT[5]:I0, fifo_data_out[5]:I0
+Signal FEE_DATA_OUT_c[6] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO24
+   Load Comps: FEE_DATA_OUT[6]:I0, fifo_data_out[6]:I0
+Signal FEE_DATA_OUT_c[7] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO25
+   Load Comps: FEE_DATA_OUT[7]:I0, fifo_data_out[7]:I0
+Signal FEE_DATA_OUT_c[8] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO26
+   Load Comps: FEE_DATA_OUT[8]:I0, fifo_data_out[8]:I0
+Signal FEE_DATA_OUT_c[9] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO27
+   Load Comps: FEE_DATA_OUT[9]:I0, fifo_data_out[9]:I0
+Signal FEE_DATA_OUT_c[10] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO28
+   Load Comps: FEE_DATA_OUT[10]:I0, fifo_data_out[10]:I0
+Signal FEE_DATA_OUT_c[11] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO29
+   Load Comps: FEE_DATA_OUT[11]:I0, fifo_data_out[11]:I0
+Signal FEE_DATA_OUT_c[12] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO30
+   Load Comps: FEE_DATA_OUT[12]:I0, fifo_data_out[12]:I0
+Signal FEE_DATA_OUT_c[13] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO31
+   Load Comps: FEE_DATA_OUT[13]:I0, fifo_data_out[13]:I0
+Signal FEE_DATA_OUT_c[14] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO32
+   Load Comps: FEE_DATA_OUT[14]:I0, fifo_data_out[14]:I0
+Signal FEE_DATA_OUT_c[15] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO33
+   Load Comps: FEE_DATA_OUT[15]:I0, fifo_data_out[15]:I0
+Signal FEE_DATA_OUT_c[16] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO34
+   Load Comps: FEE_DATA_OUT[16]:I0, fifo_data_out[16]:I0
+Signal FEE_DATA_OUT_c[17] - Driver Comp:
+     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO35
+   Load Comps: FEE_DATA_OUT[17]:I0, fifo_data_out[17]:I0
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w29 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_161:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I7
+Signal fifo_colector_inst/fifo40_inst/wptr_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_186:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_691:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_691:I8
+Signal fifo_colector_inst/fifo40_inst/full_cmp_clr - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_691:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I7
+Signal fifo_colector_inst/fifo40_inst/full_d - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_103:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I12
+Signal fifo_colector_inst/fifo40_inst/Full - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_103:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I1
+Signal fifo_colector_inst/fifo40_inst/empty_d - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_96:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I12
+Signal last_buf_empty_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_96:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_720:I1, last_buf_empty:I0
+Signal fifo_colector_inst/fifo40_inst/rcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I5,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I7
+Signal fifo_colector_inst/fifo40_inst/rptr_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_166:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_692:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I8
+Signal fifo_colector_inst/fifo40_inst/ircount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_91:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r29 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_181:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_692:I6
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r28 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_181:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I1
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r27 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_180:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I2
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r26 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_180:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I7
+Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_673:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_673:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I6
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r25 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_179:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I7
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r24 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_179:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I8
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r23 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_178:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I9
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r22 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_178:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I3
+Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_674:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_702:I0
+Signal fifo_colector_inst/fifo40_inst/wcount_r8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_675:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_675:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_676:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_676:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_675:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_676:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I1
+Signal fifo_colector_inst/fifo40_inst/wcount_r3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_702:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_702:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I1
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r21 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_177:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_674:I6
+Signal fifo_colector_inst/fifo40_inst/wcount_r1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_674:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I7
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r20 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_177:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I7
+Signal fifo_colector_inst/fifo40_inst/wcount_r0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_673:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w28 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_161:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I7
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w27 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_160:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I2
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w26 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_160:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_648:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_649:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I3,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I7
+Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_677:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I0
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w25 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_159:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_649:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w24 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_159:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I9,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I2
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w23 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_158:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I2,
+        fifo_colector_inst/fifo40_inst/SLICE_703:I3
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w22 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_158:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I3
+Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_678:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_677:I8,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_703:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I1
+Signal fifo_colector_inst/fifo40_inst/rcount_w7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_679:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_679:I6
+Signal fifo_colector_inst/fifo40_inst/rcount_w5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_649:O2
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_679:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I1
+Signal fifo_colector_inst/fifo40_inst/rcount_w3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_703:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_648:O2
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I1
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w21 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_157:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_678:I6
+Signal fifo_colector_inst/fifo40_inst/rcount_w1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_678:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I7
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w20 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_157:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I7
+Signal fifo_colector_inst/fifo40_inst/rcount_w0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_677:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I1
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_set - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_692:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I6
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_clr - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_692:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I7
+Signal fifo_colector_inst/fifo40_inst/full_cmp_set - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_691:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I6
+Signal fifo_colector_inst/fifo40_inst/iwcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_98:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_98:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_182:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_99:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_167:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_99:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_183:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_100:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_168:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_100:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_184:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_101:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_169:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I13
+Signal fifo_colector_inst/fifo40_inst/wcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_101:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_185:I5
+Signal fifo_colector_inst/fifo40_inst/iwcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I12
+Signal fifo_colector_inst/fifo40_inst/wcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_102:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_170:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_171:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_186:I4
+Signal fifo_colector_inst/fifo40_inst/iwcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_83:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I13
+Signal fifo_colector_inst/fifo40_inst/w_gdata_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_167:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_168:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_169:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I4
+Signal fifo_colector_inst/fifo40_inst/w_gdata_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I13
+Signal fifo_colector_inst/fifo40_inst/w_gcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_170:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I5
+Signal fifo_colector_inst/fifo40_inst/w_gdata_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_171:I12
+Signal fifo_colector_inst/fifo40_inst/w_gcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_171:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_91:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_162:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_92:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_147:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_92:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_163:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_93:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_148:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_93:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_164:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_94:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_149:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I13
+Signal fifo_colector_inst/fifo40_inst/rcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_94:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I1,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I6,
+        fifo_colector_inst/fifo40_inst/SLICE_165:I5
+Signal fifo_colector_inst/fifo40_inst/ircount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I12
+Signal fifo_colector_inst/fifo40_inst/rcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_95:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_150:I7,
+        fifo_colector_inst/fifo40_inst/SLICE_151:I0,
+        fifo_colector_inst/fifo40_inst/SLICE_166:I4
+Signal fifo_colector_inst/fifo40_inst/ircount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_89:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I13
+Signal fifo_colector_inst/fifo40_inst/r_gdata_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_147:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_148:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_149:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I4
+Signal fifo_colector_inst/fifo40_inst/r_gdata_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O1
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I13
+Signal fifo_colector_inst/fifo40_inst/r_gcount_7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_150:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I5
+Signal fifo_colector_inst/fifo40_inst/r_gdata_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O0
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_151:I12
+Signal fifo_colector_inst/fifo40_inst/r_gcount_8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_151:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_172:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_172:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_173:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_173:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_174:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_174:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_175:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_175:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I5
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_176:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I4
+Signal fifo_colector_inst/fifo40_inst/w_gcount_r9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_176:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_152:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_152:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_153:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_153:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w4 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_154:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w5 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_154:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w6 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_155:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w7 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_155:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I5
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w8 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_156:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I4
+Signal fifo_colector_inst/fifo40_inst/r_gcount_w9 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_156:O4
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I5
+Signal fifo_colector_inst/fifo40_inst/w_gctr_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_78:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I17
+Signal fifo_colector_inst/fifo40_inst/co0 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_79:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I17
+Signal fifo_colector_inst/fifo40_inst/co1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_80:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I17
+Signal fifo_colector_inst/fifo40_inst/co2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_81:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I17
+Signal fifo_colector_inst/fifo40_inst/co3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_82:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I17
+Signal fifo_colector_inst/fifo40_inst/r_gctr_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_84:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I17
+Signal fifo_colector_inst/fifo40_inst/co0_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_85:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I17
+Signal fifo_colector_inst/fifo40_inst/co1_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_86:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I17
+Signal fifo_colector_inst/fifo40_inst/co2_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_87:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I17
+Signal fifo_colector_inst/fifo40_inst/co3_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_88:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I17
+Signal fifo_colector_inst/fifo40_inst/cmp_ci - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_90:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I17
+Signal fifo_colector_inst/fifo40_inst/co0_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_91:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I17
+Signal fifo_colector_inst/fifo40_inst/co1_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_92:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I17
+Signal fifo_colector_inst/fifo40_inst/co2_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_93:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I17
+Signal fifo_colector_inst/fifo40_inst/co3_2 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_94:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I17
+Signal fifo_colector_inst/fifo40_inst/empty_d_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_95:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I17
+Signal fifo_colector_inst/fifo40_inst/cmp_ci_1 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_97:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I17
+Signal fifo_colector_inst/fifo40_inst/co0_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_98:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I17
+Signal fifo_colector_inst/fifo40_inst/co1_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_99:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I17
+Signal fifo_colector_inst/fifo40_inst/co2_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_100:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I17
+Signal fifo_colector_inst/fifo40_inst/co3_3 - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_101:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I17
+Signal fifo_colector_inst/fifo40_inst/full_d_c - Driver Comp:
+     fifo_colector_inst/fifo40_inst/SLICE_102:O6
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I17
+Signal fifo_rden_c - Driver Comp: trb_adapter_inst/SLICE_188:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I1, trb_adapter_inst/SLICE_632:I4,
+        fifo_colector_inst/fifo40_inst/SLICE_720:I0,
+        trb_adapter_inst/SLICE_724:I16, FEE_DATA_WRITE_OUT_MGIOL:I10,
+        fifo_rden:I0
+Signal fifo_colector_inst/buffer_wr_enable - Driver Comp:
+     fifo_colector_inst/SLICE_125:O3
+   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I0
+Signal fifo_colector_inst/iterator[1] - Driver Comp:
+     fifo_colector_inst/SLICE_187:O4
+   Load Comps: fifo_colector_inst/SLICE_125:I4, fifo_colector_inst/SLICE_126:I3,
+        fifo_colector_inst/SLICE_126:I9, fifo_colector_inst/SLICE_127:I3,
+        fifo_colector_inst/SLICE_127:I9, fifo_colector_inst/SLICE_128:I3,
+        fifo_colector_inst/SLICE_128:I9, fifo_colector_inst/SLICE_129:I3,
+        fifo_colector_inst/SLICE_129:I9, fifo_colector_inst/SLICE_130:I3,
+        fifo_colector_inst/SLICE_130:I9, fifo_colector_inst/SLICE_131:I3,
+        fifo_colector_inst/SLICE_131:I9, fifo_colector_inst/SLICE_132:I3,
+        fifo_colector_inst/SLICE_132:I9, fifo_colector_inst/SLICE_133:I3,
+        fifo_colector_inst/SLICE_133:I9, fifo_colector_inst/SLICE_146:I5,
+        fifo_colector_inst/SLICE_187:I1, fifo_colector_inst/SLICE_189:I1,
+        fifo_colector_inst/SLICE_190:I0, fifo_colector_inst/SLICE_680:I1,
+        fifo_colector_inst/SLICE_722:I0
+Signal fifo_colector_inst/iterator[0] - Driver Comp:
+     fifo_colector_inst/SLICE_187:O3
+   Load Comps: fifo_colector_inst/SLICE_125:I0, fifo_colector_inst/SLICE_126:I0,
+        fifo_colector_inst/SLICE_126:I6, fifo_colector_inst/SLICE_127:I0,
+        fifo_colector_inst/SLICE_127:I6, fifo_colector_inst/SLICE_128:I0,
+        fifo_colector_inst/SLICE_128:I6, fifo_colector_inst/SLICE_129:I0,
+        fifo_colector_inst/SLICE_129:I6, fifo_colector_inst/SLICE_130:I0,
+        fifo_colector_inst/SLICE_130:I6, fifo_colector_inst/SLICE_131:I0,
+        fifo_colector_inst/SLICE_131:I6, fifo_colector_inst/SLICE_132:I0,
+        fifo_colector_inst/SLICE_132:I6, fifo_colector_inst/SLICE_133:I0,
+        fifo_colector_inst/SLICE_133:I6, fifo_colector_inst/SLICE_134:I0,
+        fifo_colector_inst/SLICE_134:I6, fifo_colector_inst/SLICE_135:I0,
+        fifo_colector_inst/SLICE_135:I6, fifo_colector_inst/SLICE_136:I0,
+        fifo_colector_inst/SLICE_136:I6, fifo_colector_inst/SLICE_137:I0,
+        fifo_colector_inst/SLICE_137:I6, fifo_colector_inst/SLICE_138:I0,
+        fifo_colector_inst/SLICE_138:I6, fifo_colector_inst/SLICE_139:I0,
+        fifo_colector_inst/SLICE_139:I6, fifo_colector_inst/SLICE_140:I0,
+        fifo_colector_inst/SLICE_140:I6, fifo_colector_inst/SLICE_141:I0,
+        fifo_colector_inst/SLICE_141:I6, fifo_colector_inst/SLICE_142:I0,
+        fifo_colector_inst/SLICE_142:I6, fifo_colector_inst/SLICE_143:I0,
+        fifo_colector_inst/SLICE_143:I6, fifo_colector_inst/SLICE_144:I0,
+        fifo_colector_inst/SLICE_144:I6, fifo_colector_inst/SLICE_145:I0,
+        fifo_colector_inst/SLICE_145:I6, fifo_colector_inst/SLICE_146:I4,
+        fifo_colector_inst/SLICE_187:I0, fifo_colector_inst/SLICE_187:I5,
+        fifo_colector_inst/SLICE_189:I2, fifo_colector_inst/SLICE_189:I6,
+        fifo_colector_inst/SLICE_680:I6
+Signal fifo_colector_inst/fb_0 - Driver Comp: fifo_colector_inst/SLICE_189:O0
+   Load Comps: fifo_colector_inst/SLICE_189:I12
+Signal fifo_colector_inst/in_empty_pmux_0 - Driver Comp:
+     fifo_colector_inst/SLICE_680:O1
+   Load Comps: fifo_colector_inst/SLICE_680:I0
+Signal fifo_colector_inst/fb_0_0 - Driver Comp: fifo_colector_inst/SLICE_190:O0
+   Load Comps: fifo_colector_inst/SLICE_190:I12
+Signal fifo_colector_inst/fb_0_1 - Driver Comp: fifo_colector_inst/SLICE_189:O1
+   Load Comps: fifo_colector_inst/SLICE_189:I13
+Signal fifo_colector_inst/un5_in_read_enable - Driver Comp:
+     fifo_colector_inst/SLICE_187:O0
+   Load Comps: fifo_colector_inst/SLICE_187:I12
+Signal fifo_colector_inst/in_empty_pmux - Driver Comp:
+     fifo_colector_inst/SLICE_680:O0
+   Load Comps: fifo_colector_inst/SLICE_189:I16,
+        fifo_colector_inst/SLICE_190:I16
+Signal fifo_colector_inst/data_buffer_3[0] - Driver Comp:
+     fifo_colector_inst/SLICE_126:O2
+   Load Comps: fifo_colector_inst/SLICE_126:I12
+Signal fifo_colector_inst/data_buffer_3[1] - Driver Comp:
+     fifo_colector_inst/SLICE_127:O2
+   Load Comps: fifo_colector_inst/SLICE_127:I12
+Signal fifo_colector_inst/data_buffer_3[2] - Driver Comp:
+     fifo_colector_inst/SLICE_128:O2
+   Load Comps: fifo_colector_inst/SLICE_128:I12
+Signal fifo_colector_inst/data_buffer_3[3] - Driver Comp:
+     fifo_colector_inst/SLICE_129:O2
+   Load Comps: fifo_colector_inst/SLICE_129:I12
+Signal fifo_colector_inst/data_buffer_3[4] - Driver Comp:
+     fifo_colector_inst/SLICE_130:O2
+   Load Comps: fifo_colector_inst/SLICE_130:I12
+Signal fifo_colector_inst/data_buffer_3[5] - Driver Comp:
+     fifo_colector_inst/SLICE_131:O2
+   Load Comps: fifo_colector_inst/SLICE_131:I12
+Signal fifo_colector_inst/data_buffer_3[6] - Driver Comp:
+     fifo_colector_inst/SLICE_132:O2
+   Load Comps: fifo_colector_inst/SLICE_132:I12
+Signal fifo_colector_inst/data_buffer_3[7] - Driver Comp:
+     fifo_colector_inst/SLICE_133:O2
+   Load Comps: fifo_colector_inst/SLICE_133:I12
+Signal fifo_colector_inst/data_buffer_3[8] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O0
+   Load Comps: fifo_colector_inst/SLICE_134:I12
+Signal fifo_colector_inst/data_buffer_3[9] - Driver Comp:
+     fifo_colector_inst/SLICE_134:O1
+   Load Comps: fifo_colector_inst/SLICE_134:I13
+Signal fifo_colector_inst/data_buffer_3[10] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O0
+   Load Comps: fifo_colector_inst/SLICE_135:I12
+Signal fifo_colector_inst/data_buffer_3[11] - Driver Comp:
+     fifo_colector_inst/SLICE_135:O1
+   Load Comps: fifo_colector_inst/SLICE_135:I13
+Signal fifo_colector_inst/data_buffer_3[12] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O0
+   Load Comps: fifo_colector_inst/SLICE_136:I12
+Signal fifo_colector_inst/data_buffer_3[13] - Driver Comp:
+     fifo_colector_inst/SLICE_136:O1
+   Load Comps: fifo_colector_inst/SLICE_136:I13
+Signal fifo_colector_inst/data_buffer_3[14] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O0
+   Load Comps: fifo_colector_inst/SLICE_137:I12
+Signal fifo_colector_inst/data_buffer_3[15] - Driver Comp:
+     fifo_colector_inst/SLICE_137:O1
+   Load Comps: fifo_colector_inst/SLICE_137:I13
+Signal fifo_colector_inst/data_buffer_3[16] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O0
+   Load Comps: fifo_colector_inst/SLICE_138:I12
+Signal fifo_colector_inst/data_buffer_3[17] - Driver Comp:
+     fifo_colector_inst/SLICE_138:O1
+   Load Comps: fifo_colector_inst/SLICE_138:I13
+Signal fifo_colector_inst/data_buffer_3[18] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O0
+   Load Comps: fifo_colector_inst/SLICE_139:I12
+Signal fifo_colector_inst/data_buffer_3[19] - Driver Comp:
+     fifo_colector_inst/SLICE_139:O1
+   Load Comps: fifo_colector_inst/SLICE_139:I13
+Signal fifo_colector_inst/data_buffer_3[20] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O0
+   Load Comps: fifo_colector_inst/SLICE_140:I12
+Signal fifo_colector_inst/data_buffer_3[21] - Driver Comp:
+     fifo_colector_inst/SLICE_140:O1
+   Load Comps: fifo_colector_inst/SLICE_140:I13
+Signal fifo_colector_inst/data_buffer_3[22] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O0
+   Load Comps: fifo_colector_inst/SLICE_141:I12
+Signal fifo_colector_inst/data_buffer_3[23] - Driver Comp:
+     fifo_colector_inst/SLICE_141:O1
+   Load Comps: fifo_colector_inst/SLICE_141:I13
+Signal fifo_colector_inst/data_buffer_3[24] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O0
+   Load Comps: fifo_colector_inst/SLICE_142:I12
+Signal fifo_colector_inst/data_buffer_3[25] - Driver Comp:
+     fifo_colector_inst/SLICE_142:O1
+   Load Comps: fifo_colector_inst/SLICE_142:I13
+Signal fifo_colector_inst/data_buffer_3[26] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O0
+   Load Comps: fifo_colector_inst/SLICE_143:I12
+Signal fifo_colector_inst/data_buffer_3[27] - Driver Comp:
+     fifo_colector_inst/SLICE_143:O1
+   Load Comps: fifo_colector_inst/SLICE_143:I13
+Signal fifo_colector_inst/data_buffer_3[28] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O0
+   Load Comps: fifo_colector_inst/SLICE_144:I12
+Signal fifo_colector_inst/data_buffer_3[29] - Driver Comp:
+     fifo_colector_inst/SLICE_144:O1
+   Load Comps: fifo_colector_inst/SLICE_144:I13
+Signal fifo_colector_inst/data_buffer_3[30] - Driver Comp:
+     fifo_colector_inst/SLICE_145:O0
+   Load Comps: fifo_colector_inst/SLICE_145:I12
+Signal finished_c - Driver Comp: trb_adapter_inst/SLICE_724:O3
+   Load Comps: trb_adapter_inst/SLICE_633:I4, trb_adapter_inst/SLICE_724:I0,
+        finished:I0, FEE_DATAFINISHED_OUT_MGIOL:I10
+Signal trb_adapter_inst/finished_prev - Driver Comp:
+     trb_adapter_inst/SLICE_633:O3
+   Load Comps: trb_adapter_inst/SLICE_724:I1
+Signal trb_adapter_inst/buf_rden_prev - Driver Comp:
+     trb_adapter_inst/SLICE_632:O3
+   Load Comps: trb_adapter_inst/SLICE_724:I4
+Signal trb_adapter_inst/buf_rden4 - Driver Comp: trb_adapter_inst/SLICE_188:O0
+   Load Comps: trb_adapter_inst/SLICE_188:I12
+Signal trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - Driver Comp:
+     LVL1_TRG_DATA_VALID_IN_MGIOL:O2
+   Load Comps: trb_adapter_inst/SLICE_631:I4
+Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - Driver Comp:
+     trb_adapter_inst/SLICE_631:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I8, trb_adapter_inst/SLICE_631:I5,
+        trb_adapter_inst/SLICE_723:I0
+Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - Driver Comp:
+     trb_adapter_inst/SLICE_631:O4
+   Load Comps: trb_adapter_inst/SLICE_188:I7, trb_adapter_inst/SLICE_723:I1
+Signal trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - Driver Comp:
+     LVL1_INVALID_TRG_IN_MGIOL:O2
+   Load Comps: trb_adapter_inst/SLICE_124:I4
+Signal discard_c - Driver Comp: trb_adapter_inst/SLICE_124:O3
+   Load Comps: trb_adapter_inst/SLICE_188:I6, discard:I0
+Signal burst_c - Driver Comp: trb_adapter_inst/SLICE_188:O1
+   Load Comps: trb_adapter_inst/SLICE_188:I0, burst:I0
+Signal LVL1_TRG_DATA_VALI_IN_rising_c - Driver Comp:
+     trb_adapter_inst/SLICE_723:O0
+   Load Comps: LVL1_TRG_DATA_VALI_IN_rising:I0
+Signal release_out_c - Driver Comp: trb_adapter_inst/SLICE_724:O0
+   Load Comps: release_out:I0, FEE_TRG_RELEASE_OUT_MGIOL:I10
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_120:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_104:I17
+Signal hades_tdc_bundle_inst/hit_valid25 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_104:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I2,
+        hades_tdc_bundle_inst/SLICE_458:I1, hades_tdc_bundle_inst/SLICE_458:I7,
+        hades_tdc_bundle_inst/SLICE_710:I7
+Signal hades_tdc_bundle_inst/buf_finished5 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_432:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_432:I12
+Signal hades_buf_finished_c - Driver Comp: hades_tdc_bundle_inst/SLICE_432:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_433:I4, hades_buf_finished:I0
+Signal hades_dbg2_out_c[12] - Driver Comp: hades_tdc_bundle_inst/SLICE_443:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_449:I4, hades_dbg2_out[12]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - Driver Comp: SLICE_740:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I14,
+        hades_tdc_bundle_inst/SLICE_446:I14,
+        hades_tdc_bundle_inst/SLICE_447:I14,
+        hades_tdc_bundle_inst/SLICE_448:I14,
+        hades_tdc_bundle_inst/SLICE_449:I14,
+        hades_tdc_bundle_inst/SLICE_450:I14,
+        hades_tdc_bundle_inst/SLICE_451:I14,
+        hades_tdc_bundle_inst/SLICE_452:I14,
+        hades_tdc_bundle_inst/SLICE_453:I14,
+        hades_tdc_bundle_inst/SLICE_454:I14, hades_tdc_bundle_inst/SLICE_455:I14
+        
+Signal hades_drop_cmp_buf_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_449:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I8, hades_drop_cmp_buf[8]:I0
+Signal hades_tdc_bundle_inst/hades_raw_out_valid - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I0,
+        hades_tdc_bundle_inst/SLICE_459:I6, hades_tdc_bundle_inst/SLICE_460:I6,
+        hades_tdc_bundle_inst/SLICE_628:I0, hades_tdc_bundle_inst/SLICE_628:I8,
+        hades_tdc_bundle_inst/SLICE_693:I1, hades_tdc_bundle_inst/SLICE_693:I8
+Signal hades_tdc_bundle_inst/hit_i[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I1,
+        hades_tdc_bundle_inst/SLICE_459:I7, hades_tdc_bundle_inst/SLICE_460:I7,
+        hades_tdc_bundle_inst/SLICE_628:I1, hades_tdc_bundle_inst/SLICE_628:I7,
+        hades_tdc_bundle_inst/SLICE_693:I2, hades_tdc_bundle_inst/SLICE_693:I7
+Signal hades_tdc_bundle_inst/hit_i[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I4,
+        hades_tdc_bundle_inst/SLICE_459:I4, hades_tdc_bundle_inst/SLICE_460:I4,
+        hades_tdc_bundle_inst/SLICE_628:I6, hades_tdc_bundle_inst/SLICE_693:I3,
+        hades_tdc_bundle_inst/SLICE_693:I6
+Signal un1_hit_i_2_0_a2 - Driver Comp: hades_tdc_bundle_inst/SLICE_693:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I14,
+        hades_tdc_bundle_inst/SLICE_440:I14,
+        hades_tdc_bundle_inst/SLICE_441:I14,
+        hades_tdc_bundle_inst/SLICE_442:I14,
+        hades_tdc_bundle_inst/SLICE_443:I14, hades_dbg2_out[28]_MGIOL:I8,
+        hades_dbg2_out[27]_MGIOL:I8, hades_dbg2_out[26]_MGIOL:I8,
+        hades_dbg2_out[25]_MGIOL:I8, hades_dbg2_out[24]_MGIOL:I8,
+        hades_dbg2_out[23]_MGIOL:I8, hades_dbg2_out[22]_MGIOL:I8,
+        hades_dbg2_out[21]_MGIOL:I8, hades_dbg2_out[20]_MGIOL:I8,
+        hades_dbg2_out[18]_MGIOL:I8, hades_dbg2_out[17]_MGIOL:I8,
+        hades_dbg2_out[16]_MGIOL:I8, hades_dbg2_out[2]_MGIOL:I8,
+        hades_dbg2_out[1]_MGIOL:I8, hades_dbg2_out[0]_MGIOL:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_
+     out_inst/dec_neg_inst/SLICE_573:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_573:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed7_rising_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out
+     _inst/dec_neg_inst/SLICE_726:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
+        _neg_inst/SLICE_572:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out
+        _inst/dec_neg_inst/SLICE_573:I16
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_i
+     nternal - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst
+     /dec_neg_inst/SLICE_573:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_725:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_725:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I2, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
+        1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+     t/dec_neg_inst/SLICE_571:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_576:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_576:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_571:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+     t/dec_neg_inst/SLICE_571:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_576:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_576:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I5
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_571:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I13
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
+     ernal[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
+     t/dec_neg_inst/SLICE_572:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_577:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_577:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
+     nst/SLICE_572:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I12
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_563:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_567:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_567:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_728:I0
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_563:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_567:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_567:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I6, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_728:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_564:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_568:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_568:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I0, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_694:I7, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I0
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_564:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_568:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_568:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_694:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I8, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I0, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_565:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_569:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_569:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_694:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I9, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I1, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I2
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_565:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_569:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_569:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_572:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_694:I3, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_neg_inst/SLICE_727:I2, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I3, hades_tdc_bundle_inst/had
+        es_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729:I2
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_566:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_570:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_570:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_572:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_727:I3
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_566:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_570:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_726:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
+     ed[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
+     ec_neg_inst/SLICE_570:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_726:I1
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_559:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_563:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_559:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_563:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_560:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_564:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_560:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_564:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_561:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_565:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_561:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_565:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_562:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_566:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_562:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_566:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_620:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_559:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_621:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_559:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_622:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_560:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_623:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_560:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_624:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_561:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_625:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_561:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_626:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_562:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] -
+     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
+     nst/SLICE_627:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_562:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_r
+     aw_out_inst/dec_neg_inst/SLICE_694:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_573:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal35_1_0_0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_ra
+     w_out_inst/dec_neg_inst/SLICE_727:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_573:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_729:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
+     _internal31_1_i_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel
+     _raw_out_inst/dec_neg_inst/SLICE_572:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        neg_inst/SLICE_571:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_neg_inst/SLICE_572:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0
+     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
+     _inst/SLICE_728:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I1, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
+        0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLI
+     CE_725:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I14
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
+     _0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+     neg_inst/SLICE_694:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+        /SLICE_571:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal35_1_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_
+     rising_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
+        t/SLICE_556:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/de
+        c_inst/SLICE_557:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+        st/dec_inst/SLICE_558:I16
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_inter
+     nal - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_731:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I2, hades
+        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_574:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_574:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I5
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
+     l[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_575:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I4
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal31_1_i_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O2
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_557:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_551:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_558:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_696:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_696:I6
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_551:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_695:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_696:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_696:I7
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_552:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_558:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_695:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/dec_inst/SLICE_696:I2, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/dec_inst/SLICE_696:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_552:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_557:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_695:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_732:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_553:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_557:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_695:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_732:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_553:I5
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_557:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_695:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/dec_inst/SLICE_696:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/dec_inst/SLICE_732:I2
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_554:I4
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_556:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
+        inst/SLICE_557:I4, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        dec_inst/SLICE_732:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_554:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_730:I0
+Signal
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_730:I1
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_547:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_547:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_548:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_548:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_549:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_549:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_550:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_550:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_543:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_543:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_544:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_544:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_545:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_545:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_546:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_546:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_557:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+        /SLICE_558:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
+     ernal35_1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_558:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_556:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - Driver
+     Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I14
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I2
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
+        CE_555:I3
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_607:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_607:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_607:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_623:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_611:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_627:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_611:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_611:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_606:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_606:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_606:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_622:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_610:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_626:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_610:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_610:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_605:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_621:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_605:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_605:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_609:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_625:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_609:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_609:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_604:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_620:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_604:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_604:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
+     fered1[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_608:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_624:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
+     synced[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
+     st/tdc_neg_inst/SLICE_608:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_608:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_591:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_615:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_619:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_595:I4
+Signal hades_trig_c_i - Driver Comp: SLICE_747:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_588:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst
+        /SLICE_589:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
+        inst/SLICE_590:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
+        tdc_inst/SLICE_591:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_inst/SLICE_592:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
+        ut_inst/tdc_inst/SLICE_593:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_inst/SLICE_594:I5, hades_tdc_bundle_inst/hades_tdc_chann
+        el_raw_out_inst/tdc_inst/SLICE_595:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_614:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_590:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_594:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_618:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_589:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_613:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_617:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_593:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_588:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_612:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
+     ed[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_592:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
+     d1[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
+        CE_616:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I0
+Signal hades_dbg2_coarse_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I2,
+        hades_tdc_bundle_inst/SLICE_435:I7, hades_tdc_bundle_inst/SLICE_438:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I5,
+        hades_tdc_bundle_inst/SLICE_681:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I7,
+        hades_dbg2_coarse[2]:I0, hades_offset[5]_MGIOL:I10
+Signal hades_dbg2_coarse_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I9,
+        hades_tdc_bundle_inst/SLICE_434:I7, hades_tdc_bundle_inst/SLICE_435:I1,
+        hades_tdc_bundle_inst/SLICE_435:I8, hades_tdc_bundle_inst/SLICE_438:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I4,
+        hades_tdc_bundle_inst/SLICE_681:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I8,
+        hades_dbg2_coarse[1]:I0, hades_offset[4]_MGIOL:I10
+Signal hades_dbg2_coarse_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I8,
+        hades_tdc_bundle_inst/SLICE_434:I0, hades_tdc_bundle_inst/SLICE_434:I6,
+        hades_tdc_bundle_inst/SLICE_435:I0, hades_tdc_bundle_inst/SLICE_435:I9,
+        hades_tdc_bundle_inst/SLICE_438:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I5,
+        hades_tdc_bundle_inst/SLICE_681:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I9,
+        hades_dbg2_coarse[0]:I0, hades_offset[3]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I0
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I6
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
+     _19 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O1
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I0
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I14,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O3
+   Load Comps: hades_dbg2_out[0]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O4
+   Load Comps: hades_dbg2_out[1]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O3
+   Load Comps: hades_dbg2_out[2]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I4
+Signal hades_tdc_bundle_inst/hades_raw_out[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_439:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_440:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_440:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I4,
+        hades_tdc_bundle_inst/SLICE_681:I3
+Signal hades_tdc_bundle_inst/hades_raw_out[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_441:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I5
+Signal hades_tdc_bundle_inst/hades_raw_out[8] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_441:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I4
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[9] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_442:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I5
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[10] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_442:I5
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I4
+        
+Signal hades_tdc_bundle_inst/hades_raw_out[11] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_443:I4
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[12] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O4
+   Load Comps: hades_dbg2_out[16]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[13] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O3
+   Load Comps: hades_dbg2_out[17]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[14] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O4
+   Load Comps: hades_dbg2_out[18]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I4
+Signal hades_tdc_bundle_inst.hades_raw_out[15] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O3
+   Load Comps: hades_dbg2_out[20]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[16] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O4
+   Load Comps: hades_dbg2_out[21]_MGIOL:I10
+Signal hades_tdc_bundle_inst.hades_raw_out[17] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O3
+   Load Comps: hades_dbg2_out[22]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[18] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O4
+   Load Comps: hades_dbg2_out[23]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I4,
+        hades_tdc_bundle_inst/SLICE_698:I3
+Signal hades_tdc_bundle_inst.hades_raw_out[19] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O3
+   Load Comps: hades_dbg2_out[24]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I5
+Signal hades_tdc_bundle_inst.hades_raw_out[20] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O4
+   Load Comps: hades_dbg2_out[25]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[21] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O3
+   Load Comps: hades_dbg2_out[26]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O3
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I5
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[22] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O4
+   Load Comps: hades_dbg2_out[27]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O4
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I4
+        
+Signal hades_tdc_bundle_inst.hades_raw_out[23] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:O3
+   Load Comps: hades_dbg2_out[28]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I12
+Signal hades_dbg2_coarse_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I3,
+        hades_tdc_bundle_inst/SLICE_435:I6, hades_tdc_bundle_inst/SLICE_436:I0,
+        hades_tdc_bundle_inst/SLICE_436:I6, hades_tdc_bundle_inst/SLICE_437:I0,
+        hades_tdc_bundle_inst/SLICE_438:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I4,
+        hades_tdc_bundle_inst/SLICE_681:I0, hades_tdc_bundle_inst/SLICE_698:I0,
+        hades_tdc_bundle_inst/SLICE_698:I6, hades_dbg2_coarse[3]:I0,
+        hades_offset[6]_MGIOL:I10
+Signal hades_dbg2_coarse_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I1,
+        hades_tdc_bundle_inst/SLICE_436:I7, hades_tdc_bundle_inst/SLICE_455:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I5,
+        hades_tdc_bundle_inst/SLICE_681:I1, hades_tdc_bundle_inst/SLICE_698:I1,
+        hades_tdc_bundle_inst/SLICE_698:I7, hades_tdc_bundle_inst/SLICE_701:I6,
+        hades_dbg2_coarse[4]:I0, hades_offset[7]_MGIOL:I10
+Signal hades_dbg2_coarse_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I9,
+        hades_tdc_bundle_inst/SLICE_436:I8, hades_tdc_bundle_inst/SLICE_455:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I4,
+        hades_tdc_bundle_inst/SLICE_701:I7, hades_dbg2_coarse[5]:I0,
+        hades_offset[8]_MGIOL:I10
+Signal hades_dbg2_coarse_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I0,
+        hades_tdc_bundle_inst/SLICE_437:I1, hades_tdc_bundle_inst/SLICE_437:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I5,
+        hades_tdc_bundle_inst/SLICE_701:I0, hades_dbg2_coarse[6]:I0
+Signal hades_dbg2_coarse_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I1,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I1,
+        hades_tdc_bundle_inst/SLICE_437:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I4,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I4,
+        hades_tdc_bundle_inst/SLICE_701:I1, hades_dbg2_coarse[7]:I0
+Signal hades_dbg2_coarse_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_438:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I6,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I6,
+        hades_tdc_bundle_inst/SLICE_438:I0, hades_tdc_bundle_inst/SLICE_455:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I5,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I5,
+        hades_dbg2_coarse[8]:I0
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I12
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I0,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_681:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I2,
+        hades_tdc_bundle_inst/SLICE_436:I2, hades_tdc_bundle_inst/SLICE_436:I9,
+        hades_tdc_bundle_inst/SLICE_437:I3, hades_tdc_bundle_inst/SLICE_681:I2,
+        hades_tdc_bundle_inst/SLICE_698:I2, hades_tdc_bundle_inst/SLICE_698:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
+     _14 - Driver Comp: hades_tdc_bundle_inst/SLICE_681:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I6
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14
+     - Driver Comp: hades_tdc_bundle_inst/SLICE_698:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I6
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I3
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I3
+        
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
+     tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_698:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I8
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
+     tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_701:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I8,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I2,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I8,
+        hades_tdc_bundle_inst/SLICE_437:I2, hades_tdc_bundle_inst/SLICE_437:I8,
+        hades_tdc_bundle_inst/SLICE_438:I1
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_438:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I9,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I3,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I9,
+        hades_tdc_bundle_inst/SLICE_437:I9, hades_tdc_bundle_inst/SLICE_438:I3,
+        hades_tdc_bundle_inst/SLICE_455:I4
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_701:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I7,
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I7,
+        hades_tdc_bundle_inst/SLICE_438:I2, hades_tdc_bundle_inst/SLICE_455:I9
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     cry - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
+     ata_tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
+     ata_tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I17
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_cry - Driver Comp:
+     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:O6
+   Load Comps:
+        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I12,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I16
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I16
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I6
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I14,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I1,
+        hades_offset[8]_MGIOL:I8, hades_offset[7]_MGIOL:I8,
+        hades_offset[6]_MGIOL:I8, hades_offset[5]_MGIOL:I8,
+        hades_offset[4]_MGIOL:I8, hades_offset[3]_MGIOL:I8,
+        hades_offset[2]_MGIOL:I8, hades_offset[1]_MGIOL:I8,
+        hades_offset[0]_MGIOL:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I2
+Signal hades_discard_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_123:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I0,
+        hades_tdc_bundle_inst/SLICE_741:I0, hades_discard:I0
+Signal valid_fast_RNI999V - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:O0
+   Load Comps: hades_offset[8]_MGIOL:I9, hades_offset[7]_MGIOL:I9,
+        hades_offset[6]_MGIOL:I9, hades_offset[5]_MGIOL:I9,
+        hades_offset[4]_MGIOL:I9, hades_offset[3]_MGIOL:I9,
+        hades_offset[2]_MGIOL:I9, hades_offset[1]_MGIOL:I9,
+        hades_offset[0]_MGIOL:I9
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
+     _1_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I12
+Signal
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i
+     - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I16,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I16
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I4
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O3
+   Load Comps: hades_offset[0]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I5
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O4
+   Load Comps: hades_offset[1]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31
+     _1_i_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O2
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I4
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:O3
+   Load Comps: hades_offset[2]_MGIOL:I10
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I6
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I7
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
+     _1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O1
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I4
+Signal hades_lvl1_c_i - Driver Comp: SLICE_743:O0
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I5,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O3
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] -
+     Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O4
+   Load Comps:
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I2
+Signal hades_invalid_dl_c[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I1,
+        hades_invalid_dl[3]:I0
+Signal hades_invalid_dl_c[2] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I0,
+        hades_invalid_dl[2]:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I9,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I12
+Signal hades_tdc_bundle_inst/SUM1_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_628:I13
+Signal ANB3 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I7,
+        hades_tdc_bundle_inst/SLICE_122:I6, hades_tdc_bundle_inst/SLICE_123:I1,
+        hades_tdc_bundle_inst/SLICE_432:I2, hades_tdc_bundle_inst/SLICE_432:I7,
+        hades_tdc_bundle_inst/SLICE_653:I1, hades_tdc_bundle_inst/SLICE_654:I8,
+        hades_tdc_bundle_inst/SLICE_683:I7, hades_hit_out_i[3]:I0
+Signal ANB2 - Driver Comp: hades_tdc_bundle_inst/SLICE_123:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I9,
+        hades_tdc_bundle_inst/SLICE_122:I7, hades_tdc_bundle_inst/SLICE_123:I3,
+        hades_tdc_bundle_inst/SLICE_123:I7, hades_tdc_bundle_inst/SLICE_432:I0,
+        hades_tdc_bundle_inst/SLICE_653:I3, hades_tdc_bundle_inst/SLICE_654:I0,
+        hades_tdc_bundle_inst/SLICE_654:I7, hades_hit_out_i[2]:I0
+Signal ANB1 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I6,
+        hades_tdc_bundle_inst/SLICE_122:I1, hades_tdc_bundle_inst/SLICE_122:I8,
+        hades_tdc_bundle_inst/SLICE_123:I2, hades_tdc_bundle_inst/SLICE_123:I6,
+        hades_tdc_bundle_inst/SLICE_432:I3, hades_tdc_bundle_inst/SLICE_432:I6,
+        hades_tdc_bundle_inst/SLICE_653:I2, hades_tdc_bundle_inst/SLICE_654:I6,
+        hades_tdc_bundle_inst/SLICE_683:I8, hades_hit_out_i[1]:I0
+Signal ANB0 - Driver Comp: hades_tdc_bundle_inst/SLICE_121:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I0,
+        hades_tdc_bundle_inst/SLICE_121:I8, hades_tdc_bundle_inst/SLICE_122:I0,
+        hades_tdc_bundle_inst/SLICE_122:I9, hades_tdc_bundle_inst/SLICE_123:I4,
+        hades_tdc_bundle_inst/SLICE_432:I1, hades_tdc_bundle_inst/SLICE_653:I0,
+        hades_tdc_bundle_inst/SLICE_683:I6, hades_tdc_bundle_inst/SLICE_710:I0,
+        hades_hit_out_i[0]:I0
+Signal hades_tdc_bundle_inst/N_50_i_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_122:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_122:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I12
+Signal hades_window_end_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_741:I1, hades_window_end:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I4,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I7,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I3
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I1,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I7
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I12
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I13
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O4
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I3,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I9
+Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - Driver Comp:
+     hades_lvl1_MGIOL:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I4
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I5
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I12
+Signal hades_offset_valid_c - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O3
+   Load Comps: hades_offset_valid:I0, hades_raw_out_valid_MGIOL:I10
+Signal hades_invalid_dl_c[1] - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O3
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I5,
+        hades_invalid_dl[1]:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I14
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:O2
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I1
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - Driver Comp:
+     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I0
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I8,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I2,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I8
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O1
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 -
+     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O0
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I6,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I0,
+        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I6
+Signal hades_tdc_bundle_inst/N_59_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_628:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_628:I12
+Signal hades_tdc_bundle_inst/N_46_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_122:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_122:I12
+Signal hades_tdc_bundle_inst/N_44 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_693:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_458:I2
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I17
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - Driver
+     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O6
+   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I17
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_435:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I13,
+        hades_tdc_bundle_inst/SLICE_451:I5
+Signal hades_dbg2_out_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I4, hades_dbg2_out[4]:I0
+Signal hades_dbg2_out_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_445:I5, hades_dbg2_out[5]:I0
+Signal hades_dbg2_out_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_446:I4, hades_dbg2_out[6]:I0
+Signal hades_dbg2_out_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_446:I5, hades_dbg2_out[7]:I0
+Signal hades_dbg2_out_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_447:I4, hades_dbg2_out[8]:I0
+Signal hades_dbg2_out_c[9] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_447:I5, hades_dbg2_out[9]:I0
+Signal hades_dbg2_out_c[10] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_448:I4, hades_dbg2_out[10]:I0
+Signal hades_dbg2_out_c[11] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_448:I5, hades_dbg2_out[11]:I0
+Signal hades_tdc_bundle_inst/N_246_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_457:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I12
+Signal hades_hit_valid_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_457:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I3,
+        hades_tdc_bundle_inst/SLICE_457:I7, hades_tdc_bundle_inst/SLICE_654:I3,
+        hades_hit_valid[0]:I0
+Signal hades_tdc_bundle_inst/N_243_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_458:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_458:I12
+Signal hades_hit_valid_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_458:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I1,
+        hades_tdc_bundle_inst/SLICE_458:I4, hades_tdc_bundle_inst/SLICE_710:I1,
+        SLICE_740:I0, hades_hit_valid[1]:I0
+Signal hades_tdc_bundle_inst/N_245_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_459:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_459:I12
+Signal hades_hit_valid_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_459:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_459:I1,
+        hades_tdc_bundle_inst/SLICE_459:I9, hades_tdc_bundle_inst/SLICE_710:I2,
+        hades_hit_valid[2]:I0
+Signal hades_tdc_bundle_inst/N_244_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_460:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_460:I12
+Signal hades_hit_valid_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_460:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_460:I1,
+        hades_tdc_bundle_inst/SLICE_460:I9, hades_tdc_bundle_inst/SLICE_683:I1,
+        hades_hit_valid[3]:I0
+Signal hades_tdc_bundle_inst/N_247_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_121:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I12
+Signal hades_tdc_bundle_inst/hit_out_i_6[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_123:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_123:I12
+Signal hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_456:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I12
+Signal hades_drop_cmp_buf_valid_c - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_456:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_456:I0,
+        hades_tdc_bundle_inst/SLICE_458:I0, hades_tdc_bundle_inst/SLICE_458:I6,
+        hades_tdc_bundle_inst/SLICE_710:I6, hades_drop_cmp_buf_valid:I0
+Signal hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_434:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_434:I12,
+        hades_tdc_bundle_inst/SLICE_450:I4
+Signal hades_drop_cmp_buf_coarse_c[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_450:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I8,
+        hades_drop_cmp_buf_coarse[0]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_434:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_434:I13,
+        hades_tdc_bundle_inst/SLICE_450:I5
+Signal hades_drop_cmp_buf_coarse_c[1] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_450:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I6,
+        hades_drop_cmp_buf_coarse[1]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_435:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_435:I12,
+        hades_tdc_bundle_inst/SLICE_451:I4
+Signal hades_drop_cmp_buf_coarse_c[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_451:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I2,
+        hades_drop_cmp_buf_coarse[2]:I0
+Signal hades_drop_cmp_buf_coarse_c[3] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_451:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I0,
+        hades_drop_cmp_buf_coarse[3]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_436:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I12,
+        hades_tdc_bundle_inst/SLICE_452:I4
+Signal hades_drop_cmp_buf_coarse_c[4] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_452:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I8,
+        hades_drop_cmp_buf_coarse[4]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_436:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_436:I13,
+        hades_tdc_bundle_inst/SLICE_452:I5
+Signal hades_drop_cmp_buf_coarse_c[5] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_452:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I6,
+        hades_drop_cmp_buf_coarse[5]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_437:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_437:I12,
+        hades_tdc_bundle_inst/SLICE_453:I4
+Signal hades_drop_cmp_buf_coarse_c[6] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_453:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I2,
+        hades_drop_cmp_buf_coarse[6]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_437:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_437:I13,
+        hades_tdc_bundle_inst/SLICE_453:I5
+Signal hades_drop_cmp_buf_coarse_c[7] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_453:O4
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I0,
+        hades_drop_cmp_buf_coarse[7]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_438:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_438:I12,
+        hades_tdc_bundle_inst/SLICE_454:I4
+Signal hades_drop_cmp_buf_coarse_c[8] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_454:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I7,
+        hades_drop_cmp_buf_coarse[8]:I0
+Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_455:O2
+   Load Comps: hades_tdc_bundle_inst/SLICE_455:I12
+Signal hades_drop_cmp_buf_coarse_c[9] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_455:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I6,
+        hades_drop_cmp_buf_coarse[9]:I0
+Signal hades_drop_cmp_buf_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I9, hades_drop_cmp_buf[0]:I0
+Signal hades_drop_cmp_buf_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_118:I7, hades_drop_cmp_buf[1]:I0
+Signal hades_drop_cmp_buf_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I3, hades_drop_cmp_buf[2]:I0
+Signal hades_drop_cmp_buf_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I1, hades_drop_cmp_buf[3]:I0
+Signal hades_drop_cmp_buf_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I9, hades_drop_cmp_buf[4]:I0
+Signal hades_drop_cmp_buf_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I7, hades_drop_cmp_buf[5]:I0
+Signal hades_drop_cmp_buf_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O3
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I3, hades_drop_cmp_buf[6]:I0
+Signal hades_drop_cmp_buf_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O4
+     
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I1, hades_drop_cmp_buf[7]:I0
+Signal hades_buf_release_c - Driver Comp: hades_tdc_bundle_inst/SLICE_433:O3
+   Load Comps: hades_tdc_bundle_inst/SLICE_457:I2,
+        hades_tdc_bundle_inst/SLICE_457:I6, hades_tdc_bundle_inst/SLICE_458:I3,
+        hades_tdc_bundle_inst/SLICE_458:I8, hades_tdc_bundle_inst/SLICE_459:I0,
+        hades_tdc_bundle_inst/SLICE_459:I8, hades_tdc_bundle_inst/SLICE_460:I0,
+        hades_tdc_bundle_inst/SLICE_460:I8, hades_buf_release:I0
+Signal hades_tdc_bundle_inst/N_90 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_683:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_683:I0
+Signal hades_tdc_bundle_inst/N_80 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_432:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I2
+Signal hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_741:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_121:I4
+Signal hades_tdc_bundle_inst/N_66 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_654:O1
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I1
+Signal hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_654:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_683:I2
+Signal hades_tdc_bundle_inst/N_45 - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_710:O0
+   Load Comps: hades_tdc_bundle_inst/SLICE_654:I9
+Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_118:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_119:I17
+Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - Driver Comp:
+     hades_tdc_bundle_inst/SLICE_119:O6
+   Load Comps: hades_tdc_bundle_inst/SLICE_120:I17
+Signal pll0inst/GND - Driver Comp: pll0inst/SLICE_742:O0
+   Load Comps: pll0inst/PLLInst_0:STDBY
+Signal LVL1_TRG_DATA_VALID_IN_c - Driver Comp: LVL1_TRG_DATA_VALID_IN:O0
+   Load Comps: LVL1_TRG_DATA_VALID_IN_MGIOL:I5
+Signal LVL1_INVALID_TRG_IN_c - Driver Comp: LVL1_INVALID_TRG_IN:O0
+   Load Comps: LVL1_INVALID_TRG_IN_MGIOL:I5
+Signal reset_dc_c - Driver Comp: reset_dc:O0
+   Load Comps: reset_dc_MGIOL:I5
+Signal hades_lvl1_c - Driver Comp: hades_lvl1:O0
+   Load Comps: SLICE_743:I0, hades_lvl1_MGIOL:I5
+Signal FEE_TRG_RELEASE_OUT_c - Driver Comp: FEE_TRG_RELEASE_OUT_MGIOL:O0
+   Load Comps: FEE_TRG_RELEASE_OUT:I1
+Signal FEE_DATA_WRITE_OUT_c - Driver Comp: FEE_DATA_WRITE_OUT_MGIOL:O0
+   Load Comps: FEE_DATA_WRITE_OUT:I1
+Signal FEE_DATAFINISHED_OUT_c - Driver Comp: FEE_DATAFINISHED_OUT_MGIOL:O0
+   Load Comps: FEE_DATAFINISHED_OUT:I1
+Signal hades_raw_out_valid_c - Driver Comp: hades_raw_out_valid_MGIOL:O0
+   Load Comps: hades_raw_out_valid:I1
+Signal hades_dbg2_out_c[0] - Driver Comp: hades_dbg2_out[0]_MGIOL:O0
+   Load Comps: hades_dbg2_out[0]:I1
+Signal hades_dbg2_out_c[1] - Driver Comp: hades_dbg2_out[1]_MGIOL:O0
+   Load Comps: hades_dbg2_out[1]:I1
+Signal hades_dbg2_out_c[2] - Driver Comp: hades_dbg2_out[2]_MGIOL:O0
+   Load Comps: hades_dbg2_out[2]:I1
+Signal hades_dbg2_out_c[16] - Driver Comp: hades_dbg2_out[16]_MGIOL:O0
+   Load Comps: hades_dbg2_out[16]:I1
+Signal hades_dbg2_out_c[17] - Driver Comp: hades_dbg2_out[17]_MGIOL:O0
+   Load Comps: hades_dbg2_out[17]:I1
+Signal hades_dbg2_out_c[18] - Driver Comp: hades_dbg2_out[18]_MGIOL:O0
+   Load Comps: hades_dbg2_out[18]:I1
+Signal hades_dbg2_out_c[20] - Driver Comp: hades_dbg2_out[20]_MGIOL:O0
+   Load Comps: hades_dbg2_out[20]:I1
+Signal hades_dbg2_out_c[21] - Driver Comp: hades_dbg2_out[21]_MGIOL:O0
+   Load Comps: hades_dbg2_out[21]:I1
+Signal hades_dbg2_out_c[22] - Driver Comp: hades_dbg2_out[22]_MGIOL:O0
+   Load Comps: hades_dbg2_out[22]:I1
+Signal hades_dbg2_out_c[23] - Driver Comp: hades_dbg2_out[23]_MGIOL:O0
+   Load Comps: hades_dbg2_out[23]:I1
+Signal hades_dbg2_out_c[24] - Driver Comp: hades_dbg2_out[24]_MGIOL:O0
+   Load Comps: hades_dbg2_out[24]:I1
+Signal hades_dbg2_out_c[25] - Driver Comp: hades_dbg2_out[25]_MGIOL:O0
+   Load Comps: hades_dbg2_out[25]:I1
+Signal hades_dbg2_out_c[26] - Driver Comp: hades_dbg2_out[26]_MGIOL:O0
+   Load Comps: hades_dbg2_out[26]:I1
+Signal hades_dbg2_out_c[27] - Driver Comp: hades_dbg2_out[27]_MGIOL:O0
+   Load Comps: hades_dbg2_out[27]:I1
+Signal hades_dbg2_out_c[28] - Driver Comp: hades_dbg2_out[28]_MGIOL:O0
+   Load Comps: hades_dbg2_out[28]:I1
+Signal hades_offset_c[0] - Driver Comp: hades_offset[0]_MGIOL:O0
+   Load Comps: hades_offset[0]:I1
+Signal hades_offset_c[1] - Driver Comp: hades_offset[1]_MGIOL:O0
+   Load Comps: hades_offset[1]:I1
+Signal hades_offset_c[2] - Driver Comp: hades_offset[2]_MGIOL:O0
+   Load Comps: hades_offset[2]:I1
+Signal hades_offset_c[3] - Driver Comp: hades_offset[3]_MGIOL:O0
+   Load Comps: hades_offset[3]:I1
+Signal hades_offset_c[4] - Driver Comp: hades_offset[4]_MGIOL:O0
+   Load Comps: hades_offset[4]:I1
+Signal hades_offset_c[5] - Driver Comp: hades_offset[5]_MGIOL:O0
+   Load Comps: hades_offset[5]:I1
+Signal hades_offset_c[6] - Driver Comp: hades_offset[6]_MGIOL:O0
+   Load Comps: hades_offset[6]:I1
+Signal hades_offset_c[7] - Driver Comp: hades_offset[7]_MGIOL:O0
+   Load Comps: hades_offset[7]:I1
+Signal hades_offset_c[8] - Driver Comp: hades_offset[8]_MGIOL:O0
+   Load Comps: hades_offset[8]:I1
+Signal hades_trig_c - Driver Comp: hades_trig:O0
+   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+        /SLICE_604:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
+        neg_inst/SLICE_605:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
+        nst/tdc_neg_inst/SLICE_606:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
+        aw_out_inst/tdc_neg_inst/SLICE_607:I5, hades_tdc_bundle_inst/hades_tdc_c
+        hannel_raw_out_inst/tdc_neg_inst/SLICE_608:I5, hades_tdc_bundle_inst/had
+        es_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:I5, hades_tdc_bundle_
+        inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:I5, hades_tdc
+        _bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I5,
+        SLICE_747:I0
+Signal trig_c[2] - Driver Comp: trig[2]:O0
+   Load Comps: SLICE_746:I0
+Signal trig_c[1] - Driver Comp: trig[1]:O0
+   Load Comps: SLICE_745:I0
+Signal trig_c[0] - Driver Comp: trig[0]:O0
+   Load Comps: SLICE_744:I0
+   Number of warnings:  13
+   Number of errors:    0
+     
+
+
+<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
+
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic
+     error in "BLOCK NET "tdc_out*" ;": tdc_out* does not match any nets in the
+     design. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic
+     error in "LOCATE COMP "reset" SITE "D11" ;": COMP "reset" cannot be found
+     in design. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic
+     error in "UGROUP "trig_gate0" BBOX 1 1 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO
+     	BLKNAME trig_pad_RNII4FF[0];": Block
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2" of UGROUP
+     "trig_gate0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO" of UGROUP
+     "trig_gate0" not found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic
+     error in "LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;": UGROUP "trig_gate0"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic
+     error in "UGROUP "tdc_ch0" BBOX 1 6 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de   ....
+     _inst/dec_inst/out_internal[2]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;":
+     Block "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP
+     "tdc_ch0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc_ch0"
+     not found in designBlock
+
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]" of UGROUP "tdc_ch0"
+     not found in designBlock "genblk1[0].tdc_cha   ....   out_internal[1]" of
+     UGROUP "tdc_ch0" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]" of UGROUP
+     "tdc_ch0" not found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic
+     error in "LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;": UGROUP "tdc_ch0"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic
+     error in "UGROUP "tdc2" BBOX 1 6 
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_   ....
+     st/dec_inst/valid
+     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+     	BLKNAME
+     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
+     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]" of
+     UGROUP "tdc2" not found in designBlock
+     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc2" not
+     found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]"
+     of UGROUP "tdc2" not found in designBlock "genblk1[1].td   ....
+     ternal[2]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channe
+     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "tdc2" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic
+     error in "LOCATE UGROUP "tdc2" SITE "R65C41D" ;": UGROUP "tdc2" cannot be
+     found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic
+     error in "UGROUP "dec3" BBOX 1 6 
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_   ....
+     st/dec_inst/valid
+     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+     	BLKNAME
+     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
+     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]" of
+     UGROUP "dec3" not found in designBlock
+     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "dec3" not
+     found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]"
+     of UGROUP "dec3" not found in designBlock "genblk1[2].td   ....
+     ternal[2]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channe
+     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "dec3" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic
+     error in "LOCATE UGROUP "dec3" SITE "R65C49D" ;": UGROUP "dec3" cannot be
+     found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic
+     error in "UGROUP "tdc0_neg" BBOX 1 4 
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_cl
+     k_synced[0]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b
+     uffered1[0]
+
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_   ....   enblk1[0].tdc_c
+     hannel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
+     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_b
+     uffered[7];": Block "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genb
+     lk1[0].in_clk_synced[0]" of UGROUP "tdc0_neg" not found in designBlock "gen
+     blk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]"
+     of UGROUP "tdc0_neg" not found in designBlock
+     "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b   ....
+     of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_
+     out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]" of UGROUP "tdc0_neg" not
+     found in design This preference has been disabled.
+WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic
+     error in "LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;": UGROUP "tdc0_neg"
+     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
+WARNING - map: Semantic error in "PGROUP "lvl1_dec" BBOX 1 6  DEVSIZE
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_ins   ....
+     inst/SLICE_734"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735"
+     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";":
+     Group lvl1_dec is invalid because BBOX size is too small to accommodate all
+     the components. This preference has been disabled.
+
+
+
+<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| hades_raw_valid_vect[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[0]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| clk                 | INPUT     | LVDS      |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_valid| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[11]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[10]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[9]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| hades_drop_cmp_buf_coarse[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf_coarse[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[11]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[10]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[9]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_drop_cmp_buf[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[8]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[7]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[6]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[5]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[4]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[3]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[2]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_coarse[0]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[31]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[30]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[29]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| hades_dbg2_out[28]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[27]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[26]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[25]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[24]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[23]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[22]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[21]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[20]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[19]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[18]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[17]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[16]  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[15]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[14]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[13]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[12]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[11]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[10]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[9]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[8]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[7]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[6]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[5]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[4]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[3]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[2]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_dbg2_out[1]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+
+| hades_dbg2_out[0]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[3]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[2]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[1]   | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_buf_drop[0]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[3] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[2] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[1] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_invalid_dl[0] | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_discard       | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[3]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[2]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[1]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_valid[0]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[3]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[2]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[1]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_hit_out_i[0]  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_finished  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_release   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_buf_out_valid | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_window_end    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_offset_valid  | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_offset[8]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[7]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[6]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[5]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[4]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+
+| hades_offset[3]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[2]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[1]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_offset[0]     | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_lvl1_invalid  | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| hades_lvl1          | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| hades_raw_valid_vect[1]| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| hades_raw_out_valid | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| hades_trig          | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| release_out         | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| finished            | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| last_buf_empty      | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| discard             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| burst               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LVL1_TRG_DATA_VALI_IN_rising| OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_TRG_RELEASE_OUT | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATAFINISHED_OUT| OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_WRITE_OUT  | OUTPUT    | LVCMOS25  | OUT        |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[31]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[30]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[29]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[28]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[27]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[26]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[25]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[24]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[23]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[22]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| FEE_DATA_OUT[21]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[20]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[19]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[18]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[17]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[16]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[15]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[14]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[13]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[12]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[11]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[10]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[9]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[8]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[7]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[6]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[5]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[4]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[3]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[2]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[1]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| FEE_DATA_OUT[0]     | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LVL1_INVALID_TRG_IN | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| LVL1_TRG_DATA_VALID_IN| INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| fifo_empty1         | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_rden           | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[31]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[30]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| fifo_data_out[29]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[28]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[27]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[26]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[25]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[24]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[23]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[22]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[21]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[20]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[19]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[18]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[17]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[16]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[15]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[14]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[13]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[12]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[11]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[10]   | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[9]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[8]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[7]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[6]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[5]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[4]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[3]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| fifo_data_out[2]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| fifo_data_out[1]    | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| trig[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| reset_dc            | INPUT     | LVCMOS25  | IN         |
++---------------------+-----------+-----------+------------+
+| rd_clk              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/VCC undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/VCC undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/VCC undriven
+     or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/VCC
+     undriven or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/VCC undriven
+     or does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/VCC
+     undriven or does not drive anything - clipped.
+Block trb_adapter_inst/VCC undriven or does not drive anything - clipped.
+Block fifo_colector_inst/VCC undriven or does not drive anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/VCC undriven or does not drive
+     anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
+     drive anything - clipped.
+Block genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg was
+     merged into signal hades_trig_c
+Signal reset_dl_i[2] was merged into signal reset_dl[2]
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.
+     CN was merged into signal pll_clks[0]
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.
+     CN was merged into signal pll_clks[1]
+
+Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.
+     CN was merged into signal pll_clks[2]
+Signal genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN was merged into signal
+     pll_clks[3]
+Signal fifo_colector_inst/fifo40_inst/invout_0 was merged into signal
+     last_buf_empty_c
+Signal fifo_colector_inst/fifo40_inst/invout_1 was merged into signal
+     fifo_colector_inst/fifo40_inst/Full
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty1_c
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty[1]
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
+     into signal fifo_empty[2]
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
+     into signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
+Signal GND undriven or does not drive anything - clipped.
+Signal VCC undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/VCC undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/VCC undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/rRst undriven or does not drive anything -
+     clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
+     not drive anything - clipped.
+Signal pll0inst/CLKINTFB undriven or does not drive anything - clipped.
+Signal pll0inst/REFCLK undriven or does not drive anything - clipped.
+Signal pll0inst/INTLOCK undriven or does not drive anything - clipped.
+Signal pll0inst/LOCK undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1 undriven or does not drive
+
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/N_73 undriven or does not drive anything - clipped.
+     
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0
+     undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1 undriven or does not
+     drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _27_0_COUT undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _21_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _21_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _9_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _9_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _1_0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
+     _1_0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1 undriven or does
+     not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
+     0_COUT undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
+     0_S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
+     0_S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
+     _S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
+     _S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
+     _S1 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
+     _S0 undriven or does not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2 undriven or does
+     not drive anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1 undriven or does not drive
+     anything - clipped.
+Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a1_S1_2 undriven or does not drive
+
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a1_COUT_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/a0_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/a0_COUT_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2 undriven or does not
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2 undriven or does not
+
+     drive anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_0 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/co4_1 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_1 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/co4 undriven or does not drive anything -
+     clipped.
+Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2 undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/CIN_2 undriven or does not drive anything
+     - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[35] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[34] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[33] undriven or does not drive
+     anything - clipped.
+Signal fifo_colector_inst/fifo40_inst/Q_1[32] undriven or does not drive
+     anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0 undriven
+     or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14
+     undriven or does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+     does not drive anything - clipped.
+Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_0 undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_0
+
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0
+     undriven or does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+
+     does not drive anything - clipped.
+Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1 undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1
+
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
+     not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1
+     undriven or does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
+     does not drive anything - clipped.
+Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
+     does not drive anything - clipped.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1/out_RN
+     O was optimized away.
+Block reset_dl_RNISCAF[2] was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buff
+     ered1_4_.CN was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buff
+     ered1_5_.CN was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buff
+     ered1_6_.CN was optimized away.
+
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_7_.CN was
+     optimized away.
+Block fifo_colector_inst/fifo40_inst/INV_0 was optimized away.
+Block fifo_colector_inst/fifo40_inst/INV_1 was optimized away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
+     away.
+Block GND was optimized away.
+Block VCC was optimized away.
+Block hades_tdc_bundle_inst/VCC was optimized away.
+Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC was optimized away.
+Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC was optimized
+     away.
+Block fifo_colector_inst/fifo40_inst/VCC was optimized away.
+Block fifo_colector_inst/fifo40_inst/OR2_t18 was optimized away.
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
+     
+Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
+     away.
+
+
+
+<A name="mrp_mem"></A><B><U><big>Memory Usage</big></U></B>
+
+/fifo_colector_inst/fifo40_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_1:  TYPE= PDPW16KD,  Width= 32,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo40_dc.lpc
+/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+
+/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst:
+    EBRs: 1
+    RAM SLICEs: 0
+    Logic SLICEs: 81
+    PFU Registers: 102
+    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
+         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
+         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
+
+     
+
+
+
+<A name="mrp_pll"></A><B><U><big>PLL/DLL Summary</big></U></B>
+---------------
+
+PLL 1:                                     Pin/Node Value
+  PLL Instance Name:                                pll0inst/PLLInst_0
+  PLL Type:                                         EHXPLLL
+  Input Clock:                             PIN      clk_c
+  Input Clock2:                                     NONE
+  Input Clock select:                               NONE
+  Output Clock(P):                         NODE     pll_clks[0]
+  Output Clock(S):                         NODE     pll_clks[1]
+  Output Clock(S2):                        NODE     pll_clks[2]
+  Output Clock(S3):                        NODE     pll_clks[3]
+  Feedback Signal:                         NODE     pll_clks[0]
+  Reset Signal:                                     NONE
+  Standby Signal:                          NODE     pll0inst/GND
+  PLL LOCK signal:                                  NONE
+  PLL Internal LOCK Signal:                         NONE
+  Input Clock Frequency (MHz):                      100.0000
+  Output Clock(P) Frequency (MHz):                  300.0000
+  Output Clock(S) Frequency (MHz):                  300.0000
+  Output Clock(S2) Frequency (MHz):                 300.0000
+  Output Clock(S3) Frequency (MHz):                 300.0000
+  CLKOP Post Divider A Input:                       DIVA
+  CLKOS Post Divider B Input:                       DIVB
+  CLKOS2 Post Divider C Input:                      DIVC
+  CLKOS3 Post Divider D Input:                      DIVD
+  Pre Divider A Input:                              NONE
+  Pre Divider B Input:                              NONE
+  Pre Divider C Input:                              NONE
+  Pre Divider D Input:                              NONE
+  FB_MODE:                                          CLKOP
+  CLKI Divider:                                     1
+  CLKFB Divider:                                    3
+  CLKOP Divider:                                    2
+  CLKOS Divider:                                    2
+  CLKOS2 Divider:                                   2
+
+  CLKOS3 Divider:                                   2
+  Fractional N Divider:                             NONE
+  CLKOP Desired Phase Shift(degree):                0
+  CLKOP Trim Option Rising/Falling:                 FALLING
+  CLKOP Trim Option Delay:                          0
+  CLKOS Desired Phase Shift(degree):                45
+  CLKOS Trim Option Rising/Falling:                 FALLING
+  CLKOS Trim Option Delay:                          0
+  CLKOS2 Desired Phase Shift(degree):               90
+  CLKOS2 Trim Option Rising/Falling:                NONE
+  CLKOS2 Trim Option Delay:                         NONE
+  CLKOS3 Desired Phase Shift(degree):               135
+  CLKOS3 Trim Option Rising/Falling:                NONE
+  CLKOS3 Trim Option Delay:                         NONE
+
+
+
+<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
+---------------
+
+Instance Name: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
+         Type: PDPW16KD
+Instance Name: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
+         Type: PDPW16KD
+Instance Name: pll0inst/PLLInst_0
+         Type: EHXPLLL
+
+
+
+<A name="mrp_pgr"></A><B><U><big>PGROUP Utilization</big></U></B>
+
+PGROUP "tdc0":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "tdc22":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "tdc3":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "lvl1_tdc":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_dec_pos":
+   Logic contained: 23 SLICEs, 6 PFUs
+   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_dec_neg":
+   Logic contained: 23 SLICEs, 6 PFUs
+   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_tdc_pos":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "hades_tdc_neg":
+   Logic contained: 16 SLICEs, 4 PFUs
+   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
+
+PGROUP "lvl1_pad":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "gate2":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+PGROUP "trig3":
+   Logic contained: 1 SLICEs, 1 PFUs
+   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
+
+
+
+<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
+-------------------------
+
+   Total CPU Time: 4 secs  
+   Total REAL Time: 5 secs  
+   Peak Memory Usage: 361 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_ngd.asd b/impl1/s1_impl1_ngd.asd
new file mode 100644
index 0000000..c265c78
--- /dev/null
+++ b/impl1/s1_impl1_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]
diff --git a/impl1/s1_impl1_pad.html b/impl1/s1_impl1_pad.html
new file mode 100644
index 0000000..183da5b
--- /dev/null
+++ b/impl1/s1_impl1_pad.html
@@ -0,0 +1,767 @@
+<HTML>
+<HEAD><TITLE>PAD Specification File</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Pad"></A>PAD Specification File
+***************************
+
+PART TYPE:        LFE5UM5G-45F
+Performance Grade:      8
+PACKAGE:          CABGA381
+Package Status:                     Final          Version 1.38
+
+Wed Jun 16 09:20:00 2021
+
+Pinout by Port Name:
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| Port Name                     | Pin/Bank | Buffer Type  | Site  | BC Enable | Properties                        |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+| FEE_DATAFINISHED_OUT          | D13/1    | LVCMOS25_OUT | PT53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[0]               | R17/3    | LVCMOS25_OUT | PR44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[10]              | J19/2    | LVCMOS25_OUT | PR32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[11]              | R3/8     | LVCMOS25_OUT | PB15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[12]              | N5/6     | LVCMOS25_OUT | PL59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[13]              | G16/2    | LVCMOS25_OUT | PR17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[14]              | P5/6     | LVCMOS25_OUT | PL59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[15]              | M19/3    | LVCMOS25_OUT | PR35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[16]              | N19/3    | LVCMOS25_OUT | PR59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[17]              | B15/1    | LVCMOS25_OUT | PT69A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[18]              | A15/1    | LVCMOS25_OUT | PT67A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[19]              | K5/6     | LVCMOS25_OUT | PL44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[1]               | N3/6     | LVCMOS25_OUT | PL62A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[20]              | V1/8     | LVCMOS25_OUT | PB6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[21]              | G19/2    | LVCMOS25_OUT | PR29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[22]              | T2/8     | LVCMOS25_OUT | PB13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[23]              | H20/2    | LVCMOS25_OUT | PR29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[24]              | K19/2    | LVCMOS25_OUT | PR32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[25]              | H17/2    | LVCMOS25_OUT | PR20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[26]              | L19/3    | LVCMOS25_OUT | PR35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[27]              | C20/2    | LVCMOS25_OUT | PR23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[28]              | F19/2    | LVCMOS25_OUT | PR26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[29]              | U1/8     | LVCMOS25_OUT | PB6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[2]               | G18/2    | LVCMOS25_OUT | PR17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[30]              | D20/2    | LVCMOS25_OUT | PR23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[31]              | H18/2    | LVCMOS25_OUT | PR20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[3]               | M17/3    | LVCMOS25_OUT | PR41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[4]               | E18/2    | LVCMOS25_OUT | PR14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[5]               | F16/2    | LVCMOS25_OUT | PR11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[6]               | A16/1    | LVCMOS25_OUT | PT74A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[7]               | L3/6     | LVCMOS25_OUT | PL62C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[8]               | L16/3    | LVCMOS25_OUT | PR38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_OUT[9]               | F20/2    | LVCMOS25_OUT | PR26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_DATA_WRITE_OUT            | C13/1    | LVCMOS25_OUT | PT51B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| FEE_TRG_RELEASE_OUT           | E13/1    | LVCMOS25_OUT | PT53B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| LVL1_INVALID_TRG_IN           | R16/3    | LVCMOS25_IN  | PR44C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALID_IN        | A9/0     | LVCMOS25_IN  | PT33A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| LVL1_TRG_DATA_VALI_IN_rising  | N18/3    | LVCMOS25_OUT | PR41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| burst                         | N16/3    | LVCMOS25_OUT | PR41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| clk                           | P3/6     | LVDS_IN      | PL68C |           | CLAMP:ON                          |
+| discard                       | P16/3    | LVCMOS25_OUT | PR44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[0]              | P17/3    | LVCMOS25_OUT | PR41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[10]             | K20/2    | LVCMOS25_OUT | PR32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[11]             | U2/8     | LVCMOS25_OUT | PB13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[12]             | N4/6     | LVCMOS25_OUT | PL59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[13]             | J16/2    | LVCMOS25_OUT | PR20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[14]             | M4/6     | LVCMOS25_OUT | PL59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[15]             | J20/2    | LVCMOS25_OUT | PR32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[16]             | P18/3    | LVCMOS25_OUT | PR59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[17]             | C15/1    | LVCMOS25_OUT | PT69B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[18]             | E14/1    | LVCMOS25_OUT | PT58B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[19]             | L4/6     | LVCMOS25_OUT | PL44C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[1]              | M3/6     | LVCMOS25_OUT | PL62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[20]             | Y2/8     | LVCMOS25_OUT | PB9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[21]             | K18/2    | LVCMOS25_OUT | PR29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[22]             | W1/8     | LVCMOS25_OUT | PB9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[23]             | J18/2    | LVCMOS25_OUT | PR29C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[24]             | M20/3    | LVCMOS25_OUT | PR35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[25]             | J17/2    | LVCMOS25_OUT | PR20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[26]             | L20/3    | LVCMOS25_OUT | PR35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[27]             | D19/2    | LVCMOS25_OUT | PR23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[28]             | G20/2    | LVCMOS25_OUT | PR26D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[29]             | T1/8     | LVCMOS25_OUT | PB4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[2]              | F17/2    | LVCMOS25_OUT | PR17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[30]             | E19/2    | LVCMOS25_OUT | PR23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[31]             | H16/2    | LVCMOS25_OUT | PR17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[3]              | L17/3    | LVCMOS25_OUT | PR38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[4]              | F18/2    | LVCMOS25_OUT | PR14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[5]              | D17/2    | LVCMOS25_OUT | PR11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[6]              | B16/1    | LVCMOS25_OUT | PT74B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[7]              | N1/6     | LVCMOS25_OUT | PL65D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[8]              | M18/3    | LVCMOS25_OUT | PR38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_data_out[9]              | E20/2    | LVCMOS25_OUT | PR26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_empty1                   | N17/3    | LVCMOS25_OUT | PR44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| fifo_rden                     | A19/1    | LVCMOS25_OUT | PT85A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| finished                      | D14/1    | LVCMOS25_OUT | PT58A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[0]             | N20/3    | LVCMOS25_OUT | PR59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[1]             | A10/0    | LVCMOS25_OUT | PT36A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[2]             | R20/3    | LVCMOS25_OUT | PR62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_drop[3]             | U16/3    | LVCMOS25_OUT | PR68C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_finished            | A4/7     | LVCMOS25_OUT | PL11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_out_valid           | C9/0     | LVCMOS25_OUT | PT27A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_buf_release             | E7/0     | LVCMOS25_OUT | PT9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[0]          | G5/7     | LVCMOS25_OUT | PL29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[1]          | H3/7     | LVCMOS25_OUT | PL29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[2]          | E3/7     | LVCMOS25_OUT | PL20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[3]          | C2/7     | LVCMOS25_OUT | PL23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[4]          | B6/0     | LVCMOS25_OUT | PT4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[5]          | B1/7     | LVCMOS25_OUT | PL23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[6]          | E5/7     | LVCMOS25_OUT | PL20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[7]          | M5/6     | LVCMOS25_OUT | PL53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_coarse[8]          | F1/6     | LVCMOS25_OUT | PL35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[0]             | J3/6     | LVCMOS25_OUT | PL38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[10]            | A8/0     | LVCMOS25_OUT | PT18B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[11]            | D6/0     | LVCMOS25_OUT | PT6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[12]            | B8/0     | LVCMOS25_OUT | PT15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[13]            | P19/3    | LVCMOS25_OUT | PR59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[14]            | P1/6     | LVCMOS25_OUT | PL68A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[15]            | C17/1    | LVCMOS25_OUT | PT78B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[16]            | G3/7     | LVCMOS25_OUT | PL32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[17]            | G1/6     | LVCMOS25_OUT | PL35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[18]            | J5/6     | LVCMOS25_OUT | PL38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[19]            | R1/8     | LVCMOS25_OUT | PB4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[1]             | E2/7     | LVCMOS25_OUT | PL32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[20]            | K3/6     | LVCMOS25_OUT | PL38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[21]            | G2/6     | LVCMOS25_OUT | PL35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[22]            | H4/7     | LVCMOS25_OUT | PL29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[23]            | J4/6     | LVCMOS25_OUT | PL38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[24]            | H1/6     | LVCMOS25_OUT | PL41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[25]            | J1/6     | LVCMOS25_OUT | PL41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[26]            | K1/6     | LVCMOS25_OUT | PL41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[27]            | F2/7     | LVCMOS25_OUT | PL32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[28]            | H2/6     | LVCMOS25_OUT | PL35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[29]            | A17/1    | LVCMOS25_OUT | PT80A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[2]             | F3/7     | LVCMOS25_OUT | PL32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[30]            | E16/2    | LVCMOS25_OUT | PR11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[31]            | R18/3    | LVCMOS25_OUT | PR65B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[3]             | C16/1    | LVCMOS25_OUT | PT76A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[4]             | E4/7     | LVCMOS25_OUT | PL17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[5]             | C3/7     | LVCMOS25_OUT | PL17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[6]             | F4/7     | LVCMOS25_OUT | PL20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[7]             | B3/7     | LVCMOS25_OUT | PL14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[8]             | E8/0     | LVCMOS25_OUT | PT13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_dbg2_out[9]             | C7/0     | LVCMOS25_OUT | PT11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_discard                 | B11/0    | LVCMOS25_OUT | PT38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[0]         | D3/7     | LVCMOS25_OUT | PL17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[10]        | B17/1    | LVCMOS25_OUT | PT78A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[11]        | U17/3    | LVCMOS25_OUT | PR68B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[1]         | D9/0     | LVCMOS25_OUT | PT20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[2]         | A6/0     | LVCMOS25_OUT | PT4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[3]         | C6/0     | LVCMOS25_OUT | PT11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[4]         | F5/7     | LVCMOS25_OUT | PL20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[5]         | C4/7     | LVCMOS25_OUT | PL14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[6]         | D8/0     | LVCMOS25_OUT | PT13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[7]         | D5/7     | LVCMOS25_OUT | PL17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[8]         | B4/7     | LVCMOS25_OUT | PL14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf[9]         | B20/1    | LVCMOS25_OUT | PT85B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[0]  | A11/0    | LVCMOS25_OUT | PT36B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[10] | T17/3    | LVCMOS25_OUT | PR68D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[11] | D18/2    | LVCMOS25_OUT | PR14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[1]  | A13/1    | LVCMOS25_OUT | PT49B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[2]  | B10/0    | LVCMOS25_OUT | PT33B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[3]  | C12/1    | LVCMOS25_OUT | PT44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[4]  | E12/1    | LVCMOS25_OUT | PT47B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[5]  | D12/1    | LVCMOS25_OUT | PT47A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[6]  | E11/1    | LVCMOS25_OUT | PT42B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[7]  | D11/1    | LVCMOS25_OUT | PT42A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[8]  | B13/1    | LVCMOS25_OUT | PT51A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_coarse[9]  | A12/1    | LVCMOS25_OUT | PT49A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_drop_cmp_buf_valid      | A7/0     | LVCMOS25_OUT | PT18A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[0]            | E9/0     | LVCMOS25_OUT | PT20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[1]            | C11/0    | LVCMOS25_OUT | PT38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[2]            | E6/0     | LVCMOS25_OUT | PT6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_out_i[3]            | D7/0     | LVCMOS25_OUT | PT9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[0]            | A3/7     | LVCMOS25_OUT | PL14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[1]            | B5/7     | LVCMOS25_OUT | PL11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[2]            | A5/7     | LVCMOS25_OUT | PL11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_hit_valid[3]            | C5/7     | LVCMOS25_OUT | PL11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[0]           | V2/8     | LVCMOS25_OUT | PB11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[1]           | L5/6     | LVCMOS25_OUT | PL44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[2]           | K2/6     | LVCMOS25_OUT | PL41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_invalid_dl[3]           | K4/6     | LVCMOS25_OUT | PL44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_lvl1                    | E1/7     | LVCMOS25_IN  | PL26D |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_lvl1_invalid            | W2/8     | LVCMOS25_IN  | PB11B |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_offset[0]               | D10/0    | LVCMOS25_OUT | PT29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[1]               | C10/0    | LVCMOS25_OUT | PT31B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[2]               | E10/0    | LVCMOS25_OUT | PT29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[3]               | D1/7     | LVCMOS25_OUT | PL26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[4]               | C1/7     | LVCMOS25_OUT | PL26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[5]               | D2/7     | LVCMOS25_OUT | PL26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[6]               | A2/7     | LVCMOS25_OUT | PL23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[7]               | B9/0     | LVCMOS25_OUT | PT31A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset[8]               | B2/7     | LVCMOS25_OUT | PL23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_offset_valid            | D15/1    | LVCMOS25_OUT | PT71A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_out_valid           | E15/1    | LVCMOS25_OUT | PT71B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[0]       | U20/3    | LVCMOS25_OUT | PR62D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_raw_valid_vect[1]       | E17/2    | LVCMOS25_OUT | PR14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| hades_trig                    | H5/7     | LVCMOS25_IN  | PL29C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| hades_window_end              | C14/1    | LVCMOS25_OUT | PT56B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| last_buf_empty                | L18/3    | LVCMOS25_OUT | PR38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| rd_clk                        | B12/1    | LVCMOS25_IN  | PT44A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| release_out                   | A14/1    | LVCMOS25_OUT | PT56A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
+| reset_dc                      | C8/0     | LVCMOS25_IN  | PT15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[0]                       | R2/8     | LVCMOS25_IN  | PB15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[1]                       | T3/8     | LVCMOS25_IN  | PB18A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
+| trig[2]                       | T19/3    | LVCMOS25_IN  | PR65A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
++-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
+| 6    | 2.5V  |
+| 7    | 2.5V  |
+| 8    | 2.5V  |
++------+-------+
+
+
+<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| Pin/Bank | Pin Info                      | Preference | Buffer Type  | Site         | Dual Function            | BC Enable |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+| A2/7     | hades_offset[6]               |            | LVCMOS25_OUT | PL23A        | LDQ29                    |           |
+| A3/7     | hades_hit_valid[0]            |            | LVCMOS25_OUT | PL14C        | LDQ17                    |           |
+| A4/7     | hades_buf_finished            |            | LVCMOS25_OUT | PL11A        | ULC_GPLL0T_IN/LDQ17      |           |
+| A5/7     | hades_hit_valid[2]            |            | LVCMOS25_OUT | PL11B        | ULC_GPLL0C_IN/LDQ17      |           |
+| A6/0     | hades_drop_cmp_buf[2]         |            | LVCMOS25_OUT | PT4A         | ULC_GPLL1T_IN            |           |
+| A7/0     | hades_drop_cmp_buf_valid      |            | LVCMOS25_OUT | PT18A        |                          |           |
+| A8/0     | hades_dbg2_out[10]            |            | LVCMOS25_OUT | PT18B        |                          |           |
+| A9/0     | LVL1_TRG_DATA_VALID_IN        | LOCATED    | LVCMOS25_IN  | PT33A        | GR_PCLK0_1               |           |
+| A10/0    | hades_buf_drop[1]             |            | LVCMOS25_OUT | PT36A        | PCLKT0_1                 |           |
+| A11/0    | hades_drop_cmp_buf_coarse[0]  |            | LVCMOS25_OUT | PT36B        |                          |           |
+| A12/1    | hades_drop_cmp_buf_coarse[9]  |            | LVCMOS25_OUT | PT49A        |                          |           |
+| A13/1    | hades_drop_cmp_buf_coarse[1]  |            | LVCMOS25_OUT | PT49B        |                          |           |
+| A14/1    | release_out                   |            | LVCMOS25_OUT | PT56A        |                          |           |
+| A15/1    | FEE_DATA_OUT[18]              |            | LVCMOS25_OUT | PT67A        |                          |           |
+| A16/1    | FEE_DATA_OUT[6]               |            | LVCMOS25_OUT | PT74A        |                          |           |
+| A17/1    | hades_dbg2_out[29]            |            | LVCMOS25_OUT | PT80A        |                          |           |
+| A18/1    |     unused, PULL:DOWN         |            |              | PT83A        |                          |           |
+| A19/1    | fifo_rden                     |            | LVCMOS25_OUT | PT85A        | URC_GPLL1T_IN            |           |
+| B1/7     | hades_dbg2_coarse[5]          |            | LVCMOS25_OUT | PL23B        | LDQ29                    |           |
+| B2/7     | hades_offset[8]               |            | LVCMOS25_OUT | PL23C        | VREF1_7/LDQ29            |           |
+| B3/7     | hades_dbg2_out[7]             |            | LVCMOS25_OUT | PL14D        | LDQ17                    |           |
+| B4/7     | hades_drop_cmp_buf[8]         |            | LVCMOS25_OUT | PL14B        | LDQ17                    |           |
+| B5/7     | hades_hit_valid[1]            |            | LVCMOS25_OUT | PL11C        | LDQ17                    |           |
+| B6/0     | hades_dbg2_coarse[4]          |            | LVCMOS25_OUT | PT4B         | ULC_GPLL1C_IN            |           |
+| B8/0     | hades_dbg2_out[12]            |            | LVCMOS25_OUT | PT15B        |                          |           |
+| B9/0     | hades_offset[7]               |            | LVCMOS25_OUT | PT31A        |                          |           |
+| B10/0    | hades_drop_cmp_buf_coarse[2]  |            | LVCMOS25_OUT | PT33B        | GR_PCLK0_0               |           |
+| B11/0    | hades_discard                 |            | LVCMOS25_OUT | PT38A        | PCLKT0_0                 |           |
+| B12/1    | rd_clk                        |            | LVCMOS25_IN  | PT44A        | PCLKT1_0                 |           |
+| B13/1    | hades_drop_cmp_buf_coarse[8]  |            | LVCMOS25_OUT | PT51A        |                          |           |
+| B15/1    | FEE_DATA_OUT[17]              |            | LVCMOS25_OUT | PT69A        |                          |           |
+| B16/1    | fifo_data_out[6]              |            | LVCMOS25_OUT | PT74B        |                          |           |
+| B17/1    | hades_drop_cmp_buf[10]        |            | LVCMOS25_OUT | PT78A        |                          |           |
+| B18/1    |     unused, PULL:DOWN         |            |              | PT80B        |                          |           |
+| B19/1    |     unused, PULL:DOWN         |            |              | PT83B        |                          |           |
+| B20/1    | hades_drop_cmp_buf[9]         |            | LVCMOS25_OUT | PT85B        | URC_GPLL1C_IN            |           |
+| C1/7     | hades_offset[4]               |            | LVCMOS25_OUT | PL26A        | LDQ29                    |           |
+| C2/7     | hades_dbg2_coarse[3]          |            | LVCMOS25_OUT | PL23D        | LDQ29                    |           |
+| C3/7     | hades_dbg2_out[5]             |            | LVCMOS25_OUT | PL17C        | LDQ17                    |           |
+| C4/7     | hades_drop_cmp_buf[5]         |            | LVCMOS25_OUT | PL14A        | LDQ17                    |           |
+| C5/7     | hades_hit_valid[3]            |            | LVCMOS25_OUT | PL11D        | LDQ17                    |           |
+| C6/0     | hades_drop_cmp_buf[3]         |            | LVCMOS25_OUT | PT11A        |                          |           |
+| C7/0     | hades_dbg2_out[9]             |            | LVCMOS25_OUT | PT11B        |                          |           |
+| C8/0     | reset_dc                      |            | LVCMOS25_IN  | PT15A        |                          |           |
+| C9/0     | hades_buf_out_valid           |            | LVCMOS25_OUT | PT27A        |                          |           |
+| C10/0    | hades_offset[1]               |            | LVCMOS25_OUT | PT31B        |                          |           |
+| C11/0    | hades_hit_out_i[1]            |            | LVCMOS25_OUT | PT38B        |                          |           |
+| C12/1    | hades_drop_cmp_buf_coarse[3]  |            | LVCMOS25_OUT | PT44B        |                          |           |
+| C13/1    | FEE_DATA_WRITE_OUT            |            | LVCMOS25_OUT | PT51B        |                          |           |
+| C14/1    | hades_window_end              |            | LVCMOS25_OUT | PT56B        |                          |           |
+| C15/1    | fifo_data_out[17]             |            | LVCMOS25_OUT | PT69B        |                          |           |
+| C16/1    | hades_dbg2_out[3]             |            | LVCMOS25_OUT | PT76A        |                          |           |
+| C17/1    | hades_dbg2_out[15]            |            | LVCMOS25_OUT | PT78B        |                          |           |
+| C18/2    |     unused, PULL:DOWN         |            |              | PR11A        | URC_GPLL0T_IN/RDQ17      |           |
+| C20/2    | FEE_DATA_OUT[27]              |            | LVCMOS25_OUT | PR23A        | RDQ29                    |           |
+| CCLK/8   |                               |            |              | CCLK         | MCLK/SCK                 |           |
+| D1/7     | hades_offset[3]               |            | LVCMOS25_OUT | PL26B        | LDQ29                    |           |
+| D2/7     | hades_offset[5]               |            | LVCMOS25_OUT | PL26C        | LDQ29                    |           |
+| D3/7     | hades_drop_cmp_buf[0]         |            | LVCMOS25_OUT | PL17D        | LDQ17                    |           |
+| D5/7     | hades_drop_cmp_buf[7]         |            | LVCMOS25_OUT | PL17B        | LDQSN17                  |           |
+| D6/0     | hades_dbg2_out[11]            |            | LVCMOS25_OUT | PT6B         |                          |           |
+| D7/0     | hades_hit_out_i[3]            |            | LVCMOS25_OUT | PT9B         |                          |           |
+| D8/0     | hades_drop_cmp_buf[6]         |            | LVCMOS25_OUT | PT13B        |                          |           |
+| D9/0     | hades_drop_cmp_buf[1]         |            | LVCMOS25_OUT | PT20A        |                          |           |
+| D10/0    | hades_offset[0]               |            | LVCMOS25_OUT | PT29A        |                          |           |
+| D11/1    | hades_drop_cmp_buf_coarse[7]  |            | LVCMOS25_OUT | PT42A        | PCLKT1_1                 |           |
+| D12/1    | hades_drop_cmp_buf_coarse[5]  |            | LVCMOS25_OUT | PT47A        | GR_PCLK1_0               |           |
+| D13/1    | FEE_DATAFINISHED_OUT          |            | LVCMOS25_OUT | PT53A        |                          |           |
+| D14/1    | finished                      |            | LVCMOS25_OUT | PT58A        |                          |           |
+| D15/1    | hades_offset_valid            |            | LVCMOS25_OUT | PT71A        |                          |           |
+| D16/1    |     unused, PULL:DOWN         |            |              | PT76B        |                          |           |
+| D17/2    | fifo_data_out[5]              |            | LVCMOS25_OUT | PR11B        | URC_GPLL0C_IN/RDQ17      |           |
+| D18/2    | hades_drop_cmp_buf_coarse[11] |            | LVCMOS25_OUT | PR14A        | RDQ17                    |           |
+| D19/2    | fifo_data_out[27]             |            | LVCMOS25_OUT | PR23B        | RDQ29                    |           |
+| D20/2    | FEE_DATA_OUT[30]              |            | LVCMOS25_OUT | PR23C        | VREF1_2/RDQ29            |           |
+| E1/7     | hades_lvl1                    | LOCATED    | LVCMOS25_IN  | PL26D        | LDQ29                    |           |
+| E2/7     | hades_dbg2_out[1]             |            | LVCMOS25_OUT | PL32D        | PCLKC7_0/LDQ29           |           |
+| E3/7     | hades_dbg2_coarse[2]          |            | LVCMOS25_OUT | PL20B        | LDQ17                    |           |
+| E4/7     | hades_dbg2_out[4]             |            | LVCMOS25_OUT | PL17A        | LDQS17                   |           |
+| E5/7     | hades_dbg2_coarse[6]          |            | LVCMOS25_OUT | PL20C        | LDQ17                    |           |
+| E6/0     | hades_hit_out_i[2]            |            | LVCMOS25_OUT | PT6A         |                          |           |
+| E7/0     | hades_buf_release             |            | LVCMOS25_OUT | PT9A         |                          |           |
+| E8/0     | hades_dbg2_out[8]             |            | LVCMOS25_OUT | PT13A        |                          |           |
+| E9/0     | hades_hit_out_i[0]            |            | LVCMOS25_OUT | PT20B        |                          |           |
+| E10/0    | hades_offset[2]               |            | LVCMOS25_OUT | PT29B        |                          |           |
+| E11/1    | hades_drop_cmp_buf_coarse[6]  |            | LVCMOS25_OUT | PT42B        |                          |           |
+| E12/1    | hades_drop_cmp_buf_coarse[4]  |            | LVCMOS25_OUT | PT47B        | GR_PCLK1_1               |           |
+| E13/1    | FEE_TRG_RELEASE_OUT           |            | LVCMOS25_OUT | PT53B        |                          |           |
+| E14/1    | fifo_data_out[18]             |            | LVCMOS25_OUT | PT58B        |                          |           |
+| E15/1    | hades_raw_out_valid           |            | LVCMOS25_OUT | PT71B        |                          |           |
+| E16/2    | hades_dbg2_out[30]            |            | LVCMOS25_OUT | PR11C        | RDQ17                    |           |
+| E17/2    | hades_raw_valid_vect[1]       |            | LVCMOS25_OUT | PR14B        | RDQ17                    |           |
+| E18/2    | FEE_DATA_OUT[4]               |            | LVCMOS25_OUT | PR14C        | RDQ17                    |           |
+| E19/2    | fifo_data_out[30]             |            | LVCMOS25_OUT | PR23D        | RDQ29                    |           |
+| E20/2    | fifo_data_out[9]              |            | LVCMOS25_OUT | PR26A        | RDQ29                    |           |
+| F1/6     | hades_dbg2_coarse[8]          |            | LVCMOS25_OUT | PL35B        | PCLKC6_1/LDQ41           |           |
+| F2/7     | hades_dbg2_out[27]            |            | LVCMOS25_OUT | PL32C        | PCLKT7_0/LDQ29           |           |
+| F3/7     | hades_dbg2_out[2]             |            | LVCMOS25_OUT | PL32B        | PCLKC7_1/LDQ29           |           |
+| F4/7     | hades_dbg2_out[6]             |            | LVCMOS25_OUT | PL20A        | LDQ17                    |           |
+| F5/7     | hades_drop_cmp_buf[4]         |            | LVCMOS25_OUT | PL20D        | LDQ17                    |           |
+| F16/2    | FEE_DATA_OUT[5]               |            | LVCMOS25_OUT | PR11D        | RDQ17                    |           |
+| F17/2    | fifo_data_out[2]              |            | LVCMOS25_OUT | PR17A        | RDQS17                   |           |
+| F18/2    | fifo_data_out[4]              |            | LVCMOS25_OUT | PR14D        | RDQ17                    |           |
+| F19/2    | FEE_DATA_OUT[28]              |            | LVCMOS25_OUT | PR26B        | RDQ29                    |           |
+| F20/2    | FEE_DATA_OUT[9]               |            | LVCMOS25_OUT | PR26C        | RDQ29                    |           |
+| G1/6     | hades_dbg2_out[17]            |            | LVCMOS25_OUT | PL35D        | PCLKC6_0/LDQ41           |           |
+| G2/6     | hades_dbg2_out[21]            |            | LVCMOS25_OUT | PL35A        | PCLKT6_1/LDQ41           |           |
+| G3/7     | hades_dbg2_out[16]            |            | LVCMOS25_OUT | PL32A        | PCLKT7_1/LDQ29           |           |
+| G5/7     | hades_dbg2_coarse[0]          |            | LVCMOS25_OUT | PL29B        | LDQSN29                  |           |
+| G16/2    | FEE_DATA_OUT[13]              |            | LVCMOS25_OUT | PR17C        | RDQ17                    |           |
+| G18/2    | FEE_DATA_OUT[2]               |            | LVCMOS25_OUT | PR17B        | RDQSN17                  |           |
+| G19/2    | FEE_DATA_OUT[21]              |            | LVCMOS25_OUT | PR29A        | GR_PCLK2_1/RDQS29        |           |
+| G20/2    | fifo_data_out[28]             |            | LVCMOS25_OUT | PR26D        | RDQ29                    |           |
+| H1/6     | hades_dbg2_out[24]            |            | LVCMOS25_OUT | PL41C        | LDQ41                    |           |
+| H2/6     | hades_dbg2_out[28]            |            | LVCMOS25_OUT | PL35C        | PCLKT6_0/LDQ41           |           |
+| H3/7     | hades_dbg2_coarse[1]          |            | LVCMOS25_OUT | PL29D        | LDQ29                    |           |
+| H4/7     | hades_dbg2_out[22]            |            | LVCMOS25_OUT | PL29A        | GR_PCLK7_1/LDQS29        |           |
+| H5/7     | hades_trig                    | LOCATED    | LVCMOS25_IN  | PL29C        | GR_PCLK7_0/LDQ29         |           |
+| H16/2    | fifo_data_out[31]             |            | LVCMOS25_OUT | PR17D        | RDQ17                    |           |
+| H17/2    | FEE_DATA_OUT[25]              |            | LVCMOS25_OUT | PR20B        | RDQ17                    |           |
+| H18/2    | FEE_DATA_OUT[31]              |            | LVCMOS25_OUT | PR20A        | RDQ17                    |           |
+| H20/2    | FEE_DATA_OUT[23]              |            | LVCMOS25_OUT | PR29B        | RDQSN29                  |           |
+| J1/6     | hades_dbg2_out[25]            |            | LVCMOS25_OUT | PL41B        | LDQSN41                  |           |
+| J3/6     | hades_dbg2_out[0]             |            | LVCMOS25_OUT | PL38C        | GR_PCLK6_1/LDQ41         |           |
+| J4/6     | hades_dbg2_out[23]            |            | LVCMOS25_OUT | PL38A        | GR_PCLK6_0/LDQ41         |           |
+| J5/6     | hades_dbg2_out[18]            |            | LVCMOS25_OUT | PL38B        | LDQ41                    |           |
+| J16/2    | fifo_data_out[13]             |            | LVCMOS25_OUT | PR20D        | RDQ17                    |           |
+| J17/2    | fifo_data_out[25]             |            | LVCMOS25_OUT | PR20C        | RDQ17                    |           |
+| J18/2    | fifo_data_out[23]             |            | LVCMOS25_OUT | PR29C        | GR_PCLK2_0/RDQ29         |           |
+| J19/2    | FEE_DATA_OUT[10]              |            | LVCMOS25_OUT | PR32A        | PCLKT2_1/RDQ29           |           |
+| J20/2    | fifo_data_out[15]             |            | LVCMOS25_OUT | PR32C        | PCLKT2_0/RDQ29           |           |
+| K1/6     | hades_dbg2_out[26]            |            | LVCMOS25_OUT | PL41D        | LDQ41                    |           |
+| K2/6     | hades_invalid_dl[2]           |            | LVCMOS25_OUT | PL41A        | LDQS41                   |           |
+| K3/6     | hades_dbg2_out[20]            |            | LVCMOS25_OUT | PL38D        | LDQ41                    |           |
+| K4/6     | hades_invalid_dl[3]           |            | LVCMOS25_OUT | PL44A        | LDQ41                    |           |
+| K5/6     | FEE_DATA_OUT[19]              |            | LVCMOS25_OUT | PL44B        | VREF1_6/LDQ41            |           |
+| K18/2    | fifo_data_out[21]             |            | LVCMOS25_OUT | PR29D        | RDQ29                    |           |
+| K19/2    | FEE_DATA_OUT[24]              |            | LVCMOS25_OUT | PR32B        | PCLKC2_1/RDQ29           |           |
+| K20/2    | fifo_data_out[10]             |            | LVCMOS25_OUT | PR32D        | PCLKC2_0/RDQ29           |           |
+| L1/6     |     unused, PULL:DOWN         |            |              | PL65C        | LDQ65                    |           |
+| L2/6     |     unused, PULL:DOWN         |            |              | PL62D        | LDQ65                    |           |
+| L3/6     | FEE_DATA_OUT[7]               |            | LVCMOS25_OUT | PL62C        | LDQ65                    |           |
+| L4/6     | fifo_data_out[19]             |            | LVCMOS25_OUT | PL44C        | LDQ41                    |           |
+| L5/6     | hades_invalid_dl[1]           |            | LVCMOS25_OUT | PL44D        | LDQ41                    |           |
+| L16/3    | FEE_DATA_OUT[8]               |            | LVCMOS25_OUT | PR38A        | GR_PCLK3_0/RDQ41         |           |
+| L17/3    | fifo_data_out[3]              |            | LVCMOS25_OUT | PR38B        | RDQ41                    |           |
+| L18/3    | last_buf_empty                |            | LVCMOS25_OUT | PR38C        | GR_PCLK3_1/RDQ41         |           |
+| L19/3    | FEE_DATA_OUT[26]              |            | LVCMOS25_OUT | PR35C        | PCLKT3_0/RDQ41           |           |
+| L20/3    | fifo_data_out[26]             |            | LVCMOS25_OUT | PR35A        | PCLKT3_1/RDQ41           |           |
+| M1/6     |     unused, PULL:DOWN         |            |              | PL65B        | LDQSN65                  |           |
+| M3/6     | fifo_data_out[1]              |            | LVCMOS25_OUT | PL62B        | LDQ65                    |           |
+| M4/6     | fifo_data_out[14]             |            | LVCMOS25_OUT | PL59A        | LDQ65                    |           |
+| M5/6     | hades_dbg2_coarse[7]          |            | LVCMOS25_OUT | PL53A        | LDQS53                   |           |
+| M17/3    | FEE_DATA_OUT[3]               |            | LVCMOS25_OUT | PR41B        | RDQSN41                  |           |
+| M18/3    | fifo_data_out[8]              |            | LVCMOS25_OUT | PR38D        | RDQ41                    |           |
+| M19/3    | FEE_DATA_OUT[15]              |            | LVCMOS25_OUT | PR35D        | PCLKC3_0/RDQ41           |           |
+| M20/3    | fifo_data_out[24]             |            | LVCMOS25_OUT | PR35B        | PCLKC3_1/RDQ41           |           |
+| N1/6     | fifo_data_out[7]              |            | LVCMOS25_OUT | PL65D        | LDQ65                    |           |
+| N2/6     |     unused, PULL:DOWN         |            |              | PL65A        | LDQS65                   |           |
+| N3/6     | FEE_DATA_OUT[1]               |            | LVCMOS25_OUT | PL62A        | LDQ65                    |           |
+| N4/6     | fifo_data_out[12]             |            | LVCMOS25_OUT | PL59C        | LDQ65                    |           |
+| N5/6     | FEE_DATA_OUT[12]              |            | LVCMOS25_OUT | PL59B        | LDQ65                    |           |
+| N16/3    | burst                         |            | LVCMOS25_OUT | PR41A        | RDQS41                   |           |
+| N17/3    | fifo_empty1                   |            | LVCMOS25_OUT | PR44A        | RDQ41                    |           |
+| N18/3    | LVL1_TRG_DATA_VALI_IN_rising  |            | LVCMOS25_OUT | PR41C        | RDQ41                    |           |
+| N19/3    | FEE_DATA_OUT[16]              |            | LVCMOS25_OUT | PR59A        | RDQ65                    |           |
+| N20/3    | hades_buf_drop[0]             |            | LVCMOS25_OUT | PR59B        | RDQ65                    |           |
+| P1/6     | hades_dbg2_out[14]            |            | LVCMOS25_OUT | PL68A        | LDQ65                    |           |
+| P2/6     |     unused, PULL:DOWN         |            |              | PL68B        | LDQ65                    |           |
+| P3/6     | clk+                          | LOCATED    | LVDS_IN      | PL68C        | LLC_GPLL0T_IN/LDQ65      |           |
+| P4/6     | clk-                          |            | LVDS_IN      | PL68D        | LLC_GPLL0C_IN/LDQ65      |           |
+| P5/6     | FEE_DATA_OUT[14]              |            | LVCMOS25_OUT | PL59D        | LDQ65                    |           |
+| P16/3    | discard                       |            | LVCMOS25_OUT | PR44B        | VREF1_3/RDQ41            |           |
+| P17/3    | fifo_data_out[0]              |            | LVCMOS25_OUT | PR41D        | RDQ41                    |           |
+| P18/3    | fifo_data_out[16]             |            | LVCMOS25_OUT | PR59D        | RDQ65                    |           |
+| P19/3    | hades_dbg2_out[13]            |            | LVCMOS25_OUT | PR59C        | RDQ65                    |           |
+| P20/3    |     unused, PULL:DOWN         |            |              | PR62A        | RDQ65                    |           |
+| PL47A/6  |     unused, PULL:DOWN         |            |              | PL47A        | LDQ53                    |           |
+| PL47B/6  |     unused, PULL:DOWN         |            |              | PL47B        | LDQ53                    |           |
+| PL47C/6  |     unused, PULL:DOWN         |            |              | PL47C        | LDQ53                    |           |
+| PL47D/6  |     unused, PULL:DOWN         |            |              | PL47D        | LDQ53                    |           |
+| PL50A/6  |     unused, PULL:DOWN         |            |              | PL50A        | LDQ53                    |           |
+| PL50B/6  |     unused, PULL:DOWN         |            |              | PL50B        | LDQ53                    |           |
+| PL50C/6  |     unused, PULL:DOWN         |            |              | PL50C        | LDQ53                    |           |
+| PL50D/6  |     unused, PULL:DOWN         |            |              | PL50D        | LDQ53                    |           |
+| PL53B/6  |     unused, PULL:DOWN         |            |              | PL53B        | LDQSN53                  |           |
+| PL53C/6  |     unused, PULL:DOWN         |            |              | PL53C        | LDQ53                    |           |
+| PL53D/6  |     unused, PULL:DOWN         |            |              | PL53D        | LDQ53                    |           |
+| PL56A/6  |     unused, PULL:DOWN         |            |              | PL56A        | LDQ53                    |           |
+| PL56B/6  |     unused, PULL:DOWN         |            |              | PL56B        | LDQ53                    |           |
+| PL56C/6  |     unused, PULL:DOWN         |            |              | PL56C        | LDQ53                    |           |
+| PL56D/6  |     unused, PULL:DOWN         |            |              | PL56D        | LDQ53                    |           |
+| PR47A/3  |     unused, PULL:DOWN         |            |              | PR47A        | RDQ53                    |           |
+| PR47B/3  |     unused, PULL:DOWN         |            |              | PR47B        | RDQ53                    |           |
+| PR47C/3  |     unused, PULL:DOWN         |            |              | PR47C        | RDQ53                    |           |
+| PR47D/3  |     unused, PULL:DOWN         |            |              | PR47D        | RDQ53                    |           |
+| PR50A/3  |     unused, PULL:DOWN         |            |              | PR50A        | RDQ53                    |           |
+| PR50B/3  |     unused, PULL:DOWN         |            |              | PR50B        | RDQ53                    |           |
+| PR50C/3  |     unused, PULL:DOWN         |            |              | PR50C        | RDQ53                    |           |
+| PR50D/3  |     unused, PULL:DOWN         |            |              | PR50D        | RDQ53                    |           |
+| PR53B/3  |     unused, PULL:DOWN         |            |              | PR53B        | RDQSN53                  |           |
+| PR53C/3  |     unused, PULL:DOWN         |            |              | PR53C        | RDQ53                    |           |
+| PR53D/3  |     unused, PULL:DOWN         |            |              | PR53D        | RDQ53                    |           |
+| PR56A/3  |     unused, PULL:DOWN         |            |              | PR56A        | RDQ53                    |           |
+| PR56B/3  |     unused, PULL:DOWN         |            |              | PR56B        | RDQ53                    |           |
+| PR56C/3  |     unused, PULL:DOWN         |            |              | PR56C        | RDQ53                    |           |
+| PR56D/3  |     unused, PULL:DOWN         |            |              | PR56D        | RDQ53                    |           |
+| PT22A/0  |     unused, PULL:DOWN         |            |              | PT22A        |                          |           |
+| PT22B/0  |     unused, PULL:DOWN         |            |              | PT22B        |                          |           |
+| PT24A/0  |     unused, PULL:DOWN         |            |              | PT24A        |                          |           |
+| PT24B/0  |     unused, PULL:DOWN         |            |              | PT24B        |                          |           |
+| PT27B/0  |     unused, PULL:DOWN         |            |              | PT27B        |                          |           |
+| PT60A/1  |     unused, PULL:DOWN         |            |              | PT60A        |                          |           |
+| PT60B/1  |     unused, PULL:DOWN         |            |              | PT60B        |                          |           |
+| PT62A/1  |     unused, PULL:DOWN         |            |              | PT62A        |                          |           |
+| PT62B/1  |     unused, PULL:DOWN         |            |              | PT62B        |                          |           |
+| PT65A/1  |     unused, PULL:DOWN         |            |              | PT65A        |                          |           |
+| PT65B/1  |     unused, PULL:DOWN         |            |              | PT65B        |                          |           |
+| PT67B/1  |     unused, PULL:DOWN         |            |              | PT67B        |                          |           |
+| R1/8     | hades_dbg2_out[19]            |            | LVCMOS25_OUT | PB4A         | D7/IO7                   |           |
+| R2/8     | trig[0]                       | LOCATED    | LVCMOS25_IN  | PB15A        | HOLDN/DI/BUSY/CSSPIN/CEN |           |
+| R3/8     | FEE_DATA_OUT[11]              |            | LVCMOS25_OUT | PB15B        | DOUT/CSON                |           |
+| R16/3    | LVL1_INVALID_TRG_IN           |            | LVCMOS25_IN  | PR44C        | RDQ41                    |           |
+| R17/3    | FEE_DATA_OUT[0]               |            | LVCMOS25_OUT | PR44D        | RDQ41                    |           |
+| R18/3    | hades_dbg2_out[31]            |            | LVCMOS25_OUT | PR65B        | RDQSN65                  |           |
+| R20/3    | hades_buf_drop[2]             |            | LVCMOS25_OUT | PR62B        | RDQ65                    |           |
+| T1/8     | fifo_data_out[29]             |            | LVCMOS25_OUT | PB4B         | D6/IO6                   |           |
+| T2/8     | FEE_DATA_OUT[22]              |            | LVCMOS25_OUT | PB13A        | SN/CSN                   |           |
+| T3/8     | trig[1]                       | LOCATED    | LVCMOS25_IN  | PB18A        | WRITEN                   |           |
+| T16/3    |     unused, PULL:DOWN         |            |              | PR53A        | RDQS53                   |           |
+| T17/3    | hades_drop_cmp_buf_coarse[10] |            | LVCMOS25_OUT | PR68D        | LRC_GPLL0C_IN/RDQ65      |           |
+| T18/3    |     unused, PULL:DOWN         |            |              | PR65D        | RDQ65                    |           |
+| T19/3    | trig[2]                       | LOCATED    | LVCMOS25_IN  | PR65A        | RDQS65                   |           |
+| T20/3    |     unused, PULL:DOWN         |            |              | PR62C        | RDQ65                    |           |
+| TCK/40   |                               |            |              | TCK          |                          |           |
+| TDI/40   |                               |            |              | TDI          |                          |           |
+| TDO/40   |                               |            |              | TDO          |                          |           |
+| TMS/40   |                               |            |              | TMS          |                          |           |
+| U1/8     | FEE_DATA_OUT[29]              |            | LVCMOS25_OUT | PB6A         | D5/MISO2/IO5             |           |
+| U2/8     | fifo_data_out[11]             |            | LVCMOS25_OUT | PB13B        | CS1N                     |           |
+| U16/3    | hades_buf_drop[3]             |            | LVCMOS25_OUT | PR68C        | LRC_GPLL0T_IN/RDQ65      |           |
+| U17/3    | hades_drop_cmp_buf[11]        |            | LVCMOS25_OUT | PR68B        | RDQ65                    |           |
+| U18/3    |     unused, PULL:DOWN         |            |              | PR68A        | RDQ65                    |           |
+| U19/3    |     unused, PULL:DOWN         |            |              | PR65C        | RDQ65                    |           |
+| U20/3    | hades_raw_valid_vect[0]       |            | LVCMOS25_OUT | PR62D        | RDQ65                    |           |
+| V1/8     | FEE_DATA_OUT[20]              |            | LVCMOS25_OUT | PB6B         | D4/MOSI2/IO4             |           |
+| V2/8     | hades_invalid_dl[0]           |            | LVCMOS25_OUT | PB11A        | D1/MISO/IO1              |           |
+| W1/8     | fifo_data_out[22]             |            | LVCMOS25_OUT | PB9A         | D3/IO3                   |           |
+| W2/8     | hades_lvl1_invalid            |            | LVCMOS25_IN  | PB11B        | D0/MOSI/IO0              |           |
+| W4/50    |                               |            |              | HDTXP0_D0CH0 |                          |           |
+| W5/50    |                               |            |              | HDTXN0_D0CH0 |                          |           |
+| W8/50    |                               |            |              | HDTXP0_D0CH1 |                          |           |
+| W9/50    |                               |            |              | HDTXN0_D0CH1 |                          |           |
+| W13/51   |                               |            |              | HDTXP0_D1CH0 |                          |           |
+| W14/51   |                               |            |              | HDTXN0_D1CH0 |                          |           |
+| W17/51   |                               |            |              | HDTXP0_D1CH1 |                          |           |
+| W18/51   |                               |            |              | HDTXN0_D1CH1 |                          |           |
+| W20/51   |                               |            |              | REFCLKN_D1   |                          |           |
+| Y2/8     | fifo_data_out[20]             |            | LVCMOS25_OUT | PB9B         | D2/IO2                   |           |
+| Y5/50    |                               |            |              | HDRXP0_D0CH0 |                          |           |
+| Y6/50    |                               |            |              | HDRXN0_D0CH0 |                          |           |
+| Y7/50    |                               |            |              | HDRXP0_D0CH1 |                          |           |
+| Y8/50    |                               |            |              | HDRXN0_D0CH1 |                          |           |
+| Y11/50   |                               |            |              | REFCLKP_D0   |                          |           |
+| Y12/50   |                               |            |              | REFCLKN_D0   |                          |           |
+| Y14/51   |                               |            |              | HDRXP0_D1CH0 |                          |           |
+| Y15/51   |                               |            |              | HDRXN0_D1CH0 |                          |           |
+| Y16/51   |                               |            |              | HDRXP0_D1CH1 |                          |           |
+| Y17/51   |                               |            |              | HDRXN0_D1CH1 |                          |           |
+| Y19/51   |                               |            |              | REFCLKP_D1   |                          |           |
++----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "FEE_DATAFINISHED_OUT"  SITE  "D13";
+LOCATE  COMP  "FEE_DATA_OUT[0]"  SITE  "R17";
+LOCATE  COMP  "FEE_DATA_OUT[10]"  SITE  "J19";
+LOCATE  COMP  "FEE_DATA_OUT[11]"  SITE  "R3";
+LOCATE  COMP  "FEE_DATA_OUT[12]"  SITE  "N5";
+LOCATE  COMP  "FEE_DATA_OUT[13]"  SITE  "G16";
+LOCATE  COMP  "FEE_DATA_OUT[14]"  SITE  "P5";
+LOCATE  COMP  "FEE_DATA_OUT[15]"  SITE  "M19";
+LOCATE  COMP  "FEE_DATA_OUT[16]"  SITE  "N19";
+LOCATE  COMP  "FEE_DATA_OUT[17]"  SITE  "B15";
+LOCATE  COMP  "FEE_DATA_OUT[18]"  SITE  "A15";
+LOCATE  COMP  "FEE_DATA_OUT[19]"  SITE  "K5";
+LOCATE  COMP  "FEE_DATA_OUT[1]"  SITE  "N3";
+LOCATE  COMP  "FEE_DATA_OUT[20]"  SITE  "V1";
+LOCATE  COMP  "FEE_DATA_OUT[21]"  SITE  "G19";
+LOCATE  COMP  "FEE_DATA_OUT[22]"  SITE  "T2";
+LOCATE  COMP  "FEE_DATA_OUT[23]"  SITE  "H20";
+LOCATE  COMP  "FEE_DATA_OUT[24]"  SITE  "K19";
+LOCATE  COMP  "FEE_DATA_OUT[25]"  SITE  "H17";
+LOCATE  COMP  "FEE_DATA_OUT[26]"  SITE  "L19";
+LOCATE  COMP  "FEE_DATA_OUT[27]"  SITE  "C20";
+LOCATE  COMP  "FEE_DATA_OUT[28]"  SITE  "F19";
+LOCATE  COMP  "FEE_DATA_OUT[29]"  SITE  "U1";
+LOCATE  COMP  "FEE_DATA_OUT[2]"  SITE  "G18";
+LOCATE  COMP  "FEE_DATA_OUT[30]"  SITE  "D20";
+LOCATE  COMP  "FEE_DATA_OUT[31]"  SITE  "H18";
+LOCATE  COMP  "FEE_DATA_OUT[3]"  SITE  "M17";
+LOCATE  COMP  "FEE_DATA_OUT[4]"  SITE  "E18";
+LOCATE  COMP  "FEE_DATA_OUT[5]"  SITE  "F16";
+LOCATE  COMP  "FEE_DATA_OUT[6]"  SITE  "A16";
+LOCATE  COMP  "FEE_DATA_OUT[7]"  SITE  "L3";
+LOCATE  COMP  "FEE_DATA_OUT[8]"  SITE  "L16";
+LOCATE  COMP  "FEE_DATA_OUT[9]"  SITE  "F20";
+LOCATE  COMP  "FEE_DATA_WRITE_OUT"  SITE  "C13";
+LOCATE  COMP  "FEE_TRG_RELEASE_OUT"  SITE  "E13";
+LOCATE  COMP  "LVL1_INVALID_TRG_IN"  SITE  "R16";
+LOCATE  COMP  "LVL1_TRG_DATA_VALID_IN"  SITE  "A9";
+LOCATE  COMP  "LVL1_TRG_DATA_VALI_IN_rising"  SITE  "N18";
+LOCATE  COMP  "burst"  SITE  "N16";
+LOCATE  COMP  "clk"  SITE  "P3";
+LOCATE  COMP  "discard"  SITE  "P16";
+LOCATE  COMP  "fifo_data_out[0]"  SITE  "P17";
+LOCATE  COMP  "fifo_data_out[10]"  SITE  "K20";
+LOCATE  COMP  "fifo_data_out[11]"  SITE  "U2";
+LOCATE  COMP  "fifo_data_out[12]"  SITE  "N4";
+LOCATE  COMP  "fifo_data_out[13]"  SITE  "J16";
+LOCATE  COMP  "fifo_data_out[14]"  SITE  "M4";
+LOCATE  COMP  "fifo_data_out[15]"  SITE  "J20";
+LOCATE  COMP  "fifo_data_out[16]"  SITE  "P18";
+LOCATE  COMP  "fifo_data_out[17]"  SITE  "C15";
+LOCATE  COMP  "fifo_data_out[18]"  SITE  "E14";
+LOCATE  COMP  "fifo_data_out[19]"  SITE  "L4";
+LOCATE  COMP  "fifo_data_out[1]"  SITE  "M3";
+LOCATE  COMP  "fifo_data_out[20]"  SITE  "Y2";
+LOCATE  COMP  "fifo_data_out[21]"  SITE  "K18";
+LOCATE  COMP  "fifo_data_out[22]"  SITE  "W1";
+LOCATE  COMP  "fifo_data_out[23]"  SITE  "J18";
+LOCATE  COMP  "fifo_data_out[24]"  SITE  "M20";
+LOCATE  COMP  "fifo_data_out[25]"  SITE  "J17";
+LOCATE  COMP  "fifo_data_out[26]"  SITE  "L20";
+LOCATE  COMP  "fifo_data_out[27]"  SITE  "D19";
+LOCATE  COMP  "fifo_data_out[28]"  SITE  "G20";
+LOCATE  COMP  "fifo_data_out[29]"  SITE  "T1";
+LOCATE  COMP  "fifo_data_out[2]"  SITE  "F17";
+LOCATE  COMP  "fifo_data_out[30]"  SITE  "E19";
+LOCATE  COMP  "fifo_data_out[31]"  SITE  "H16";
+LOCATE  COMP  "fifo_data_out[3]"  SITE  "L17";
+LOCATE  COMP  "fifo_data_out[4]"  SITE  "F18";
+LOCATE  COMP  "fifo_data_out[5]"  SITE  "D17";
+LOCATE  COMP  "fifo_data_out[6]"  SITE  "B16";
+LOCATE  COMP  "fifo_data_out[7]"  SITE  "N1";
+LOCATE  COMP  "fifo_data_out[8]"  SITE  "M18";
+LOCATE  COMP  "fifo_data_out[9]"  SITE  "E20";
+LOCATE  COMP  "fifo_empty1"  SITE  "N17";
+LOCATE  COMP  "fifo_rden"  SITE  "A19";
+LOCATE  COMP  "finished"  SITE  "D14";
+LOCATE  COMP  "hades_buf_drop[0]"  SITE  "N20";
+LOCATE  COMP  "hades_buf_drop[1]"  SITE  "A10";
+LOCATE  COMP  "hades_buf_drop[2]"  SITE  "R20";
+LOCATE  COMP  "hades_buf_drop[3]"  SITE  "U16";
+LOCATE  COMP  "hades_buf_finished"  SITE  "A4";
+LOCATE  COMP  "hades_buf_out_valid"  SITE  "C9";
+LOCATE  COMP  "hades_buf_release"  SITE  "E7";
+LOCATE  COMP  "hades_dbg2_coarse[0]"  SITE  "G5";
+LOCATE  COMP  "hades_dbg2_coarse[1]"  SITE  "H3";
+LOCATE  COMP  "hades_dbg2_coarse[2]"  SITE  "E3";
+LOCATE  COMP  "hades_dbg2_coarse[3]"  SITE  "C2";
+LOCATE  COMP  "hades_dbg2_coarse[4]"  SITE  "B6";
+LOCATE  COMP  "hades_dbg2_coarse[5]"  SITE  "B1";
+LOCATE  COMP  "hades_dbg2_coarse[6]"  SITE  "E5";
+LOCATE  COMP  "hades_dbg2_coarse[7]"  SITE  "M5";
+LOCATE  COMP  "hades_dbg2_coarse[8]"  SITE  "F1";
+LOCATE  COMP  "hades_dbg2_out[0]"  SITE  "J3";
+LOCATE  COMP  "hades_dbg2_out[10]"  SITE  "A8";
+LOCATE  COMP  "hades_dbg2_out[11]"  SITE  "D6";
+LOCATE  COMP  "hades_dbg2_out[12]"  SITE  "B8";
+LOCATE  COMP  "hades_dbg2_out[13]"  SITE  "P19";
+LOCATE  COMP  "hades_dbg2_out[14]"  SITE  "P1";
+LOCATE  COMP  "hades_dbg2_out[15]"  SITE  "C17";
+LOCATE  COMP  "hades_dbg2_out[16]"  SITE  "G3";
+LOCATE  COMP  "hades_dbg2_out[17]"  SITE  "G1";
+LOCATE  COMP  "hades_dbg2_out[18]"  SITE  "J5";
+LOCATE  COMP  "hades_dbg2_out[19]"  SITE  "R1";
+LOCATE  COMP  "hades_dbg2_out[1]"  SITE  "E2";
+LOCATE  COMP  "hades_dbg2_out[20]"  SITE  "K3";
+LOCATE  COMP  "hades_dbg2_out[21]"  SITE  "G2";
+LOCATE  COMP  "hades_dbg2_out[22]"  SITE  "H4";
+LOCATE  COMP  "hades_dbg2_out[23]"  SITE  "J4";
+LOCATE  COMP  "hades_dbg2_out[24]"  SITE  "H1";
+LOCATE  COMP  "hades_dbg2_out[25]"  SITE  "J1";
+LOCATE  COMP  "hades_dbg2_out[26]"  SITE  "K1";
+LOCATE  COMP  "hades_dbg2_out[27]"  SITE  "F2";
+LOCATE  COMP  "hades_dbg2_out[28]"  SITE  "H2";
+LOCATE  COMP  "hades_dbg2_out[29]"  SITE  "A17";
+LOCATE  COMP  "hades_dbg2_out[2]"  SITE  "F3";
+LOCATE  COMP  "hades_dbg2_out[30]"  SITE  "E16";
+LOCATE  COMP  "hades_dbg2_out[31]"  SITE  "R18";
+LOCATE  COMP  "hades_dbg2_out[3]"  SITE  "C16";
+LOCATE  COMP  "hades_dbg2_out[4]"  SITE  "E4";
+LOCATE  COMP  "hades_dbg2_out[5]"  SITE  "C3";
+LOCATE  COMP  "hades_dbg2_out[6]"  SITE  "F4";
+LOCATE  COMP  "hades_dbg2_out[7]"  SITE  "B3";
+LOCATE  COMP  "hades_dbg2_out[8]"  SITE  "E8";
+LOCATE  COMP  "hades_dbg2_out[9]"  SITE  "C7";
+LOCATE  COMP  "hades_discard"  SITE  "B11";
+LOCATE  COMP  "hades_drop_cmp_buf[0]"  SITE  "D3";
+LOCATE  COMP  "hades_drop_cmp_buf[10]"  SITE  "B17";
+LOCATE  COMP  "hades_drop_cmp_buf[11]"  SITE  "U17";
+LOCATE  COMP  "hades_drop_cmp_buf[1]"  SITE  "D9";
+LOCATE  COMP  "hades_drop_cmp_buf[2]"  SITE  "A6";
+LOCATE  COMP  "hades_drop_cmp_buf[3]"  SITE  "C6";
+LOCATE  COMP  "hades_drop_cmp_buf[4]"  SITE  "F5";
+LOCATE  COMP  "hades_drop_cmp_buf[5]"  SITE  "C4";
+LOCATE  COMP  "hades_drop_cmp_buf[6]"  SITE  "D8";
+LOCATE  COMP  "hades_drop_cmp_buf[7]"  SITE  "D5";
+LOCATE  COMP  "hades_drop_cmp_buf[8]"  SITE  "B4";
+LOCATE  COMP  "hades_drop_cmp_buf[9]"  SITE  "B20";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[0]"  SITE  "A11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[10]"  SITE  "T17";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[11]"  SITE  "D18";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[1]"  SITE  "A13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[2]"  SITE  "B10";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[3]"  SITE  "C12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[4]"  SITE  "E12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[5]"  SITE  "D12";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[6]"  SITE  "E11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[7]"  SITE  "D11";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[8]"  SITE  "B13";
+LOCATE  COMP  "hades_drop_cmp_buf_coarse[9]"  SITE  "A12";
+LOCATE  COMP  "hades_drop_cmp_buf_valid"  SITE  "A7";
+LOCATE  COMP  "hades_hit_out_i[0]"  SITE  "E9";
+LOCATE  COMP  "hades_hit_out_i[1]"  SITE  "C11";
+LOCATE  COMP  "hades_hit_out_i[2]"  SITE  "E6";
+LOCATE  COMP  "hades_hit_out_i[3]"  SITE  "D7";
+LOCATE  COMP  "hades_hit_valid[0]"  SITE  "A3";
+LOCATE  COMP  "hades_hit_valid[1]"  SITE  "B5";
+LOCATE  COMP  "hades_hit_valid[2]"  SITE  "A5";
+LOCATE  COMP  "hades_hit_valid[3]"  SITE  "C5";
+LOCATE  COMP  "hades_invalid_dl[0]"  SITE  "V2";
+LOCATE  COMP  "hades_invalid_dl[1]"  SITE  "L5";
+LOCATE  COMP  "hades_invalid_dl[2]"  SITE  "K2";
+LOCATE  COMP  "hades_invalid_dl[3]"  SITE  "K4";
+LOCATE  COMP  "hades_lvl1"  SITE  "E1";
+LOCATE  COMP  "hades_lvl1_invalid"  SITE  "W2";
+LOCATE  COMP  "hades_offset[0]"  SITE  "D10";
+LOCATE  COMP  "hades_offset[1]"  SITE  "C10";
+LOCATE  COMP  "hades_offset[2]"  SITE  "E10";
+LOCATE  COMP  "hades_offset[3]"  SITE  "D1";
+LOCATE  COMP  "hades_offset[4]"  SITE  "C1";
+LOCATE  COMP  "hades_offset[5]"  SITE  "D2";
+LOCATE  COMP  "hades_offset[6]"  SITE  "A2";
+LOCATE  COMP  "hades_offset[7]"  SITE  "B9";
+LOCATE  COMP  "hades_offset[8]"  SITE  "B2";
+LOCATE  COMP  "hades_offset_valid"  SITE  "D15";
+LOCATE  COMP  "hades_raw_out_valid"  SITE  "E15";
+LOCATE  COMP  "hades_raw_valid_vect[0]"  SITE  "U20";
+LOCATE  COMP  "hades_raw_valid_vect[1]"  SITE  "E17";
+LOCATE  COMP  "hades_trig"  SITE  "H5";
+LOCATE  COMP  "hades_window_end"  SITE  "C14";
+LOCATE  COMP  "last_buf_empty"  SITE  "L18";
+LOCATE  COMP  "rd_clk"  SITE  "B12";
+LOCATE  COMP  "release_out"  SITE  "A14";
+LOCATE  COMP  "reset_dc"  SITE  "C8";
+LOCATE  COMP  "trig[0]"  SITE  "R2";
+LOCATE  COMP  "trig[1]"  SITE  "T3";
+LOCATE  COMP  "trig[2]"  SITE  "T19";
+
+#PLL
+LOCATE  COMP  "pll0inst/PLLInst_0"  SITE  "PLL_BL0" ;
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:20:03 2021
+
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_par.html b/impl1/s1_impl1_par.html
new file mode 100644
index 0000000..780e93e
--- /dev/null
+++ b/impl1/s1_impl1_par.html
@@ -0,0 +1,391 @@
+<HTML>
+<HEAD><TITLE>Place & Route Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
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}
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    font-weight:bold;
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    color:#5BAFD4;
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background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Jun 16 09:19:35 2021
+
+/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t
+s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset
+/home/hadaq/mmichalek/lattice/simplified/promote.xml
+
+
+Preference file: s1_impl1.prf.
+
+<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+<span style="background-color:red">5_1   *      0            -2.994       209210       -1.015       9647         48           Completed</span>
+* : Design saved.
+
+Total (real) run time for 1-seed: 48 secs 
+
+par done!
+
+Note: user must run &apos;Trace&apos; for timing closure signoff.
+
+Lattice Place and Route Report for Design &quot;s1_impl1_map.ncd&quot;
+Wed Jun 16 09:19:35 2021
+
+
+<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf
+Preference file: s1_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application par from file &apos;sa5p45m.nph&apos; in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
+
+   PIO (prelim)     187/245          76% used
+                    187/203          92% bonded
+   IOLOGIC           35/245          14% used
+
+   SLICE            692/21924         3% used
+
+   EBR                4/108           3% used
+   PLL                1/4            25% used
+
+
+Number of Signals: 1594
+Number of Connections: 3725
+
+Pin Constraint Summary:
+   7 out of 186 pins locked (3% locked).
+
+The following 5 signals are selected to use the primary clock routing resources:
+    pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
+    pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+    pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0)
+    rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0)
+    pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
+
+
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 8 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 788909.
+Finished Placer Phase 1.  REAL time: 24 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  774601
+Finished Placer Phase 2.  REAL time: 25 secs 
+
+
+
+<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 12 (8%)
+  GR_PCLK    : 0 out of 12 (0%)
+  PLL        : 1 out of 4 (25%)
+  DCS        : 0 out of 2 (0%)
+  DCC        : 0 out of 60 (0%)
+  CLKDIV     : 0 out of 4 (0%)
+
+Quadrant TL Clocks:
+  PRIMARY &quot;pll_clks[0]&quot; from CLKOP on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 12
+  PRIMARY &quot;pll_clks[1]&quot; from CLKOS on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 12
+  PRIMARY &quot;pll_clks[3]&quot; from CLKOS3 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 196
+  PRIMARY &quot;rd_clk_c&quot; from comp &quot;rd_clk&quot; on CLK_PIN site &quot;B12 (PT44A)&quot;, CLK/CE/SR load = 17
+  PRIMARY &quot;pll_clks[2]&quot; from CLKOS2 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 12
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant TR Clocks:
+  PRIMARY &quot;pll_clks[3]&quot; from CLKOS3 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 3
+  PRIMARY &quot;rd_clk_c&quot; from comp &quot;rd_clk&quot; on CLK_PIN site &quot;B12 (PT44A)&quot;, CLK/CE/SR load = 8
+
+  PRIMARY  : 2 out of 16 (12%)
+
+Quadrant BL Clocks:
+  PRIMARY &quot;pll_clks[0]&quot; from CLKOP on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 5
+  PRIMARY &quot;pll_clks[1]&quot; from CLKOS on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 4
+  PRIMARY &quot;pll_clks[3]&quot; from CLKOS3 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 132
+  PRIMARY &quot;rd_clk_c&quot; from comp &quot;rd_clk&quot; on CLK_PIN site &quot;B12 (PT44A)&quot;, CLK/CE/SR load = 4
+  PRIMARY &quot;pll_clks[2]&quot; from CLKOS2 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 4
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Quadrant BR Clocks:
+  PRIMARY &quot;pll_clks[0]&quot; from CLKOP on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 8
+  PRIMARY &quot;pll_clks[1]&quot; from CLKOS on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 8
+  PRIMARY &quot;pll_clks[3]&quot; from CLKOS3 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 115
+  PRIMARY &quot;rd_clk_c&quot; from comp &quot;rd_clk&quot; on CLK_PIN site &quot;B12 (PT44A)&quot;, CLK/CE/SR load = 9
+  PRIMARY &quot;pll_clks[2]&quot; from CLKOS2 on comp &quot;pll0inst/PLLInst_0&quot; on PLL site &quot;PLL_BL0&quot;, CLK/CE/SR load = 8
+
+  PRIMARY  : 5 out of 16 (31%)
+
+Edge Clocks:
+
+  No edge clock selected.
+
+
+
+
+
++
+I/O Usage Summary (final):
+   187 out of 245 (76.3%) PIO sites used.
+   187 out of 203 (92.1%) bonded PIO sites used.
+   Number of PIO comps: 186; differential: 1.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 27 / 27 (100%) | 2.5V       | -          | -          |
+| 1        | 29 / 33 ( 87%) | 2.5V       | -          | -          |
+| 2        | 31 / 32 ( 96%) | 2.5V       | -          | -          |
+| 3        | 27 / 33 ( 81%) | 2.5V       | -          | -          |
+| 6        | 28 / 33 ( 84%) | 2.5V       | -          | -          |
+| 7        | 32 / 32 (100%) | 2.5V       | -          | -          |
+| 8        | 13 / 13 (100%) | 2.5V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 24 secs 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+0 connections routed; 3725 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 39 secs 
+
+Start NBR router at Wed Jun 16 09:20:14 CEST 2021
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021
+
+Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021
+Level 1, iteration 1
+21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.876ns/-158.654ns; real time: 41 secs 
+Level 2, iteration 1
+46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-159.217ns; real time: 41 secs 
+Level 3, iteration 1
+167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.962ns/-163.305ns; real time: 42 secs 
+Level 4, iteration 1
+81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-177.384ns; real time: 42 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021
+Level 1, iteration 1
+53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-171.398ns; real time: 43 secs 
+Level 4, iteration 1
+54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 2
+35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-180.675ns; real time: 43 secs 
+Level 4, iteration 3
+24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 4
+12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.068ns; real time: 43 secs 
+Level 4, iteration 5
+8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.304ns; real time: 43 secs 
+Level 4, iteration 6
+5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.304ns; real time: 44 secs 
+Level 4, iteration 7
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 8
+1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.750ns; real time: 44 secs 
+Level 4, iteration 9
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-173.131ns; real time: 44 secs 
+
+Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: -2.994ns/-172.896ns; real time: 44 secs 
+
+Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 156 (4.19%)
+  Estimated worst slack&lt;setup&gt; : -2.994ns
+  Timing score&lt;setup&gt; : 209210
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 46 secs 
+Total REAL time: 47 secs 
+Completely routed.
+End of route.  3725 routed (100.00%); 0 unrouted.
+
+Generating &quot;par&quot; statistics.
+
+
+   The Delay Summary Report
+
+   The SCORE FOR THIS DESIGN is: 284326
+
+
+   The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
+
+   The AVERAGE CONNECTION DELAY for this design is:          0.79 (  0.79)
+   The AVERAGE CONNECTION DELAY on CRITICAL NETS is:         0.00 (  0.00)
+   The CLOCK SKEW AVERAGE for this design is:                0.03
+   The MAXIMUM PIN DELAY IS:                                 4.32 (  4.32)
+   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:     3.37 (  3.37)
+
+   Listing Pin Delays by value: (nsec)
+
+    d &lt;= 10    &lt; d &lt;= 20   &lt; d &lt;= 30   &lt; d &lt;= 40   &lt; d &lt;= 50    d &gt; 50
+   ---------   ---------   ---------   ---------   ---------   ---------
+        3725           0           0           0           0           0
+
+Hold time timing score: 9, hold timing errors: 18
+
+
+Timing score: 209210 
+
+Dumping design to file s1_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = -2.994
+PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 209.210
+PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = -1.015
+PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 9.647
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 48 secs 
+Total REAL time to completion: 48 secs 
+
+par done!
+
+Note: user must run &apos;Trace&apos; for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_scck.rpt b/impl1/s1_impl1_scck.rpt
new file mode 100644
index 0000000..5daaa5a
--- /dev/null
+++ b/impl1/s1_impl1_scck.rpt
@@ -0,0 +1,70 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+
+# Written on Wed Jun 16 09:19:17 2021
+
+##### FILES SYNTAX CHECKED ##############################################
+Constraint File(s):      (none)
+
+#Run constraint checker to find more issues with constraints.
+#########################################################################
+
+
+
+No issues found in constraint syntax.
+
+
+
+Clock Summary
+*************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+Clock Load Summary
+******************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
diff --git a/impl1/s1_impl1_scck.rpt.db b/impl1/s1_impl1_scck.rpt.db
new file mode 100644
index 0000000..33612a2
Binary files /dev/null and b/impl1/s1_impl1_scck.rpt.db differ
diff --git a/impl1/s1_impl1_summary.html b/impl1/s1_impl1_summary.html
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index 0000000..a6e896e
--- /dev/null
+++ b/impl1/s1_impl1_summary.html
@@ -0,0 +1,83 @@
+<HTML>
+<HEAD><TITLE>Project Summary</TITLE>
+<STYLE TYPE="text/css">
+<!--
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+<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
+<TR>
+<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>s1 project summary</B></SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">s1</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LFE5UM5G-45F-8BG381C</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">ECP5UM5G</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LFE5UM5G-45F</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">CABGA381</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">8</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">s1.lpf</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/s1_impl1.prf</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.2.446</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2021/06/16 12:37:07</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">/home/hadaq/mmichalek/lattice/simplified/impl1</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">/home/hadaq/mmichalek/lattice/simplified/s1.ldf</SPAN></TD>
+</TR>
+</small></TABLE>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
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+<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Jun 16 09:19:13 2021
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
+Premap Report
+
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Jun 16 09:19:25 2021
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS2_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS3_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: top_tf|rd_clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_synplify.lpf b/impl1/s1_impl1_synplify.lpf
new file mode 100644
index 0000000..fda6a86
--- /dev/null
+++ b/impl1/s1_impl1_synplify.lpf
@@ -0,0 +1,45 @@
+#
+# Logical Preferences generated for Lattice by Synplify maprc, Build 4745R.
+#
+
+# Period Constraints 
+#FREQUENCY NET "pll0inst/pll_clks[3]" 200.0 MHz;
+#FREQUENCY NET "pll0inst/pll_clks[0]" 200.0 MHz;
+#FREQUENCY NET "pll0inst/pll_clks[1]" 200.0 MHz;
+#FREQUENCY NET "pll0inst/pll_clks[2]" 200.0 MHz;
+#FREQUENCY PORT "rd_clk" 200.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[2]";
+#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[1]";
+#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[0]";
+#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[3]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "rd_clk_c";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[1]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[0]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[3]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "rd_clk_c";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[2]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[0]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[3]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "rd_clk_c";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[2]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[1]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[3]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "rd_clk_c";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[2]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[1]";
+#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[0]";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.
diff --git a/impl1/s1_impl1_synplify.tcl b/impl1/s1_impl1_synplify.tcl
new file mode 100644
index 0000000..bb23f2b
--- /dev/null
+++ b/impl1/s1_impl1_synplify.tcl
@@ -0,0 +1,84 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file
+
+#device options
+set_option -technology ECP5UM5G
+set_option -part LFE5UM5G_45F
+set_option -package BG381C
+set_option -speed_grade -8
+
+#compilation/mapping options
+set_option -symbolic_fsm_compiler true
+set_option -resource_sharing false
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 200
+set_option -maxfan 1000
+set_option -auto_constrain_io 0
+set_option -disable_io_insertion false
+set_option -retiming false; set_option -pipe true
+set_option -force_gsr auto
+set_option -compiler_compatible 0
+set_option -dup false
+
+set_option -default_enum_encoding default
+
+#simulation options
+
+
+#timing analysis options
+set_option -num_critical_paths 3
+
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#synplifyPro options
+set_option -fix_gated_and_generated_clocks 1
+set_option -update_models_cp 0
+set_option -resolve_multiple_driver 0
+
+
+
+#-- add_file options
+set_option -hdl_define -set SBP_SYNTHESIS
+set_option -include_path {/home/hadaq/mmichalek/lattice/simplified}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd}
+add_file -verilog {/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/modules2.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/top2.v}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd}
+add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/hades_modules.v}
+add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v}
+
+#-- top module name
+set_option -top_module top_tf
+
+#-- set result format/file last
+project -result_file {/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi}
+
+#-- error message log file
+project -log_file {s1_impl1.srf}
+
+#-- set any command lines input by customer
+
+
+#-- run Synplify with 'arrange HDL file'
+project -run hdl_info_gen -fileorder
+project -run
diff --git a/impl1/s1_impl1_synplify_tmp2.lpf b/impl1/s1_impl1_synplify_tmp2.lpf
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/s1_impl1_synplify_tmp4.lpf b/impl1/s1_impl1_synplify_tmp4.lpf
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/s1_impl1_synplify_tmp8.lpf b/impl1/s1_impl1_synplify_tmp8.lpf
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/s1_impl1_trce.asd b/impl1/s1_impl1_trce.asd
new file mode 100644
index 0000000..cf448ab
--- /dev/null
+++ b/impl1/s1_impl1_trce.asd
@@ -0,0 +1,23 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Fmax_0 = - (-);
+Fmax_1 = 158.003 MHz (300.000 MHz);
+Fmax_2 = 562.430 MHz (300.000 MHz);
+Fmax_3 = 562.430 MHz (300.000 MHz);
+Fmax_4 = 562.430 MHz (300.000 MHz);
+Fmax_5 = 370.096 MHz (100.000 MHz);
+Fmax_6 = 562.430 MHz (300.000 MHz);
+Failed = 1 (Total 7);
+Clock_ports = 2;
+Clock_nets = 6;
+; Hold Analysis
+Fmax_0 = - (-);
+Fmax_1 = -1.015 ns (0.000 ns);
+Fmax_2 = 0.157 ns (0.000 ns);
+Fmax_3 = 0.157 ns (0.000 ns);
+Fmax_4 = 0.157 ns (0.000 ns);
+Fmax_5 = - (-);
+Fmax_6 = - (-);
+Failed = 1 (Total 7);
+Clock_ports = 2;
+Clock_nets = 6;
diff --git a/impl1/s1_impl1_tw1.html b/impl1/s1_impl1_tw1.html
new file mode 100644
index 0000000..a3a6db9
--- /dev/null
+++ b/impl1/s1_impl1_tw1.html
@@ -0,0 +1,743 @@
+<HTML>
+<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
+
+Loading design for application trce from file s1_impl1_map.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446</big></U></B>
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
+
+<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<FONT COLOR=red><LI><A href='#map_twr_pref_0_1' Target='right'><FONT COLOR=red>FREQUENCY NET "pll_clks[3]" 300.000000 MHz (78 errors)</FONT></A></LI>
+</FONT>            3875 items scored, 78 timing errors detected.
+Warning: 181.028MHz is the maximum frequency for this preference.
+
+<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#map_twr_pref_0_4' Target='right'>FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#map_twr_pref_0_5' Target='right'>FREQUENCY PORT "clk" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+Report:  370.096MHz is the maximum frequency for this preference.
+
+<LI><A href='#map_twr_pref_0_6' Target='right'>FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 78 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.095ns (weighted slack = -2.190ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.537ns  (44.3% logic, 55.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      2.537ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.095ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.CLK to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5   e 0.156 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+C1TOFCO_DE  ---     0.278 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
+ROUTE         1   e 0.001 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
+FCITOF1_DE  ---     0.273 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.537   (44.3% logic, 55.7% route), 5 logic levels.
+
+Warning: 181.028MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="map_twr_pref_0_4"></A>Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.722ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      3.333ns delay constraint less
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="map_twr_pref_0_5"></A>Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.298ns
+         The internal maximum frequency of the following component is 370.096 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
+
+   Delay:               2.702ns -- based on Minimum Pulse Width
+
+Report:  370.096MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="map_twr_pref_0_6"></A>Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  181.028 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/valid_fast                        |       5|      48|     61.54%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_2_0                |      10|      46|     58.97%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_1_0_S1           |       1|      33|     42.31%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window_6[2]                       |       1|      33|     42.31%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_0                |       1|      21|     26.92%
+                                        |        |        |
+valid_fast_RNI999V                      |       9|      18|     23.08%
+                                        |        |        |
+hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
+_inst.offset_1_sqmuxa_i_0               |      11|      18|     23.08%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_4                |       1|      15|     19.23%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_cry_2                |       1|      15|     19.23%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_reset_0_a2_c                  |       7|      14|     17.95%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/N_97                              |       3|      14|     17.95%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/discard4_0_a2_0_3                 |       3|      12|     15.38%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/un1_window_8_s_7_0_S0             |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/window_6[7]                       |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/G_25_0_a3_5_0                     |       1|       8|     10.26%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+_inst/G_25_0_a3_4_0                     |       1|       8|     10.26%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
+---------------
+
+Timing errors: 78  Score: 41485
+Cumulative negative slack: 24538
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446</big></U></B>
+Wed Jun 16 09:19:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
+------------------
+Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
+Design file:     s1_impl1_map.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
+
+<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY NET "pll_clks[3]" 300.000000 MHz (0 errors)</A></LI>            3875 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_4' Target='right'>FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_5' Target='right'>FREQUENCY PORT "clk" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<LI><A href='#map_twr_pref_1_6' Target='right'>FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]  (from pll_clks[3] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]  (to pll_clks[3] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (from pll_clks[3])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] (to pll_clks[3])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+<A name="map_twr_pref_1_4"></A>Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.096ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
+
+
+================================================================================
+<A name="map_twr_pref_1_5"></A>Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="map_twr_pref_1_6"></A>Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.096 ns|   1  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
+---------------
+
+Timing errors: 78 (setup), 0 (hold)
+Score: 41485 (setup), 0 (hold)
+Cumulative negative slack: 24538 (24538+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
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+<BR>
+<BR>
+<BR>
+<BR>
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+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
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+<BR>
+<BR>
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+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_twr.html b/impl1/s1_impl1_twr.html
new file mode 100644
index 0000000..d6ea0cc
--- /dev/null
+++ b/impl1/s1_impl1_twr.html
@@ -0,0 +1,4240 @@
+<HTML>
+<HEAD><TITLE>Lattice TRACE Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
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    font-size:78%;
}
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{
    border-width: 1px 1px 1px 1px;
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    padding: 4px;
    border-width: 1px 1px 1px 1px;
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    font-size:78%;
}
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    padding: 4px;
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    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
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a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
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{
background-color: #00ff00;
}
.fail
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background-color: #ff0000;
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.comment
{
    font-size: 90%;
    font-style: italic;
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+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
+
+Loading design for application trce from file s1_impl1.ncd.
+Design name: top_tf
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LFE5UM5G-45F
+Package:     CABGA381
+Performance: 8
+Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Performance Hardware Data Status:   Final          Version 55.1.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446</big></U></B>
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,8
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
+
+<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<FONT COLOR=red><LI><A href='#par_twr_pref_0_1' Target='right'><FONT COLOR=red>FREQUENCY NET "pll_clks[3]" 300.000000 MHz (280 errors)</FONT></A></LI>
+</FONT>            3875 items scored, 280 timing errors detected.
+Warning: 158.003MHz is the maximum frequency for this preference.
+
+<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#par_twr_pref_0_4' Target='right'>FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<LI><A href='#par_twr_pref_0_5' Target='right'>FREQUENCY PORT "clk" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+Report:  370.096MHz is the maximum frequency for this preference.
+
+<LI><A href='#par_twr_pref_0_6' Target='right'>FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+Report:  562.430MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 280 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.497ns (weighted slack = -2.994ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.939ns  (38.2% logic, 61.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      2.939ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.000ns skew and
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.497ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10     0.731     R29C37C.F0 to     R31C37A.A1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+C1TOFCO_DE  ---     0.278     R31C37A.A1 to    R31C37A.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
+ROUTE         1     0.000    R31C37A.FCO to    R31C37B.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
+FCITOF1_DE  ---     0.273    R31C37B.FCI to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.939   (38.2% logic, 61.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.396ns (weighted slack = -2.792ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
+
+   Delay:               3.050ns  (22.0% logic, 78.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.050ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.396ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.050   (22.0% logic, 78.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.387ns (weighted slack = -2.774ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
+
+   Delay:               3.041ns  (22.0% logic, 78.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.041ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.387ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.041   (22.0% logic, 78.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
+
+   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
+
+   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.354ns (weighted slack = -2.708ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
+
+   Delay:               3.008ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.008ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.354ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.008   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
+
+   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
+
+   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.345ns (weighted slack = -2.690ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
+
+   Delay:               2.999ns  (22.3% logic, 77.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      2.999ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
+      1.667ns delay constraint less
+     -0.063ns skew and
+      0.076ns RST_SET requirement (totaling 1.654ns) by 1.345ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
+ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
+CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
+ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
+                  --------
+                    2.999   (22.3% logic, 77.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
+                  --------
+                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.337ns (weighted slack = -2.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
+
+   Delay:               2.779ns  (34.7% logic, 65.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      2.779ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
+      1.667ns delay constraint less
+      0.000ns skew and
+      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.337ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
+ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
+CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
+ROUTE        10     0.730     R29C37C.F0 to     R31C37B.B0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
+CTOF1_DEL   ---     0.392     R31C37B.B0 to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
+ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
+CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
+ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
+                  --------
+                    2.779   (34.7% logic, 65.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 158.003MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.251      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.251     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C6B.CLK to      R28C6B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (from pll_clks[2])
+ROUTE         1     0.251      R28C6B.Q0 to      R28C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.251     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C51D.CLK to     R66C51D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (from pll_clks[2])
+ROUTE         1     0.251     R66C51D.Q0 to     R66C51A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C14B.CLK to     R68C14B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (from pll_clks[2])
+ROUTE         1     0.251     R68C14B.Q0 to     R68C14A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R25C5D.CLK to      R25C5D.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (from pll_clks[2])
+ROUTE         1     0.251      R25C5D.Q0 to      R25C5A.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.251     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C41B.CLK to     R66C41B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (from pll_clks[2])
+ROUTE         1     0.251     R66C41B.Q0 to     R66C41A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41B.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C3D.CLK to      R29C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 (from pll_clks[2])
+ROUTE         1     0.251      R29C3D.Q0 to      R29C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] (to pll_clks[2])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3D.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3A.CLK pll_clks[2]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.685ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.765ns  (40.4% logic, 59.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.765ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.685ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C16C.CLK to     R68C16C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1     0.456     R68C16C.Q0 to     R68C16A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.765   (40.4% logic, 59.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.840ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.610ns  (50.5% logic, 49.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.610ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.840ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.308    R68C16C.CLK to     R68C16C.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
+ROUTE         1     0.302     R68C16C.Q1 to     R68C16C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.610   (50.5% logic, 49.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.251      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.251     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C6D.CLK to      R29C6D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 (from pll_clks[1])
+ROUTE         1     0.251      R29C6D.Q0 to      R29C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C14D.CLK to     R68C14D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (from pll_clks[1])
+ROUTE         1     0.251     R68C14D.Q0 to     R68C14C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C50C.CLK to     R66C50C.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (from pll_clks[1])
+ROUTE         1     0.251     R66C50C.Q0 to     R66C50B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.251      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C5C.CLK to      R28C5C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (from pll_clks[1])
+ROUTE         1     0.251      R28C5C.Q0 to      R28C5A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5A.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.251     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="par_twr_pref_0_4"></A>Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.251      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.251     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R28C4D.CLK to      R28C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (from pll_clks[0])
+ROUTE         1     0.251      R28C4D.Q0 to      R28C4C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.251     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C52D.CLK to     R66C52D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (from pll_clks[0])
+ROUTE         1     0.251     R66C52D.Q0 to     R66C52A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R68C15C.CLK to     R68C15C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (from pll_clks[0])
+ROUTE         1     0.251     R68C15C.Q0 to     R68C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R25C5B.CLK to      R25C5B.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (from pll_clks[0])
+ROUTE         1     0.251      R25C5B.Q0 to      R25C5C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.309    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.251     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290    R66C43D.CLK to     R66C43D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (from pll_clks[0])
+ROUTE         1     0.251     R66C43D.Q0 to     R66C43A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43D.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 2.890ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
+
+   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 meets
+      3.333ns delay constraint less
+      0.000ns skew and
+     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.290     R29C3B.CLK to      R29C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 (from pll_clks[0])
+ROUTE         1     0.251      R29C3B.Q0 to      R29C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] (to pll_clks[0])
+                  --------
+                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3B.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
+                  --------
+                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="par_twr_pref_0_5"></A>Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.298ns
+         The internal maximum frequency of the following component is 370.096 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
+
+   Delay:               2.702ns -- based on Minimum Pulse Width
+
+Report:  370.096MHz is the maximum frequency for this preference.
+
+
+================================================================================
+<A name="par_twr_pref_0_6"></A>Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.555ns
+         The internal maximum frequency of the following component is 562.430 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
+
+   Delay:               1.778ns -- based on Minimum Pulse Width
+
+Report:  562.430MHz is the maximum frequency for this preference.
+
+<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  158.003 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97">_inst/N_97</a>                              |       3|     141|     50.36%
+                                        |        |        |
+hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
+_inst.offset_1_sqmuxa_i_0               |      11|     130|     46.43%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3">_inst/discard4_0_a2_0_3</a>                 |       3|     122|     43.57%
+                                        |        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=valid_fast_RNI999V">valid_fast_RNI999V</a>                      |       9|      82|     29.29%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast">_inst/valid_fast</a>                        |       5|      82|     29.29%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0">_inst/un1_reset_0_a2_2_0</a>                |      10|      66|     23.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c">_inst/un1_reset_0_a2_c</a>                  |       7|      52|     18.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7]">_inst/window[7]</a>                         |       3|      45|     16.07%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5]">_inst/window[5]</a>                         |       3|      45|     16.07%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4">_inst/un1_window_8_cry_4</a>                |       1|      44|     15.71%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]">_inst/window_6[2]</a>                       |       1|      44|     15.71%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1">_inst/un1_window_8_cry_1_0_S1</a>           |       1|      43|     15.36%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2">_inst/un1_window_8_cry_2</a>                |       1|      38|     13.57%
+                                        |        |        |
+hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
+<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0">_inst/un1_window_8_cry_0</a>                |       1|      33|     11.79%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
+---------------
+
+Timing errors: 280  Score: 209210
+Cumulative negative slack: 139580
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+--------------------------------------------------------------------------------
+<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446</big></U></B>
+Wed Jun 16 09:20:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
+------------------
+Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
+Design file:     s1_impl1.ncd
+Preference file: s1_impl1.prf
+Device,speed:    LFE5UM5G-45F,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
+
+<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<FONT COLOR=red><LI><A href='#par_twr_pref_1_1' Target='right'><FONT COLOR=red>FREQUENCY NET "pll_clks[3]" 300.000000 MHz (18 errors)</FONT></A></LI>
+</FONT>            3875 items scored, 18 timing errors detected.
+
+<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#par_twr_pref_1_4' Target='right'>FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)</A></LI>            24 items scored, 0 timing errors detected.
+
+<LI><A href='#par_twr_pref_1_5' Target='right'>FREQUENCY PORT "clk" 100.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+<LI><A href='#par_twr_pref_1_6' Target='right'>FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)</A></LI>            0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+            3875 items scored, 18 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 1.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.328ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R29C3C.CLK to      R29C3C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 (from pll_clks[0])
+ROUTE         1     0.195      R29C3C.Q0 to      R30C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] (to pll_clks[3])
+                  --------
+                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R30C3B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 1.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.328ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R68C15A.CLK to     R68C15A.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (from pll_clks[0])
+ROUTE         1     0.195     R68C15A.Q0 to     R66C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 1.000ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.343ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.000ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R25C5C.CLK to      R25C5C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (from pll_clks[0])
+ROUTE         1     0.210      R25C5C.Q0 to      R25C8C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.939ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.404ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.939ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R28C4C.CLK to      R28C4C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (from pll_clks[0])
+ROUTE         1     0.271      R28C4C.Q0 to      R27C6B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R27C6B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.928ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.415ns  (32.0% logic, 68.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.415ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.928ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C52A.CLK to     R66C52A.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (from pll_clks[0])
+ROUTE         1     0.282     R66C52A.Q0 to     R66C47D.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.415   (32.0% logic, 68.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.914ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
+
+   Delay:               0.429ns  (31.0% logic, 69.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.429ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
+      0.093ns M_HLD and
+      0.000ns delay constraint less
+     -1.250ns skew less
+      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.914ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C43A.CLK to     R66C43A.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (from pll_clks[0])
+ROUTE         1     0.296     R66C43A.Q0 to     R66C39B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
+                  --------
+                    0.429   (31.0% logic, 69.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
+                  --------
+                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.588ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.340ns  (39.1% logic, 60.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.340ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.588ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C41C.CLK to     R66C41C.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (from pll_clks[1])
+ROUTE         1     0.207     R66C41C.Q0 to     R66C39B.M1 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.340   (39.1% logic, 60.9% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C41C.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.585ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.343ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.585ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R66C50B.CLK to     R66C50B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (from pll_clks[1])
+ROUTE         1     0.210     R66C50B.Q0 to     R66C47D.M1 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.353ns  (37.7% logic, 62.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.353ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.575ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R25C4A.CLK to      R25C4A.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (from pll_clks[1])
+ROUTE         1     0.220      R25C4A.Q0 to      R25C8C.M1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.353   (37.7% logic, 62.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C4A.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+Error: The following path exceeds requirements by 0.524ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
+
+   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.404ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
+      0.094ns M_HLD and
+      0.000ns delay constraint less
+     -0.834ns skew less
+      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.524ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R68C14C.CLK to     R68C14C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (from pll_clks[1])
+ROUTE         1     0.271     R68C14C.Q0 to     R66C15A.M1 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
+                  --------
+                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
+                  --------
+                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
+
+      Source Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
+ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
+CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
+ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
+                  --------
+                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
+
+      Destination Clock f/b:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
+ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
+                  --------
+                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
+
+
+================================================================================
+<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C52B.CLK to     R66C52B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.119     R66C52B.Q1 to     R66C52B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R68C15B.CLK to     R68C15B.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.119     R68C15B.Q1 to     R68C15B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C3B.CLK to      R28C3B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.119      R28C3B.Q1 to      R28C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C42D.CLK to     R66C42D.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.119     R66C42D.Q1 to     R66C42D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C4B.CLK to      R25C4B.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (from pll_clks[2])
+ROUTE         1     0.119      R25C4B.Q1 to      R25C4B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C5B.CLK to      R29C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 (from pll_clks[2])
+ROUTE         1     0.119      R29C5B.Q1 to      R29C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] (to pll_clks[2])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
+ROUTE         1     0.119     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
+ROUTE         1     0.119      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
+ROUTE         1     0.119     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
+ROUTE         1     0.119     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C3C.CLK to      R25C3C.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.119      R25C3C.Q1 to      R25C3C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C44B.CLK to     R66C44B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.119     R66C44B.Q1 to     R66C44B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C4D.CLK to      R29C4D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
+ROUTE         1     0.119      R29C4D.Q1 to      R29C4D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C51B.CLK to     R66C51B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.119     R66C51B.Q1 to     R66C51B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C3D.CLK to      R28C3D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.119      R28C3D.Q1 to      R28C3D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
+ROUTE         1     0.119     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
+ROUTE         1     0.119      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
+ROUTE         1     0.119      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R29C4D.CLK to      R29C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
+ROUTE         1     0.119      R29C4D.Q0 to      R29C4A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4A.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
+ROUTE         1     0.119     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+<A name="par_twr_pref_1_4"></A>Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+            24 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C49B.CLK to     R66C49B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.119     R66C49B.Q1 to     R66C49B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R68C16D.CLK to     R68C16D.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.119     R68C16D.Q1 to     R68C16D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R28C5B.CLK to      R28C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.119      R28C5B.Q1 to      R28C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141    R66C43B.CLK to     R66C43B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.119     R66C43B.Q1 to     R66C43B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R25C6D.CLK to      R25C6D.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (from pll_clks[0])
+ROUTE         1     0.119      R25C6D.Q1 to      R25C6D.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.157ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
+
+   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.141     R29C4B.CLK to      R29C4B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 (from pll_clks[0])
+ROUTE         1     0.119      R29C4B.Q1 to      R29C4B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] (to pll_clks[0])
+                  --------
+                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
+ROUTE         1     0.119     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
+ROUTE         1     0.119      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
+ROUTE         1     0.119     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
+   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
+
+   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
+      0.103ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
+
+ Physical Path Details:
+
+      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.142    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
+ROUTE         1     0.119     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
+                  --------
+                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
+                  --------
+                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+<A name="par_twr_pref_1_5"></A>Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+<A name="par_twr_pref_1_6"></A>Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|    -1.015 ns|   1 *
+                                        |             |             |
+FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
+MHz ;                                   |     0.000 ns|     0.157 ns|   1  
+                                        |             |             |
+FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY NET "pll_clks*" 300.000000    |             |             |
+MHz ;                                   |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+No net is responsible for more than 10% of the timing errors.
+
+
+<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
+------------------------
+
+Found 6 clocks:
+
+Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
+   No transfer within this clock domain is found
+
+Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
+   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
+
+   Data transfers from:
+   Clock Domain: rd_clk_c   Source: rd_clk.PAD
+      Not reported because source and destination domains are unrelated.
+
+   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
+      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
+
+Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
+   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
+
+Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
+   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
+
+Clock Domain: clk_c   Source: clk.PAD   Loads: 1
+   No transfer within this clock domain is found
+
+
+<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
+---------------
+
+Timing errors: 18  Score: 9647
+Cumulative negative slack: 9647
+
+Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
+
+
+
+<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
+---------------
+
+Timing errors: 280 (setup), 18 (hold)
+Score: 209210 (setup), 9647 (hold)
+Cumulative negative slack: 149227 (139580+9647)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/s1_impl1_vho.sdf b/impl1/s1_impl1_vho.sdf
new file mode 100644
index 0000000..f5b641c
--- /dev/null
+++ b/impl1/s1_impl1_vho.sdf
@@ -0,0 +1,26828 @@
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "top_tf")
+  (DATE "Wed Jun 16 09:20:42 2021")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.11.2.446")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_79")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_79I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_80")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_80I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_81")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_81I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_82")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_82I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_83")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_83I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_85")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_85I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_86")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_86I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_87")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_87I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_88")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_88I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_89")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_89I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_90")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_90I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_91")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_91I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_92")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_92I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_93")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_93I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_94")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_94I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_95")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_95I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_96")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_96I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_97")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_97I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_98")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_98I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_99")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_99I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_100")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_100I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_101")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_101I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_102")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_102I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_103")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_103I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_104")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_104I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F1 (352:372:392)(352:372:392))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F1 (352:372:392)(352:372:392))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F1 (352:372:392)(352:372:392))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_118")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_118I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_119")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_119I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_120")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_120I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 FCO (112:195:278)(112:195:278))
+        (IOPATH C1 FCO (112:195:278)(112:195:278))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH D0 FCO (112:195:278)(112:195:278))
+        (IOPATH C0 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_121")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_121I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_122")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_122I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_123")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_123I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_124")
+    (INSTANCE trb_adapter_inst_SLICE_124I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_125")
+    (INSTANCE fifo_colector_inst_SLICE_125I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_126")
+    (INSTANCE fifo_colector_inst_SLICE_126I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_127")
+    (INSTANCE fifo_colector_inst_SLICE_127I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_128")
+    (INSTANCE fifo_colector_inst_SLICE_128I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_129")
+    (INSTANCE fifo_colector_inst_SLICE_129I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_130")
+    (INSTANCE fifo_colector_inst_SLICE_130I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_131")
+    (INSTANCE fifo_colector_inst_SLICE_131I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_132")
+    (INSTANCE fifo_colector_inst_SLICE_132I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_133")
+    (INSTANCE fifo_colector_inst_SLICE_133I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_134")
+    (INSTANCE fifo_colector_inst_SLICE_134I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_135")
+    (INSTANCE fifo_colector_inst_SLICE_135I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_136")
+    (INSTANCE fifo_colector_inst_SLICE_136I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_137")
+    (INSTANCE fifo_colector_inst_SLICE_137I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_138")
+    (INSTANCE fifo_colector_inst_SLICE_138I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_139")
+    (INSTANCE fifo_colector_inst_SLICE_139I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_140")
+    (INSTANCE fifo_colector_inst_SLICE_140I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_141")
+    (INSTANCE fifo_colector_inst_SLICE_141I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_142")
+    (INSTANCE fifo_colector_inst_SLICE_142I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_143")
+    (INSTANCE fifo_colector_inst_SLICE_143I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_144")
+    (INSTANCE fifo_colector_inst_SLICE_144I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_145")
+    (INSTANCE fifo_colector_inst_SLICE_145I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_146")
+    (INSTANCE fifo_colector_inst_SLICE_146I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_147")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_147I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_148")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_148I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_149")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_149I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_150")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_150I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_151")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_151I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_152")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_152I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_153")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_153I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_154")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_154I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_155")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_155I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_156")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_156I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_157")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_157I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_158")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_158I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_159")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_159I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_160")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_160I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_161")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_161I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_162")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_162I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_163")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_163I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_164")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_164I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_165")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_165I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_166")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_166I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_167")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_167I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_168")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_168I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_169")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_169I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_170")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_170I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_171")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_171I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_172")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_172I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_173")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_173I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_174")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_174I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_175")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_175I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_176")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_176I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_177")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_177I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_178")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_178I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_179")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_179I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_180")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_180I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_181")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_181I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_182")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_182I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_183")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_183I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_184")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_184I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_185")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_185I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_186")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_186I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_187")
+    (INSTANCE fifo_colector_inst_SLICE_187I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_188")
+    (INSTANCE trb_adapter_inst_SLICE_188I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_189")
+    (INSTANCE fifo_colector_inst_SLICE_189I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_190")
+    (INSTANCE fifo_colector_inst_SLICE_190I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_SLICE_246")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_SLICE_326")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_SLICE_406")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_432")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_432I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_433")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_433I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_434")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_434I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_435")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_435I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_436")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_436I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_437")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_437I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_438")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_438I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_439")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_439I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_440")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_440I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_441")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_441I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_442")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_442I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_443")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_443I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_445")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_445I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_446")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_446I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_447")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_447I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_448")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_448I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_449")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_449I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_450")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_450I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_451")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_451I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_452")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_452I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_453")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_453I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_454")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_454I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_455")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_455I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_456")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_456I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_457")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_457I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_458")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_458I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_459")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_459I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_460")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_460I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (negedge CLK) (-148:-148:-148)(148:156:164))
+      (SETUPHOLD DI0 (negedge CLK) (-148:-148:-148)(148:156:164))
+      (SETUPHOLD LSR (negedge CLK) (165:204:243)(-165:-151:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+        (IOPATH CLK Q1 (237:263:289)(237:263:289))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164))
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_628")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_628I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_631")
+    (INSTANCE trb_adapter_inst_SLICE_631I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_632")
+    (INSTANCE trb_adapter_inst_SLICE_632I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_633")
+    (INSTANCE trb_adapter_inst_SLICE_633I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_648")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_648I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_649")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_649I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A1 OFX0 (156:197:239)(156:197:239))
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_653")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_653I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH C0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH B0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH A0 OFX0 (156:197:239)(156:197:239))
+        (IOPATH M0 OFX0 (113:132:151)(113:132:151))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_654")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_654I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_673")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_673I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_674")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_674I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_675")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_675I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_676")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_676I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_677")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_677I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_678")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_678I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_679")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_679I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_680")
+    (INSTANCE fifo_colector_inst_SLICE_680I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_681")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_681I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_683")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_683I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_691")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_691I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_692")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_692I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_693")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_693I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_698")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_698I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_701")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_701I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_702")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_702I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_703")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_703I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_710")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_710I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (119:130:141)(119:130:141))
+        (IOPATH C1 F1 (119:130:141)(119:130:141))
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_SLICE_711")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_SLICE_714")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_SLICE_717")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+      (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_720")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_720I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_721")
+    (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_721I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_SLICE_722")
+    (INSTANCE fifo_colector_inst_SLICE_722I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_723")
+    (INSTANCE trb_adapter_inst_SLICE_723I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "trb_adapter_inst_SLICE_724")
+    (INSTANCE trb_adapter_inst_SLICE_724I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732")
+    (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (239:264:290)(239:264:290))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739")
+    (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_740")
+    (INSTANCE SLICE_740I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_tdc_bundle_inst_SLICE_741")
+    (INSTANCE hades_tdc_bundle_inst_SLICE_741I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_743")
+    (INSTANCE SLICE_743I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_744")
+    (INSTANCE SLICE_744I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_745")
+    (INSTANCE SLICE_745I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_746")
+    (INSTANCE SLICE_746I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_747")
+    (INSTANCE SLICE_747I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_raw_valid_vect_0_B")
+    (INSTANCE hades_raw_valid_vect_0_I)
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_0_B")
+    (INSTANCE fifo_data_out_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "clkB")
+    (INSTANCE clkI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH clkS PADDI (437:437:437)(437:437:437))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge clkS) (1250:1250:1250))
+      (WIDTH (negedge clkS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_validB")
+    (INSTANCE hades_drop_cmp_buf_validI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufvalid (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_11_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_11_I)
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_10_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_10_I)
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_9_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse9 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_8_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_7_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_6_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_5_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_4_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_3_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_2_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_1_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_coarse_0_B")
+    (INSTANCE hades_drop_cmp_buf_coarse_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbufcoarse0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_11_B")
+    (INSTANCE hades_drop_cmp_buf_11_I)
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_10_B")
+    (INSTANCE hades_drop_cmp_buf_10_I)
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_9_B")
+    (INSTANCE hades_drop_cmp_buf_9_I)
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_8_B")
+    (INSTANCE hades_drop_cmp_buf_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_7_B")
+    (INSTANCE hades_drop_cmp_buf_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_6_B")
+    (INSTANCE hades_drop_cmp_buf_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_5_B")
+    (INSTANCE hades_drop_cmp_buf_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_4_B")
+    (INSTANCE hades_drop_cmp_buf_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_3_B")
+    (INSTANCE hades_drop_cmp_buf_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_2_B")
+    (INSTANCE hades_drop_cmp_buf_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_1_B")
+    (INSTANCE hades_drop_cmp_buf_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_drop_cmp_buf_0_B")
+    (INSTANCE hades_drop_cmp_buf_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdropcmpbuf0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_8_B")
+    (INSTANCE hades_dbg2_coarse_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_7_B")
+    (INSTANCE hades_dbg2_coarse_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_6_B")
+    (INSTANCE hades_dbg2_coarse_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_5_B")
+    (INSTANCE hades_dbg2_coarse_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_4_B")
+    (INSTANCE hades_dbg2_coarse_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_3_B")
+    (INSTANCE hades_dbg2_coarse_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_2_B")
+    (INSTANCE hades_dbg2_coarse_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_1_B")
+    (INSTANCE hades_dbg2_coarse_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_coarse_0_B")
+    (INSTANCE hades_dbg2_coarse_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2coarse0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_31_B")
+    (INSTANCE hades_dbg2_out_31_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_30_B")
+    (INSTANCE hades_dbg2_out_30_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_29_B")
+    (INSTANCE hades_dbg2_out_29_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_28_B")
+    (INSTANCE hades_dbg2_out_28_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out28 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_28_MGIOL")
+    (INSTANCE hades_dbg2_out_28_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_27_B")
+    (INSTANCE hades_dbg2_out_27_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out27 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_27_MGIOL")
+    (INSTANCE hades_dbg2_out_27_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_26_B")
+    (INSTANCE hades_dbg2_out_26_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out26 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_26_MGIOL")
+    (INSTANCE hades_dbg2_out_26_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_25_B")
+    (INSTANCE hades_dbg2_out_25_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out25 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_25_MGIOL")
+    (INSTANCE hades_dbg2_out_25_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_24_B")
+    (INSTANCE hades_dbg2_out_24_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out24 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_24_MGIOL")
+    (INSTANCE hades_dbg2_out_24_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_23_B")
+    (INSTANCE hades_dbg2_out_23_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out23 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_23_MGIOL")
+    (INSTANCE hades_dbg2_out_23_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_22_B")
+    (INSTANCE hades_dbg2_out_22_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out22 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_22_MGIOL")
+    (INSTANCE hades_dbg2_out_22_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_21_B")
+    (INSTANCE hades_dbg2_out_21_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out21 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_21_MGIOL")
+    (INSTANCE hades_dbg2_out_21_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_20_B")
+    (INSTANCE hades_dbg2_out_20_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out20 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_20_MGIOL")
+    (INSTANCE hades_dbg2_out_20_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_19_B")
+    (INSTANCE hades_dbg2_out_19_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_18_B")
+    (INSTANCE hades_dbg2_out_18_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out18 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_18_MGIOL")
+    (INSTANCE hades_dbg2_out_18_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_17_B")
+    (INSTANCE hades_dbg2_out_17_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out17 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_17_MGIOL")
+    (INSTANCE hades_dbg2_out_17_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_16_B")
+    (INSTANCE hades_dbg2_out_16_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out16 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_16_MGIOL")
+    (INSTANCE hades_dbg2_out_16_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_15_B")
+    (INSTANCE hades_dbg2_out_15_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_14_B")
+    (INSTANCE hades_dbg2_out_14_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_13_B")
+    (INSTANCE hades_dbg2_out_13_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_12_B")
+    (INSTANCE hades_dbg2_out_12_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out12 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_11_B")
+    (INSTANCE hades_dbg2_out_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out11 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_10_B")
+    (INSTANCE hades_dbg2_out_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out10 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_9_B")
+    (INSTANCE hades_dbg2_out_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out9 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_8_B")
+    (INSTANCE hades_dbg2_out_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_7_B")
+    (INSTANCE hades_dbg2_out_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_6_B")
+    (INSTANCE hades_dbg2_out_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_5_B")
+    (INSTANCE hades_dbg2_out_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_4_B")
+    (INSTANCE hades_dbg2_out_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdbg2out4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_3_B")
+    (INSTANCE hades_dbg2_out_3_I)
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_2_B")
+    (INSTANCE hades_dbg2_out_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_2_MGIOL")
+    (INSTANCE hades_dbg2_out_2_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_1_B")
+    (INSTANCE hades_dbg2_out_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_1_MGIOL")
+    (INSTANCE hades_dbg2_out_1_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_0_B")
+    (INSTANCE hades_dbg2_out_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesdbg2out0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_dbg2_out_0_MGIOL")
+    (INSTANCE hades_dbg2_out_0_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_drop_3_B")
+    (INSTANCE hades_buf_drop_3_I)
+  )
+  (CELL
+    (CELLTYPE "hades_buf_drop_2_B")
+    (INSTANCE hades_buf_drop_2_I)
+  )
+  (CELL
+    (CELLTYPE "hades_buf_drop_1_B")
+    (INSTANCE hades_buf_drop_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesbufdrop1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_drop_1_MGIOL")
+    (INSTANCE hades_buf_drop_1_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_drop_0_B")
+    (INSTANCE hades_buf_drop_0_I)
+  )
+  (CELL
+    (CELLTYPE "hades_invalid_dl_3_B")
+    (INSTANCE hades_invalid_dl_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesinvaliddl3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_invalid_dl_2_B")
+    (INSTANCE hades_invalid_dl_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesinvaliddl2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_invalid_dl_1_B")
+    (INSTANCE hades_invalid_dl_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesinvaliddl1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_invalid_dl_0_B")
+    (INSTANCE hades_invalid_dl_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesinvaliddl0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_discardB")
+    (INSTANCE hades_discardI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesdiscard (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_valid_3_B")
+    (INSTANCE hades_hit_valid_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitvalid3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_valid_2_B")
+    (INSTANCE hades_hit_valid_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitvalid2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_valid_1_B")
+    (INSTANCE hades_hit_valid_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitvalid1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_valid_0_B")
+    (INSTANCE hades_hit_valid_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitvalid0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_out_i_3_B")
+    (INSTANCE hades_hit_out_i_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitouti3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_out_i_2_B")
+    (INSTANCE hades_hit_out_i_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitouti2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_out_i_1_B")
+    (INSTANCE hades_hit_out_i_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitouti1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_hit_out_i_0_B")
+    (INSTANCE hades_hit_out_i_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeshitouti0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_finishedB")
+    (INSTANCE hades_buf_finishedI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesbuffinished (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_releaseB")
+    (INSTANCE hades_buf_releaseI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesbufrelease (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_out_validB")
+    (INSTANCE hades_buf_out_validI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesbufoutvalid (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_buf_out_valid_MGIOL")
+    (INSTANCE hades_buf_out_valid_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_window_endB")
+    (INSTANCE hades_window_endI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadeswindowend (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_validB")
+    (INSTANCE hades_offset_validI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO hadesoffsetvalid (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_8_B")
+    (INSTANCE hades_offset_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_8_MGIOL")
+    (INSTANCE hades_offset_8_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_7_B")
+    (INSTANCE hades_offset_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_7_MGIOL")
+    (INSTANCE hades_offset_7_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_6_B")
+    (INSTANCE hades_offset_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_6_MGIOL")
+    (INSTANCE hades_offset_6_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_5_B")
+    (INSTANCE hades_offset_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_5_MGIOL")
+    (INSTANCE hades_offset_5_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_4_B")
+    (INSTANCE hades_offset_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_4_MGIOL")
+    (INSTANCE hades_offset_4_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_3_B")
+    (INSTANCE hades_offset_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_3_MGIOL")
+    (INSTANCE hades_offset_3_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_2_B")
+    (INSTANCE hades_offset_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_2_MGIOL")
+    (INSTANCE hades_offset_2_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_1_B")
+    (INSTANCE hades_offset_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_1_MGIOL")
+    (INSTANCE hades_offset_1_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_0_B")
+    (INSTANCE hades_offset_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesoffset0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_offset_0_MGIOL")
+    (INSTANCE hades_offset_0_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_lvl1_invalidB")
+    (INSTANCE hades_lvl1_invalidI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH hadeslvl1invalid PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge hadeslvl1invalid) (2500:2500:2500))
+      (WIDTH (negedge hadeslvl1invalid) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_lvl1_invalid_MGIOL")
+    (INSTANCE hades_lvl1_invalid_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK INFF (301:301:301)(301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_lvl1B")
+    (INSTANCE hades_lvl1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH hadeslvl1 PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge hadeslvl1) (2500:2500:2500))
+      (WIDTH (negedge hadeslvl1) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_lvl1_MGIOL")
+    (INSTANCE hades_lvl1_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK INFF (301:301:301)(301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_raw_valid_vect_1_B")
+    (INSTANCE hades_raw_valid_vect_1_I)
+  )
+  (CELL
+    (CELLTYPE "hades_raw_out_validB")
+    (INSTANCE hades_raw_out_validI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO hadesrawoutvalid (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_raw_out_valid_MGIOL")
+    (INSTANCE hades_raw_out_valid_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "hades_trigB")
+    (INSTANCE hades_trigI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH hadestrig PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge hadestrig) (2500:2500:2500))
+      (WIDTH (negedge hadestrig) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "release_outB")
+    (INSTANCE release_outI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO releaseout (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "finishedB")
+    (INSTANCE finishedI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO finishedS (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "last_buf_emptyB")
+    (INSTANCE last_buf_emptyI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO lastbufempty (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "discardB")
+    (INSTANCE discardI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO discardS (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "burstB")
+    (INSTANCE burstI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO burstS (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LVL1_TRG_DATA_VALI_IN_risingB")
+    (INSTANCE LVL1_TRG_DATA_VALI_IN_risingI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LVL1TRGDATAVALIINrising (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_TRG_RELEASE_OUTB")
+    (INSTANCE FEE_TRG_RELEASE_OUTI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO FEETRGRELEASEOUT (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_TRG_RELEASE_OUT_MGIOL")
+    (INSTANCE FEE_TRG_RELEASE_OUT_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATAFINISHED_OUTB")
+    (INSTANCE FEE_DATAFINISHED_OUTI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO FEEDATAFINISHEDOUT (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATAFINISHED_OUT_MGIOL")
+    (INSTANCE FEE_DATAFINISHED_OUT_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_WRITE_OUTB")
+    (INSTANCE FEE_DATA_WRITE_OUTI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO FEEDATAWRITEOUT (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_WRITE_OUT_MGIOL")
+    (INSTANCE FEE_DATA_WRITE_OUT_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (841:841:841)(841:841:841))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73))
+      (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_31_B")
+    (INSTANCE FEE_DATA_OUT_31_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT31 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_30_B")
+    (INSTANCE FEE_DATA_OUT_30_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT30 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_29_B")
+    (INSTANCE FEE_DATA_OUT_29_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT29 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_28_B")
+    (INSTANCE FEE_DATA_OUT_28_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT28 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_27_B")
+    (INSTANCE FEE_DATA_OUT_27_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT27 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_26_B")
+    (INSTANCE FEE_DATA_OUT_26_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT26 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_25_B")
+    (INSTANCE FEE_DATA_OUT_25_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT25 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_24_B")
+    (INSTANCE FEE_DATA_OUT_24_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT24 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_23_B")
+    (INSTANCE FEE_DATA_OUT_23_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT23 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_22_B")
+    (INSTANCE FEE_DATA_OUT_22_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT22 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_21_B")
+    (INSTANCE FEE_DATA_OUT_21_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT21 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_20_B")
+    (INSTANCE FEE_DATA_OUT_20_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT20 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_19_B")
+    (INSTANCE FEE_DATA_OUT_19_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT19 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_18_B")
+    (INSTANCE FEE_DATA_OUT_18_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT18 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_17_B")
+    (INSTANCE FEE_DATA_OUT_17_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT17 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_16_B")
+    (INSTANCE FEE_DATA_OUT_16_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT16 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_15_B")
+    (INSTANCE FEE_DATA_OUT_15_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT15 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_14_B")
+    (INSTANCE FEE_DATA_OUT_14_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT14 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_13_B")
+    (INSTANCE FEE_DATA_OUT_13_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT13 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_12_B")
+    (INSTANCE FEE_DATA_OUT_12_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT12 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_11_B")
+    (INSTANCE FEE_DATA_OUT_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT11 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_10_B")
+    (INSTANCE FEE_DATA_OUT_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT10 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_9_B")
+    (INSTANCE FEE_DATA_OUT_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT9 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_8_B")
+    (INSTANCE FEE_DATA_OUT_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_7_B")
+    (INSTANCE FEE_DATA_OUT_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_6_B")
+    (INSTANCE FEE_DATA_OUT_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_5_B")
+    (INSTANCE FEE_DATA_OUT_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_4_B")
+    (INSTANCE FEE_DATA_OUT_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_3_B")
+    (INSTANCE FEE_DATA_OUT_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_2_B")
+    (INSTANCE FEE_DATA_OUT_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_1_B")
+    (INSTANCE FEE_DATA_OUT_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "FEE_DATA_OUT_0_B")
+    (INSTANCE FEE_DATA_OUT_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO FEEDATAOUT0 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LVL1_INVALID_TRG_INB")
+    (INSTANCE LVL1_INVALID_TRG_INI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH LVL1INVALIDTRGIN PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LVL1INVALIDTRGIN) (2500:2500:2500))
+      (WIDTH (negedge LVL1INVALIDTRGIN) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "LVL1_INVALID_TRG_IN_MGIOL")
+    (INSTANCE LVL1_INVALID_TRG_IN_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK INFF (301:301:301)(301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "LVL1_TRG_DATA_VALID_INB")
+    (INSTANCE LVL1_TRG_DATA_VALID_INI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH LVL1TRGDATAVALIDIN PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LVL1TRGDATAVALIDIN) (2500:2500:2500))
+      (WIDTH (negedge LVL1TRGDATAVALIDIN) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "LVL1_TRG_DATA_VALID_IN_MGIOL")
+    (INSTANCE LVL1_TRG_DATA_VALID_IN_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK INFF (301:301:301)(301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_empty1B")
+    (INSTANCE fifo_empty1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifoempty1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_rdenB")
+    (INSTANCE fifo_rdenI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fiforden (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_31_B")
+    (INSTANCE fifo_data_out_31_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout31 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_30_B")
+    (INSTANCE fifo_data_out_30_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout30 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_29_B")
+    (INSTANCE fifo_data_out_29_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout29 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_28_B")
+    (INSTANCE fifo_data_out_28_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout28 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_27_B")
+    (INSTANCE fifo_data_out_27_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout27 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_26_B")
+    (INSTANCE fifo_data_out_26_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout26 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_25_B")
+    (INSTANCE fifo_data_out_25_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout25 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_24_B")
+    (INSTANCE fifo_data_out_24_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout24 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_23_B")
+    (INSTANCE fifo_data_out_23_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout23 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_22_B")
+    (INSTANCE fifo_data_out_22_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout22 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_21_B")
+    (INSTANCE fifo_data_out_21_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout21 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_20_B")
+    (INSTANCE fifo_data_out_20_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout20 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_19_B")
+    (INSTANCE fifo_data_out_19_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout19 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_18_B")
+    (INSTANCE fifo_data_out_18_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout18 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_17_B")
+    (INSTANCE fifo_data_out_17_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout17 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_16_B")
+    (INSTANCE fifo_data_out_16_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout16 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_15_B")
+    (INSTANCE fifo_data_out_15_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout15 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_14_B")
+    (INSTANCE fifo_data_out_14_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout14 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_13_B")
+    (INSTANCE fifo_data_out_13_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout13 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_12_B")
+    (INSTANCE fifo_data_out_12_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout12 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_11_B")
+    (INSTANCE fifo_data_out_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout11 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_10_B")
+    (INSTANCE fifo_data_out_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout10 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_9_B")
+    (INSTANCE fifo_data_out_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout9 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_8_B")
+    (INSTANCE fifo_data_out_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout8 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_7_B")
+    (INSTANCE fifo_data_out_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout7 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_6_B")
+    (INSTANCE fifo_data_out_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout6 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_5_B")
+    (INSTANCE fifo_data_out_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout5 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_4_B")
+    (INSTANCE fifo_data_out_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout4 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_3_B")
+    (INSTANCE fifo_data_out_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout3 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_2_B")
+    (INSTANCE fifo_data_out_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout2 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_data_out_1_B")
+    (INSTANCE fifo_data_out_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO fifodataout1 (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "trig_2_B")
+    (INSTANCE trig_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH trig2 PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge trig2) (2500:2500:2500))
+      (WIDTH (negedge trig2) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "trig_1_B")
+    (INSTANCE trig_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH trig1 PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge trig1) (2500:2500:2500))
+      (WIDTH (negedge trig1) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "trig_0_B")
+    (INSTANCE trig_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH trig0 PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge trig0) (2500:2500:2500))
+      (WIDTH (negedge trig0) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "reset_dcB")
+    (INSTANCE reset_dcI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH resetdc PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge resetdc) (2500:2500:2500))
+      (WIDTH (negedge resetdc) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "reset_dc_MGIOL")
+    (INSTANCE reset_dc_MGIOLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK INFF (301:301:301)(301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1351:1351:1351))
+      (WIDTH (negedge CLK) (1351:1351:1351))
+    )
+  )
+  (CELL
+    (CELLTYPE "rd_clkB")
+    (INSTANCE rd_clkI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH rdclk PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge rdclk) (2500:2500:2500))
+      (WIDTH (negedge rdclk) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0")
+    (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22))
+      (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14))
+      (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18))
+      (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLKA) (562:562:562))
+      (WIDTH (negedge CLKA) (562:562:562))
+      (WIDTH (posedge CLKB) (561:561:561))
+      (WIDTH (negedge CLKB) (561:561:561))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0")
+    (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22))
+      (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14))
+      (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18))
+      (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLKA) (562:562:562))
+      (WIDTH (negedge CLKA) (562:562:562))
+      (WIDTH (posedge CLKB) (561:561:561))
+      (WIDTH (negedge CLKB) (561:561:561))
+    )
+  )
+  (CELL
+    (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0")
+    (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22))
+      (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14))
+      (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18))
+      (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLKA) (562:562:562))
+      (WIDTH (negedge CLKA) (562:562:562))
+      (WIDTH (posedge CLKB) (561:561:561))
+      (WIDTH (negedge CLKB) (561:561:561))
+    )
+  )
+  (CELL
+    (CELLTYPE "fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1")
+    (INSTANCE fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418))
+        (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB6 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB7 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB8 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB9 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB10 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB11 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB12 (1417:1420:1424)(1417:1420:1424))
+        (IOPATH CLKB DOB13 (1417:1420:1424)(1417:1420:1424))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DIA17 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA16 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA14 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA10 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA8 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA7 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA6 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA5 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA4 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA3 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA2 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA1 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD DIA0 (posedge CLKA) (57:57:57)(12:12:12))
+      (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4))
+      (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22))
+      (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14))
+      (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18))
+      (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26))
+      (SETUPHOLD DIB0 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB1 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB2 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB3 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB4 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB5 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB7 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB10 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB11 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB12 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB13 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB14 (posedge CLKA) (74:74:74)(17:17:17))
+      (SETUPHOLD DIB15 (posedge CLKA) (74:74:74)(17:17:17))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLKA) (562:562:562))
+      (WIDTH (negedge CLKA) (562:562:562))
+      (WIDTH (posedge CLKB) (561:561:561))
+      (WIDTH (negedge CLKB) (561:561:561))
+    )
+  )
+  (CELL
+    (CELLTYPE "pll0inst_PLLInst_0")
+    (INSTANCE pll0inst_PLLInst_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLKI CLKOS3 (0:0:0)(0:0:0))
+        (IOPATH CLKI CLKOS2 (0:0:0)(0:0:0))
+        (IOPATH CLKI CLKOS (0:0:0)(0:0:0))
+        (IOPATH CLKI CLKOP (0:0:0)(0:0:0))
+        (IOPATH CLKFB CLKOS3 (0:0:0)(0:0:0))
+        (IOPATH CLKFB CLKOS2 (0:0:0)(0:0:0))
+        (IOPATH CLKFB CLKOS (0:0:0)(0:0:0))
+        (IOPATH CLKFB CLKOP (0:0:0)(0:0:0))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "top_tf")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/B1 (535:620:706)
+          (535:620:706))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/M1 (500:574:649)
+          (500:574:649))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/A0 (631:731:831)
+          (631:731:831))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/C0 (239:335:432)
+          (239:335:432))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/M0 (506:586:667)
+          (506:586:667))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CE (346:392:438)
+          (346:392:438))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CE (346:392:438)
+          (346:392:438))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CE (238:280:322)
+          (238:280:322))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CE (238:280:322)
+          (238:280:322))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CE (238:280:322)
+          (238:280:322))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CE (238:280:322)
+          (238:280:322))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CE (374:438:502)
+          (374:438:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CE (374:438:502)
+          (374:438:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CE (374:438:502)
+          (374:438:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CE (374:438:502)
+          (374:438:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/A1 (780:910:1040)
+          (780:910:1040))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/B1 (682:797:913)
+          (682:797:913))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CE (378:445:512)
+          (378:445:512))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CE (378:445:512)
+          (378:445:512))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CE (618:701:785)
+          (618:701:785))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CE (618:701:785)
+          (618:701:785))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CE (618:701:785)
+          (618:701:785))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CE (618:701:785)
+          (618:701:785))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CE (364:414:465)
+          (364:414:465))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CE (364:414:465)
+          (364:414:465))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CE (378:445:512)
+          (378:445:512))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CE (378:445:512)
+          (378:445:512))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA 
+          (709:835:961)(709:835:961))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_103I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_121I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_122I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_122I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_123I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_125I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_126I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_127I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_128I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_129I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_130I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_131I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_132I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_133I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_134I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_134I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_135I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_135I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_136I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_136I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_137I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_137I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_138I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_138I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_139I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_139I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_140I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_140I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_141I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_141I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_142I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_142I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_143I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_143I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_144I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_144I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_145I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_145I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_146I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_146I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_152I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_152I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_153I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_153I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_154I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_154I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_155I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_155I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_156I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_156I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_157I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_157I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_158I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_158I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_159I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_159I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_160I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_160I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_161I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_161I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/CLK (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_187I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_187I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_189I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_189I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_190I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_432I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_433I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_434I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_434I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_435I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_435I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_436I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_436I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_437I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_437I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_438I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_439I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_439I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_440I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_440I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_441I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_441I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_442I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_442I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_443I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_445I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_445I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_446I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_446I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_447I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_447I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_448I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_448I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_449I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_450I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_450I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_451I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_451I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_452I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_452I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_453I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_453I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_454I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_455I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_456I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_457I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_458I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_459I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_460I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_628I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_628I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 SLICE_740I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_28_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_27_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_26_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_25_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_24_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_23_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_22_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_21_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_20_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_18_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_17_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_16_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_2_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_1_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_0_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_buf_drop_1_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_buf_out_valid_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_8_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_7_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_6_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_5_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_4_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_3_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_2_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_1_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_0_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_lvl1_invalid_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_lvl1_MGIOLI/CLK (1523:1620:1717)
+          (1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_raw_out_valid_MGIOLI/CLK 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 reset_dc_MGIOLI/CLK (1523:1620:1717)
+          (1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB 
+          (1523:1620:1717)(1523:1620:1717))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CLKA (1523:1620:1717)
+          (1523:1620:1717))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/A1 (633:733:833)
+          (633:733:833))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/M1 (465:526:588)
+          (465:526:588))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/A0 (363:431:500)
+          (363:431:500))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/B0 (648:740:832)
+          (648:740:832))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/D1 (217:258:299)
+          (217:258:299))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/C0 (643:779:916)
+          (643:779:916))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/M0 (640:715:790)
+          (640:715:790))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/A1 (521:614:707)
+          (521:614:707))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/M1 (336:378:420)
+          (336:378:420))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/B0 (397:470:544)
+          (397:470:544))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/A0 (785:904:1023)
+          (785:904:1023))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/C1 (246:345:444)
+          (246:345:444))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/D0 (747:840:933)
+          (747:840:933))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/M0 (345:392:439)
+          (345:392:439))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/A1 (633:733:833)
+          (633:733:833))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/B1 (405:479:553)
+          (405:479:553))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/B0 (405:479:553)
+          (405:479:553))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/M1 (336:378:420)
+          (336:378:420))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/B0 (649:744:840)
+          (649:744:840))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/D1 (354:412:471)
+          (354:412:471))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/D0 (214:255:297)
+          (214:255:297))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/M0 (347:397:448)
+          (347:397:448))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/C0 (379:498:618)
+          (379:498:618))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/M1 (477:545:613)
+          (477:545:613))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/M1 (506:576:646)
+          (506:576:646))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/D1 (489:568:647)
+          (489:568:647))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/D0 (489:568:647)
+          (489:568:647))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/A0 (637:739:842)
+          (637:739:842))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/D1 (221:264:308)
+          (221:264:308))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/B0 (517:597:677)
+          (517:597:677))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/M0 (610:683:757)
+          (610:683:757))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/B1 (396:464:532)
+          (396:464:532))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/M1 (476:535:594)
+          (476:535:594))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/A0 (366:437:509)
+          (366:437:509))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/A0 (495:581:667)
+          (495:581:667))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/C0 (244:343:443)
+          (244:343:443))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/M0 (473:532:592)
+          (473:532:592))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CE (624:710:797)
+          (624:710:797))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CE (624:710:797)
+          (624:710:797))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CE (516:598:681)
+          (516:598:681))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CE (516:598:681)
+          (516:598:681))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CE (516:598:681)
+          (516:598:681))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CE (516:598:681)
+          (516:598:681))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/A1 (785:908:1031)
+          (785:908:1031))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/B1 (797:920:1044)
+          (797:920:1044))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CE (368:427:487)
+          (368:427:487))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CE (368:427:487)
+          (368:427:487))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CE (627:705:784)
+          (627:705:784))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CE (627:705:784)
+          (627:705:784))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CE (497:563:630)
+          (497:563:630))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CE (497:563:630)
+          (497:563:630))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CE (781:890:999)
+          (781:890:999))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CE (781:890:999)
+          (781:890:999))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CE (504:578:652)
+          (504:578:652))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CE (504:578:652)
+          (504:578:652))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CE (471:532:593)
+          (471:532:593))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CE (471:532:593)
+          (471:532:593))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CE (499:566:634)
+          (499:566:634))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CE (770:878:986)
+          (770:878:986))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB 
+          (808:923:1038)(808:923:1038))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB 
+          (808:923:1038)(808:923:1038))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/A1 (494:576:659)
+          (494:576:659))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/M1 (606:677:748)
+          (606:677:748))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/B0 (406:486:566)
+          (406:486:566))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/B0 (406:486:566)
+          (406:486:566))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/D1 (214:255:297)
+          (214:255:297))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/C0 (244:343:443)
+          (244:343:443))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/M0 (603:674:745)
+          (603:674:745))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/A1 (260:318:376)
+          (260:318:376))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/A1 (654:759:865)
+          (654:759:865))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/A1 (393:475:558)
+          (393:475:558))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/A0 (393:475:558)
+          (393:475:558))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/M1 (348:397:446)
+          (348:397:446))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/B0 (527:617:707)
+          (527:617:707))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/C1 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/C0 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/M0 (347:397:448)
+          (347:397:448))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/A1 (499:584:670)
+          (499:584:670))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/B1 (536:621:707)
+          (536:621:707))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/B0 (536:621:707)
+          (536:621:707))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/M1 (466:520:574)
+          (466:520:574))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/B0 (383:450:517)
+          (383:450:517))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/A0 (627:735:843)
+          (627:735:843))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/D1 (222:269:317)
+          (222:269:317))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/D0 (347:403:459)
+          (347:403:459))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/M0 (476:538:601)
+          (476:538:601))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/B1 (278:332:386)
+          (278:332:386))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/B0 (532:624:716)
+          (532:624:716))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/M1 (472:538:604)
+          (472:538:604))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/M1 (237:278:319)
+          (237:278:319))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/B1 (403:475:548)
+          (403:475:548))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/B0 (403:475:548)
+          (403:475:548))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/B0 (519:602:686)
+          (519:602:686))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/D1 (354:412:471)
+          (354:412:471))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/C0 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/M0 (237:279:321)
+          (237:279:321))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/A1 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/B1 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/OFX0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/A0 (506:597:689)
+          (506:597:689))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/OFX0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/B1 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/A0 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/B1 (637:721:806)
+          (637:721:806))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/D1 (92:112:133)
+          (92:112:133))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/B0 (640:728:817)
+          (640:728:817))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/A1 (386:469:552)
+          (386:469:552))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/D1 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/D0 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/B1 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/A1 (380:457:535)
+          (380:457:535))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/A0 (507:591:675)
+          (507:591:675))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 
+          fifo_colector_inst_SLICE_125I/B1 (940:1113:1287)(940:1113:1287))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 
+          fifo_colector_inst_SLICE_680I/D0 (1017:1200:1383)(1017:1200:1383))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/A0 (734:884:1035)
+          (734:884:1035))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 
+          fifo_colector_inst_SLICE_722I/A0 (925:1106:1288)(925:1106:1288))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/A1 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/B0 (522:598:674)
+          (522:598:674))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/B1 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/OFX0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/A0 (489:568:648)
+          (489:568:648))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/OFX0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/B1 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/B0 (634:717:800)
+          (634:717:800))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/B1 (397:468:540)
+          (397:468:540))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/A0 (384:465:547)
+          (384:465:547))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/D1 (94:116:138)
+          (94:116:138))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/D1 (218:259:300)
+          (218:259:300))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/D0 (218:259:300)
+          (218:259:300))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/B1 (374:431:489)
+          (374:431:489))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/A1 (380:457:535)
+          (380:457:535))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/B0 (522:598:674)
+          (522:598:674))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/FCO 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/C0 (233:323:413)(233:323:413))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/A1 (915:1059:1204)
+          (915:1059:1204))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/B1 (687:805:924)
+          (687:805:924))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/B0 (687:805:924)
+          (687:805:924))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/M1 (340:383:426)
+          (340:383:426))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/A0 (911:1054:1198)
+          (911:1054:1198))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/D0 (500:587:675)
+          (500:587:675))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/M0 (340:384:429)
+          (340:384:429))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CE (375:447:520)
+          (375:447:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/A1 (505:595:686)
+          (505:595:686))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/B1 (519:602:685)
+          (519:602:685))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CE (352:401:451)
+          (352:401:451))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CE (352:401:451)
+          (352:401:451))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CE (352:401:451)
+          (352:401:451))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CE (352:401:451)
+          (352:401:451))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CE (219:251:284)
+          (219:251:284))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CE (364:423:482)
+          (364:423:482))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CE (364:423:482)
+          (364:423:482))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CE (369:430:492)
+          (369:430:492))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CE (369:430:492)
+          (369:430:492))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CE (400:482:564)
+          (400:482:564))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CE (400:482:564)
+          (400:482:564))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CE (400:482:564)
+          (400:482:564))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CE (400:482:564)
+          (400:482:564))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CE (364:430:496)
+          (364:430:496))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CE (364:430:496)
+          (364:430:496))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CE (656:774:892)
+          (656:774:892))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CE (656:774:892)
+          (656:774:892))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CE (369:430:492)
+          (369:430:492))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CE (369:430:492)
+          (369:430:492))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA 
+          (865:1020:1175)(865:1020:1175))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/A1 (260:318:376)
+          (260:318:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/A1 (915:1059:1204)
+          (915:1059:1204))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/A1 (672:798:925)
+          (672:798:925))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/A0 (672:798:925)
+          (672:798:925))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/M1 (340:383:426)
+          (340:383:426))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/A0 (366:437:509)
+          (366:437:509))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/A0 (537:651:766)
+          (537:651:766))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/C1 (528:673:819)
+          (528:673:819))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/C0 (528:673:819)
+          (528:673:819))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/M0 (343:390:438)
+          (343:390:438))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/A1 (687:832:977)
+          (687:832:977))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/A1 (408:510:612)
+          (408:510:612))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/A0 (408:510:612)
+          (408:510:612))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/M1 (336:378:420)
+          (336:378:420))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/B0 (400:476:553)
+          (400:476:553))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/B0 (941:1081:1222)
+          (941:1081:1222))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/C1 (392:523:654)
+          (392:523:654))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/C0 (262:381:501)
+          (262:381:501))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/M0 (242:280:318)
+          (242:280:318))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/A1 (897:1021:1146)
+          (897:1021:1146))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/D1 (616:696:776)
+          (616:696:776))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/D0 (616:696:776)
+          (616:696:776))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/M1 (340:383:426)
+          (340:383:426))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/A0 (369:440:512)
+          (369:440:512))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/B0 (796:904:1012)
+          (796:904:1012))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/B1 (384:447:511)
+          (384:447:511))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/A0 (781:897:1013)
+          (781:897:1013))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/M0 (340:384:429)
+          (340:384:429))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/B0 (538:624:711)
+          (538:624:711))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/M1 (484:548:612)
+          (484:548:612))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/M1 (484:548:612)
+          (484:548:612))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/B1 (538:624:711)
+          (538:624:711))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/B0 (538:624:711)
+          (538:624:711))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/B0 (422:512:602)
+          (422:512:602))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/B0 (791:896:1001)
+          (791:896:1001))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/C1 (507:629:751)
+          (507:629:751))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/A0 (639:742:845)
+          (639:742:845))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/M0 (482:544:606)
+          (482:544:606))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/B1 (556:662:769)
+          (556:662:769))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/B1 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/B0 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/M1 (478:538:599)
+          (478:538:599))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/A0 (650:770:890)
+          (650:770:890))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/D0 (221:264:308)
+          (221:264:308))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/M0 (475:534:593)
+          (475:534:593))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CE (511:584:658)
+          (511:584:658))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CE (670:765:860)
+          (670:765:860))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CE (670:765:860)
+          (670:765:860))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CE (670:765:860)
+          (670:765:860))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CE (670:765:860)
+          (670:765:860))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/A1 (699:838:978)
+          (699:838:978))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/B1 (825:964:1103)
+          (825:964:1103))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CE (505:576:647)
+          (505:576:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CE (505:576:647)
+          (505:576:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CE (505:576:647)
+          (505:576:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CE (505:576:647)
+          (505:576:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CE (527:604:682)
+          (527:604:682))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CE (527:604:682)
+          (527:604:682))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CE (528:605:683)
+          (528:605:683))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CE (528:605:683)
+          (528:605:683))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CE (794:897:1000)
+          (794:897:1000))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CE (794:897:1000)
+          (794:897:1000))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CE (631:710:790)
+          (631:710:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CE (631:710:790)
+          (631:710:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CE (631:710:790)
+          (631:710:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CE (631:710:790)
+          (631:710:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CE (527:604:682)
+          (527:604:682))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CE (527:604:682)
+          (527:604:682))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CE (635:716:798)
+          (635:716:798))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CE (635:716:798)
+          (635:716:798))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CE (551:635:720)
+          (551:635:720))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CE (551:635:720)
+          (551:635:720))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB 
+          (541:628:715)(541:628:715))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB 
+          (541:628:715)(541:628:715))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/A1 (260:318:376)
+          (260:318:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/B1 (686:804:923)
+          (686:804:923))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/B1 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/B0 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/M1 (478:538:599)
+          (478:538:599))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/A0 (537:651:766)
+          (537:651:766))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/C1 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/D0 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/M0 (477:539:602)
+          (477:539:602))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/A1 (260:318:376)
+          (260:318:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/B1 (660:768:876)
+          (660:768:876))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/A1 (820:978:1137)
+          (820:978:1137))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/A0 (820:978:1137)
+          (820:978:1137))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/M1 (775:899:1024)
+          (775:899:1024))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/B0 (553:664:776)
+          (553:664:776))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/C1 (245:347:449)
+          (245:347:449))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/B0 (837:994:1152)
+          (837:994:1152))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/M0 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/A1 (636:737:838)
+          (636:737:838))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/A1 (393:475:558)
+          (393:475:558))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/A0 (393:475:558)
+          (393:475:558))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/M1 (626:718:811)
+          (626:718:811))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/A0 (632:732:832)
+          (632:732:832))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/B1 (930:1068:1207)
+          (930:1068:1207))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/C0 (246:345:444)
+          (246:345:444))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/M0 (628:721:815)
+          (628:721:815))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/A0 (511:604:697)
+          (511:604:697))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/M1 (354:406:458)
+          (354:406:458))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/M1 (348:397:446)
+          (348:397:446))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/B1 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/B0 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/B0 (383:450:517)
+          (383:450:517))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/B0 (529:622:716)
+          (529:622:716))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/C1 (242:341:441)
+          (242:341:441))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/D0 (222:269:317)
+          (222:269:317))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/M0 (346:396:447)
+          (346:396:447))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/A1 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/A1 (489:568:648)
+          (489:568:648))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/OFX0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/B0 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/OFX0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/A1 (686:799:913)
+          (686:799:913))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/A0 (380:457:535)
+          (380:457:535))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/B1 (377:436:495)
+          (377:436:495))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/B0 (404:481:558)
+          (404:481:558))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/A1 (517:615:713)
+          (517:615:713))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/D1 (94:116:138)
+          (94:116:138))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/C0 (220:306:393)
+          (220:306:393))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/B1 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/A1 (380:457:535)
+          (380:457:535))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/A0 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 
+          fifo_colector_inst_SLICE_125I/D0 (643:747:851)(643:747:851))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 
+          fifo_colector_inst_SLICE_680I/A1 (682:812:942)(682:812:942))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/A0 (682:812:942)
+          (682:812:942))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/B1 (409:493:578)
+          (409:493:578))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/B0 (409:493:578)
+          (409:493:578))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/B1 (419:505:592)
+          (419:505:592))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/OFX0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/B0 (652:755:859)
+          (652:755:859))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/OFX0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/B1 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/A0 (395:487:579)
+          (395:487:579))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/B1 (524:617:711)
+          (524:617:711))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/A0 (513:618:723)
+          (513:618:723))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/D1 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/D1 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/D0 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/B1 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/A1 (489:568:648)
+          (489:568:648))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/A0 (395:487:579)
+          (395:487:579))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/FCO 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/C0 (381:503:625)(381:503:625))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/B1 (535:620:706)
+          (535:620:706))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/M1 (336:378:420)
+          (336:378:420))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/A0 (631:731:831)
+          (631:731:831))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/C0 (244:343:443)
+          (244:343:443))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/M0 (338:383:428)
+          (338:383:428))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CE (247:294:342)
+          (247:294:342))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CE (247:294:342)
+          (247:294:342))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CE (247:294:342)
+          (247:294:342))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CE (247:294:342)
+          (247:294:342))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/A1 (513:609:705)
+          (513:609:705))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/B1 (528:616:704)
+          (528:616:704))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CE (372:436:500)
+          (372:436:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CE (361:416:471)
+          (361:416:471))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CE (361:416:471)
+          (361:416:471))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CE (364:423:482)
+          (364:423:482))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CE (364:423:482)
+          (364:423:482))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CE (353:403:453)
+          (353:403:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CE (361:416:471)
+          (361:416:471))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CE (361:416:471)
+          (361:416:471))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA 
+          (593:694:796)(593:694:796))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/B1 (926:1046:1166)
+          (926:1046:1166))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/A1 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/A0 (391:472:554)
+          (391:472:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/M1 (336:378:420)
+          (336:378:420))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/B0 (383:450:517)
+          (383:450:517))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/A0 (515:616:717)
+          (515:616:717))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/D1 (222:269:317)
+          (222:269:317))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/C0 (247:349:452)
+          (247:349:452))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/M0 (340:388:437)
+          (340:388:437))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/A1 (517:607:697)
+          (517:607:697))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/C1 (246:348:451)
+          (246:348:451))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/A0 (386:465:544)
+          (386:465:544))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/M1 (471:536:601)
+          (471:536:601))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/A0 (635:738:841)
+          (635:738:841))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/C1 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/C0 (248:350:453)
+          (248:350:453))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/M0 (467:531:595)
+          (467:531:595))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/A1 (1026:1169:1313)
+          (1026:1169:1313))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/C1 (510:641:772)
+          (510:641:772))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/C0 (510:641:772)
+          (510:641:772))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/M1 (368:420:473)
+          (368:420:473))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/A0 (915:1053:1191)
+          (915:1053:1191))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/B1 (781:895:1009)
+          (781:895:1009))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/B0 (669:776:883)
+          (669:776:883))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/M0 (470:533:597)
+          (470:533:597))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/D0 (207:244:282)
+          (207:244:282))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/M1 (218:252:287)
+          (218:252:287))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/M1 (218:252:287)
+          (218:252:287))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/B1 (531:613:696)
+          (531:613:696))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/B0 (531:613:696)
+          (531:613:696))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/A0 (523:624:725)
+          (523:624:725))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/B0 (542:638:735)
+          (542:638:735))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/B1 (672:780:888)
+          (672:780:888))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/C0 (252:357:463)
+          (252:357:463))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/M0 (247:292:338)
+          (247:292:338))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/A1 (646:751:857)
+          (646:751:857))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/B1 (553:647:741)
+          (553:647:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/B0 (553:647:741)
+          (553:647:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/M1 (494:557:621)
+          (494:557:621))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/B0 (380:444:508)
+          (380:444:508))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/A0 (648:756:864)
+          (648:756:864))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/D0 (367:430:494)
+          (367:430:494))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/M0 (468:524:581)
+          (468:524:581))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CE (486:549:612)
+          (486:549:612))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CE (486:549:612)
+          (486:549:612))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CE (378:437:496)
+          (378:437:496))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CE (378:437:496)
+          (378:437:496))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CE (378:437:496)
+          (378:437:496))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CE (378:437:496)
+          (378:437:496))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CE (488:551:615)
+          (488:551:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CE (488:551:615)
+          (488:551:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CE (488:551:615)
+          (488:551:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CE (488:551:615)
+          (488:551:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/A1 (545:650:756)
+          (545:650:756))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/B1 (671:776:881)
+          (671:776:881))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CE (395:462:529)
+          (395:462:529))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CE (395:462:529)
+          (395:462:529))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CE (633:715:798)
+          (633:715:798))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CE (633:715:798)
+          (633:715:798))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CE (645:726:807)
+          (645:726:807))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CE (645:726:807)
+          (645:726:807))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CE (639:717:795)
+          (639:717:795))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CE (639:717:795)
+          (639:717:795))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CE (395:462:529)
+          (395:462:529))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CE (395:462:529)
+          (395:462:529))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CE (374:430:486)
+          (374:430:486))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CE (214:243:272)
+          (214:243:272))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CE (229:265:301)
+          (229:265:301))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CE (229:265:301)
+          (229:265:301))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CE (645:726:807)
+          (645:726:807))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CE (645:726:807)
+          (645:726:807))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB 
+          (553:650:747)(553:650:747))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB 
+          (553:650:747)(553:650:747))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/A1 (260:318:376)
+          (260:318:376))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/A1 (897:1021:1146)
+          (897:1021:1146))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/C1 (511:634:758)
+          (511:634:758))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/C0 (511:634:758)
+          (511:634:758))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/M1 (340:383:426)
+          (340:383:426))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/A0 (363:431:500)
+          (363:431:500))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/A0 (1176:1329:1483)
+          (1176:1329:1483))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/C1 (642:778:915)
+          (642:778:915))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/D0 (487:556:626)
+          (487:556:626))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/M0 (239:273:308)
+          (239:273:308))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/A1 (262:322:382)
+          (262:322:382))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/A1 (674:782:891)
+          (674:782:891))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/B1 (824:939:1054)
+          (824:939:1054))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/B0 (824:939:1054)
+          (824:939:1054))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/M1 (466:520:574)
+          (466:520:574))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/B0 (400:476:553)
+          (400:476:553))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/A0 (653:764:875)
+          (653:764:875))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/A1 (535:636:738)
+          (535:636:738))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/A0 (671:786:902)
+          (671:786:902))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/M0 (367:413:460)
+          (367:413:460))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/B1 (277:329:381)
+          (277:329:381))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/A1 (646:751:857)
+          (646:751:857))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/B1 (553:647:741)
+          (553:647:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/B0 (553:647:741)
+          (553:647:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/M1 (364:415:467)
+          (364:415:467))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/B0 (1173:1321:1470)
+          (1173:1321:1470))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/D1 (747:847:948)
+          (747:847:948))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/C0 (637:778:919)
+          (637:778:919))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/M0 (470:533:597)
+          (470:533:597))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/B1 (275:325:375)
+          (275:325:375))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/A0 (519:610:702)
+          (519:610:702))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/M1 (474:531:589)
+          (474:531:589))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/M1 (609:681:753)
+          (609:681:753))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/C1 (646:784:922)
+          (646:784:922))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/C0 (646:784:922)
+          (646:784:922))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/B0 (378:438:499)
+          (378:438:499))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/B0 (912:1030:1148)
+          (912:1030:1148))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/D1 (487:556:626)
+          (487:556:626))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/C0 (372:479:587)
+          (372:479:587))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/M0 (610:683:757)
+          (610:683:757))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/B1 (522:598:674)
+          (522:598:674))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/B1 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/OFX0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/B0 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/OFX0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/B1 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/B1 (637:721:806)
+          (637:721:806))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/A0 (625:729:833)
+          (625:729:833))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/D1 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/D1 (214:254:295)
+          (214:254:295))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/D0 (95:119:143)
+          (95:119:143))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/B1 (374:431:489)
+          (374:431:489))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/A1 (380:457:535)
+          (380:457:535))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/A0 (507:591:675)
+          (507:591:675))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 
+          fifo_colector_inst_SLICE_125I/A0 (693:800:907)(693:800:907))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 
+          fifo_colector_inst_SLICE_680I/C1 (592:732:873)(592:732:873))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/A0 (529:624:719)
+          (529:624:719))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 
+          fifo_empty1I/PADDO (2169:2376:2583)(2169:2376:2583))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/A1 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/A1 (506:597:689)
+          (506:597:689))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/OFX0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/B0 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/OFX0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/B1 (633:724:815)
+          (633:724:815))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/B0 (522:598:674)
+          (522:598:674))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/B1 (397:468:540)
+          (397:468:540))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/B0 (643:733:823)
+          (643:733:823))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/D1 (94:116:138)
+          (94:116:138))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/D1 (94:116:138)
+          (94:116:138))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/D0 (218:259:300)
+          (218:259:300))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/B1 (374:431:489)
+          (374:431:489))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/A1 (258:314:370)
+          (258:314:370))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/A0 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/FCO 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/C0 (363:464:566)(363:464:566))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_78I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/B1 (277:329:381)(277:329:381))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_98I/B1 (396:464:532)(396:464:532))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/B1 (405:479:553)(405:479:553))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/B0 (405:479:553)(405:479:553))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/M1 (476:535:594)(476:535:594))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/B0 (378:438:499)(378:438:499))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_98I/A0 (763:874:986)(763:874:986))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/D0 (217:258:299)(217:258:299))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/M0 (476:535:594)(476:535:594))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_79I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/CE (494:562:630)(494:562:630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/CE (481:540:599)(481:540:599))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/CE (481:540:599)(481:540:599))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/CE (481:540:599)(481:540:599))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/CE (481:540:599)(481:540:599))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_97I/A1 (503:591:680)(503:591:680))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_97I/B1 (517:598:679)(517:598:679))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/CE (245:290:336)(245:290:336))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/CE (245:290:336)(245:290:336))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/CE (493:560:627)(493:560:627))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/CE (493:560:627)(493:560:627))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/CE (520:597:675)(520:597:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/CE (520:597:675)(520:597:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/CE (628:709:791)(628:709:791))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/CE (628:709:791)(628:709:791))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/CE (375:432:490)(375:432:490))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/CE (375:432:490)(375:432:490))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/CE (206:230:254)(206:230:254))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_182I/CE (206:230:254)(206:230:254))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/CE (638:726:814)(638:726:814))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/CE (638:726:814)(638:726:814))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/CE (638:726:814)(638:726:814))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/CE (638:726:814)(638:726:814))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/CE (524:604:685)(524:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/CE (524:604:685)(524:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/CE (245:290:336)(245:290:336))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/CE (245:290:336)(245:290:336))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CEA (800:910:1021)(800:910:1021))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/A1 (260:318:376)(260:318:376))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_99I/B1 (399:468:538)(399:468:538))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/D1 (486:554:622)(486:554:622))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/D0 (486:554:622)(486:554:622))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/M1 (768:853:939)(768:853:939))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/A0 (366:437:509)(366:437:509))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_99I/A0 (643:752:861)(643:752:861))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/C1 (244:343:443)(244:343:443))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/C0 (510:635:760)(510:635:760))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_183I/M0 (999:1107:1216)(999:1107:1216))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_80I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/A1 (260:318:376)(260:318:376))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_100I/A1 (497:581:665)(497:581:665))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/C1 (772:918:1065)(772:918:1065))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/C0 (772:918:1065)(772:918:1065))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/M1 (504:563:622)(504:563:622))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/B0 (403:480:557)(403:480:557))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_100I/B0 (924:1048:1172)(924:1048:1172))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/C1 (393:512:631)(393:512:631))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/A0 (663:779:895)(663:779:895))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_184I/M0 (492:559:627)(492:559:627))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_81I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/B1 (277:329:381)(277:329:381))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_101I/A1 (499:584:670)(499:584:670))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/B1 (531:613:696)(531:613:696))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/B0 (531:613:696)(531:613:696))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/M1 (471:527:584)(471:527:584))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/B0 (380:444:508)(380:444:508))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_101I/B0 (510:588:666)(510:588:666))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/D1 (354:412:471)(354:412:471))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/D0 (354:412:471)(354:412:471))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_185I/M0 (738:823:908)(738:823:908))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_82I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/B1 (275:325:375)(275:325:375))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/D0 (600:675:751)(600:675:751))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/M1 (611:683:756)(611:683:756))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/M1 (475:532:590)(475:532:590))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/C1 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/C0 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/B0 (378:438:499)(378:438:499))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_102I/B0 (512:589:667)(512:589:667))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/D1 (487:556:626)(487:556:626))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/C0 (511:636:761)(511:636:761))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_186I/M0 (480:541:603)(480:541:603))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_83I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_84I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/B1 (275:325:375)(275:325:375))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_91I/B1 (616:738:860)(616:738:860))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/C1 (891:1100:1309)(891:1100:1309))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/C0 (891:1100:1309)(891:1100:1309))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_162I/M1 (990:1147:1304)(990:1147:1304))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/A0 (363:431:500)(363:431:500))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_91I/B0 (617:740:864)(617:740:864))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/D0 (993:1157:1321)(993:1157:1321))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_162I/M0 (1117:1284:1452)(1117:1284:1452))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/CE (397:471:546)(397:471:546))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_85I/CE (397:471:546)(397:471:546))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/CE (511:593:675)(511:593:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/CE (511:593:675)(511:593:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/CE (511:593:675)(511:593:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/CE (511:593:675)(511:593:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/CE (269:332:396)(269:332:396))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/CE (269:332:396)(269:332:396))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/CE (269:332:396)(269:332:396))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/CE (269:332:396)(269:332:396))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_90I/A1 (994:1174:1355)(994:1174:1355))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_90I/B1 (1008:1181:1354)(1008:1181:1354))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/CE (523:604:685)(523:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/CE (523:604:685)(523:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/CE (728:859:991)(728:859:991))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/CE (728:859:991)(728:859:991))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_162I/CE (523:604:685)(523:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_162I/CE (523:604:685)(523:604:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_163I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_163I/CE (972:1123:1274)(972:1123:1274))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_164I/CE (832:954:1077)(832:954:1077))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_164I/CE (832:954:1077)(832:954:1077))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_165I/CE (561:649:737)(561:649:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_165I/CE (561:649:737)(561:649:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_166I/CE (710:830:951)(710:830:951))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_166I/CE (710:830:951)(710:830:951))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CEB (632:753:874)(632:753:874))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/OCEB (632:753:874)(632:753:874))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_85I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_85I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_86I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_86I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_87I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_87I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_88I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_88I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_89I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_89I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_96I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_124I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_147I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_147I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_148I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_148I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_149I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_149I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_150I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_150I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_151I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_151I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_162I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_162I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_163I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_163I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_164I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_164I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_165I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_165I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_166I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_166I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_172I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_172I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_173I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_173I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_174I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_174I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_175I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_175I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_176I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_176I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_177I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_177I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_178I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_178I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_179I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_179I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_180I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_180I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_181I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_181I/CLK 
+          (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_188I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_631I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_631I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_632I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_633I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_724I/CLK (1588:1665:1742)
+          (1588:1665:1742))
+        (INTERCONNECT rd_clkI/PADDI FEE_TRG_RELEASE_OUT_MGIOLI/CLK (1627:1716:1805)
+          (1627:1716:1805))
+        (INTERCONNECT rd_clkI/PADDI FEE_DATAFINISHED_OUT_MGIOLI/CLK (1627:1716:1805)
+          (1627:1716:1805))
+        (INTERCONNECT rd_clkI/PADDI FEE_DATA_WRITE_OUT_MGIOLI/CLK (1627:1716:1805)
+          (1627:1716:1805))
+        (INTERCONNECT rd_clkI/PADDI LVL1_INVALID_TRG_IN_MGIOLI/CLK (1627:1716:1805)
+          (1627:1716:1805))
+        (INTERCONNECT rd_clkI/PADDI LVL1_TRG_DATA_VALID_IN_MGIOLI/CLK (1627:1716:1805)
+          (1627:1716:1805))
+        (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CLKB 
+          (1627:1716:1805)(1627:1716:1805))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/A1 (260:318:376)(260:318:376))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_92I/B1 (724:861:999)(724:861:999))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/A1 (710:854:999)(710:854:999))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/A0 (710:854:999)(710:854:999))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_163I/M1 (1084:1231:1379)(1084:1231:1379))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/B0 (380:444:508)(380:444:508))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_92I/A0 (764:914:1065)(764:914:1065))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/A1 (694:823:953)(694:823:953))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/B0 (623:743:864)(623:743:864))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_163I/M0 (547:649:751)(547:649:751))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_86I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/A1 (262:322:382)(262:322:382))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_93I/A1 (603:735:867)(603:735:867))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/A1 (739:885:1031)(739:885:1031))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/A0 (739:885:1031)(739:885:1031))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_164I/M1 (614:705:796)(614:705:796))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/B0 (380:444:508)(380:444:508))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_93I/A0 (605:739:874)(605:739:874))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/D1 (537:649:762)(537:649:762))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/D0 (679:794:910)(679:794:910))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_164I/M0 (396:469:543)(396:469:543))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_87I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/B1 (275:325:375)(275:325:375))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_94I/B1 (813:941:1069)(813:941:1069))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/D1 (801:938:1076)(801:938:1076))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/D0 (801:938:1076)(801:938:1076))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_165I/M1 (386:457:529)(386:457:529))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/B0 (380:444:508)(380:444:508))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_94I/B0 (620:746:873)(620:746:873))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/C1 (597:763:930)(597:763:930))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/C0 (597:763:930)(597:763:930))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_165I/M0 (485:567:649)(485:567:649))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_88I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/B1 (275:325:375)(275:325:375))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/D0 (517:624:732)(517:624:732))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/M1 (528:632:737)(528:632:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_166I/M1 (528:632:737)(528:632:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/D1 (654:776:898)(654:776:898))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/D0 (654:776:898)(654:776:898))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/B0 (378:438:499)(378:438:499))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_95I/B0 (625:754:884)(625:754:884))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/C1 (597:763:930)(597:763:930))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/B0 (756:896:1037)(756:896:1037))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_166I/M0 (696:810:925)(696:810:925))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_89I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_90I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_91I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_91I/A1 (395:487:579)(395:487:579))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_91I/A0 (380:457:535)(380:457:535))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_91I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_92I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_702I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_92I/A1 (395:487:579)(395:487:579))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_702I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_92I/B0 (394:464:534)(394:464:534))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_92I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_93I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_93I/B1 (504:575:647)(504:575:647))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_93I/B0 (409:493:578)(409:493:578))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_93I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_94I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_94I/A1 (657:782:907)(657:782:907))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/D1 (92:112:133)(92:112:133))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_94I/A0 (515:621:728)(515:621:728))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/D1 (97:123:149)(97:123:149))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/D1 (97:123:149)(97:123:149))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/C1 (224:314:404)(224:314:404))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/D0 (97:123:149)(97:123:149))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_94I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_95I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_692I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_95I/B1 (374:431:489)(374:431:489))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_692I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_95I/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_95I/A0 (640:753:866)(640:753:866))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/D1 (92:112:133)(92:112:133))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_95I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_96I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_96I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 
+          trb_adapter_inst_SLICE_188I/C0 (2119:2373:2627)(2119:2373:2627))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_720I/D0 (803:911:1020)(803:911:1020))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 last_buf_emptyI/PADDO 
+          (2267:2485:2703)(2267:2485:2703))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_97I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_98I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_98I/A1 (507:591:675)(507:591:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_98I/B0 (522:598:674)(522:598:674))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_98I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_99I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_703I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_99I/A1 (506:597:689)(506:597:689))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_648I/OFX0 
+          fifo_colector_inst_fifo40_inst_SLICE_99I/B0 (504:575:647)(504:575:647))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_99I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_100I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_649I/OFX0 
+          fifo_colector_inst_fifo40_inst_SLICE_100I/B1 (394:464:534)(394:464:534))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_100I/A0 (507:591:675)(507:591:675))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_100I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_101I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_101I/B1 (636:728:821)(636:728:821))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/D1 (92:112:133)(92:112:133))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_101I/A0 (512:609:706)(512:609:706))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/D1 (95:119:143)(95:119:143))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/D1 (95:119:143)(95:119:143))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/B0 (400:475:551)(400:475:551))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_101I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_102I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_691I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_102I/B1 (374:431:489)(374:431:489))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_691I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_102I/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_703I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_102I/A0 (377:449:521)(377:449:521))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_102I/FCO 
+          fifo_colector_inst_fifo40_inst_SLICE_103I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_103I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_103I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_103I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_721I/C0 (233:323:413)(233:323:413))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_120I/FCO 
+          hades_tdc_bundle_inst_SLICE_104I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 
+          hades_tdc_bundle_inst_SLICE_456I/B0 (825:948:1071)(825:948:1071))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 
+          hades_tdc_bundle_inst_SLICE_458I/C1 (672:823:974)(672:823:974))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 
+          hades_tdc_bundle_inst_SLICE_458I/C0 (672:823:974)(672:823:974))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 
+          hades_tdc_bundle_inst_SLICE_710I/C1 (386:499:612)(386:499:612))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/D1 (740:836:933)
+          (740:836:933))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/D1 (344:403:463)
+          (344:403:463))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_SLICE_434I/B1 (278:332:386)(278:332:386))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_SLICE_435I/D1 (208:248:288)(208:248:288))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_SLICE_435I/D0 (208:248:288)(208:248:288))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_SLICE_438I/D1 (208:248:288)(208:248:288))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/M0 
+          (830:934:1039)(830:934:1039))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/M0 (390:450:510)
+          (390:450:510))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_SLICE_681I/D1 (340:396:452)(340:396:452))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/B1 (411:489:568)
+          (411:489:568))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/B0 (411:489:568)
+          (411:489:568))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 hades_dbg2_coarse_1_I/PADDO 
+          (1479:1645:1811)(1479:1645:1811))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 hades_offset_4_MGIOLI/TXDATA0 
+          (1167:1312:1457)(1167:1312:1457))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/C1 
+          (764:916:1069)(764:916:1069))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/C1 (374:491:609)
+          (374:491:609))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_434I/C1 (238:337:437)(238:337:437))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_434I/D0 (95:120:145)(95:120:145))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_435I/A1 (382:463:545)(382:463:545))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_435I/A0 (382:463:545)(382:463:545))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_438I/B1 (397:470:544)(397:470:544))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/M1 
+          (1224:1363:1503)(1224:1363:1503))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/M1 
+          (963:1079:1196)(963:1079:1196))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_SLICE_681I/B1 (532:624:716)(532:624:716))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/D1 (237:292:347)
+          (237:292:347))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/D0 (237:292:347)
+          (237:292:347))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 hades_dbg2_coarse_0_I/PADDO 
+          (1432:1597:1762)(1432:1597:1762))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 hades_offset_3_MGIOLI/TXDATA0 
+          (1148:1290:1432)(1148:1290:1432))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/B1 
+          (832:940:1049)(832:940:1049))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/M1 
+          (931:1023:1115)(931:1023:1115))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/A1 
+          (1002:1125:1248)(1002:1125:1248))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/M0 (233:270:308)
+          (233:270:308))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/D1 (324:369:414)
+          (324:369:414))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/A1 (380:455:531)
+          (380:455:531))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/C1 (233:323:413)
+          (233:323:413))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/B1 
+          (799:908:1018)(799:908:1018))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/B1 
+          (804:916:1029)(804:916:1029))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_SLICE_436I/D1 (194:223:253)(194:223:253))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_SLICE_455I/A1 (519:610:702)(519:610:702))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/M0 
+          (1886:2089:2293)(1886:2089:2293))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/M0 
+          (1315:1458:1601)(1315:1458:1601))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 
+          hades_tdc_bundle_inst_SLICE_701I/B1 (534:617:701)(534:617:701))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 hades_dbg2_coarse_5_I/PADDO 
+          (2336:2605:2875)(2336:2605:2875))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 hades_offset_8_MGIOLI/TXDATA0 
+          (2183:2440:2698)(2183:2440:2698))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/A1 
+          (985:1109:1234)(985:1109:1234))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/M1 (465:518:572)
+          (465:518:572))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/D0 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/C0 
+          (785:926:1068)(785:926:1068))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/M1 (335:377:419)
+          (335:377:419))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/B0 (403:480:557)
+          (403:480:557))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/B0 (408:488:568)
+          (408:488:568))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_436I/B1 (808:929:1050)(808:929:1050))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_436I/B0 (808:929:1050)(808:929:1050))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_437I/B0 (673:779:886)(673:779:886))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_681I/B0 (283:344:406)(283:344:406))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_698I/B1 (283:344:406)(283:344:406))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 
+          hades_tdc_bundle_inst_SLICE_698I/B0 (283:344:406)(283:344:406))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/A0 (534:635:737)
+          (534:635:737))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/A0 (403:493:584)
+          (403:493:584))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_435I/C1 (246:348:451)(246:348:451))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_436I/A1 (652:756:861)(652:756:861))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_436I/A0 (652:756:861)(652:756:861))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_437I/A0 (517:607:697)(517:607:697))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_438I/C1 (246:348:451)(246:348:451))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/M0 
+          (934:1049:1164)(934:1049:1164))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/M0 (494:564:635)
+          (494:564:635))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_681I/A0 (403:493:584)(403:493:584))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_698I/A1 (403:493:584)(403:493:584))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 
+          hades_tdc_bundle_inst_SLICE_698I/C0 (372:487:602)(372:487:602))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 hades_dbg2_coarse_3_I/PADDO 
+          (1627:1811:1995)(1627:1811:1995))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 hades_offset_6_MGIOLI/TXDATA0 
+          (1473:1645:1818)(1473:1645:1818))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/D1 (464:524:585)
+          (464:524:585))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/C1 (371:477:584)
+          (371:477:584))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 
+          hades_tdc_bundle_inst_SLICE_438I/D0 (482:547:612)(482:547:612))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 
+          hades_tdc_bundle_inst_SLICE_455I/B1 (377:436:495)(377:436:495))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/C1 (622:762:903)
+          (622:762:903))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/D1 (217:263:310)
+          (217:263:310))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_SLICE_438I/C0 (120:200:281)(120:200:281))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_SLICE_455I/C1 (248:353:458)(248:353:458))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/M1 
+          (1500:1660:1821)(1500:1660:1821))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/M1 
+          (1048:1175:1302)(1048:1175:1302))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 hades_dbg2_coarse_8_I/PADDO 
+          (1914:2148:2383)(1914:2148:2383))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/B1 (540:627:715)
+          (540:627:715))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/B0 (540:627:715)
+          (540:627:715))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/B1 (540:627:715)
+          (540:627:715))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/B0 (540:627:715)
+          (540:627:715))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_SLICE_437I/B1 (400:470:541)(400:470:541))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_SLICE_437I/D0 (329:377:425)(329:377:425))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 
+          hades_tdc_bundle_inst_SLICE_438I/A0 (390:471:552)(390:471:552))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/A1 (658:768:879)
+          (658:768:879))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/A0 (658:768:879)
+          (658:768:879))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/A1 (392:476:561)
+          (392:476:561))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/A0 (392:476:561)
+          (392:476:561))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_SLICE_437I/A1 (518:611:704)(518:611:704))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_SLICE_438I/B0 (380:444:508)(380:444:508))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 
+          hades_tdc_bundle_inst_SLICE_455I/M0 (343:390:438)(343:390:438))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/D0 (598:673:749)
+          (598:673:749))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/C0 
+          (753:895:1037)(753:895:1037))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_SLICE_437I/D1 (194:223:253)(194:223:253))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/M0 
+          (1501:1651:1802)(1501:1651:1802))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/M0 
+          (1151:1281:1412)(1151:1281:1412))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 
+          hades_tdc_bundle_inst_SLICE_701I/A0 (385:461:538)(385:461:538))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 hades_dbg2_coarse_7_I/PADDO 
+          (2712:2996:3280)(2712:2996:3280))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/C0 (620:749:878)
+          (620:749:878))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/D0 (488:557:627)
+          (488:557:627))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_SLICE_437I/C1 (245:347:449)(245:347:449))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_SLICE_437I/C0 (245:347:449)(245:347:449))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/M1 
+          (1751:1937:2124)(1751:1937:2124))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/M1 
+          (1181:1311:1441)(1181:1311:1441))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 
+          hades_tdc_bundle_inst_SLICE_701I/C0 (242:338:434)(242:338:434))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 hades_dbg2_coarse_6_I/PADDO 
+          (2074:2294:2515)(2074:2294:2515))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/B0 (552:632:713)
+          (552:632:713))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/B1 (507:582:657)
+          (507:582:657))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/M1 (483:544:606)
+          (483:544:606))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/A1 
+          (975:1106:1238)(975:1106:1238))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/M0 (772:859:947)
+          (772:859:947))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/D1 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/C1 (496:616:737)
+          (496:616:737))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/M1 (465:525:586)
+          (465:525:586))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/D0 (211:251:291)
+          (211:251:291))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/C0 (237:330:423)
+          (237:330:423))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/M1 (595:667:740)
+          (595:667:740))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/FCO 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I/FCI (0:0:0)
+          (0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/C0 (380:490:601)
+          (380:490:601))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/C1 (247:345:444)
+          (247:345:444))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/C1 (247:345:444)
+          (247:345:444))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/C0 (247:345:444)
+          (247:345:444))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/C1 (375:490:606)
+          (375:490:606))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/C0 (375:490:606)
+          (375:490:606))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/C1 (375:490:606)
+          (375:490:606))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/C0 (375:490:606)
+          (375:490:606))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/B1 (545:639:733)
+          (545:639:733))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/B1 (662:762:863)
+          (662:762:863))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/B1 (386:453:520)
+          (386:453:520))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/B0 (386:453:520)
+          (386:453:520))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/C1 (517:648:779)
+          (517:648:779))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/B0 (550:643:737)
+          (550:643:737))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/D0 (363:427:491)
+          (363:427:491))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/C0 (257:365:473)
+          (257:365:473))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/D0 (232:284:337)
+          (232:284:337))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/A1 (525:628:731)
+          (525:628:731))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/B1 (540:635:730)
+          (540:635:730))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/B0 (540:635:730)
+          (540:635:730))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/B1 (540:635:730)
+          (540:635:730))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/B0 (540:635:730)
+          (540:635:730))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/A1 (525:628:731)
+          (525:628:731))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/A0 (525:628:731)
+          (525:628:731))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/C1 (243:339:436)
+          (243:339:436))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/C0 (243:339:436)
+          (243:339:436))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/D0 (325:370:416)
+          (325:370:416))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/FCO 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/A1 (683:804:925)
+          (683:804:925))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/D1 (220:267:314)
+          (220:267:314))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/D0 (220:267:314)
+          (220:267:314))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/A0 (517:618:719)
+          (517:618:719))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/D1 (748:848:949)
+          (748:848:949))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/M0 (477:539:602)
+          (477:539:602))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/M0 (788:887:986)
+          (788:887:986))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/M0 (376:428:481)
+          (376:428:481))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/B0 (527:617:707)
+          (527:617:707))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/A0 (517:618:719)
+          (517:618:719))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/D0 (211:251:291)
+          (211:251:291))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/D0 (321:362:404)
+          (321:362:404))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/FCO 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/A1 (500:588:677)
+          (500:588:677))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/A1 (391:478:566)
+          (391:478:566))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/C0 (248:353:458)
+          (248:353:458))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/B1 (400:476:553)
+          (400:476:553))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/B0 (515:596:677)
+          (515:596:677))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/A0 (494:576:659)
+          (494:576:659))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/D1 (482:556:631)
+          (482:556:631))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/B0 (777:888:1000)
+          (777:888:1000))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/D1 (482:556:631)
+          (482:556:631))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/C0 (220:306:393)
+          (220:306:393))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/D1 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/D0 (321:362:404)
+          (321:362:404))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/FCO 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/B1 (397:470:544)
+          (397:470:544))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/C1 (242:338:434)
+          (242:338:434))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/C0 (242:338:434)
+          (242:338:434))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/B0 (506:579:653)
+          (506:579:653))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/B1 (399:468:538)
+          (399:468:538))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/B0 (399:468:538)
+          (399:468:538))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/D1 (321:362:404)
+          (321:362:404))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/D0 (211:251:291)
+          (211:251:291))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/FCO 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/B0 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/A0 (380:454:528)
+          (380:454:528))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/A1 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/A0 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/D1 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q0 
+          hades_tdc_bundle_inst_SLICE_118I/D1 (471:536:602)(471:536:602))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q0 hades_drop_cmp_buf_0_I/PADDO 
+          (895:994:1094)(895:994:1094))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q0 
+          hades_tdc_bundle_inst_SLICE_118I/C1 (351:450:550)(351:450:550))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q0 
+          hades_drop_cmp_buf_coarse_0_I/PADDO (1199:1350:1502)(1199:1350:1502))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q1 
+          hades_tdc_bundle_inst_SLICE_118I/B1 (397:464:531)(397:464:531))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q1 
+          hades_drop_cmp_buf_coarse_1_I/PADDO (1527:1719:1911)(1527:1719:1911))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q1 
+          hades_tdc_bundle_inst_SLICE_118I/A1 (673:781:890)(673:781:890))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q1 hades_drop_cmp_buf_1_I/PADDO 
+          (1068:1208:1348)(1068:1208:1348))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_118I/FCO 
+          hades_tdc_bundle_inst_SLICE_119I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q1 
+          hades_tdc_bundle_inst_SLICE_119I/D1 (344:401:458)(344:401:458))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q1 
+          hades_drop_cmp_buf_coarse_5_I/PADDO (1528:1724:1921)(1528:1724:1921))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q1 
+          hades_tdc_bundle_inst_SLICE_119I/C1 (653:787:921)(653:787:921))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q1 hades_drop_cmp_buf_5_I/PADDO 
+          (1165:1280:1395)(1165:1280:1395))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q0 
+          hades_tdc_bundle_inst_SLICE_119I/B1 (527:614:701)(527:614:701))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q0 
+          hades_drop_cmp_buf_coarse_4_I/PADDO (1408:1582:1757)(1408:1582:1757))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q0 
+          hades_tdc_bundle_inst_SLICE_119I/A1 (671:775:879)(671:775:879))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q0 hades_drop_cmp_buf_4_I/PADDO 
+          (1199:1324:1450)(1199:1324:1450))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q1 
+          hades_tdc_bundle_inst_SLICE_119I/D0 (343:399:456)(343:399:456))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q1 
+          hades_drop_cmp_buf_coarse_3_I/PADDO (1621:1818:2016)(1621:1818:2016))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q0 
+          hades_tdc_bundle_inst_SLICE_119I/C0 (384:497:611)(384:497:611))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q0 hades_drop_cmp_buf_2_I/PADDO 
+          (1253:1395:1537)(1253:1395:1537))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q0 
+          hades_tdc_bundle_inst_SLICE_119I/B0 (526:612:699)(526:612:699))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q0 
+          hades_drop_cmp_buf_coarse_2_I/PADDO (1197:1351:1505)(1197:1351:1505))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q1 
+          hades_tdc_bundle_inst_SLICE_119I/A0 (797:913:1029)(797:913:1029))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q1 hades_drop_cmp_buf_3_I/PADDO 
+          (1226:1373:1521)(1226:1373:1521))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_119I/FCO 
+          hades_tdc_bundle_inst_SLICE_120I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_449I/Q0 
+          hades_tdc_bundle_inst_SLICE_120I/D1 (488:559:630)(488:559:630))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_449I/Q0 hades_drop_cmp_buf_8_I/PADDO 
+          (1182:1308:1435)(1182:1308:1435))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/Q0 
+          hades_tdc_bundle_inst_SLICE_120I/C1 (417:539:662)(417:539:662))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/Q0 
+          hades_drop_cmp_buf_coarse_9_I/PADDO (1586:1785:1985)(1586:1785:1985))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_454I/Q0 
+          hades_tdc_bundle_inst_SLICE_120I/B1 (509:583:658)(509:583:658))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_454I/Q0 
+          hades_drop_cmp_buf_coarse_8_I/PADDO (1537:1718:1900)(1537:1718:1900))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q1 
+          hades_tdc_bundle_inst_SLICE_120I/D0 (323:366:410)(323:366:410))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q1 
+          hades_drop_cmp_buf_coarse_7_I/PADDO (1250:1414:1579)(1250:1414:1579))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q0 
+          hades_tdc_bundle_inst_SLICE_120I/C0 (351:450:550)(351:450:550))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q0 
+          hades_drop_cmp_buf_coarse_6_I/PADDO (1380:1557:1735)(1380:1557:1735))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q0 
+          hades_tdc_bundle_inst_SLICE_120I/B0 (542:630:718)(542:630:718))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q0 hades_drop_cmp_buf_6_I/PADDO 
+          (936:1059:1182)(936:1059:1182))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q1 
+          hades_tdc_bundle_inst_SLICE_120I/A0 (642:743:845)(642:743:845))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q1 hades_drop_cmp_buf_7_I/PADDO 
+          (1325:1450:1576)(1325:1450:1576))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_121I/D1 (475:546:617)(475:546:617))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_122I/D1 (203:240:278)(203:240:278))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_122I/B0 (386:453:520)(386:453:520))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/A1 (711:850:989)(711:850:989))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/C0 (680:843:1007)(680:843:1007))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_432I/D1 (232:284:337)(232:284:337))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_432I/C0 (369:484:599)(369:484:599))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_653I/A0 (982:1137:1292)(982:1137:1292))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_654I/C1 (257:365:473)(257:365:473))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 
+          hades_tdc_bundle_inst_SLICE_683I/C1 (257:365:473)(257:365:473))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 hades_hit_out_i_1_I/PADDO 
+          (1061:1198:1336)(1061:1198:1336))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_121I/C1 (580:743:907)(580:743:907))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_122I/B1 (738:876:1014)(738:876:1014))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/B1 (410:490:570)(410:490:570))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/B0 (410:490:570)(410:490:570))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_432I/A0 (873:1034:1195)(873:1034:1195))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_653I/B0 (689:803:917)(689:803:917))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_654I/B1 (888:1041:1194)(888:1041:1194))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 
+          hades_tdc_bundle_inst_SLICE_654I/B0 (888:1041:1194)(888:1041:1194))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 hades_hit_out_i_2_I/PADDO 
+          (1200:1335:1471)(1200:1335:1471))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_121I/B1 (386:456:526)(386:456:526))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_121I/D0 (100:131:163)(100:131:163))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_122I/C1 (389:520:651)(389:520:651))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_122I/C0 (389:520:651)(389:520:651))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/M0 (671:775:879)(671:775:879))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_432I/D0 (225:275:326)(225:275:326))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_653I/C0 (1002:1211:1421)(1002:1211:1421))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_683I/D1 (225:275:326)(225:275:326))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 
+          hades_tdc_bundle_inst_SLICE_710I/D0 (228:284:341)(228:284:341))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 hades_hit_out_i_0_I/PADDO 
+          (1178:1350:1522)(1178:1350:1522))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_121I/A1 (529:628:727)(529:628:727))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_122I/A1 (262:322:382)(262:322:382))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_123I/A0 (705:838:971)(705:838:971))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_432I/B1 (414:493:573)(414:493:573))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_432I/B0 (414:493:573)(414:493:573))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_653I/D0 (584:676:769)(584:676:769))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_654I/A1 (399:486:574)(399:486:574))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 
+          hades_tdc_bundle_inst_SLICE_683I/A1 (399:486:574)(399:486:574))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 hades_hit_out_i_3_I/PADDO 
+          (1365:1533:1701)(1365:1533:1701))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/OFX0 
+          hades_tdc_bundle_inst_SLICE_121I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_741I/F0 
+          hades_tdc_bundle_inst_SLICE_121I/M0 (332:370:409)(332:370:409))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_121I/LSR (639:721:804)
+          (639:721:804))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_122I/LSR (634:721:808)
+          (634:721:808))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_122I/LSR (634:721:808)
+          (634:721:808))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_123I/LSR (1166:1305:1444)
+          (1166:1305:1444))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/LSR 
+          (1645:1867:2089)(1645:1867:2089))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/LSR 
+          (1933:2188:2444)(1933:2188:2444))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/LSR 
+          (2737:3090:3444)(2737:3090:3444))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_432I/LSR (396:467:538)
+          (396:467:538))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_433I/LSR (747:838:929)
+          (747:838:929))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_434I/LSR (1628:1818:2008)
+          (1628:1818:2008))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_434I/LSR (1628:1818:2008)
+          (1628:1818:2008))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_435I/LSR (1628:1818:2008)
+          (1628:1818:2008))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_435I/LSR (1628:1818:2008)
+          (1628:1818:2008))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_436I/LSR (1741:1938:2135)
+          (1741:1938:2135))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_436I/LSR (1741:1938:2135)
+          (1741:1938:2135))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_437I/LSR (1611:1796:1982)
+          (1611:1796:1982))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_437I/LSR (1611:1796:1982)
+          (1611:1796:1982))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_438I/LSR (1628:1818:2008)
+          (1628:1818:2008))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/LSR (1466:1631:1797)
+          (1466:1631:1797))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_456I/CE (342:389:437)
+          (342:389:437))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_457I/CE (487:554:622)
+          (487:554:622))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_458I/CE (357:414:471)
+          (357:414:471))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_459I/CE (357:414:471)
+          (357:414:471))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_460I/CE (379:442:506)
+          (379:442:506))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/LSR (1573:1755:1937)
+          (1573:1755:1937))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/LSR 
+          (1545:1730:1916)(1545:1730:1916))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/LSR 
+          (1545:1730:1916)(1545:1730:1916))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/LSR 
+          (1832:2051:2270)(1832:2051:2270))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/LSR 
+          (1832:2051:2270)(1832:2051:2270))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/LSR 
+          (1810:2021:2233)(1810:2021:2233))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/LSR 
+          (1810:2021:2233)(1810:2021:2233))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/LSR 
+          (1567:1760:1953)(1567:1760:1953))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/LSR 
+          (1567:1760:1953)(1567:1760:1953))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/LSR 
+          (1107:1248:1390)(1107:1248:1390))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/LSR 
+          (1107:1248:1390)(1107:1248:1390))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/LSR 
+          (1567:1760:1953)(1567:1760:1953))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/LSR 
+          (1567:1760:1953)(1567:1760:1953))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/LSR 
+          (1810:2021:2233)(1810:2021:2233))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/LSR 
+          (1810:2021:2233)(1810:2021:2233))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/LSR 
+          (1810:2021:2233)(1810:2021:2233))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/A1 (1763:2002:2242)
+          (1763:2002:2242))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/A0 (1763:2002:2242)
+          (1763:2002:2242))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/M0 (1443:1617:1791)
+          (1443:1617:1791))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/C1 (1219:1435:1652)
+          (1219:1435:1652))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/C0 (1219:1435:1652)
+          (1219:1435:1652))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/C1 (1598:1848:2099)
+          (1598:1848:2099))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/C0 (1598:1848:2099)
+          (1598:1848:2099))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/LSR 
+          (825:932:1039)(825:932:1039))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/LSR 
+          (1383:1548:1714)(1383:1548:1714))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/LSR 
+          (1383:1548:1714)(1383:1548:1714))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/LSR 
+          (1253:1406:1560)(1253:1406:1560))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/LSR 
+          (956:1074:1192)(956:1074:1192))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/CE (713:813:913)
+          (713:813:913))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/CE (717:820:923)
+          (717:820:923))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_628I/LSR (660:759:859)
+          (660:759:859))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_628I/LSR (660:759:859)
+          (660:759:859))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_653I/M0 (1320:1477:1634)
+          (1320:1477:1634))
+        (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_693I/A0 (927:1074:1222)
+          (927:1074:1222))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/LSR 
+          (2499:2836:3174)(2499:2836:3174))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/LSR 
+          (2243:2540:2837)(2243:2540:2837))
+        (INTERCONNECT SLICE_740I/Q0 genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/LSR 
+          (1775:2008:2242)(1775:2008:2242))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/A0 
+          (1591:1814:2037)(1591:1814:2037))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/C0 
+          (1173:1382:1591)(1173:1382:1591))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/B0 
+          (1648:1856:2064)(1648:1856:2064))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/A0 
+          (2024:2286:2549)(2024:2286:2549))
+        (INTERCONNECT SLICE_740I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/C0 (1219:1435:1652)
+          (1219:1435:1652))
+        (INTERCONNECT SLICE_740I/Q0 SLICE_740I/D0 (100:131:163)(100:131:163))
+        (INTERCONNECT SLICE_740I/Q0 hades_buf_drop_1_MGIOLI/LSR (1068:1212:1357)
+          (1068:1212:1357))
+        (INTERCONNECT SLICE_740I/Q0 FEE_TRG_RELEASE_OUT_MGIOLI/LSR (1463:1651:1839)
+          (1463:1651:1839))
+        (INTERCONNECT SLICE_740I/Q0 FEE_DATAFINISHED_OUT_MGIOLI/LSR (1463:1651:1839)
+          (1463:1651:1839))
+        (INTERCONNECT SLICE_740I/Q0 FEE_DATA_WRITE_OUT_MGIOLI/LSR (1566:1755:1944)
+          (1566:1755:1944))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/F1 
+          hades_tdc_bundle_inst_SLICE_122I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/F0 
+          hades_tdc_bundle_inst_SLICE_122I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_SLICE_123I/D0 (1195:1358:1521)(1195:1358:1521))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/A0 (836:976:1117)
+          (836:976:1117))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/M0 (791:897:1004)
+          (791:897:1004))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/B1 (855:991:1127)
+          (855:991:1127))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/B0 (855:991:1127)
+          (855:991:1127))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/A1 (705:834:963)
+          (705:834:963))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/A0 (705:834:963)
+          (705:834:963))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/B1 (855:991:1127)
+          (855:991:1127))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/B0 (855:991:1127)
+          (855:991:1127))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/C1 (250:352:454)
+          (250:352:454))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/A0 (506:597:688)
+          (506:597:688))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/A0 (705:834:963)
+          (705:834:963))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/A0 
+          (524:619:715)(524:619:715))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/B0 (567:657:748)
+          (567:657:748))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/B0 (694:798:902)
+          (694:798:902))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_tdc_bundle_inst_SLICE_741I/A0 (1025:1173:1321)(1025:1173:1321))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 
+          hades_discardI/PADDO (1677:1899:2121)(1677:1899:2121))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/OFX0 
+          hades_tdc_bundle_inst_SLICE_123I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT LVL1_INVALID_TRG_IN_MGIOLI/INFF trb_adapter_inst_SLICE_124I/M0 
+          (515:570:626)(515:570:626))
+        (INTERCONNECT trb_adapter_inst_SLICE_124I/Q0 trb_adapter_inst_SLICE_188I/C1 
+          (514:639:764)(514:639:764))
+        (INTERCONNECT trb_adapter_inst_SLICE_124I/Q0 discardI/PADDO (275:331:387)
+          (275:331:387))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_125I/C0 
+          (565:731:897)(565:731:897))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_126I/D1 
+          (588:734:881)(588:734:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_126I/D0 
+          (588:734:881)(588:734:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_127I/D1 
+          (417:520:623)(417:520:623))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_127I/D0 
+          (417:520:623)(417:520:623))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_128I/D1 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_128I/D0 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_129I/D1 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_129I/D0 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_130I/C1 
+          (266:384:502)(266:384:502))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_130I/C0 
+          (266:384:502)(266:384:502))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_131I/D1 
+          (345:405:465)(345:405:465))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_131I/D0 
+          (345:405:465)(345:405:465))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_132I/C1 
+          (251:356:462)(251:356:462))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_132I/C0 
+          (251:356:462)(251:356:462))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_133I/B1 
+          (906:1097:1288)(906:1097:1288))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_133I/B0 
+          (906:1097:1288)(906:1097:1288))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_134I/D1 
+          (715:870:1026)(715:870:1026))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_134I/D0 
+          (715:870:1026)(715:870:1026))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_135I/D1 
+          (588:734:881)(588:734:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_135I/D0 
+          (588:734:881)(588:734:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_136I/D1 
+          (732:898:1065)(732:898:1065))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_136I/A0 
+          (1013:1224:1435)(1013:1224:1435))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_137I/D1 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_137I/D0 
+          (403:502:602)(403:502:602))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_138I/D1 
+          (580:720:861)(580:720:861))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_138I/B0 
+          (886:1070:1255)(886:1070:1255))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_139I/D1 
+          (580:720:861)(580:720:861))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_139I/A0 
+          (871:1063:1256)(871:1063:1256))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_140I/D1 
+          (732:898:1065)(732:898:1065))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_140I/D0 
+          (732:898:1065)(732:898:1065))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_141I/D1 
+          (651:772:894)(651:772:894))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_141I/D0 
+          (651:772:894)(651:772:894))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_142I/D1 
+          (558:691:825)(558:691:825))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_142I/C0 
+          (435:589:743)(435:589:743))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_143I/D1 
+          (395:495:596)(395:495:596))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_143I/B0 
+          (408:491:575)(408:491:575))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_144I/B1 
+          (711:850:989)(711:850:989))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_144I/B0 
+          (711:850:989)(711:850:989))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_145I/B1 
+          (712:852:992)(712:852:992))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_145I/C0 
+          (442:600:759)(442:600:759))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_146I/M0 
+          (714:865:1017)(714:865:1017))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_187I/C0 
+          (123:206:290)(123:206:290))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_187I/M1 
+          (417:511:606)(417:511:606))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_189I/C1 
+          (435:589:743)(435:589:743))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_189I/C0 
+          (435:589:743)(435:589:743))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_680I/D1 
+          (410:509:608)(410:509:608))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 
+          fifo_colector_inst_SLICE_125I/DI0 (4:8:12)(4:8:12))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_126I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_127I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_128I/CE 
+          (544:637:730)(544:637:730))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_129I/CE 
+          (544:637:730)(544:637:730))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_130I/CE 
+          (1052:1246:1440)(1052:1246:1440))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_131I/CE 
+          (944:1133:1323)(944:1133:1323))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_132I/CE 
+          (944:1133:1323)(944:1133:1323))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_133I/CE 
+          (340:381:423)(340:381:423))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_134I/CE 
+          (340:381:423)(340:381:423))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_134I/CE 
+          (340:381:423)(340:381:423))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_135I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_135I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_136I/CE 
+          (842:982:1123)(842:982:1123))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_136I/CE 
+          (842:982:1123)(842:982:1123))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_137I/CE 
+          (538:627:717)(538:627:717))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_137I/CE 
+          (538:627:717)(538:627:717))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_138I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_138I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_139I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_139I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_140I/CE 
+          (842:982:1123)(842:982:1123))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_140I/CE 
+          (842:982:1123)(842:982:1123))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_141I/CE 
+          (673:777:881)(673:777:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_141I/CE 
+          (673:777:881)(673:777:881))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_142I/CE 
+          (735:870:1006)(735:870:1006))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_142I/CE 
+          (735:870:1006)(735:870:1006))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_143I/CE 
+          (563:659:756)(563:659:756))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_143I/CE 
+          (563:659:756)(563:659:756))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_144I/CE 
+          (627:758:889)(627:758:889))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_144I/CE 
+          (627:758:889)(627:758:889))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_145I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_145I/CE 
+          (885:1043:1202)(885:1043:1202))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_146I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_146I/CE 
+          (1020:1193:1367)(1020:1193:1367))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_125I/M0 
+          (696:825:954)(696:825:954))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_126I/A1 
+          (602:747:893)(602:747:893))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_126I/A0 
+          (602:747:893)(602:747:893))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_127I/A1 
+          (602:747:893)(602:747:893))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_127I/A0 
+          (602:747:893)(602:747:893))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_128I/A1 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_128I/A0 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_129I/A1 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_129I/A0 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_130I/A1 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_130I/A0 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_131I/A1 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_131I/A0 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_132I/A1 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_132I/A0 
+          (429:536:643)(429:536:643))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_133I/A1 
+          (737:897:1057)(737:897:1057))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_133I/A0 
+          (737:897:1057)(737:897:1057))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_146I/M1 
+          (957:1109:1261)(957:1109:1261))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_187I/B0 
+          (379:440:501)(379:440:501))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_189I/A0 
+          (556:674:793)(556:674:793))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_190I/A0 
+          (556:674:793)(556:674:793))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_680I/B0 
+          (570:681:792)(570:681:792))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_722I/D0 
+          (573:698:824)(573:698:824))
+        (INTERCONNECT fifo_colector_inst_SLICE_125I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_721I/B0 (713:819:926)(713:819:926))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 
+          fifo_colector_inst_SLICE_126I/C1 (569:712:855)(569:712:855))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 
+          fifo_colector_inst_SLICE_126I/C0 (569:712:855)(569:712:855))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 
+          fifo_colector_inst_SLICE_126I/B1 (795:925:1056)(795:925:1056))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 
+          fifo_colector_inst_SLICE_126I/B0 (795:925:1056)(795:925:1056))
+        (INTERCONNECT fifo_colector_inst_SLICE_126I/OFX0 
+          fifo_colector_inst_SLICE_126I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 
+          fifo_colector_inst_SLICE_126I/M0 (754:866:979)(754:866:979))
+        (INTERCONNECT fifo_colector_inst_SLICE_126I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA0 (679:781:883)(679:781:883))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 
+          fifo_colector_inst_SLICE_127I/C1 (569:712:855)(569:712:855))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 
+          fifo_colector_inst_SLICE_127I/C0 (569:712:855)(569:712:855))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 
+          fifo_colector_inst_SLICE_127I/B1 (795:921:1047)(795:921:1047))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 
+          fifo_colector_inst_SLICE_127I/B0 (795:921:1047)(795:921:1047))
+        (INTERCONNECT fifo_colector_inst_SLICE_127I/OFX0 
+          fifo_colector_inst_SLICE_127I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 
+          fifo_colector_inst_SLICE_127I/M0 (749:870:991)(749:870:991))
+        (INTERCONNECT fifo_colector_inst_SLICE_127I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA1 (669:776:884)(669:776:884))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 
+          fifo_colector_inst_SLICE_128I/C1 (681:819:957)(681:819:957))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 
+          fifo_colector_inst_SLICE_128I/C0 (681:819:957)(681:819:957))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 
+          fifo_colector_inst_SLICE_128I/B1 (692:784:877)(692:784:877))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 
+          fifo_colector_inst_SLICE_128I/B0 (692:784:877)(692:784:877))
+        (INTERCONNECT fifo_colector_inst_SLICE_128I/OFX0 
+          fifo_colector_inst_SLICE_128I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 
+          fifo_colector_inst_SLICE_128I/M0 (663:750:838)(663:750:838))
+        (INTERCONNECT fifo_colector_inst_SLICE_128I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA2 (438:515:593)(438:515:593))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 
+          fifo_colector_inst_SLICE_129I/C1 (568:698:829)(568:698:829))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 
+          fifo_colector_inst_SLICE_129I/C0 (568:698:829)(568:698:829))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 
+          fifo_colector_inst_SLICE_129I/B1 (579:664:749)(579:664:749))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 
+          fifo_colector_inst_SLICE_129I/B0 (579:664:749)(579:664:749))
+        (INTERCONNECT fifo_colector_inst_SLICE_129I/OFX0 
+          fifo_colector_inst_SLICE_129I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 
+          fifo_colector_inst_SLICE_129I/M0 (663:750:838)(663:750:838))
+        (INTERCONNECT fifo_colector_inst_SLICE_129I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA3 (550:634:719)(550:634:719))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 
+          fifo_colector_inst_SLICE_130I/D1 (683:773:863)(683:773:863))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 
+          fifo_colector_inst_SLICE_130I/D0 (683:773:863)(683:773:863))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 
+          fifo_colector_inst_SLICE_130I/B1 (452:531:611)(452:531:611))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 
+          fifo_colector_inst_SLICE_130I/B0 (452:531:611)(452:531:611))
+        (INTERCONNECT fifo_colector_inst_SLICE_130I/OFX0 
+          fifo_colector_inst_SLICE_130I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 
+          fifo_colector_inst_SLICE_130I/M0 (663:750:838)(663:750:838))
+        (INTERCONNECT fifo_colector_inst_SLICE_130I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA4 (550:634:719)(550:634:719))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 
+          fifo_colector_inst_SLICE_131I/C1 (294:399:504)(294:399:504))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 
+          fifo_colector_inst_SLICE_131I/C0 (294:399:504)(294:399:504))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 
+          fifo_colector_inst_SLICE_131I/B1 (866:986:1106)(866:986:1106))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 
+          fifo_colector_inst_SLICE_131I/B0 (866:986:1106)(866:986:1106))
+        (INTERCONNECT fifo_colector_inst_SLICE_131I/OFX0 
+          fifo_colector_inst_SLICE_131I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 
+          fifo_colector_inst_SLICE_131I/M0 (713:802:892)(713:802:892))
+        (INTERCONNECT fifo_colector_inst_SLICE_131I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA5 (550:634:719)(550:634:719))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 
+          fifo_colector_inst_SLICE_132I/D1 (266:309:353)(266:309:353))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 
+          fifo_colector_inst_SLICE_132I/D0 (266:309:353)(266:309:353))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 
+          fifo_colector_inst_SLICE_132I/B1 (727:832:937)(727:832:937))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 
+          fifo_colector_inst_SLICE_132I/B0 (727:832:937)(727:832:937))
+        (INTERCONNECT fifo_colector_inst_SLICE_132I/OFX0 
+          fifo_colector_inst_SLICE_132I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 
+          fifo_colector_inst_SLICE_132I/M0 (713:802:892)(713:802:892))
+        (INTERCONNECT fifo_colector_inst_SLICE_132I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA6 (698:799:900)(698:799:900))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 
+          fifo_colector_inst_SLICE_133I/D1 (577:673:770)(577:673:770))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 
+          fifo_colector_inst_SLICE_133I/D0 (577:673:770)(577:673:770))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 
+          fifo_colector_inst_SLICE_133I/C1 (569:712:855)(569:712:855))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 
+          fifo_colector_inst_SLICE_133I/C0 (569:712:855)(569:712:855))
+        (INTERCONNECT fifo_colector_inst_SLICE_133I/OFX0 
+          fifo_colector_inst_SLICE_133I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 
+          fifo_colector_inst_SLICE_133I/M0 (720:831:943)(720:831:943))
+        (INTERCONNECT fifo_colector_inst_SLICE_133I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA7 (539:638:737)(539:638:737))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 
+          fifo_colector_inst_SLICE_134I/C1 (578:720:863)(578:720:863))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 
+          fifo_colector_inst_SLICE_134I/A1 (864:991:1118)(864:991:1118))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 
+          fifo_colector_inst_SLICE_134I/C0 (449:578:707)(449:578:707))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 
+          fifo_colector_inst_SLICE_134I/B0 (737:854:971)(737:854:971))
+        (INTERCONNECT fifo_colector_inst_SLICE_134I/F1 fifo_colector_inst_SLICE_134I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_134I/F0 fifo_colector_inst_SLICE_134I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_134I/LSR 
+          (919:1045:1172)(919:1045:1172))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_134I/LSR 
+          (919:1045:1172)(919:1045:1172))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_135I/LSR 
+          (645:739:834)(645:739:834))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_135I/LSR 
+          (645:739:834)(645:739:834))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_136I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_136I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_137I/LSR 
+          (980:1137:1295)(980:1137:1295))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_137I/LSR 
+          (980:1137:1295)(980:1137:1295))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_138I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_138I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_139I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_139I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_140I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_140I/LSR 
+          (681:791:902)(681:791:902))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_141I/LSR 
+          (957:1107:1258)(957:1107:1258))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_141I/LSR 
+          (957:1107:1258)(957:1107:1258))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_142I/LSR 
+          (505:582:660)(505:582:660))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_142I/LSR 
+          (505:582:660)(505:582:660))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_143I/LSR 
+          (636:725:814)(636:725:814))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_143I/LSR 
+          (636:725:814)(636:725:814))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_144I/LSR 
+          (505:582:660)(505:582:660))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_144I/LSR 
+          (505:582:660)(505:582:660))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_145I/LSR 
+          (645:739:834)(645:739:834))
+        (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_145I/LSR 
+          (645:739:834)(645:739:834))
+        (INTERCONNECT fifo_colector_inst_SLICE_134I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA8 (411:495:580)(411:495:580))
+        (INTERCONNECT fifo_colector_inst_SLICE_134I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA9 (411:495:580)(411:495:580))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 
+          fifo_colector_inst_SLICE_135I/B1 (721:835:950)(721:835:950))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 
+          fifo_colector_inst_SLICE_135I/A1 (907:1049:1192)(907:1049:1192))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 
+          fifo_colector_inst_SLICE_135I/C0 (596:745:894)(596:745:894))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 
+          fifo_colector_inst_SLICE_135I/B0 (609:716:824)(609:716:824))
+        (INTERCONNECT fifo_colector_inst_SLICE_135I/F1 fifo_colector_inst_SLICE_135I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_135I/F0 fifo_colector_inst_SLICE_135I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_135I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA10 (409:491:573)(409:491:573))
+        (INTERCONNECT fifo_colector_inst_SLICE_135I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA11 (409:491:573)(409:491:573))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 
+          fifo_colector_inst_SLICE_136I/B1 (607:710:814)(607:710:814))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 
+          fifo_colector_inst_SLICE_136I/A1 (593:704:815)(593:704:815))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 
+          fifo_colector_inst_SLICE_136I/D0 (579:674:770)(579:674:770))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 
+          fifo_colector_inst_SLICE_136I/C0 (449:578:707)(449:578:707))
+        (INTERCONNECT fifo_colector_inst_SLICE_136I/F1 fifo_colector_inst_SLICE_136I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_136I/F0 fifo_colector_inst_SLICE_136I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_136I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA12 (410:490:570)(410:490:570))
+        (INTERCONNECT fifo_colector_inst_SLICE_136I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA13 (524:615:706)(524:615:706))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 
+          fifo_colector_inst_SLICE_137I/C1 (528:642:757)(528:642:757))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 
+          fifo_colector_inst_SLICE_137I/B1 (574:656:738)(574:656:738))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 
+          fifo_colector_inst_SLICE_137I/C0 (416:523:631)(416:523:631))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 
+          fifo_colector_inst_SLICE_137I/A0 (672:768:865)(672:768:865))
+        (INTERCONNECT fifo_colector_inst_SLICE_137I/F1 fifo_colector_inst_SLICE_137I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_137I/F0 fifo_colector_inst_SLICE_137I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_137I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA14 (488:561:635)(488:561:635))
+        (INTERCONNECT fifo_colector_inst_SLICE_137I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA15 (375:441:508)(375:441:508))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 
+          fifo_colector_inst_SLICE_138I/C1 (744:903:1063)(744:903:1063))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 
+          fifo_colector_inst_SLICE_138I/B1 (607:712:817)(607:712:817))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 
+          fifo_colector_inst_SLICE_138I/D0 (424:499:575)(424:499:575))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 
+          fifo_colector_inst_SLICE_138I/C0 (634:791:949)(634:791:949))
+        (INTERCONNECT fifo_colector_inst_SLICE_138I/F1 fifo_colector_inst_SLICE_138I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_138I/F0 fifo_colector_inst_SLICE_138I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_138I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA16 (411:495:580)(411:495:580))
+        (INTERCONNECT fifo_colector_inst_SLICE_138I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA17 (654:756:859)(654:756:859))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 
+          fifo_colector_inst_SLICE_139I/B1 (783:916:1049)(783:916:1049))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 
+          fifo_colector_inst_SLICE_139I/A1 (864:991:1118)(864:991:1118))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 
+          fifo_colector_inst_SLICE_139I/D0 (583:665:748)(583:665:748))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 
+          fifo_colector_inst_SLICE_139I/B0 (783:916:1049)(783:916:1049))
+        (INTERCONNECT fifo_colector_inst_SLICE_139I/F1 fifo_colector_inst_SLICE_139I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_139I/F0 fifo_colector_inst_SLICE_139I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_139I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB0 (409:491:573)(409:491:573))
+        (INTERCONNECT fifo_colector_inst_SLICE_139I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB1 (409:491:573)(409:491:573))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 
+          fifo_colector_inst_SLICE_140I/B1 (813:952:1091)(813:952:1091))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 
+          fifo_colector_inst_SLICE_140I/A1 (722:847:972)(722:847:972))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 
+          fifo_colector_inst_SLICE_140I/C0 (578:720:863)(578:720:863))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 
+          fifo_colector_inst_SLICE_140I/B0 (660:775:891)(660:775:891))
+        (INTERCONNECT fifo_colector_inst_SLICE_140I/F1 fifo_colector_inst_SLICE_140I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_140I/F0 fifo_colector_inst_SLICE_140I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_140I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB2 (410:490:570)(410:490:570))
+        (INTERCONNECT fifo_colector_inst_SLICE_140I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB3 (410:490:570)(410:490:570))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 
+          fifo_colector_inst_SLICE_141I/B1 (759:877:996)(759:877:996))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 
+          fifo_colector_inst_SLICE_141I/A1 (690:791:892)(690:791:892))
+        (INTERCONNECT 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 
+          fifo_colector_inst_SLICE_141I/C0 (546:665:784)(546:665:784))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 
+          fifo_colector_inst_SLICE_141I/A0 (744:870:997)(744:870:997))
+        (INTERCONNECT fifo_colector_inst_SLICE_141I/F1 fifo_colector_inst_SLICE_141I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_141I/F0 fifo_colector_inst_SLICE_141I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_141I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB4 (375:441:508)(375:441:508))
+        (INTERCONNECT fifo_colector_inst_SLICE_141I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB5 (278:349:420)(278:349:420))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 
+          fifo_colector_inst_SLICE_142I/C1 (596:759:922)(596:759:922))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 
+          fifo_colector_inst_SLICE_142I/A1 (740:885:1030)(740:885:1030))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 
+          fifo_colector_inst_SLICE_142I/B0 (755:892:1029)(755:892:1029))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 
+          fifo_colector_inst_SLICE_142I/A0 (646:768:891)(646:768:891))
+        (INTERCONNECT fifo_colector_inst_SLICE_142I/F1 fifo_colector_inst_SLICE_142I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_142I/F0 fifo_colector_inst_SLICE_142I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_142I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB6 (557:657:757)(557:657:757))
+        (INTERCONNECT fifo_colector_inst_SLICE_142I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB7 (669:776:884)(669:776:884))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 
+          fifo_colector_inst_SLICE_143I/C1 (458:588:718)(458:588:718))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 
+          fifo_colector_inst_SLICE_143I/B1 (574:656:738)(574:656:738))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 
+          fifo_colector_inst_SLICE_143I/D0 (391:443:495)(391:443:495))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 
+          fifo_colector_inst_SLICE_143I/A0 (601:713:826)(601:713:826))
+        (INTERCONNECT fifo_colector_inst_SLICE_143I/F1 fifo_colector_inst_SLICE_143I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_143I/F0 fifo_colector_inst_SLICE_143I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_143I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB8 (669:776:884)(669:776:884))
+        (INTERCONNECT fifo_colector_inst_SLICE_143I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB9 (757:889:1022)(757:889:1022))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 
+          fifo_colector_inst_SLICE_144I/D1 (572:679:787)(572:679:787))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 
+          fifo_colector_inst_SLICE_144I/A1 (593:704:815)(593:704:815))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 
+          fifo_colector_inst_SLICE_144I/C0 (449:578:707)(449:578:707))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 
+          fifo_colector_inst_SLICE_144I/A0 (740:885:1030)(740:885:1030))
+        (INTERCONNECT fifo_colector_inst_SLICE_144I/F1 fifo_colector_inst_SLICE_144I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_144I/F0 fifo_colector_inst_SLICE_144I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_144I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB10 (557:657:757)(557:657:757))
+        (INTERCONNECT fifo_colector_inst_SLICE_144I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB11 (557:657:757)(557:657:757))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 
+          fifo_colector_inst_SLICE_145I/D1 (596:704:812)(596:704:812))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 
+          fifo_colector_inst_SLICE_145I/C1 (451:583:716)(451:583:716))
+        (INTERCONNECT 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 
+          fifo_colector_inst_SLICE_145I/D0 (424:497:571)(424:497:571))
+        (INTERCONNECT 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 
+          fifo_colector_inst_SLICE_145I/B0 (779:917:1055)(779:917:1055))
+        (INTERCONNECT fifo_colector_inst_SLICE_145I/F1 fifo_colector_inst_SLICE_145I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_145I/F0 fifo_colector_inst_SLICE_145I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_145I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB12 (522:609:696)(522:609:696))
+        (INTERCONNECT fifo_colector_inst_SLICE_145I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB13 (522:609:696)(522:609:696))
+        (INTERCONNECT fifo_colector_inst_SLICE_146I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB14 (334:432:531)(334:432:531))
+        (INTERCONNECT fifo_colector_inst_SLICE_146I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB15 (411:495:580)(411:495:580))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_147I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_152I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_152I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_148I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_153I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_153I/M1 (360:408:456)(360:408:456))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_149I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_154I/M0 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_154I/M1 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_150I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_155I/M0 (461:518:576)(461:518:576))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_155I/M1 (360:408:456)(360:408:456))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_151I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_156I/M0 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_156I/M1 (231:266:302)(231:266:302))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_152I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_157I/M0 (495:566:638)(495:566:638))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_152I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_157I/M1 (495:566:638)(495:566:638))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_153I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_158I/M0 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_153I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_158I/M1 (461:518:576)(461:518:576))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_154I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_159I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_154I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_159I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_155I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_160I/M0 (360:408:456)(360:408:456))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_155I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_160I/M1 (461:518:576)(461:518:576))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_156I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_161I/M0 (609:679:750)(609:679:750))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_156I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_161I/M1 (609:679:750)(609:679:750))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/B1 (666:772:879)(666:772:879))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/A1 (545:655:765)(545:655:765))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/B1 (559:661:764)(559:661:764))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/B0 (504:575:647)(504:575:647))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/D0 (217:260:304)(217:260:304))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/D0 (217:260:304)(217:260:304))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/C0 (243:338:434)(243:338:434))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/C1 (243:338:434)(243:338:434))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/C0 (243:338:434)(243:338:434))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/M0 (476:534:593)(476:534:593))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/A0 (391:471:552)(391:471:552))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/A1 (391:471:552)(391:471:552))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/A0 (391:471:552)(391:471:552))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/D1 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/D0 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/D1 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/D0 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/A0 (513:607:701)(513:607:701))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/B1 (528:614:700)(528:614:700))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/C1 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/C0 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/A1 (503:590:677)(503:590:677))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/C0 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/C0 (244:345:446)(244:345:446))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/C0 (244:345:446)(244:345:446))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/A1 (513:607:701)(513:607:701))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/A0 (513:607:701)(513:607:701))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/C1 (369:481:593)(369:481:593))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/A0 (513:607:701)(513:607:701))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/D0 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/D0 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/D1 (226:272:318)(226:272:318))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/B1 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/B0 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/B1 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_649I/B0 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/B0 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_679I/B0 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/A1 (543:649:756)(543:649:756))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/A0 (543:649:756)(543:649:756))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_703I/B1 (422:506:591)(422:506:591))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_162I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB5 (539:638:737)(539:638:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_162I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB6 (522:609:696)(522:609:696))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_163I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB7 (506:584:662)(506:584:662))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_163I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB8 (411:495:580)(411:495:580))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_164I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB9 (539:638:737)(539:638:737))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_164I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB10 (410:490:570)(410:490:570))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_165I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB11 (724:835:947)(724:835:947))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_165I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB12 (409:491:573)(409:491:573))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB13 (781:928:1076)(781:928:1076))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/C1 (242:340:439)(242:340:439))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/C0 (242:340:439)(242:340:439))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_167I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_172I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_172I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_168I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_173I/M0 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_173I/M1 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_169I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_174I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_174I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/F1 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_170I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_175I/M0 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_175I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_171I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_176I/M0 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_176I/M1 (203:227:251)(203:227:251))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_172I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_177I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_172I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_177I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_173I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_178I/M0 (231:259:288)(231:259:288))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_173I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_178I/M1 (332:370:409)(332:370:409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_174I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_179I/M0 (462:512:562)(462:512:562))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_174I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_179I/M1 (462:512:562)(462:512:562))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_175I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_180I/M0 (361:401:441)(361:401:441))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_175I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_180I/M1 (461:518:576)(461:518:576))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_176I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_181I/M0 (504:576:649)(504:576:649))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_176I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_181I/M1 (504:576:649)(504:576:649))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/C1 (475:591:707)(475:591:707))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/A1 (382:457:532)(382:457:532))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/B1 (397:464:531)(397:464:531))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/D0 (208:243:278)(208:243:278))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/B0 (397:464:531)(397:464:531))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/B1 (397:464:531)(397:464:531))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/A0 (500:585:671)(500:585:671))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/B1 (515:592:670)(515:592:670))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/D1 (214:251:289)(214:251:289))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/C0 (359:464:569)(359:464:569))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/A1 (382:461:541)(382:461:541))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/A1 (385:461:538)(385:461:538))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/A1 (503:590:677)(503:590:677))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/A0 (499:584:670)(499:584:670))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/B1 (525:619:714)(525:619:714))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/C1 (355:458:562)(355:458:562))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/B0 (680:793:907)(680:793:907))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/C1 (368:488:608)(368:488:608))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/B0 (680:793:907)(680:793:907))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/D0 (217:258:299)(217:258:299))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/D0 (214:257:301)(214:257:301))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/D0 (217:258:299)(217:258:299))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/C0 (354:456:558)(354:456:558))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_675I/B0 (417:506:595)(417:506:595))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_676I/A0 (498:582:667)(498:582:667))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/A1 (538:649:760)(538:649:760))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_692I/A0 (538:649:760)(538:649:760))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_182I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA5 (375:441:508)(375:441:508))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_182I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA6 (249:301:354)(249:301:354))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_183I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA7 (522:609:696)(522:609:696))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_183I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA8 (391:468:546)(391:468:546))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_184I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA9 (391:468:546)(391:468:546))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_184I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA10 (249:301:354)(249:301:354))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_185I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA11 (278:349:420)(278:349:420))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_185I/Q1 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA12 (391:468:546)(391:468:546))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q0 
+          fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA13 (376:435:494)(376:435:494))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/B1 (527:606:685)(527:606:685))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q1 
+          fifo_colector_inst_fifo40_inst_SLICE_691I/B0 (527:606:685)(527:606:685))
+        (INTERCONNECT fifo_colector_inst_SLICE_187I/F0 fifo_colector_inst_SLICE_187I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_188I/B1 
+          (384:447:511)(384:447:511))
+        (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_631I/M1 
+          (206:233:261)(206:233:261))
+        (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_723I/B0 
+          (384:447:511)(384:447:511))
+        (INTERCONNECT trb_adapter_inst_SLICE_631I/Q1 trb_adapter_inst_SLICE_188I/A1 
+          (366:434:502)(366:434:502))
+        (INTERCONNECT trb_adapter_inst_SLICE_631I/Q1 trb_adapter_inst_SLICE_723I/D0 
+          (197:228:259)(197:228:259))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_188I/D0 
+          (93:114:136)(93:114:136))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_632I/M0 
+          (2781:3054:3327)(2781:3054:3327))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 
+          fifo_colector_inst_fifo40_inst_SLICE_720I/C0 (2117:2371:2626)(2117:2371:2626))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_724I/LSR 
+          (2780:3049:3318)(2780:3049:3318))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 FEE_DATA_WRITE_OUT_MGIOLI/TXDATA0 
+          (2802:3087:3372)(2802:3087:3372))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 fifo_rdenI/PADDO (3622:3972:4322)
+          (3622:3972:4322))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/F1 trb_adapter_inst_SLICE_188I/B0 
+          (276:327:379)(276:327:379))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/F1 burstI/PADDO (275:331:387)
+          (275:331:387))
+        (INTERCONNECT trb_adapter_inst_SLICE_188I/F0 trb_adapter_inst_SLICE_188I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/Q1 fifo_colector_inst_SLICE_189I/B1 
+          (275:325:375)(275:325:375))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/D0 (194:223:253)
+          (194:223:253))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/Q0 fifo_colector_inst_SLICE_189I/D0 
+          (93:114:136)(93:114:136))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/B0 (542:630:718)
+          (542:630:718))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/F1 fifo_colector_inst_SLICE_189I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_189I/F0 fifo_colector_inst_SLICE_189I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_189I/LSR 
+          (202:222:243)(202:222:243))
+        (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_189I/LSR 
+          (202:222:243)(202:222:243))
+        (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_190I/LSR 
+          (202:222:243)(202:222:243))
+        (INTERCONNECT fifo_colector_inst_SLICE_190I/Q0 fifo_colector_inst_SLICE_190I/D0 
+          (93:114:136)(93:114:136))
+        (INTERCONNECT fifo_colector_inst_SLICE_190I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/D0 (384:456:529)
+          (384:456:529))
+        (INTERCONNECT fifo_colector_inst_SLICE_190I/F0 fifo_colector_inst_SLICE_190I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/M0 (637:705:774)
+          (637:705:774))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/M0 (378:426:475)
+          (378:426:475))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/M1 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/M1 (337:378:419)
+          (337:378:419))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/A0 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/D0 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/A0 (506:597:689)
+          (506:597:689))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/B0 (380:441:502)
+          (380:441:502))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/M0 (208:235:263)
+          (208:235:263))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/A1 (366:434:502)
+          (366:434:502))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/C0 (222:308:394)
+          (222:308:394))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/B1 (380:441:502)
+          (380:441:502))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/B0 (380:441:502)
+          (380:441:502))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/C1 (242:340:439)
+          (242:340:439))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/A0 (512:607:702)
+          (512:607:702))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/D1 (214:251:289)
+          (214:251:289))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/D0 (214:251:289)
+          (214:251:289))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/C0 (216:299:382)
+          (216:299:382))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/OFX0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/C0 (114:188:262)
+          (114:188:262))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/LSR (331:365:400)
+          (331:365:400))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/M0 (1329:1479:1629)
+          (1329:1479:1629))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/B0 (1340:1487:1634)
+          (1340:1487:1634))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/M0 (1291:1409:1528)
+          (1291:1409:1528))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/M1 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/B1 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/A1 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/B0 (521:604:688)
+          (521:604:688))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/D0 (217:260:304)
+          (217:260:304))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/A0 (625:726:828)
+          (625:726:828))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/C0 (238:331:424)
+          (238:331:424))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/A1 (760:868:976)
+          (760:868:976))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/C0 (504:622:741)
+          (504:622:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/M0 (477:535:594)
+          (477:535:594))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/A0 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/D1 (465:527:589)
+          (465:527:589))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/B0 (536:620:705)
+          (536:620:705))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/C1 (360:466:573)
+          (360:466:573))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/C0 (360:466:573)
+          (360:466:573))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/C1 (231:323:416)
+          (231:323:416))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/C0 (231:323:416)
+          (231:323:416))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/D0 (217:258:299)
+          (217:258:299))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/B1 (389:456:523)
+          (389:456:523))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/B1 (401:472:543)
+          (401:472:543))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/B0 (401:472:543)
+          (401:472:543))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/A1 (390:474:559)
+          (390:474:559))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/A0 (390:474:559)
+          (390:474:559))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/C0 (246:348:451)
+          (246:348:451))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/C0 (373:489:605)
+          (373:489:605))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/A1 (377:455:533)
+          (377:455:533))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/A0 (377:455:533)
+          (377:455:533))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/D1 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/D0 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/B0 (391:461:532)
+          (391:461:532))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/D0 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/C1 (242:344:446)
+          (242:344:446))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/D1 (205:241:277)
+          (205:241:277))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/D0 (205:241:277)
+          (205:241:277))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/B1 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/B0 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/A0 (374:447:520)
+          (374:447:520))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/B0 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/A1 (533:632:732)
+          (533:632:732))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/A0 (533:632:732)
+          (533:632:732))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/B1 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 
+          (521:610:700)(521:610:700))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 
+          (539:638:737)(539:638:737))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 
+          (564:666:768)(564:666:768))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 
+          (547:644:741)(547:644:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 
+          (411:495:580)(411:495:580))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 
+          (411:495:580)(411:495:580))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 
+          (539:638:737)(539:638:737))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 
+          (652:750:849)(652:750:849))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 
+          (669:776:884)(669:776:884))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/B0 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/M0 (609:679:750)
+          (609:679:750))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/M1 (609:679:750)
+          (609:679:750))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/F1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/M1 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/C1 (236:331:427)
+          (236:331:427))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/A0 (360:425:490)
+          (360:425:490))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/C0 (219:303:388)
+          (219:303:388))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/B0 (394:460:527)
+          (394:460:527))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/D0 (195:225:256)
+          (195:225:256))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/A1 (628:725:822)
+          (628:725:822))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/C0 (242:338:434)
+          (242:338:434))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/M0 (475:532:590)
+          (475:532:590))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/B0 (523:609:695)
+          (523:609:695))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/B1 (534:618:702)
+          (534:618:702))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/A0 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/A1 (372:446:521)
+          (372:446:521))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/A0 (372:446:521)
+          (372:446:521))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/D1 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/D0 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/A0 (366:437:509)
+          (366:437:509))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/D1 (224:271:318)
+          (224:271:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/C1 (230:321:412)
+          (230:321:412))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/C0 (230:321:412)
+          (230:321:412))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/B1 (403:475:548)
+          (403:475:548))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/B0 (403:475:548)
+          (403:475:548))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/C0 (230:321:412)
+          (230:321:412))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/B0 (403:475:548)
+          (403:475:548))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/D1 (226:272:318)
+          (226:272:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/D0 (226:272:318)
+          (226:272:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/C1 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/C0 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/D0 (226:272:318)
+          (226:272:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/C0 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/D1 (226:272:318)
+          (226:272:318))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/B1 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/B0 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/A1 (537:639:742)
+          (537:639:742))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/A0 (537:639:742)
+          (537:639:742))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/B0 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/A0 (537:639:742)
+          (537:639:742))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/A1 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/A0 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/B1 (412:489:567)
+          (412:489:567))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 
+          (547:644:741)(547:644:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 
+          (652:750:849)(652:750:849))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 
+          (434:524:615)(434:524:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 
+          (434:524:615)(434:524:615))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 
+          (547:644:741)(547:644:741))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 
+          (540:631:723)(540:631:723))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 
+          (564:666:768)(564:666:768))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/C1 (482:593:705)
+          (482:593:705))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/C0 (482:593:705)
+          (482:593:705))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/D0 (93:114:136)(93:114:136))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 
+          (348:456:565)(348:456:565))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 
+          (593:725:858)(593:725:858))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 
+          (593:725:858)(593:725:858))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 
+          (608:749:891)(608:749:891))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 
+          (608:749:891)(608:749:891))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 
+          (608:749:891)(608:749:891))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 
+          (484:612:740)(484:612:740))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 
+          (484:612:740)(484:612:740))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/M1 (485:549:613)
+          (485:549:613))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/M1 (384:438:492)
+          (384:438:492))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/M1 (347:394:442)
+          (347:394:442))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/M1 (485:549:613)
+          (485:549:613))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/M1 (347:394:442)
+          (347:394:442))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/M1 (477:536:595)
+          (477:536:595))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/M1 (477:536:595)
+          (477:536:595))
+        (INTERCONNECT SLICE_744I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/M1 (384:438:492)
+          (384:438:492))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOP pll0inst_PLLInst_0I/CLKFB (1523:1620:1717)
+          (1523:1620:1717))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/M0 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/CLK (1484:1569:1654)
+          (1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/CLK 
+          (1484:1569:1654)(1484:1569:1654))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/Q1 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/M0 (361:401:441)
+          (361:401:441))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/M1 (350:408:466)
+          (350:408:466))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/M0 (504:576:649)
+          (504:576:649))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/M1 (403:466:529)
+          (403:466:529))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/M0 (350:408:466)
+          (350:408:466))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/M0 (378:444:510)
+          (378:444:510))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/M0 (248:296:345)
+          (248:296:345))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/M1 (350:408:466)
+          (350:408:466))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/M0 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/M1 (350:408:466)
+          (350:408:466))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/M1 (464:523:583)
+          (464:523:583))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/B0 (394:460:527)
+          (394:460:527))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/D0 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/B0 (391:455:520)
+          (391:455:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/A0 (363:431:500)
+          (363:431:500))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/M0 (234:273:312)
+          (234:273:312))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/D1 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/D0 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/B1 (425:514:604)
+          (425:514:604))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/B0 (425:514:604)
+          (425:514:604))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/A1 (513:615:718)
+          (513:615:718))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/A0 (513:615:718)
+          (513:615:718))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/C1 (256:369:482)
+          (256:369:482))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/C0 (256:369:482)
+          (256:369:482))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/D0 (191:218:246)
+          (191:218:246))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/OFX0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/C0 (114:188:262)
+          (114:188:262))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/LSR (349:403:458)
+          (349:403:458))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/M0 (637:722:808)
+          (637:722:808))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/A0 (1268:1479:1690)
+          (1268:1479:1690))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/M0 (875:987:1100)(875:987:1100))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/M1 (378:444:510)
+          (378:444:510))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/M1 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/M0 (378:444:510)
+          (378:444:510))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/M1 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/M1 (255:307:360)
+          (255:307:360))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/B1 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/A1 (386:467:548)
+          (386:467:548))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/A1 (386:467:548)
+          (386:467:548))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/C0 (233:323:413)
+          (233:323:413))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/B0 (397:468:540)
+          (397:468:540))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/A0 (509:602:695)
+          (509:602:695))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/D0 (220:267:314)
+          (220:267:314))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/D1 (230:287:345)
+          (230:287:345))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/B0 (403:480:557)
+          (403:480:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/M0 (488:562:637)
+          (488:562:637))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/A0 (388:471:554)
+          (388:471:554))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/B1 (417:506:595)
+          (417:506:595))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/C0 (244:345:446)
+          (244:345:446))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/C1 (266:384:503)
+          (266:384:503))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/A0 (783:918:1053)
+          (783:918:1053))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/A1 (372:446:521)
+          (372:446:521))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/A0 (372:446:521)
+          (372:446:521))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/D0 (372:450:529)
+          (372:450:529))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/A1 (653:776:899)
+          (653:776:899))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/B1 (687:805:924)
+          (687:805:924))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/B0 (687:805:924)
+          (687:805:924))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/C1 (225:312:400)
+          (225:312:400))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/C0 (225:312:400)
+          (225:312:400))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/C0 (505:641:778)
+          (505:641:778))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/C0 (505:641:778)
+          (505:641:778))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/D1 (243:309:376)
+          (243:309:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/D0 (243:309:376)
+          (243:309:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/D1 (243:309:376)
+          (243:309:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/D0 (243:309:376)
+          (243:309:376))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/A0 (650:770:890)
+          (650:770:890))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/D0 (369:444:520)
+          (369:444:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/D1 (369:444:520)
+          (369:444:520))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/A1 (529:642:755)
+          (529:642:755))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/C0 (386:516:647)
+          (386:516:647))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/B1 (426:520:615)
+          (426:520:615))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/B0 (426:520:615)
+          (426:520:615))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/B0 (565:677:789)
+          (565:677:789))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/A0 (551:670:790)
+          (551:670:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/A1 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/A0 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/A1 (551:670:790)
+          (551:670:790))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 
+          (706:813:920)(706:813:920))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 
+          (798:922:1047)(798:922:1047))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 
+          (706:813:920)(706:813:920))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 
+          (567:657:747)(567:657:747))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 
+          (570:664:759)(570:664:759))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 
+          (495:603:712)(495:603:712))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 
+          (567:673:779)(567:673:779))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 
+          (698:861:1024)(698:861:1024))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 
+          (748:863:979)(748:863:979))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/D1 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/D0 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/F1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/M1 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/D1 (338:392:446)
+          (338:392:446))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/A1 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/D0 (339:385:431)
+          (339:385:431))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/A0 (625:719:814)
+          (625:719:814))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/B0 (640:726:813)
+          (640:726:813))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/C0 (373:480:587)
+          (373:480:587))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/D1 (478:541:605)
+          (478:541:605))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/A0 (629:725:822)
+          (629:725:822))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/M0 (233:270:308)
+          (233:270:308))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/B0 (534:618:702)
+          (534:618:702))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/A1 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/D0 (464:524:585)
+          (464:524:585))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/B1 (528:615:702)
+          (528:615:702))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/B0 (528:615:702)
+          (528:615:702))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/C1 (247:345:444)
+          (247:345:444))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/C0 (247:345:444)
+          (247:345:444))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/D0 (346:402:459)
+          (346:402:459))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/B1 (778:881:984)
+          (778:881:984))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/A1 (399:485:572)
+          (399:485:572))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/A0 (399:485:572)
+          (399:485:572))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/A1 (399:485:572)
+          (399:485:572))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/A0 (399:485:572)
+          (399:485:572))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/B0 (526:611:697)
+          (526:611:697))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/B0 (674:776:878)
+          (674:776:878))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/C1 (254:359:464)
+          (254:359:464))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/C0 (254:359:464)
+          (254:359:464))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/B1 (403:480:557)
+          (403:480:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/B0 (403:480:557)
+          (403:480:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/C0 (254:359:464)
+          (254:359:464))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/C0 (385:501:617)
+          (385:501:617))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/D1 (230:279:328)
+          (230:279:328))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/D1 (343:398:454)
+          (343:398:454))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/D0 (343:398:454)
+          (343:398:454))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/D1 (200:232:265)
+          (200:232:265))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/D0 (200:232:265)
+          (200:232:265))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/A0 (393:475:558)
+          (393:475:558))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/A0 (775:893:1012)
+          (775:893:1012))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/A1 (533:632:732)
+          (533:632:732))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/A0 (533:632:732)
+          (533:632:732))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/B1 (408:482:557)
+          (408:482:557))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 
+          (540:631:723)(540:631:723))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 
+          (652:750:849)(652:750:849))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 
+          (564:666:768)(564:666:768))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 
+          (677:785:894)(677:785:894))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 
+          (478:579:680)(478:579:680))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 
+          (591:698:806)(591:698:806))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 
+          (688:811:935)(688:811:935))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 
+          (695:824:953)(695:824:953))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 
+          (706:824:943)(706:824:943))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/C1 (222:308:394)
+          (222:308:394))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/C0 (222:308:394)
+          (222:308:394))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/D0 (95:120:145)(95:120:145))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 
+          (427:523:619)(427:523:619))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 
+          (539:642:746)(539:642:746))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 
+          (294:377:460)(294:377:460))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 
+          (406:496:586)(406:496:586))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 
+          (675:793:912)(675:793:912))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 
+          (675:793:912)(675:793:912))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 
+          (429:526:624)(429:526:624))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 
+          (429:526:624)(429:526:624))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/M1 (632:716:800)
+          (632:716:800))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/M1 (493:559:626)
+          (493:559:626))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/M1 (626:706:787)
+          (626:706:787))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/M1 (525:596:667)
+          (525:596:667))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/M1 (632:716:800)
+          (632:716:800))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/M1 (340:384:428)
+          (340:384:428))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/M1 (340:384:428)
+          (340:384:428))
+        (INTERCONNECT SLICE_745I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/M1 (493:559:626)
+          (493:559:626))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/M0 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/Q1 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/M1 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/M0 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/M1 (361:401:441)
+          (361:401:441))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/M0 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/M1 (490:549:609)
+          (490:549:609))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/M1 (208:235:263)
+          (208:235:263))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/C0 (222:308:394)
+          (222:308:394))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/B0 (504:575:647)
+          (504:575:647))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/A0 (377:449:521)
+          (377:449:521))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/C0 (239:338:437)
+          (239:338:437))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/M0 (206:233:261)
+          (206:233:261))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/A1 (366:434:502)
+          (366:434:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/A0 (366:434:502)
+          (366:434:502))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/D1 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/D0 (197:228:259)
+          (197:228:259))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/B1 (400:473:547)
+          (400:473:547))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/B0 (400:473:547)
+          (400:473:547))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/C1 (368:472:577)
+          (368:472:577))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/C0 (368:472:577)
+          (368:472:577))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/D0 (191:218:246)
+          (191:218:246))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/OFX0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/D0 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/LSR (331:365:400)
+          (331:365:400))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/M0 (1161:1296:1431)
+          (1161:1296:1431))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/B0 (690:802:914)(690:802:914))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/M0 (467:520:573)(467:520:573))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/B1 (394:464:534)
+          (394:464:534))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/A1 (363:429:496)
+          (363:429:496))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/A1 (382:461:541)
+          (382:461:541))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/D0 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/B0 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/B0 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/C0 (242:338:434)
+          (242:338:434))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/D1 (341:398:456)
+          (341:398:456))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/C0 (242:338:434)
+          (242:338:434))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/M0 (344:390:436)
+          (344:390:436))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/A0 (389:468:548)
+          (389:468:548))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/B1 (377:436:495)
+          (377:436:495))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/A0 (389:468:548)
+          (389:468:548))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/D1 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/D0 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/D1 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/D0 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/D0 (218:258:299)
+          (218:258:299))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/A1 (499:583:668)
+          (499:583:668))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/B1 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/B0 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/B1 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/B0 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/B0 (401:471:541)
+          (401:471:541))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/A0 (386:464:542)
+          (386:464:542))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/C1 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/C0 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/C1 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/C0 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/C0 (243:338:434)
+          (243:338:434))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/D0 (218:258:299)
+          (218:258:299))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/C1 (391:509:628)
+          (391:509:628))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/A1 (543:649:756)
+          (543:649:756))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/A0 (543:649:756)
+          (543:649:756))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/A1 (543:649:756)
+          (543:649:756))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/A0 (543:649:756)
+          (543:649:756))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/A0 (395:478:562)
+          (395:478:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/B0 (409:485:561)
+          (409:485:561))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/B1 (409:485:561)
+          (409:485:561))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/B0 (409:485:561)
+          (409:485:561))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/A1 (543:649:756)
+          (543:649:756))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 
+          (723:854:985)(723:854:985))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 
+          (723:854:985)(723:854:985))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 
+          (411:495:580)(411:495:580))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 
+          (598:721:844)(598:721:844))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 
+          (670:773:876)(670:773:876))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 
+          (598:721:844)(598:721:844))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 
+          (598:721:844)(598:721:844))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 
+          (869:1009:1149)(869:1009:1149))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/C1 (351:451:552)
+          (351:451:552))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/C0 (351:451:552)
+          (351:451:552))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/M0 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/M1 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/F1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/M0 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/M1 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/M0 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/M1 (479:537:596)
+          (479:537:596))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/M1 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/D1 (208:243:278)
+          (208:243:278))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/B1 (397:464:531)
+          (397:464:531))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/A0 (489:568:648)
+          (489:568:648))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/C0 (242:340:439)
+          (242:340:439))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/C0 (242:340:439)
+          (242:340:439))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/D0 (217:258:299)
+          (217:258:299))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/A1 (363:431:500)
+          (363:431:500))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/A0 (498:583:668)
+          (498:583:668))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/M0 (207:234:262)
+          (207:234:262))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/B0 (401:472:543)
+          (401:472:543))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/B1 (379:440:501)
+          (379:440:501))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/B0 (401:472:543)
+          (401:472:543))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/D1 (222:265:308)
+          (222:265:308))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/D0 (222:265:308)
+          (222:265:308))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/D1 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/D0 (362:422:483)
+          (362:422:483))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/D0 (222:265:308)
+          (222:265:308))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/C1 (499:621:744)
+          (499:621:744))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/B1 (405:478:551)
+          (405:478:551))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/B0 (405:478:551)
+          (405:478:551))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/B1 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/B0 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/B0 (405:478:551)
+          (405:478:551))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/B0 (545:635:725)
+          (545:635:725))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/C1 (398:519:641)
+          (398:519:641))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/C0 (398:519:641)
+          (398:519:641))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/C1 (538:676:815)
+          (538:676:815))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/C0 (538:676:815)
+          (538:676:815))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/C0 (398:519:641)
+          (398:519:641))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/C0 (538:676:815)
+          (538:676:815))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/C1 (398:519:641)
+          (398:519:641))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/A1 (667:781:896)
+          (667:781:896))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
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+          (667:781:896))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
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+          (523:617:712))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
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+          (523:617:712))
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+          (667:781:896))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
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+          (523:617:712))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/A1 (385:461:538)
+          (385:461:538))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
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+          (385:461:538))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/B1 (682:788:895)
+          (682:788:895))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 
+          (521:610:700)(521:610:700))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 
+          (411:495:580)(411:495:580))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 
+          (539:638:737)(539:638:737))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 
+          (539:638:737)(539:638:737))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 
+          (522:609:696)(522:609:696))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 
+          (710:840:970)(710:840:970))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/A1 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/A0 (382:457:532)
+          (382:457:532))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/C0 (117:194:272)(117:194:272))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 
+          (427:518:610)(427:518:610))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 
+          (550:655:761)(550:655:761))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 
+          (720:856:993)(720:856:993))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/M1 (343:387:432)
+          (343:387:432))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/M1 (487:551:616)
+          (487:551:616))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/M1 (617:693:769)
+          (617:693:769))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/M1 (343:387:432)
+          (343:387:432))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/M1 (617:693:769)
+          (617:693:769))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/M1 (380:431:483)
+          (380:431:483))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/M1 (487:551:616)
+          (487:551:616))
+        (INTERCONNECT SLICE_746I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/M1 (481:542:603)
+          (481:542:603))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/M0 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/Q1 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/F0 
+          hades_tdc_bundle_inst_SLICE_432I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/Q0 
+          hades_tdc_bundle_inst_SLICE_433I/M0 (744:829:914)(744:829:914))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/Q0 hades_buf_finishedI/PADDO 
+          (1026:1137:1249)(1026:1137:1249))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/F1 
+          hades_tdc_bundle_inst_SLICE_654I/A0 (258:314:370)(258:314:370))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/B1 (928:1054:1180)(928:1054:1180))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/D0 (632:721:811)(632:721:811))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_458I/D1 (615:700:786)(615:700:786))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_458I/D0 (615:700:786)(615:700:786))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/C1 (522:652:782)(522:652:782))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/C0 (522:652:782)(522:652:782))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/B1 (648:740:832)(648:740:832))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/C0 (378:488:598)(378:488:598))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 hades_buf_releaseI/PADDO 
+          (1031:1166:1301)(1031:1166:1301))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F1 
+          hades_tdc_bundle_inst_SLICE_434I/DI1 (3:6:10)(3:6:10))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F1 
+          hades_tdc_bundle_inst_SLICE_450I/M1 (670:760:850)(670:760:850))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F0 
+          hades_tdc_bundle_inst_SLICE_434I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F0 
+          hades_tdc_bundle_inst_SLICE_450I/M0 (643:724:806)(643:724:806))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_SLICE_435I/B1 (386:453:520)(386:453:520))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_SLICE_435I/C0 (120:200:281)(120:200:281))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_SLICE_438I/A1 (372:446:521)(372:446:521))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/M1 
+          (1029:1155:1282)(1029:1155:1282))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/M1 (487:554:622)
+          (487:554:622))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_SLICE_681I/C1 (253:358:463)(253:358:463))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/C1 (253:358:463)
+          (253:358:463))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/A0 (509:603:697)
+          (509:603:697))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 hades_dbg2_coarse_2_I/PADDO 
+          (2163:2415:2667)(2163:2415:2667))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 hades_offset_5_MGIOLI/TXDATA0 
+          (1830:2041:2252)(1830:2041:2252))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F1 
+          hades_tdc_bundle_inst_SLICE_435I/DI1 (3:6:10)(3:6:10))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F1 
+          hades_tdc_bundle_inst_SLICE_451I/M1 (684:774:864)(684:774:864))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F0 
+          hades_tdc_bundle_inst_SLICE_435I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F0 
+          hades_tdc_bundle_inst_SLICE_451I/M0 (513:583:653)(513:583:653))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_436I/C1 (222:311:400)(222:311:400))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_436I/D0 (95:120:145)(95:120:145))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_455I/D1 (358:419:481)(358:419:481))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/M1 
+          (1225:1368:1512)(1225:1368:1512))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/M1 
+          (891:1002:1113)(891:1002:1113))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_681I/C0 (769:924:1080)(769:924:1080))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_698I/D1 (632:725:818)(632:725:818))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_698I/D0 (632:725:818)(632:725:818))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 
+          hades_tdc_bundle_inst_SLICE_701I/D1 (358:419:481)(358:419:481))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 hades_dbg2_coarse_4_I/PADDO 
+          (2449:2712:2975)(2449:2712:2975))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 hades_offset_7_MGIOLI/TXDATA0 
+          (1544:1734:1924)(1544:1734:1924))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F1 
+          hades_tdc_bundle_inst_SLICE_436I/DI1 (3:6:10)(3:6:10))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F1 
+          hades_tdc_bundle_inst_SLICE_452I/M1 (360:411:462)(360:411:462))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F0 
+          hades_tdc_bundle_inst_SLICE_436I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F0 
+          hades_tdc_bundle_inst_SLICE_452I/M0 (359:408:458)(359:408:458))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F1 
+          hades_tdc_bundle_inst_SLICE_437I/DI1 (3:6:10)(3:6:10))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F1 
+          hades_tdc_bundle_inst_SLICE_453I/M1 (514:585:657)(514:585:657))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F0 
+          hades_tdc_bundle_inst_SLICE_437I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F0 
+          hades_tdc_bundle_inst_SLICE_453I/M0 (513:583:653)(513:583:653))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F0 
+          hades_tdc_bundle_inst_SLICE_438I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F0 
+          hades_tdc_bundle_inst_SLICE_454I/M0 (669:757:846)(669:757:846))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/Q1 
+          hades_tdc_bundle_inst_SLICE_439I/M1 (643:727:811)(643:727:811))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/Q0 
+          hades_tdc_bundle_inst_SLICE_439I/M0 (511:579:647)(511:579:647))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_439I/CE (345:387:430)(345:387:430))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_439I/CE (345:387:430)(345:387:430))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_440I/CE (345:387:430)(345:387:430))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_440I/CE (345:387:430)(345:387:430))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_441I/CE (469:520:571)(469:520:571))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_441I/CE (469:520:571)(469:520:571))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_442I/CE (1077:1195:1313)(1077:1195:1313))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_442I/CE (1077:1195:1313)(1077:1195:1313))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 
+          hades_tdc_bundle_inst_SLICE_443I/CE (817:912:1007)(817:912:1007))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_28_MGIOLI/CE 
+          (1280:1433:1586)(1280:1433:1586))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_27_MGIOLI/CE 
+          (1259:1404:1550)(1259:1404:1550))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_26_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_25_MGIOLI/CE 
+          (1426:1598:1771)(1426:1598:1771))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_24_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_23_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_22_MGIOLI/CE 
+          (1162:1289:1416)(1162:1289:1416))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_21_MGIOLI/CE 
+          (1253:1395:1538)(1253:1395:1538))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_20_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_18_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_17_MGIOLI/CE 
+          (1280:1433:1586)(1280:1433:1586))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_16_MGIOLI/CE 
+          (1205:1335:1465)(1205:1335:1465))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_2_MGIOLI/CE 
+          (1205:1335:1465)(1205:1335:1465))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_1_MGIOLI/CE 
+          (1259:1404:1550)(1259:1404:1550))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_0_MGIOLI/CE 
+          (1431:1606:1781)(1431:1606:1781))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q0 
+          hades_tdc_bundle_inst_SLICE_445I/M0 (614:687:760)(614:687:760))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q0 hades_dbg2_out_4_I/PADDO 
+          (1518:1682:1846)(1518:1682:1846))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q1 
+          hades_tdc_bundle_inst_SLICE_445I/M1 (495:557:620)(495:557:620))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q1 hades_dbg2_out_5_I/PADDO 
+          (1127:1260:1393)(1127:1260:1393))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/Q1 
+          hades_tdc_bundle_inst_SLICE_440I/M1 (511:579:647)(511:579:647))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/Q0 
+          hades_tdc_bundle_inst_SLICE_440I/M0 (511:579:647)(511:579:647))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q0 
+          hades_tdc_bundle_inst_SLICE_446I/M0 (466:526:587)(466:526:587))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q0 hades_dbg2_out_6_I/PADDO 
+          (1239:1379:1519)(1239:1379:1519))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q1 
+          hades_tdc_bundle_inst_SLICE_446I/M1 (597:669:741)(597:669:741))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q1 hades_dbg2_out_7_I/PADDO 
+          (1127:1260:1393)(1127:1260:1393))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/Q1 
+          hades_tdc_bundle_inst_SLICE_441I/M1 (643:727:811)(643:727:811))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/Q0 
+          hades_tdc_bundle_inst_SLICE_441I/M0 (651:728:806)(651:728:806))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q0 
+          hades_tdc_bundle_inst_SLICE_447I/M0 (467:520:573)(467:520:573))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q0 hades_dbg2_out_8_I/PADDO 
+          (1198:1344:1490)(1198:1344:1490))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q1 
+          hades_tdc_bundle_inst_SLICE_447I/M1 (464:523:583)(464:523:583))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q1 hades_dbg2_out_9_I/PADDO 
+          (1206:1344:1482)(1206:1344:1482))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/Q1 
+          hades_tdc_bundle_inst_SLICE_442I/M1 (462:512:562)(462:512:562))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/Q0 
+          hades_tdc_bundle_inst_SLICE_442I/M0 (462:512:562)(462:512:562))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q0 
+          hades_tdc_bundle_inst_SLICE_448I/M0 (674:754:834)(674:754:834))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q0 hades_dbg2_out_10_I/PADDO 
+          (1359:1529:1700)(1359:1529:1700))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q1 
+          hades_tdc_bundle_inst_SLICE_448I/M1 (674:754:834)(674:754:834))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q1 hades_dbg2_out_11_I/PADDO 
+          (1563:1746:1930)(1563:1746:1930))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/Q0 
+          hades_tdc_bundle_inst_SLICE_443I/M0 (332:370:409)(332:370:409))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_443I/Q0 
+          hades_tdc_bundle_inst_SLICE_449I/M0 (834:923:1013)(834:923:1013))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_443I/Q0 hades_dbg2_out_12_I/PADDO 
+          (1372:1531:1691)(1372:1531:1691))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/C1 (117:192:268)
+          (117:192:268))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/DI0 (3:4:6)(3:4:6))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/A1 (662:777:892)
+          (662:777:892))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/D0 (494:571:649)
+          (494:571:649))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/D0 (195:225:256)
+          (195:225:256))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/D0 (1158:1302:1447)
+          (1158:1302:1447))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/B0 (1197:1357:1517)
+          (1197:1357:1517))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 
+          hades_invalid_dl_3_I/PADDO (1007:1114:1221)(1007:1114:1221))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/C0 (1348:1559:1770)
+          (1348:1559:1770))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/M0 (1253:1366:1480)
+          (1253:1366:1480))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/D0 (1316:1456:1597)
+          (1316:1456:1597))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 
+          hades_invalid_dl_2_I/PADDO (738:827:917)(738:827:917))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/B0 (397:470:544)
+          (397:470:544))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/C0 (497:613:730)
+          (497:613:730))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/A0 (964:1088:1213)
+          (964:1088:1213))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/M0 (807:890:974)
+          (807:890:974))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/A0 (1134:1269:1405)
+          (1134:1269:1405))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/CE (202:222:243)
+          (202:222:243))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_445I/CE (632:718:805)
+          (632:718:805))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_445I/CE (632:718:805)
+          (632:718:805))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_446I/CE (632:718:805)
+          (632:718:805))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_446I/CE (632:718:805)
+          (632:718:805))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_447I/CE (518:597:676)
+          (518:597:676))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_447I/CE (518:597:676)
+          (518:597:676))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_448I/CE (518:597:676)
+          (518:597:676))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_448I/CE (518:597:676)
+          (518:597:676))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_449I/CE (757:851:945)
+          (757:851:945))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_450I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_450I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_451I/CE (780:870:960)
+          (780:870:960))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_451I/CE (780:870:960)
+          (780:870:960))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_452I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_452I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_453I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_453I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_454I/CE (1057:1179:1302)
+          (1057:1179:1302))
+        (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_455I/CE (1122:1258:1395)
+          (1122:1258:1395))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/OFX0 
+          hades_tdc_bundle_inst_SLICE_455I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 
+          hades_tdc_bundle_inst_SLICE_456I/D0 (483:561:639)(483:561:639))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 
+          hades_tdc_bundle_inst_SLICE_458I/M0 (375:435:495)(375:435:495))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 
+          hades_tdc_bundle_inst_SLICE_710I/C0 (400:512:625)(400:512:625))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 SLICE_740I/C0 (378:499:621)
+          (378:499:621))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 hades_hit_valid_1_I/PADDO 
+          (851:951:1052)(851:951:1052))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 
+          hades_tdc_bundle_inst_SLICE_456I/C0 (120:200:281)(120:200:281))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 
+          hades_tdc_bundle_inst_SLICE_458I/B1 (651:746:842)(651:746:842))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 
+          hades_tdc_bundle_inst_SLICE_458I/B0 (651:746:842)(651:746:842))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 
+          hades_tdc_bundle_inst_SLICE_710I/D1 (362:423:484)(362:423:484))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 hades_drop_cmp_buf_validI/PADDO 
+          (1045:1188:1332)(1045:1188:1332))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/F0 
+          hades_tdc_bundle_inst_SLICE_456I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/D1 (200:237:274)(200:237:274))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/C0 (123:206:290)(123:206:290))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 
+          hades_tdc_bundle_inst_SLICE_654I/C0 (389:509:629)(389:509:629))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 hades_hit_valid_0_I/PADDO 
+          (984:1099:1214)(984:1099:1214))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/B0 (977:1118:1259)(977:1118:1259))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/D1 (929:1055:1181)(929:1055:1181))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/D1 (799:913:1027)(799:913:1027))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_628I/C1 (537:668:800)(537:668:800))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_628I/C0 (537:668:800)(537:668:800))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_693I/D1 (512:588:665)(512:588:665))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 
+          hades_tdc_bundle_inst_SLICE_693I/D0 (512:588:665)(512:588:665))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_457I/A0 (667:780:893)(667:780:893))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/B1 (794:906:1018)(794:906:1018))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/A1 (537:638:740)(537:638:740))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_628I/D1 (211:251:292)(211:251:292))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_628I/A0 (380:458:536)(380:458:536))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_693I/B1 (394:464:535)(394:464:535))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 
+          hades_tdc_bundle_inst_SLICE_693I/B0 (394:464:535)(394:464:535))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/OFX0 
+          hades_tdc_bundle_inst_SLICE_457I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_457I/M0 (623:702:782)(623:702:782))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_459I/M0 (623:702:782)(623:702:782))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_460I/M0 (493:561:629)(493:561:629))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_628I/A1 (262:322:382)(262:322:382))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_693I/C1 (226:316:406)(226:316:406))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 
+          hades_tdc_bundle_inst_SLICE_693I/C0 (226:316:406)(226:316:406))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F1 
+          hades_tdc_bundle_inst_SLICE_458I/A0 (767:878:989)(767:878:989))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/OFX0 
+          hades_tdc_bundle_inst_SLICE_458I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/A1 (368:443:518)(368:443:518))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 
+          hades_tdc_bundle_inst_SLICE_459I/D0 (98:126:154)(98:126:154))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 
+          hades_tdc_bundle_inst_SLICE_710I/B0 (547:641:736)(547:641:736))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 hades_hit_valid_2_I/PADDO 
+          (984:1099:1214)(984:1099:1214))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/OFX0 
+          hades_tdc_bundle_inst_SLICE_459I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/C1 (225:317:410)(225:317:410))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 
+          hades_tdc_bundle_inst_SLICE_460I/D0 (98:126:154)(98:126:154))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 
+          hades_tdc_bundle_inst_SLICE_683I/A0 (645:754:863)(645:754:863))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 hades_hit_valid_3_I/PADDO 
+          (755:847:940)(755:847:940))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/OFX0 
+          hades_tdc_bundle_inst_SLICE_460I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/M1 (206:233:261)
+          (206:233:261))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q0 
+          hades_invalid_dl_1_I/PADDO (1011:1130:1249)(1011:1130:1249))
+        (INTERCONNECT hades_lvl1_invalid_MGIOLI/INFF 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/M0 (1212:1349:1486)
+          (1212:1349:1486))
+        (INTERCONNECT hades_lvl1_invalid_MGIOLI/INFF hades_invalid_dl_0_I/PADDO 
+          (490:550:610)(490:550:610))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/D0 (212:250:288)
+          (212:250:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/C1 (381:494:608)
+          (381:494:608))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/C0 (381:494:608)
+          (381:494:608))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/B1 (523:607:692)
+          (523:607:692))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/B0 (523:607:692)
+          (523:607:692))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/A1 (774:891:1008)
+          (774:891:1008))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/A0 (774:891:1008)
+          (774:891:1008))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/A0 (509:601:693)
+          (509:601:693))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/CE (484:544:605)
+          (484:544:605))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/D0 
+          (220:263:306)(220:263:306))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_8_MGIOLI/CE (1066:1186:1307)(1066:1186:1307))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_7_MGIOLI/CE (967:1102:1237)(967:1102:1237))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_6_MGIOLI/CE (1196:1328:1460)(1196:1328:1460))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_5_MGIOLI/CE (1052:1164:1276)(1052:1164:1276))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_4_MGIOLI/CE (1066:1186:1307)(1066:1186:1307))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_3_MGIOLI/CE (1066:1186:1307)(1066:1186:1307))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_2_MGIOLI/CE (1103:1252:1402)(1103:1252:1402))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_1_MGIOLI/CE (1103:1252:1402)(1103:1252:1402))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 
+          hades_offset_0_MGIOLI/CE (1097:1243:1390)(1097:1243:1390))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/Q0 
+          hades_offset_validI/PADDO (2204:2432:2661)(2204:2432:2661))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/Q0 
+          hades_raw_out_valid_MGIOLI/TXDATA0 (2050:2267:2485)(2050:2267:2485))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/M1 
+          (747:836:925)(747:836:925))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/M0 
+          (679:770:861)(679:770:861))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/Q0 
+          hades_offset_0_MGIOLI/TXDATA0 (822:916:1010)(822:916:1010))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/Q1 
+          hades_offset_1_MGIOLI/TXDATA0 (868:964:1061)(868:964:1061))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/M0 
+          (768:847:927)(768:847:927))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/Q0 
+          hades_offset_2_MGIOLI/TXDATA0 (864:980:1097)(864:980:1097))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/M1 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/M0 (462:512:562)
+          (462:512:562))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CE 
+          (1079:1190:1302)(1079:1190:1302))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CE 
+          (1079:1190:1302)(1079:1190:1302))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CE 
+          (846:936:1027)(846:936:1027))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CE 
+          (846:936:1027)(846:936:1027))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CE 
+          (825:916:1008)(825:916:1008))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CE 
+          (825:916:1008)(825:916:1008))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CE 
+          (955:1058:1161)(955:1058:1161))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CE 
+          (955:1058:1161)(955:1058:1161))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CE (655:730:806)
+          (655:730:806))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CE (655:730:806)
+          (655:730:806))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CE 
+          (955:1058:1161)(955:1058:1161))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CE 
+          (955:1058:1161)(955:1058:1161))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CE 
+          (825:916:1008)(825:916:1008))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CE 
+          (825:916:1008)(825:916:1008))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/CE 
+          (825:916:1008)(825:916:1008))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CE (346:391:437)
+          (346:391:437))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CE (655:730:806)
+          (655:730:806))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CE (655:730:806)
+          (655:730:806))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/CE (785:872:960)
+          (785:872:960))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/DI0 (4:8:12)
+          (4:8:12))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/Q0 
+          hades_dbg2_out_0_MGIOLI/TXDATA0 (752:861:971)(752:861:971))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/Q1 
+          hades_dbg2_out_1_MGIOLI/TXDATA0 (593:693:793)(593:693:793))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/M0 (609:679:750)
+          (609:679:750))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/Q0 
+          hades_dbg2_out_2_MGIOLI/TXDATA0 (407:470:534)(407:470:534))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/Q1 
+          hades_dbg2_out_16_MGIOLI/TXDATA0 (407:470:534)(407:470:534))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/M1 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/Q0 
+          hades_dbg2_out_17_MGIOLI/TXDATA0 (705:812:919)(705:812:919))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/Q1 
+          hades_dbg2_out_18_MGIOLI/TXDATA0 (706:813:920)(706:813:920))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/Q0 
+          hades_dbg2_out_20_MGIOLI/TXDATA0 (966:1096:1226)(966:1096:1226))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/Q1 
+          hades_dbg2_out_21_MGIOLI/TXDATA0 (868:1008:1148)(868:1008:1148))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/M0 (334:374:415)
+          (334:374:415))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/C0 (654:782:911)
+          (654:782:911))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/Q0 
+          hades_dbg2_out_22_MGIOLI/TXDATA0 (822:916:1010)(822:916:1010))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/Q1 
+          hades_dbg2_out_23_MGIOLI/TXDATA0 (910:1029:1149)(910:1029:1149))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/M0 
+          (931:1023:1115)(931:1023:1115))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q1 
+          hades_tdc_bundle_inst_SLICE_698I/A0 (688:792:897)(688:792:897))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/Q0 
+          hades_dbg2_out_24_MGIOLI/TXDATA0 (996:1129:1262)(996:1129:1262))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/Q1 
+          hades_dbg2_out_25_MGIOLI/TXDATA0 (1001:1144:1288)(1001:1144:1288))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/M1 (231:266:302)
+          (231:266:302))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/M0 (722:795:869)
+          (722:795:869))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/Q0 
+          hades_dbg2_out_26_MGIOLI/TXDATA0 (1011:1145:1279)(1011:1145:1279))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/Q1 
+          hades_dbg2_out_27_MGIOLI/TXDATA0 (506:580:654)(506:580:654))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/M0 (360:408:456)
+          (360:408:456))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/Q0 
+          hades_dbg2_out_28_MGIOLI/TXDATA0 (592:692:792)(592:692:792))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/M1 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/M0 
+          (488:545:602)(488:545:602))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/M1 
+          (488:545:602)(488:545:602))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/M1 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/M0 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/M0 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/M1 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/M1 
+          (378:426:475)(378:426:475))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/M0 
+          (361:401:441)(361:401:441))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/M0 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/M1 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/M1 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/M0 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/M0 
+          (515:570:625)(515:570:625))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/M1 
+          (515:570:625)(515:570:625))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/M0 
+          (635:712:789)(635:712:789))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/M1 
+          (635:712:789)(635:712:789))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/M0 
+          (511:579:647)(511:579:647))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/M1 
+          (409:467:526)(409:467:526))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/M0 
+          (488:550:612)(488:550:612))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/M1 
+          (488:550:612)(488:550:612))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/M1 
+          (337:378:419)(337:378:419))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/B0 
+          (397:464:531)(397:464:531))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/C0 
+          (243:338:434)(243:338:434))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/A0 
+          (499:583:668)(499:583:668))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/A1 
+          (505:593:681)(505:593:681))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/A0 
+          (505:593:681)(505:593:681))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/D0 
+          (337:388:439)(337:388:439))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/C0 
+          (351:450:550)(351:450:550))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/D1 
+          (337:388:439)(337:388:439))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/D0 
+          (337:388:439)(337:388:439))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/C1 
+          (250:352:454)(250:352:454))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/A0 
+          (521:622:723)(521:622:723))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/C0 
+          (250:352:454)(250:352:454))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/B1 
+          (408:488:568)(408:488:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/B0 
+          (408:488:568)(408:488:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/C1 
+          (250:352:454)(250:352:454))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/C0 
+          (250:352:454)(250:352:454))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/A1 
+          (385:461:538)(385:461:538))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/A1 
+          (385:461:538)(385:461:538))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/D1 
+          (205:241:277)(205:241:277))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/D0 
+          (205:241:277)(205:241:277))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/D0 
+          (205:241:277)(205:241:277))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/D1 
+          (217:258:299)(217:258:299))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/D1 
+          (217:258:299)(217:258:299))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/A1 
+          (394:481:569)(394:481:569))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/A0 
+          (394:481:569)(394:481:569))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/A0 
+          (394:481:569)(394:481:569))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/B1 
+          (414:492:571)(414:492:571))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/B0 
+          (414:492:571)(414:492:571))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/B1 
+          (414:492:571)(414:492:571))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/C1 
+          (368:479:590)(368:479:590))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/B1 
+          (414:492:571)(414:492:571))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/B0 
+          (414:492:571)(414:492:571))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/C0 
+          (515:641:768)(515:641:768))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/D0 
+          (355:411:468)(355:411:468))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/M0 
+          (501:569:637)(501:569:637))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/C0 
+          (380:491:603)(380:491:603))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/C0 
+          (216:299:382)(216:299:382))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/D0 
+          (214:257:301)(214:257:301))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/B0 
+          (276:327:379)(276:327:379))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/B0 
+          (391:455:520)(391:455:520))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/A0 
+          (258:314:370)(258:314:370))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/LSR 
+          (751:833:915)(751:833:915))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/LSR 
+          (361:408:455)(361:408:455))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/LSR 
+          (751:833:915)(751:833:915))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/LSR 
+          (751:833:915)(751:833:915))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/M0 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/C1 
+          (114:188:262)(114:188:262))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/M0 
+          (1020:1122:1225)(1020:1122:1225))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/M0 
+          (1252:1375:1499)(1252:1375:1499))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/M1 
+          (493:559:626)(493:559:626))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/M1 
+          (243:279:315)(243:279:315))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/M1 
+          (350:399:448)(350:399:448))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/M1 
+          (344:390:436)(344:390:436))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/M1 
+          (623:701:779)(623:701:779))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/M1 
+          (350:399:448)(350:399:448))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/M1 
+          (623:701:779)(623:701:779))
+        (INTERCONNECT SLICE_743I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/M1 
+          (493:559:626)(493:559:626))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/Q1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/M1 (203:227:251)
+          (203:227:251))
+        (INTERCONNECT hades_lvl1_MGIOLI/INFF 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/M0 (690:764:838)
+          (690:764:838))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/D1 (344:393:442)
+          (344:393:442))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/A0 (494:576:658)
+          (494:576:658))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/D0 (327:375:423)
+          (327:375:423))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/D1 (483:556:630)
+          (483:556:630))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/C0 (396:517:639)
+          (396:517:639))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/C0 
+          (554:685:816)(554:685:816))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/C0 
+          (120:200:281)(120:200:281))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/LSR (363:421:480)
+          (363:421:480))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/LSR (602:676:750)
+          (602:676:750))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/LSR (602:676:750)
+          (602:676:750))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/DI0 (6:11:17)(6:11:17))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/LSR (337:377:418)
+          (337:377:418))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/LSR (337:377:418)
+          (337:377:418))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/LSR (337:377:418)
+          (337:377:418))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/LSR (337:377:418)
+          (337:377:418))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/LSR (331:365:400)
+          (331:365:400))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/M0 (380:431:482)
+          (380:431:482))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/A1 (382:461:541)
+          (382:461:541))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/M0 (626:700:775)
+          (626:700:775))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q1 
+          hades_tdc_bundle_inst_SLICE_681I/D0 (217:260:304)(217:260:304))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/M0 (389:435:482)
+          (389:435:482))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/D0 (220:269:319)
+          (220:269:319))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/C0 (242:341:441)
+          (242:341:441))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/A0 (368:443:518)
+          (368:443:518))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/C0 
+          (836:986:1137)(836:986:1137))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/C0 (372:479:587)
+          (372:479:587))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/A0 (363:431:500)
+          (363:431:500))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/B0 (773:873:974)
+          (773:873:974))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CE (335:373:412)
+          (335:373:412))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CE (335:373:412)
+          (335:373:412))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CE (471:532:593)
+          (471:532:593))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CE (471:532:593)
+          (471:532:593))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CE (651:724:797)
+          (651:724:797))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CE (651:724:797)
+          (651:724:797))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CE (651:724:797)
+          (651:724:797))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CE (651:724:797)
+          (651:724:797))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CE (488:549:610)
+          (488:549:610))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CE (488:549:610)
+          (488:549:610))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CE (363:419:476)
+          (363:419:476))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CE (363:419:476)
+          (363:419:476))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/M0 (461:518:576)
+          (461:518:576))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/D0 (676:753:831)
+          (676:753:831))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/D0 
+          (93:114:136)(93:114:136))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/M1 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/M0 (332:370:409)
+          (332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CE (231:266:301)
+          (231:266:301))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CE (231:266:301)
+          (231:266:301))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CE (491:549:608)
+          (491:549:608))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CE (491:549:608)
+          (491:549:608))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CE (814:898:982)
+          (814:898:982))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CE (814:898:982)
+          (814:898:982))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CE (814:898:982)
+          (814:898:982))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CE (814:898:982)
+          (814:898:982))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CE (541:608:676)
+          (541:608:676))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CE (541:608:676)
+          (541:608:676))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CE (378:433:488)
+          (378:433:488))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CE (378:433:488)
+          (378:433:488))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/M0 (231:259:288)
+          (231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/D0 (647:731:816)
+          (647:731:816))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/D0 
+          (93:114:136)(93:114:136))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/DI0 (0:0:0)
+          (0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/M1 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/M0 
+          (361:401:441)(361:401:441))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/M1 
+          (609:679:750)(609:679:750))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/M0 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/M0 
+          (361:401:441)(361:401:441))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/M1 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/M1 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/M0 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/M1 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/M0 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/M1 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/M1 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/M1 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/M1 
+          (208:235:263)(208:235:263))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/C0 
+          (222:308:394)(222:308:394))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/B0 
+          (520:601:682)(520:601:682))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/D0 
+          (214:251:289)(214:251:289))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/C1 
+          (362:468:575)(362:468:575))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/A0 
+          (505:594:683)(505:594:683))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/C0 
+          (359:464:570)(359:464:570))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/C0 
+          (359:464:570)(359:464:570))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/B1 
+          (405:478:551)(405:478:551))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/B0 
+          (405:478:551)(405:478:551))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/B1 
+          (549:642:735)(549:642:735))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/D0 
+          (231:279:328)(231:279:328))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/B0 
+          (549:642:735)(549:642:735))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/D1 
+          (231:279:328)(231:279:328))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/D0 
+          (231:279:328)(231:279:328))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/D1 
+          (231:279:328)(231:279:328))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/D0 
+          (231:279:328)(231:279:328))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/D1 
+          (469:533:598)(469:533:598))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/B1 
+          (409:485:561)(409:485:561))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/B1 
+          (409:485:561)(409:485:561))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/B0 
+          (409:485:561)(409:485:561))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/C0 
+          (381:494:607)(381:494:607))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/C1 
+          (242:344:446)(242:344:446))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/A1 
+          (397:487:578)(397:487:578))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/A1 
+          (397:487:578)(397:487:578))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/A0 
+          (397:487:578)(397:487:578))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/A0 
+          (366:437:509)(366:437:509))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/A1 
+          (517:615:713)(517:615:713))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/A0 
+          (674:795:917)(674:795:917))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/C1 
+          (648:798:948)(648:798:948))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/C1 
+          (648:798:948)(648:798:948))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/A1 
+          (674:795:917)(674:795:917))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/B0 
+          (405:481:558)(405:481:558))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/D0 
+          (334:384:435)(334:384:435))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/C0 
+          (247:345:444)(247:345:444))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/M0 
+          (244:281:318)(244:281:318))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/D0 
+          (334:384:435)(334:384:435))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/B0 
+          (374:431:489)(374:431:489))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/C0 
+          (236:331:427)(236:331:427))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/B0 
+          (394:464:534)(394:464:534))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/A0 
+          (261:320:380)(261:320:380))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/A0 
+          (261:320:380)(261:320:380))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/LSR 
+          (336:373:411)(336:373:411))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/LSR 
+          (336:373:411)(336:373:411))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/LSR 
+          (336:373:411)(336:373:411))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/LSR 
+          (336:373:411)(336:373:411))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/M0 
+          (536:594:653)(536:594:653))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/OFX0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/M1 
+          (462:512:562)(462:512:562))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/D1 
+          (89:107:126)(89:107:126))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/OFX0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/OFX0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/M1 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/M0 
+          (461:518:576)(461:518:576))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/M1 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/M0 
+          (461:518:576)(461:518:576))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/M1 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/M1 
+          (479:537:596)(479:537:596))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/M0 
+          (592:653:715)(592:653:715))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/M1 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/M1 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/M0 
+          (360:408:456)(360:408:456))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/M1 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/M1 
+          (231:266:302)(231:266:302))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/M1 
+          (208:235:263)(208:235:263))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/C0 
+          (222:308:394)(222:308:394))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/C1 
+          (242:338:434)(242:338:434))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/C0 
+          (242:338:434)(242:338:434))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/D0 
+          (195:225:256)(195:225:256))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/B1 
+          (516:595:674)(516:595:674))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/B0 
+          (516:595:674)(516:595:674))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/A1 
+          (389:468:548)(389:468:548))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/B0 
+          (377:436:495)(377:436:495))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/D1 
+          (226:272:318)(226:272:318))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/D0 
+          (226:272:318)(226:272:318))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/D1 
+          (226:272:318)(226:272:318))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/D0 
+          (226:272:318)(226:272:318))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/A0 
+          (363:431:500)(363:431:500))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/D0 
+          (337:389:441)(337:389:441))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/B1 
+          (408:482:557)(408:482:557))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/B0 
+          (408:482:557)(408:482:557))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/D0 
+          (467:530:594)(467:530:594))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/C0 
+          (219:303:388)(219:303:388))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/C0 
+          (246:345:444)(246:345:444))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/C1 
+          (246:345:444)(246:345:444))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/C0 
+          (246:345:444)(246:345:444))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/A0 
+          (389:473:557)(389:473:557))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/C0 
+          (648:796:945)(648:796:945))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/A1 
+          (397:482:568)(397:482:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/A0 
+          (397:482:568)(397:482:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/A0 
+          (397:482:568)(397:482:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/B0 
+          (377:436:495)(377:436:495))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/A0 
+          (397:482:568)(397:482:568))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/D0 
+          (359:418:478)(359:418:478))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/A1 
+          (512:599:686)(512:599:686))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/C0 
+          (238:331:424)(238:331:424))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/D0 
+          (191:218:246)(191:218:246))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/D1 
+          (191:218:246)(191:218:246))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/B1 
+          (278:333:388)(278:333:388))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/B0 
+          (278:333:388)(278:333:388))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/B0 
+          (278:333:388)(278:333:388))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/D0 
+          (208:243:278)(208:243:278))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/C0 
+          (238:335:433)(238:335:433))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/A0 
+          (363:429:496)(363:429:496))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/A0 
+          (380:457:535)(380:457:535))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/F1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/DI1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/LSR 
+          (619:683:748)(619:683:748))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/LSR 
+          (619:683:748)(619:683:748))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/LSR 
+          (619:683:748)(619:683:748))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/LSR 
+          (619:683:748)(619:683:748))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/M1 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/OFX0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/DI0 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/M0 
+          (332:370:409)(332:370:409))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/M0 
+          (231:259:288)(231:259:288))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/M1 
+          (541:613:685)(541:613:685))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/M1 
+          (494:561:628)(494:561:628))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/M1 
+          (494:561:628)(494:561:628))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/M1 
+          (392:448:505)(392:448:505))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/M1 
+          (541:613:685)(541:613:685))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/M1 
+          (643:724:805)(643:724:805))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/M1 
+          (494:560:626)(494:560:626))
+        (INTERCONNECT SLICE_747I/F0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/M1 
+          (541:613:685)(541:613:685))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/M1 
+          (568:641:715)(568:641:715))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/M1 
+          (568:641:715)(568:641:715))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/M1 
+          (703:791:880)(703:791:880))
+        (INTERCONNECT hades_trigI/PADDI SLICE_747I/A0 (872:1002:1133)(872:1002:1133))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/Q1 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/Q0 
+          hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/F1 
+          hades_tdc_bundle_inst_SLICE_628I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/F0 
+          hades_tdc_bundle_inst_SLICE_628I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/B1 (523:609:695)
+          (523:609:695))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/A0 (388:471:554)
+          (388:471:554))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/C1 (244:345:446)
+          (244:345:446))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/OFX0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/Q0 
+          hades_tdc_bundle_inst_SLICE_741I/C0 (894:1044:1195)(894:1044:1195))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/Q0 
+          hades_window_endI/PADDO (2102:2316:2531)(2102:2316:2531))
+        (INTERCONNECT LVL1_TRG_DATA_VALID_IN_MGIOLI/INFF trb_adapter_inst_SLICE_631I/M0 
+          (3148:3448:3749)(3148:3448:3749))
+        (INTERCONNECT trb_adapter_inst_SLICE_632I/Q0 trb_adapter_inst_SLICE_724I/M0 
+          (203:227:251)(203:227:251))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 trb_adapter_inst_SLICE_633I/M0 
+          (369:423:478)(369:423:478))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 trb_adapter_inst_SLICE_724I/A0 
+          (389:473:557)(389:473:557))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 finishedI/PADDO (797:901:1006)
+          (797:901:1006))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 FEE_DATAFINISHED_OUT_MGIOLI/TXDATA0 
+          (367:427:488)(367:427:488))
+        (INTERCONNECT trb_adapter_inst_SLICE_633I/Q0 trb_adapter_inst_SLICE_724I/B0 
+          (374:431:489)(374:431:489))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/M0 (207:234:262)
+          (207:234:262))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/M0 (207:234:262)
+          (207:234:262))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/C1 (237:331:425)
+          (237:331:425))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 
+          genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/M0 (364:415:467)
+          (364:415:467))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/M0 (334:374:415)
+          (334:374:415))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/C1 (501:640:780)
+          (501:640:780))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 
+          genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/B1 (403:478:553)
+          (403:478:553))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/M0 (464:523:583)
+          (464:523:583))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/A1 (388:471:554)
+          (388:471:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/A1 (388:471:554)
+          (388:471:554))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/M0 (207:234:262)
+          (207:234:262))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 
+          genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/C1 (118:195:273)
+          (118:195:273))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_648I/M0 (235:267:299)(235:267:299))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_677I/C1 (118:195:273)(118:195:273))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_678I/C1 (118:195:273)(118:195:273))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_653I/OFX0 hades_buf_out_valid_MGIOLI/CE 
+          (261:306:351)(261:306:351))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_710I/F0 
+          hades_tdc_bundle_inst_SLICE_654I/D1 (321:362:404)(321:362:404))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_654I/F1 
+          hades_tdc_bundle_inst_SLICE_654I/D0 (191:218:246)(191:218:246))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_654I/F0 
+          hades_tdc_bundle_inst_SLICE_683I/D0 (89:107:126)(89:107:126))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_673I/B1 (379:440:501)(379:440:501))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_674I/C1 (118:195:273)(118:195:273))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 
+          fifo_colector_inst_fifo40_inst_SLICE_702I/C0 (118:195:273)(118:195:273))
+        (INTERCONNECT fifo_colector_inst_SLICE_680I/F1 fifo_colector_inst_SLICE_680I/A0 
+          (258:314:370)(258:314:370))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_683I/F1 
+          hades_tdc_bundle_inst_SLICE_683I/B0 (272:320:369)(272:320:369))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_683I/F0 
+          hades_buf_out_valid_MGIOLI/TXDATA0 (592:692:792)(592:692:792))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F1 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/B0 
+          (391:455:520)(391:455:520))
+        (INTERCONNECT hades_tdc_bundle_inst_SLICE_710I/F1 hades_buf_drop_1_MGIOLI/TXDATA0 
+          (752:861:971)(752:861:971))
+        (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/Q0 
+          genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/D0 (191:218:246)(191:218:246))
+        (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/Q0 
+          genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/D0 (191:218:246)(191:218:246))
+        (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/Q0 
+          genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/D0 (89:107:126)(89:107:126))
+        (INTERCONNECT trb_adapter_inst_SLICE_723I/F0 LVL1_TRG_DATA_VALI_IN_risingI/PADDO 
+          (512:577:643)(512:577:643))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/F0 release_outI/PADDO (534:611:688)
+          (534:611:688))
+        (INTERCONNECT trb_adapter_inst_SLICE_724I/F0 FEE_TRG_RELEASE_OUT_MGIOLI/TXDATA0 
+          (641:730:819)(641:730:819))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_8_MGIOLI/LSR (1055:1166:1277)(1055:1166:1277))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_7_MGIOLI/LSR (1078:1215:1353)(1078:1215:1353))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_6_MGIOLI/LSR (1164:1278:1393)(1164:1278:1393))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_5_MGIOLI/LSR (1204:1319:1435)(1204:1319:1435))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_4_MGIOLI/LSR (1164:1280:1396)(1164:1280:1396))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_3_MGIOLI/LSR (1164:1280:1396)(1164:1280:1396))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_2_MGIOLI/LSR (975:1111:1247)(975:1111:1247))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_1_MGIOLI/LSR (969:1102:1236)(969:1102:1236))
+        (INTERCONNECT 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 
+          hades_offset_0_MGIOLI/LSR (975:1111:1247)(975:1111:1247))
+        (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/F0 
+          hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/D0 
+          (211:251:291)(211:251:291))
+        (INTERCONNECT reset_dc_MGIOLI/INFF SLICE_740I/M0 (890:996:1103)(890:996:1103))
+        (INTERCONNECT pll0inst_SLICE_742I/F0 pll0inst_PLLInst_0I/STDBY (369:416:463)
+          (369:416:463))
+        (INTERCONNECT hades_lvl1I/PADDI SLICE_743I/D0 (723:821:919)(723:821:919))
+        (INTERCONNECT hades_lvl1I/PADDI hades_lvl1_MGIOLI/DI (21:21:22)(21:21:22))
+        (INTERCONNECT trig_0_I/PADDI SLICE_744I/D0 (330:373:416)(330:373:416))
+        (INTERCONNECT trig_1_I/PADDI SLICE_745I/D0 (1230:1366:1503)(1230:1366:1503))
+        (INTERCONNECT trig_2_I/PADDI SLICE_746I/D0 (1480:1613:1747)(1480:1613:1747))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA0 
+          fifo_data_out_0_I/PADDO (2121:2332:2543)(2121:2332:2543))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA0 
+          FEE_DATA_OUT_0_I/PADDO (2312:2542:2772)(2312:2542:2772))
+        (INTERCONNECT clkI/PADDI pll0inst_PLLInst_0I/CLKI (56:56:56)(56:56:56))
+        (INTERCONNECT hades_dbg2_out_28_MGIOLI/IOLDO hades_dbg2_out_28_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_27_MGIOLI/IOLDO hades_dbg2_out_27_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_26_MGIOLI/IOLDO hades_dbg2_out_26_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_25_MGIOLI/IOLDO hades_dbg2_out_25_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_24_MGIOLI/IOLDO hades_dbg2_out_24_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_23_MGIOLI/IOLDO hades_dbg2_out_23_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_22_MGIOLI/IOLDO hades_dbg2_out_22_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_21_MGIOLI/IOLDO hades_dbg2_out_21_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_20_MGIOLI/IOLDO hades_dbg2_out_20_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_18_MGIOLI/IOLDO hades_dbg2_out_18_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_17_MGIOLI/IOLDO hades_dbg2_out_17_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_16_MGIOLI/IOLDO hades_dbg2_out_16_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_2_MGIOLI/IOLDO hades_dbg2_out_2_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_1_MGIOLI/IOLDO hades_dbg2_out_1_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_dbg2_out_0_MGIOLI/IOLDO hades_dbg2_out_0_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_buf_drop_1_MGIOLI/IOLDO hades_buf_drop_1_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_buf_out_valid_MGIOLI/IOLDO hades_buf_out_validI/IOLDO 
+          (23:23:23)(23:23:23))
+        (INTERCONNECT hades_offset_8_MGIOLI/IOLDO hades_offset_8_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_7_MGIOLI/IOLDO hades_offset_7_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_6_MGIOLI/IOLDO hades_offset_6_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_5_MGIOLI/IOLDO hades_offset_5_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_4_MGIOLI/IOLDO hades_offset_4_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_3_MGIOLI/IOLDO hades_offset_3_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_2_MGIOLI/IOLDO hades_offset_2_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_1_MGIOLI/IOLDO hades_offset_1_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_offset_0_MGIOLI/IOLDO hades_offset_0_I/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT hades_lvl1_invalidI/PADDI hades_lvl1_invalid_MGIOLI/DI (69:71:74)
+          (69:71:74))
+        (INTERCONNECT hades_raw_out_valid_MGIOLI/IOLDO hades_raw_out_validI/IOLDO 
+          (23:23:23)(23:23:23))
+        (INTERCONNECT FEE_TRG_RELEASE_OUT_MGIOLI/IOLDO FEE_TRG_RELEASE_OUTI/IOLDO 
+          (23:23:23)(23:23:23))
+        (INTERCONNECT FEE_DATAFINISHED_OUT_MGIOLI/IOLDO FEE_DATAFINISHED_OUTI/IOLDO 
+          (23:23:23)(23:23:23))
+        (INTERCONNECT FEE_DATA_WRITE_OUT_MGIOLI/IOLDO FEE_DATA_WRITE_OUTI/IOLDO (23:23:23)
+          (23:23:23))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB13 
+          FEE_DATA_OUT_31_I/PADDO (2203:2425:2648)(2203:2425:2648))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB13 
+          fifo_data_out_31_I/PADDO (2334:2567:2801)(2334:2567:2801))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB12 
+          FEE_DATA_OUT_30_I/PADDO (2209:2426:2643)(2209:2426:2643))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB12 
+          fifo_data_out_30_I/PADDO (2209:2426:2643)(2209:2426:2643))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB11 
+          FEE_DATA_OUT_29_I/PADDO (2229:2456:2684)(2229:2456:2684))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB11 
+          fifo_data_out_29_I/PADDO (2229:2456:2684)(2229:2456:2684))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB10 
+          FEE_DATA_OUT_28_I/PADDO (2301:2531:2761)(2301:2531:2761))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB10 
+          fifo_data_out_28_I/PADDO (2431:2672:2914)(2431:2672:2914))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB9 
+          FEE_DATA_OUT_27_I/PADDO (2373:2594:2816)(2373:2594:2816))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB9 
+          fifo_data_out_27_I/PADDO (2373:2594:2816)(2373:2594:2816))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB8 
+          FEE_DATA_OUT_26_I/PADDO (2209:2433:2658)(2209:2433:2658))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB8 
+          fifo_data_out_26_I/PADDO (2340:2575:2811)(2340:2575:2811))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB7 
+          FEE_DATA_OUT_25_I/PADDO (2363:2594:2826)(2363:2594:2826))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB7 
+          fifo_data_out_25_I/PADDO (2363:2594:2826)(2363:2594:2826))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB6 
+          FEE_DATA_OUT_24_I/PADDO (2025:2217:2409)(2025:2217:2409))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB6 
+          fifo_data_out_24_I/PADDO (2225:2449:2674)(2225:2449:2674))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB5 
+          FEE_DATA_OUT_23_I/PADDO (2053:2243:2433)(2053:2243:2433))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB5 
+          fifo_data_out_23_I/PADDO (2053:2243:2433)(2053:2243:2433))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB4 
+          FEE_DATA_OUT_22_I/PADDO (2200:2430:2661)(2200:2430:2661))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB4 
+          fifo_data_out_22_I/PADDO (2358:2598:2839)(2358:2598:2839))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB3 
+          FEE_DATA_OUT_21_I/PADDO (2034:2219:2405)(2034:2219:2405))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB3 
+          fifo_data_out_21_I/PADDO (1922:2100:2279)(1922:2100:2279))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB2 
+          FEE_DATA_OUT_20_I/PADDO (2319:2571:2824)(2319:2571:2824))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB2 
+          fifo_data_out_20_I/PADDO (2477:2739:3002)(2477:2739:3002))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB1 
+          FEE_DATA_OUT_19_I/PADDO (1846:2041:2237)(1846:2041:2237))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB1 
+          fifo_data_out_19_I/PADDO (1846:2041:2237)(1846:2041:2237))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB0 
+          FEE_DATA_OUT_18_I/PADDO (2286:2518:2751)(2286:2518:2751))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB0 
+          fifo_data_out_18_I/PADDO (2693:2969:3246)(2693:2969:3246))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA17 
+          FEE_DATA_OUT_17_I/PADDO (2275:2518:2761)(2275:2518:2761))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA17 
+          fifo_data_out_17_I/PADDO (2405:2659:2914)(2405:2659:2914))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA16 
+          FEE_DATA_OUT_16_I/PADDO (2647:2909:3171)(2647:2909:3171))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA16 
+          fifo_data_out_16_I/PADDO (2777:3050:3324)(2777:3050:3324))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA15 
+          FEE_DATA_OUT_15_I/PADDO (2094:2307:2521)(2094:2307:2521))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA15 
+          fifo_data_out_15_I/PADDO (1736:1907:2078)(1736:1907:2078))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA14 
+          FEE_DATA_OUT_14_I/PADDO (2174:2402:2630)(2174:2402:2630))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA14 
+          fifo_data_out_14_I/PADDO (2304:2543:2783)(2304:2543:2783))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA13 
+          FEE_DATA_OUT_13_I/PADDO (2403:2621:2840)(2403:2621:2840))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA13 
+          fifo_data_out_13_I/PADDO (2357:2573:2789)(2357:2573:2789))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA12 
+          FEE_DATA_OUT_12_I/PADDO (2018:2224:2430)(2018:2224:2430))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA12 
+          fifo_data_out_12_I/PADDO (2148:2365:2583)(2148:2365:2583))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA11 
+          FEE_DATA_OUT_11_I/PADDO (2042:2262:2483)(2042:2262:2483))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA11 
+          fifo_data_out_11_I/PADDO (2042:2262:2483)(2042:2262:2483))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA10 
+          FEE_DATA_OUT_10_I/PADDO (1765:1932:2100)(1765:1932:2100))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA10 
+          fifo_data_out_10_I/PADDO (1765:1932:2100)(1765:1932:2100))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA9 
+          FEE_DATA_OUT_9_I/PADDO (2042:2243:2444)(2042:2243:2444))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA9 
+          fifo_data_out_9_I/PADDO (2172:2384:2597)(2172:2384:2597))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA8 
+          FEE_DATA_OUT_8_I/PADDO (2083:2306:2530)(2083:2306:2530))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA8 
+          fifo_data_out_8_I/PADDO (2083:2306:2530)(2083:2306:2530))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA7 
+          FEE_DATA_OUT_7_I/PADDO (2418:2669:2920)(2418:2669:2920))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA7 
+          fifo_data_out_7_I/PADDO (2576:2837:3098)(2576:2837:3098))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA6 
+          FEE_DATA_OUT_6_I/PADDO (2433:2685:2938)(2433:2685:2938))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA6 
+          fifo_data_out_6_I/PADDO (2563:2827:3092)(2563:2827:3092))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA5 
+          FEE_DATA_OUT_5_I/PADDO (2561:2790:3019)(2561:2790:3019))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA5 
+          fifo_data_out_5_I/PADDO (2691:2931:3172)(2691:2931:3172))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA4 
+          FEE_DATA_OUT_4_I/PADDO (2391:2621:2851)(2391:2621:2851))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA4 
+          fifo_data_out_4_I/PADDO (2391:2621:2851)(2391:2621:2851))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA3 
+          FEE_DATA_OUT_3_I/PADDO (2077:2284:2492)(2077:2284:2492))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA3 
+          fifo_data_out_3_I/PADDO (2077:2284:2492)(2077:2284:2492))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA2 
+          FEE_DATA_OUT_2_I/PADDO (2390:2620:2850)(2390:2620:2850))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA2 
+          fifo_data_out_2_I/PADDO (2390:2620:2850)(2390:2620:2850))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA1 
+          FEE_DATA_OUT_1_I/PADDO (2345:2621:2898)(2345:2621:2898))
+        (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA1 
+          fifo_data_out_1_I/PADDO (2345:2621:2898)(2345:2621:2898))
+        (INTERCONNECT LVL1_INVALID_TRG_INI/PADDI LVL1_INVALID_TRG_IN_MGIOLI/DI (21:21:22)
+          (21:21:22))
+        (INTERCONNECT LVL1_TRG_DATA_VALID_INI/PADDI LVL1_TRG_DATA_VALID_IN_MGIOLI/DI 
+          (21:21:22)(21:21:22))
+        (INTERCONNECT reset_dcI/PADDI reset_dc_MGIOLI/DI (21:21:22)(21:21:22))
+      )
+    )
+  )
+)
diff --git a/impl1/s1_impl1_vho.vho b/impl1/s1_impl1_vho.vho
new file mode 100644
index 0000000..9c28730
--- /dev/null
+++ b/impl1/s1_impl1_vho.vho
@@ -0,0 +1,174140 @@
+
+-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.11.2.446
+
+-- ldbanno -n VHDL -o s1_impl1_vho.vho -noslice -w -neg -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd 
+-- Netlist created on Wed Jun 16 09:19:26 2021
+-- Netlist written on Wed Jun 16 09:20:42 2021
+-- Design is for device LFE5UM5G-45F
+-- Design is for package CABGA381
+-- Design is for performance grade 8
+
+-- entity ccu2B0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu2B0 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE;
+
+  end ccu2B0;
+
+  architecture Structure of ccu2B0 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"0000", INIT1 => X"66AA", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity gnd
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity gnd is
+    port (PWR0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
+
+  end gnd;
+
+  architecture Structure of gnd is
+  begin
+    INST1: VLO
+      port map (Z=>PWR0);
+  end Structure;
+
+-- entity vcc
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity vcc is
+    port (PWR1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
+
+  end vcc;
+
+  architecture Structure of vcc is
+  begin
+    INST1: VHI
+      port map (Z=>PWR1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity svmuxregsre
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity svmuxregsre is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF svmuxregsre : ENTITY IS TRUE;
+
+  end svmuxregsre;
+
+  architecture Structure of svmuxregsre is
+  begin
+    INST01: FL1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity svmuxregsre0001
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity svmuxregsre0001 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF svmuxregsre0001 : ENTITY IS TRUE;
+
+  end svmuxregsre0001;
+
+  architecture Structure of svmuxregsre0001 is
+  begin
+    INST01: FL1P3BX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity ccu20002
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20002 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE;
+
+  end ccu20002;
+
+  architecture Structure of ccu20002 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"CCCC", INIT1 => X"CCCC", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20003
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20003 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20003 : ENTITY IS TRUE;
+
+  end ccu20003;
+
+  architecture Structure of ccu20003 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"AAAA", INIT1 => X"AAAA", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20003
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20003
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20004
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20004 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20004 : ENTITY IS TRUE;
+
+  end ccu20004;
+
+  architecture Structure of ccu20004 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"CCCC", INIT1 => X"AAAA", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20005
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20005 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20005 : ENTITY IS TRUE;
+
+  end ccu20005;
+
+  architecture Structure of ccu20005 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"AAAA", INIT1 => X"CCCC", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20005
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20005
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20006
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20006 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20006 : ENTITY IS TRUE;
+
+  end ccu20006;
+
+  architecture Structure of ccu20006 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"99AA", INIT1 => X"99CC", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20007
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20007 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20007 : ENTITY IS TRUE;
+
+  end ccu20007;
+
+  architecture Structure of ccu20007 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"99CC", INIT1 => X"99AA", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20008
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20008 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20008 : ENTITY IS TRUE;
+
+  end ccu20008;
+
+  architecture Structure of ccu20008 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"99AA", INIT1 => X"99AA", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20009
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20009 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20009 : ENTITY IS TRUE;
+
+  end ccu20009;
+
+  architecture Structure of ccu20009 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"0000", INIT1 => X"0000", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20003
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20003
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20005
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20005
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20010
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20010 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20010 : ENTITY IS TRUE;
+
+  end ccu20010;
+
+  architecture Structure of ccu20010 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"99CC", INIT1 => X"99CC", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20010
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20010
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20005
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20005
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58"
+        );
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20003
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20003
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61"
+        ;
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20010
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20010
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77"
+        ;
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_78
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_78 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_78");
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_78 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_78;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_78 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_w_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_79
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_79 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_79";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_79 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_79;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_79 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_100: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_101: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_w_gctr_0: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_80
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_80 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_80";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_80 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_80;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_80 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20003
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_98: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_99: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_w_gctr_1: ccu20003
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_81
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_81 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_81";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_81 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_81;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_81 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_96: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_97: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_w_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_82
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_82 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_82";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_82 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_82;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_82 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_94: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_95: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_w_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_83
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_83 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_83";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_83 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_83;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_83 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_92: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_93: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_w_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_84
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_84 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_84");
+
+    port (FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_84 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_84;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_84 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_r_gctr_cia: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCO_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO 	<= FCO_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_85
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_85 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_85";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_85 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_85;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_85 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20005
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_70: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_71: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_r_gctr_0: ccu20005
+      port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_86
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_86 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_86";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_86 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_86;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_86 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_68: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_69: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_r_gctr_1: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_87
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_87 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_87";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_87 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_87;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_87 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20004
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_66: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_67: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_r_gctr_2: ccu20004
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_88
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_88 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_88";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_88 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_88;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_88 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_64: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_65: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_r_gctr_3: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_89
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_89 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_89";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_89 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_89;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_89 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20002
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_62: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_63: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    fifo_colector_inst_fifo40_inst_r_gctr_4: ccu20002
+      port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, 
+      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_90
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_90 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_90";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_90 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_90;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_90 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_91
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_91 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_91";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_91 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_91;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_91 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20010
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_0: ccu20010
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_92
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_92 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_92";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_92 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_92;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_92 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_1: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_93
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_93 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_93";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_93 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_93;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_93 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20008
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_2: ccu20008
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_94
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_94 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_94";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_94 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_94;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_94 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20010
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_3: ccu20010
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_95
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_95 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_95";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_95 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_95;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_95 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20010
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_empty_cmp_4: ccu20010
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_96
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_96 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_96";
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_96 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_96;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_96 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0001
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_1: svmuxregsre0001
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_a0: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_97
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_97 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_97";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_97 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_97;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_97 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component ccu2B0
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_ci_a: ccu2B0
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_98
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_98 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_98";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_98 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_98;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_98 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_0: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_99
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_99 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_99";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_99 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_99;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_99 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20006
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_1: ccu20006
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_100
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_100 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_100";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_100 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_100;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_100 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_2: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_101
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_101 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_101";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_101 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_101;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_101 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_3: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_102
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_102 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_102";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_102 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_102;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_102 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20007
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_full_cmp_4: ccu20007
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_103
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_103 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_103";
+
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_103 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_103;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_103 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component ccu20009
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_a1: ccu20009
+      port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20011
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20011 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20011 : ENTITY IS TRUE;
+
+  end ccu20011;
+
+  architecture Structure of ccu20011 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"5003", INIT1 => X"0000", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_104
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_104 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_104";
+
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (FCI: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_104 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_104;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_104 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20011
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid25_0_I_27_0: ccu20011
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCI_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20012
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20012 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20012 : ENTITY IS TRUE;
+
+  end ccu20012;
+
+  architecture Structure of ccu20012 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"500C", INIT1 => X"1842", INJECT1_0 => "NO", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20012
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_1_0: ccu20012
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, 
+                CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20013
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20013 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20013 : ENTITY IS TRUE;
+
+  end ccu20013;
+
+  architecture Structure of ccu20013 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"0069", INIT1 => X"0609", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    component ccu20013
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_0: ccu20013
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20014
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20014 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20014 : ENTITY IS TRUE;
+
+  end ccu20014;
+
+  architecture Structure of ccu20014 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"8007", INIT1 => X"070F", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    component ccu20014
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_21_0: ccu20014
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20015
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20015 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20015 : ENTITY IS TRUE;
+
+  end ccu20015;
+
+  architecture Structure of ccu20015 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"a003", INIT1 => X"0000", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108"
+        ;
+
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (FCI: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20015
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_0: ccu20015
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCI_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20012
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_1_0: ccu20012
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, 
+                CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20016
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20016 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20016 : ENTITY IS TRUE;
+
+  end ccu20016;
+
+  architecture Structure of ccu20016 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"0069", INIT1 => X"0069", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    component ccu20016
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0: ccu20016
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20017
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20017 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20017 : ENTITY IS TRUE;
+
+  end ccu20017;
+
+  architecture Structure of ccu20017 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"8007", INIT1 => X"007F", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    component ccu20017
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_21_0: ccu20017
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112"
+        ;
+
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (FCI: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20015
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_0: ccu20015
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (FCI_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20018
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20018 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20018 : ENTITY IS TRUE;
+
+  end ccu20018;
+
+  architecture Structure of ccu20018 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"5003", INIT1 => X"C90C", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20018
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0_0: ccu20018
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>C1_ipd, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, 
+                CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20019
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20019 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20019 : ENTITY IS TRUE;
+
+  end ccu20019;
+
+  architecture Structure of ccu20019 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"a90a", INIT1 => X"a90a", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20019
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0: ccu20019
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, 
+                S1=>F1_out, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      FCI_ipd, F0_out, F1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F1,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20019
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0: ccu20019
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, 
+                S1=>F1_out, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      FCI_ipd, F0_out, F1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F1,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20020
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20020 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20020 : ENTITY IS TRUE;
+
+  end ccu20020;
+
+  architecture Structure of ccu20020 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"C90C", INIT1 => X"C90C", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+          FCO: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20020
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0: ccu20020
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, 
+                S1=>F1_out, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      FCI_ipd, F0_out, F1_out, FCO_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F1,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F1,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F1,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20021
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20021 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20021 : ENTITY IS TRUE;
+
+  end ccu20021;
+
+  architecture Structure of ccu20021 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"900a", INIT1 => X"5003", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117"
+        ;
+
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20021
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0: ccu20021
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, 
+                C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
+                CO1=>open);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B0_ipd, A0_ipd, FCI_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20022
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20022 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20022 : ENTITY IS TRUE;
+
+  end ccu20022;
+
+  architecture Structure of ccu20022 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"500C", INIT1 => X"9009", INJECT1_0 => "NO", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_118
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_118 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_118";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_118 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_118;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_118 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20022
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid25_0_I_1_0: ccu20022
+      port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, 
+                C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, 
+                CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20023
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20023 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20023 : ENTITY IS TRUE;
+
+  end ccu20023;
+
+  architecture Structure of ccu20023 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"8241", INIT1 => X"9009", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_119
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_119 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_119";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_119 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_119;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_119 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    component ccu20023
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid25_0_I_9_0: ccu20023
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20024
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity ccu20024 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20024 : ENTITY IS TRUE;
+
+  end ccu20024;
+
+  architecture Structure of ccu20024 is
+  begin
+    inst1: CCU2C
+      generic map (INIT0 => X"8241", INIT1 => X"0852", INJECT1_0 => "YES", 
+                   INJECT1_1 => "YES")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_120
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_120 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_120";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_120 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_120;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_120 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component ccu20024
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid25_0_I_21_0: ccu20024
+      port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>VCCI, 
+                B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, 
+                S1=>open, CO1=>FCO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, FCI_ipd, FCO_out)
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_FCO,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_FCO,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_FCO,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_FCO,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => FCI_ipd'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut4
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut4 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
+
+  end lut4;
+
+  architecture Structure of lut4 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3332")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40025
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40025 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
+
+  end lut40025;
+
+  architecture Structure of lut40025 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity svmuxregsre0026
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity svmuxregsre0026 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF svmuxregsre0026 : ENTITY IS TRUE;
+
+  end svmuxregsre0026;
+
+  architecture Structure of svmuxregsre0026 is
+  begin
+    INST01: FL1P3IY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity selmux2
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity selmux2 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
+
+  end selmux2;
+
+  architecture Structure of selmux2 is
+  begin
+    INST1: MUX21
+      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_121
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_121 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_121";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_121 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_121;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_121 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40025
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_121_K1: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1
+                );
+    hades_tdc_bundle_inst_hit_out_i_RNO_0: lut40025
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_out_i_0: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_SLICE_121_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, DI0_dly, 
+      M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40027
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40027 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
+
+  end lut40027;
+
+  architecture Structure of lut40027 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6AAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40028
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40028 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
+
+  end lut40028;
+
+  architecture Structure of lut40028 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3C3C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_122
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_122 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_122";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_122 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_122;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_122 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40027
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_50_i_i: lut40027
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_1_x2: lut40028
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_out_i_3: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hit_out_i_1: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40029
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40029 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
+
+  end lut40029;
+
+  architecture Structure of lut40029 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6666")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40030
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40030 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
+
+  end lut40030;
+
+  architecture Structure of lut40030 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CDCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_123
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_123 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_123";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_123 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_123;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_123 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40029
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40030
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_123_K1: lut40029
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_out_i_6_f1_0_2: lut40030
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0
+                );
+    hades_tdc_bundle_inst_hit_out_i_2: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_SLICE_123_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_124
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_124 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_124";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_124 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_124;
+
+  architecture Structure of trb_adapter_inst_SLICE_124 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40031
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40031 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
+
+  end lut40031;
+
+  architecture Structure of lut40031 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3333")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40032
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40032 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
+
+  end lut40032;
+
+  architecture Structure of lut40032 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"05F5")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_125
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_125 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_125";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_125 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_125;
+
+  architecture Structure of fifo_colector_inst_SLICE_125 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40031
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40032
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_125_K1: lut40031
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>GNDI, 
+                Z=>fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_in_empty_pmux_0_RNIDRET: lut40032
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0
+                );
+    fifo_colector_inst_buffer_wr_enable: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_SLICE_125_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, D0_ipd, C0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40033
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40033 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
+
+  end lut40033;
+
+  architecture Structure of lut40033 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FAEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40034
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40034 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
+
+  end lut40034;
+
+  architecture Structure of lut40034 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5044")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_126
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_126 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_126";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_126 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_126;
+
+  architecture Structure of fifo_colector_inst_SLICE_126 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_126_K1: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_0: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0
+                );
+    fifo_colector_inst_data_buffer_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_126_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_127
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_127 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_127";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_127 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_127;
+
+  architecture Structure of fifo_colector_inst_SLICE_127 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_127_K1: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_1: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0
+                );
+    fifo_colector_inst_data_buffer_1: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_127_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40035
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40035 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
+
+  end lut40035;
+
+  architecture Structure of lut40035 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EEFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40036
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40036 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
+
+  end lut40036;
+
+  architecture Structure of lut40036 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4450")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_128
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_128 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_128";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_128 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_128;
+
+  architecture Structure of fifo_colector_inst_SLICE_128 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_128_K1: lut40035
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_2: lut40036
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0
+                );
+    fifo_colector_inst_data_buffer_2: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_128_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_129
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_129 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_129";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_129 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_129;
+
+  architecture Structure of fifo_colector_inst_SLICE_129 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_129_K1: lut40035
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_3: lut40036
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0
+                );
+    fifo_colector_inst_data_buffer_3: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_129_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40037
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40037 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
+
+  end lut40037;
+
+  architecture Structure of lut40037 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EFEA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40038
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40038 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
+
+  end lut40038;
+
+  architecture Structure of lut40038 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4540")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_130
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_130 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_130";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_130 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_130;
+
+  architecture Structure of fifo_colector_inst_SLICE_130 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_130_K1: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_4: lut40038
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0
+                );
+    fifo_colector_inst_data_buffer_4: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_130_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_131
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_131 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_131";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_131 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_131;
+
+  architecture Structure of fifo_colector_inst_SLICE_131 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_131_K1: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_5: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0
+                );
+    fifo_colector_inst_data_buffer_5: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_131_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40039
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40039 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
+
+  end lut40039;
+
+  architecture Structure of lut40039 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FEAE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40040
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40040 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
+
+  end lut40040;
+
+  architecture Structure of lut40040 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_132
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_132 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_132";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_132 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_132;
+
+  architecture Structure of fifo_colector_inst_SLICE_132 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40039
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_132_K1: lut40039
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_6: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0
+                );
+    fifo_colector_inst_data_buffer_6: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_132_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40041
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40041 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
+
+  end lut40041;
+
+  architecture Structure of lut40041 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FBEA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40042
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40042 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
+
+  end lut40042;
+
+  architecture Structure of lut40042 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5140")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_133
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_133 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_133";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_133 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_133;
+
+  architecture Structure of fifo_colector_inst_SLICE_133 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40042
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_SLICE_133_K1: lut40041
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1
+                );
+    fifo_colector_inst_data_buffer_3_7: lut40042
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0
+                );
+    fifo_colector_inst_data_buffer_7: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_SLICE_133_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0
+                , 
+                D1=>fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40043
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40043 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
+
+  end lut40043;
+
+  architecture Structure of lut40043 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"AAF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40044
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40044 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
+
+  end lut40044;
+
+  architecture Structure of lut40044 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F0CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_134
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_134 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_134";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_134 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_134;
+
+  architecture Structure of fifo_colector_inst_SLICE_134 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_9: lut40043
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_8: lut40044
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_9: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_8: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40045
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40045 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
+
+  end lut40045;
+
+  architecture Structure of lut40045 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CCAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40046
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40046 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
+
+  end lut40046;
+
+  architecture Structure of lut40046 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CCF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_135
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_135 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_135";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_135 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_135;
+
+  architecture Structure of fifo_colector_inst_SLICE_135 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_11: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_10: lut40046
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_11: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_10: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40047
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40047 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
+
+  end lut40047;
+
+  architecture Structure of lut40047 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FA50")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_136
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_136 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_136";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_136 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_136;
+
+  architecture Structure of fifo_colector_inst_SLICE_136 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40047
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_13: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_12: lut40047
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_13: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_12: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40048
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40048 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
+
+  end lut40048;
+
+  architecture Structure of lut40048 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F0AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_137
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_137 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_137";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_137 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_137;
+
+  architecture Structure of fifo_colector_inst_SLICE_137 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_15: lut40044
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_14: lut40048
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_15: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_14: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40049
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40049 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
+
+  end lut40049;
+
+  architecture Structure of lut40049 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F3C0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_138
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_138 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_138";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_138 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_138;
+
+  architecture Structure of fifo_colector_inst_SLICE_138 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_17: lut40044
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_16: lut40049
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_17: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_16: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40050
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40050 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
+
+  end lut40050;
+
+  architecture Structure of lut40050 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"DD88")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_139
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_139 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_139";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_139 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_139;
+
+  architecture Structure of fifo_colector_inst_SLICE_139 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40050
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_19: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_18: lut40050
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_19: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_18: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_140
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_140 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_140";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_140 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_140;
+
+  architecture Structure of fifo_colector_inst_SLICE_140 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_21: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_20: lut40046
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_21: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_20: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_141
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_141 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_141";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_141 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_141;
+
+  architecture Structure of fifo_colector_inst_SLICE_141 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_23: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_22: lut40043
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_23: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_22: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40051
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40051 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
+
+  end lut40051;
+
+  architecture Structure of lut40051 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CACA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_142
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_142 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_142";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_142 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_142;
+
+  architecture Structure of fifo_colector_inst_SLICE_142 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40051
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_25: lut40048
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_24: lut40051
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    fifo_colector_inst_data_buffer_25: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_24: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40052
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40052 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
+
+  end lut40052;
+
+  architecture Structure of lut40052 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"BB88")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_143
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_143 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_143";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_143 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_143;
+
+  architecture Structure of fifo_colector_inst_SLICE_143 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40052
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_27: lut40044
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_26: lut40052
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_27: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_26: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40053
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40053 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
+
+  end lut40053;
+
+  architecture Structure of lut40053 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EE22")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40054
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40054 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
+
+  end lut40054;
+
+  architecture Structure of lut40054 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"B8B8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_144
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_144 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_144";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_144 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_144;
+
+  architecture Structure of fifo_colector_inst_SLICE_144 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40054
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_29: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_28: lut40054
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    fifo_colector_inst_data_buffer_29: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_28: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40055
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40055 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
+
+  end lut40055;
+
+  architecture Structure of lut40055 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FC30")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40056
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40056 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
+
+  end lut40056;
+
+  architecture Structure of lut40056 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CFC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_145
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_145 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_145";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_145 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_145;
+
+  architecture Structure of fifo_colector_inst_SLICE_145 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40055
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40056
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_3_0_31: lut40055
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_3_0_30: lut40056
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_data_buffer_31: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_data_buffer_30: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_146
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_146 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_146";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_146 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_146;
+
+  architecture Structure of fifo_colector_inst_SLICE_146 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_data_buffer_33: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_data_buffer_32: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40057
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40057 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
+
+  end lut40057;
+
+  architecture Structure of lut40057 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5A5A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40058
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40058 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
+
+  end lut40058;
+
+  architecture Structure of lut40058 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0FF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_147
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_147 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_147";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_147 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_147;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_147 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t7: lut40057
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t8: lut40058
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_60: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_61: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40059
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40059 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
+
+  end lut40059;
+
+  architecture Structure of lut40059 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"55AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40060
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40060 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
+
+  end lut40060;
+
+  architecture Structure of lut40060 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6666")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_148
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_148 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_148";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_148 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_148;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_148 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t5: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t6: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_58: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_59: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40061
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40061 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
+
+  end lut40061;
+
+  architecture Structure of lut40061 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5A5A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40062
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40062 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
+
+  end lut40062;
+
+  architecture Structure of lut40062 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"55AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_149
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_149 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_149";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_149 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_149;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_149 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t3: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t4: lut40062
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_56: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_57: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40063
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40063 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
+
+  end lut40063;
+
+  architecture Structure of lut40063 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0FF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_150
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_150 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_150";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_150 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_150;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_150 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t1: lut40058
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t2: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_54: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_55: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40064
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40064 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
+
+  end lut40064;
+
+  architecture Structure of lut40064 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"33CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_151
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_151 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_151";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_151 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_151;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_151 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t0: lut40064
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_52: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_53: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_152
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_152 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_152";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_152 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_152;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_152 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_30: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_31: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_153
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_153 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_153";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_153 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_153;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_153 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_28: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_29: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_154
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_154 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_154";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_154 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_154;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_154 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_26: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_27: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_155
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_155 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_155";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_155 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_155;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_155 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_24: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_25: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_156
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_156 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_156";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_156 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_156;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_156 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_22: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_23: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_157
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_157 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_157";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_157 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_157;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_157 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_10: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_11: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_158
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_158 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_158";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_158 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_158;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_158 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_8: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_9: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_159
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_159 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_159";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_159 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_159;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_159 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_160
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_160 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_160";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_160 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_160;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_160 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_161
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_161 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_161";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_161 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_161;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_161 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_162
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_162 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_162";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_162 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_162;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_162 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_50: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_51: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_163
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_163 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_163";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_163 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_163;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_163 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_48: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_49: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_164
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_164 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_164";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_164 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_164;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_164 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_46: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_47: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_165
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_165 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_165";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_165 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_165;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_165 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_44: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_45: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_166
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_166 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_166";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_166 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_166;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_166 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_42: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_43: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40065
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40065 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
+
+  end lut40065;
+
+  architecture Structure of lut40065 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3C3C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40066
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40066 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
+
+  end lut40066;
+
+  architecture Structure of lut40066 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"33CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_167
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_167 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_167";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_167 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_167;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_167 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t16: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t17: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_90: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_91: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_168
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_168 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_168";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_168 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_168;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_168 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t14: lut40058
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t15: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_88: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_89: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_169
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_169 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_169";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_169 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_169;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_169 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t12: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t13: lut40061
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_86: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_87: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_170
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_170 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_170";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_170 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_170;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_170 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t10: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_XOR2_t11: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_fifo40_inst_FF_84: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_85: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_171
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_171 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_171";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_171 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_171;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_171 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_XOR2_t9: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_82: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_fifo40_inst_FF_83: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_172
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_172 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_172";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_172 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_172;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_172 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_40: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_41: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_173
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_173 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_173";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_173 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_173;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_173 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_38: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_39: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_174
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_174 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_174";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_174 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_174;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_174 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_36: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_37: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_175
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_175 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_175";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_175 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_175;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_175 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_34: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_35: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_176
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_176 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_176";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_176 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_176;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_176 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_32: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_33: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_177
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_177 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_177";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_177 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_177;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_177 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_20: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_21: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_178
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_178 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_178";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_178 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_178;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_178 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_18: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_19: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_179
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_179 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_179";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_179 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_179;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_179 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_16: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_17: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_180
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_180 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_180";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_180 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_180;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_180 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_14: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_15: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_181
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_181 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_181";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_181 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_181;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_181 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_12: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_13: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_182
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_182 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_182";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_182 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_182;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_182 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_80: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_81: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_183
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_183 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_183";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_183 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_183;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_183 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_78: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_79: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_184
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_184 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_184";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_184 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_184;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_184 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_76: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_77: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_185
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_185 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_185";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_185 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_185;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_185 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_74: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_75: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_186
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_186 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_186";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_186 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_186;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_186 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_FF_72: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_FF_73: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40067
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40067 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
+
+  end lut40067;
+
+  architecture Structure of lut40067 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0303")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_187
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_187 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_187";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_187 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_187;
+
+  architecture Structure of fifo_colector_inst_SLICE_187 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40067
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_un5_in_read_enable: lut40067
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_iterator_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_iterator_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, 
+      Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40068
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40068 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
+
+  end lut40068;
+
+  architecture Structure of lut40068 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40069
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40069 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
+
+  end lut40069;
+
+  architecture Structure of lut40069 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CFCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_188
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_188 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_188";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_188 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_188;
+
+  architecture Structure of trb_adapter_inst_SLICE_188 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40068
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_burst: lut40068
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    trb_adapter_inst_buf_rden4: lut40069
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    trb_adapter_inst_buf_rden: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40070
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40070 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
+
+  end lut40070;
+
+  architecture Structure of lut40070 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FCFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40071
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40071 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
+
+  end lut40071;
+
+  architecture Structure of lut40071 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF05")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_189
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_189 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_189";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_189 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_189;
+
+  architecture Structure of fifo_colector_inst_SLICE_189 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40070
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40071
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_in_read_enable_1_fb: lut40070
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_in_read_enable_0_fb: lut40071
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    fifo_colector_inst_in_read_enable_1: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    fifo_colector_inst_in_read_enable_0: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40072
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40072 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
+
+  end lut40072;
+
+  architecture Structure of lut40072 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_190
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_190 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_190";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_190 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_190;
+
+  architecture Structure of fifo_colector_inst_SLICE_190 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_in_read_enable_2_fb: lut40072
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_in_read_enable_2: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity inverter
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity inverter is
+    port (I: in Std_logic; Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
+
+  end inverter;
+
+  architecture Structure of inverter is
+  begin
+    INST1: INV
+      port map (A=>I, Z=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40073
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40073 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
+
+  end lut40073;
+
+  architecture Structure of lut40073 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"080D")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40073
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40073
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40057
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40058
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40074
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40074 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
+
+  end lut40074;
+
+  architecture Structure of lut40074 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6666")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40074
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40028
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40028
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40028
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40065
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40075
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40075 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
+
+  end lut40075;
+
+  architecture Structure of lut40075 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_246
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_SLICE_246";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_SLICE_246;
+
+  architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40075
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40075
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40076
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40076 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
+
+  end lut40076;
+
+  architecture Structure of lut40076 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"080B")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40076
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40076
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40074
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40062
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308"
+        ;
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40074
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40058
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40059
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310"
+        ;
+
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40074
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_326
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_SLICE_326";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_SLICE_326;
+
+  architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40072
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40077
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40077 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
+
+  end lut40077;
+
+  architecture Structure of lut40077 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00B1")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40077
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40077
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40028
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40062
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40066
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, 
+      CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40065
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40078
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40078 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
+
+  end lut40078;
+
+  architecture Structure of lut40078 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FCFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_406
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_SLICE_406";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_SLICE_406;
+
+  architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40078
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40078
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40079
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40079 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
+
+  end lut40079;
+
+  architecture Structure of lut40079 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0033")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40080
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40080 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
+
+  end lut40080;
+
+  architecture Structure of lut40080 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_432
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_432 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_432";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_432 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_432;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_432 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40079
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40080
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_buf_finished5_0_a2_0: lut40079
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_buf_finished_RNO: lut40080
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_buf_finished: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_433
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_433 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_433";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_433 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_433;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_433 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_buf_release: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, LSR_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40081
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40081 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
+
+  end lut40081;
+
+  architecture Structure of lut40081 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_434
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_434 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_434";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_434 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_434;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_434 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc1: lut40028
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_coarse_RNI8DE6_0: lut40081
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_coarse_1: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_coarse_0: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, DI1_dly, DI0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40082
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40082 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
+
+  end lut40082;
+
+  architecture Structure of lut40082 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"78F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40083
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40083 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
+
+  end lut40083;
+
+  architecture Structure of lut40083 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5AF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_435
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_435 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_435";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_435 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_435;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_435 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40082
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40083
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_coarse_RNI6RPP_2: lut40082
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc2: lut40083
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_coarse_3: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_coarse_2: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40084
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40084 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
+
+  end lut40084;
+
+  architecture Structure of lut40084 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7F80")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40085
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40085 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
+
+  end lut40085;
+
+  architecture Structure of lut40085 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7788")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_436
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_436 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_436";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_436 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_436;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_436 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40084
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40085
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc5: lut40084
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc4: lut40085
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_coarse_5: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_coarse_4: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40086
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40086 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
+
+  end lut40086;
+
+  architecture Structure of lut40086 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7F80")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40087
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40087 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
+
+  end lut40087;
+
+  architecture Structure of lut40087 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"78F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_437
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_437 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_437";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_437 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_437;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_437 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40086
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40087
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc7: lut40086
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc6: lut40087
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_coarse_7: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_coarse_6: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, 
+      F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40088
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40088 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
+
+  end lut40088;
+
+  architecture Structure of lut40088 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40089
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40089 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
+
+  end lut40089;
+
+  architecture Structure of lut40089 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"78F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_438
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_438 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_438";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_438 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_438;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_438 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40088
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40089
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_5: lut40088
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc8: lut40089
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_coarse_8: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_439
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_439 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_439";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_439 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_439;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_439 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hitbuffer_1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_440
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_440 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_440";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_440 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_440;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_440 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hitbuffer_1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_441
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_441 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_441";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_441 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_441;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_441 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_8: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hitbuffer_1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_442
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_442 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_442";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_442 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_442;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_442 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_10: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hitbuffer_1_9: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_443
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_443 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_443";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_443 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_443;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_443 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_11: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40090
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40090 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
+
+  end lut40090;
+
+  architecture Structure of lut40090 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F0F8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40091
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40091 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
+
+  end lut40091;
+
+  architecture Structure of lut40091 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EEE0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40090
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40091
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en: lut40090
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_RNI41GL1_3: lut40091
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_445
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_445 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_445";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_445 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_445;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_445 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_446
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_446 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_446";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_446 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_446;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_446 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_447
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_447 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_447";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_447 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_447;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_447 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_448
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_448 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_448";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_448 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_448;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_448 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_449
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_449 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_449";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_449 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_449;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_449 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_1_8: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_450
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_450 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_450";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_450 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_450;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_450 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_451
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_451 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_451";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_451 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_451;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_451 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_452
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_452 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_452";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_452 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_452;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_452 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_453
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_453 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_453";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_453 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_453;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_453 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_454
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_454 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_454";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_454 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_454;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_454 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_8: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40092
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40092 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
+
+  end lut40092;
+
+  architecture Structure of lut40092 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40093
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40093 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
+
+  end lut40093;
+
+  architecture Structure of lut40093 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_455
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_455 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_455";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_455 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_455;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_455 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40092
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_455_K1: lut40092
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1
+                );
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_9: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_SLICE_455_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, 
+      CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40094
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40094 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
+
+  end lut40094;
+
+  architecture Structure of lut40094 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3F30")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_456
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_456 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_456";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_456 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_456;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_456 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40094
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i: lut40094
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_valid: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, DI0_dly, CE_dly, CLK_dly, 
+      F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40095
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40095 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
+
+  end lut40095;
+
+  architecture Structure of lut40095 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40096
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40096 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
+
+  end lut40096;
+
+  architecture Structure of lut40096 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00F4")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_457
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_457 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_457";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_457 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_457;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_457 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40095
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40096
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_457_K1: lut40095
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_1_RNO_0: lut40096
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0
+                );
+    hades_tdc_bundle_inst_hit_valid_1_0: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    hades_tdc_bundle_inst_SLICE_457_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40097
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40097 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
+
+  end lut40097;
+
+  architecture Structure of lut40097 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"003F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40098
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40098 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
+
+  end lut40098;
+
+  architecture Structure of lut40098 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0015")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_458
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_458 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_458";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_458 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_458;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_458 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40097
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40098
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_458_K1: lut40097
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_1_RNO_1: lut40098
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0
+                );
+    hades_tdc_bundle_inst_hit_valid_1_1: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    hades_tdc_bundle_inst_SLICE_458_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40099
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40099 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
+
+  end lut40099;
+
+  architecture Structure of lut40099 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0B0A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40100
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40100 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
+
+  end lut40100;
+
+  architecture Structure of lut40100 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0F00")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_459
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_459 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_459";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_459 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_459;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_459 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40099
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40100
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_459_K1: lut40099
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1
+                );
+    hades_tdc_bundle_inst_hit_valid_1_RNO_2: lut40100
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_1_2: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    hades_tdc_bundle_inst_SLICE_459_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40101
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40101 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
+
+  end lut40101;
+
+  architecture Structure of lut40101 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3230")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_460
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_460 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_460";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_460 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_460;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_460 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40100
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40101
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_460_K1: lut40101
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1
+                );
+    hades_tdc_bundle_inst_hit_valid_1_RNO_3: lut40100
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_1_3: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    hades_tdc_bundle_inst_SLICE_460_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40102
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40102 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
+
+  end lut40102;
+
+  architecture Structure of lut40102 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5500")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40102
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_valid_RNO: lut40102
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_valid: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, 
+      F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_1: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_0: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_12: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_2: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_14: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_13: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_16: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_15: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_18: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_17: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_20: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_19: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_22: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_21: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_23: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40103
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40103 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
+
+  end lut40103;
+
+  architecture Structure of lut40103 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7350")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40104
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40104 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
+
+  end lut40104;
+
+  architecture Structure of lut40104 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity svmuxregsre0105
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity svmuxregsre0105 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF svmuxregsre0105 : ENTITY IS TRUE;
+
+  end svmuxregsre0105;
+
+  architecture Structure of svmuxregsre0105 is
+  begin
+    INST01: FL1P3JY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40103
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40104
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_o7: lut40103
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i: lut40104
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40106
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40106 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
+
+  end lut40106;
+
+  architecture Structure of lut40106 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40107
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40107 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
+
+  end lut40107;
+
+  architecture Structure of lut40107 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"73FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40107
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1: lut40106
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i: lut40107
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40108
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40108 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
+
+  end lut40108;
+
+  architecture Structure of lut40108 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40108
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1: lut40108
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: lut40106
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40109
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40109 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
+
+  end lut40109;
+
+  architecture Structure of lut40109 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3011")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40109
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO: lut40109
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40110
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40110 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE;
+
+  end lut40110;
+
+  architecture Structure of lut40110 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CCC3")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40111
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40111 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE;
+
+  end lut40111;
+
+  architecture Structure of lut40111 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CFC3")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40110
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40111
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1: lut40110
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0: lut40111
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0
+                );
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI0_dly, M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40112
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40112 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE;
+
+  end lut40112;
+
+  architecture Structure of lut40112 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF10")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40112
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3: lut40112
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1: lut40112
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, 
+      F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40113
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40113 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE;
+
+  end lut40113;
+
+  architecture Structure of lut40113 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FAC8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40113
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup: lut40113
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0
+                );
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40114
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40114 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE;
+
+  end lut40114;
+
+  architecture Structure of lut40114 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF04")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40114
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5: lut40114
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4: lut40114
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, 
+      F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40115
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40115 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE;
+
+  end lut40115;
+
+  architecture Structure of lut40115 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF02")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40115
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7: lut40115
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6: lut40115
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, 
+      F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_4: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_3: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_6: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_5: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_8: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_7: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+          Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_10: svmuxregsre0026
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_9: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, 
+      Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_11: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40116
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40116 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE;
+
+  end lut40116;
+
+  architecture Structure of lut40116 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40116
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_RNIG7JA: lut40116
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_valid: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40117
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40117 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40117 : ENTITY IS TRUE;
+
+  end lut40117;
+
+  architecture Structure of lut40117 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5808")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40117
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4_f0_0_0: lut40117
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, 
+      CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40118
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40118 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40118 : ENTITY IS TRUE;
+
+  end lut40118;
+
+  architecture Structure of lut40118 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7520")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CE_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40118
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready_4_iv_i_0: lut40118
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CE_INVERTERIN: inverter
+      port map (I=>CE_dly, Z=>CE_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, 
+      CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40119
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40119 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40119 : ENTITY IS TRUE;
+
+  end lut40119;
+
+  architecture Structure of lut40119 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"50DC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40120
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40120 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40120 : ENTITY IS TRUE;
+
+  end lut40120;
+
+  architecture Structure of lut40120 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FEFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40119
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40120
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_o7: lut40119
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i: lut40120
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40121
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40121 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40121 : ENTITY IS TRUE;
+
+  end lut40121;
+
+  architecture Structure of lut40121 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5FDF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40121
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1: lut40106
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i: lut40121
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40122
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40122 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40122 : ENTITY IS TRUE;
+
+  end lut40122;
+
+  architecture Structure of lut40122 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40122
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1: lut40122
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: lut40106
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40123
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40123 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40123 : ENTITY IS TRUE;
+
+  end lut40123;
+
+  architecture Structure of lut40123 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4045")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40123
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO: lut40123
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40124
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40124 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40124 : ENTITY IS TRUE;
+
+  end lut40124;
+
+  architecture Structure of lut40124 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFDD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40125
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40125 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40125 : ENTITY IS TRUE;
+
+  end lut40125;
+
+  architecture Structure of lut40125 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFFD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40124
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40125
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m15_i: lut40124
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i: lut40125
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
+        SetupLow => tsetup_DI1_CLK_noedge_negedge,
+        HoldHigh => thold_DI1_CLK_noedge_negedge,
+        HoldLow => thold_DI1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40126
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40126 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40126 : ENTITY IS TRUE;
+
+  end lut40126;
+
+  architecture Structure of lut40126 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"75FD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40127
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40127 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40127 : ENTITY IS TRUE;
+
+  end lut40127;
+
+  architecture Structure of lut40127 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"DFFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component svmuxregsre0105
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40126
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40127
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5: lut40126
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0: lut40127
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2: svmuxregsre0105
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40128
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40128 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40128 : ENTITY IS TRUE;
+
+  end lut40128;
+
+  architecture Structure of lut40128 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4501")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40128
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO: lut40128
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, 
+      LSR_dly, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_in_clk_synced_0: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered1_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_in_clk_synced_1: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered1_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_in_clk_synced_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered1_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_in_clk_synced_3: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered1_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_in_clk_synced_4: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered1_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_in_clk_synced_5: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered1_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_in_clk_synced_6: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered1_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611"
+        ;
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_in_clk_synced_7: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered1_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered_0: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered_3: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered_4: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered_5: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered_6: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627"
+        ;
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered_7: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40129
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40129 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40129 : ENTITY IS TRUE;
+
+  end lut40129;
+
+  architecture Structure of lut40129 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5AAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_628
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_628 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_628";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_628 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_628;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_628 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40129
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_0_0: lut40129
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM0_1_0_x2: lut40057
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    hades_tdc_bundle_inst_hit_i_1: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hit_i_0: svmuxregsre0026
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40130
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40130 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40130 : ENTITY IS TRUE;
+
+  end lut40130;
+
+  architecture Structure of lut40130 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0004")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1: Std_logic;
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40130
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1: lut40130
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1
+                );
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end: svmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, 
+      CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_631
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_631 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_631";
+
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_631 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_631;
+
+  architecture Structure of trb_adapter_inst_SLICE_631 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2: svmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_632
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_632 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_632";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_632 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_632;
+
+  architecture Structure of trb_adapter_inst_SLICE_632 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_buf_rden_prev: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_633
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_633 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_633";
+
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_633 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_633;
+
+  architecture Structure of trb_adapter_inst_SLICE_633 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_finished_prev: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40131
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40131 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40131 : ENTITY IS TRUE;
+
+  end lut40131;
+
+  architecture Structure of lut40131 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"DC50")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40100
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40131
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1: lut40100
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0: lut40131
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0
+                );
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40132
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40132 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40132 : ENTITY IS TRUE;
+
+  end lut40132;
+
+  architecture Structure of lut40132 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0002")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40132
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1: lut40132
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0
+                );
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0
+                , 
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40133
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40133 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40133 : ENTITY IS TRUE;
+
+  end lut40133;
+
+  architecture Structure of lut40133 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40134
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40134 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40134 : ENTITY IS TRUE;
+
+  end lut40134;
+
+  architecture Structure of lut40134 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40133
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40134
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1: lut40133
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40134
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                , 
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40133
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40134
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1: lut40133
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40134
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                , 
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40133
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40134
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1: lut40133
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40134
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                , 
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40133
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40134
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1: lut40133
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40134
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                , 
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40135
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40135 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40135 : ENTITY IS TRUE;
+
+  end lut40135;
+
+  architecture Structure of lut40135 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40136
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40136 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40136 : ENTITY IS TRUE;
+
+  end lut40136;
+
+  architecture Structure of lut40136 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40135
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40136
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1: lut40135
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40136
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                , 
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40137
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40137 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40137 : ENTITY IS TRUE;
+
+  end lut40137;
+
+  architecture Structure of lut40137 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40138
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40138 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40138 : ENTITY IS TRUE;
+
+  end lut40138;
+
+  architecture Structure of lut40138 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40137
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40138
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1: lut40137
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40138
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                , 
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40139
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40139 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40139 : ENTITY IS TRUE;
+
+  end lut40139;
+
+  architecture Structure of lut40139 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40140
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40140 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40140 : ENTITY IS TRUE;
+
+  end lut40140;
+
+  architecture Structure of lut40140 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40139
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40140
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1: lut40139
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40140
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                , 
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40141
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40141 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40141 : ENTITY IS TRUE;
+
+  end lut40141;
+
+  architecture Structure of lut40141 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40142
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40142 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40142 : ENTITY IS TRUE;
+
+  end lut40142;
+
+  architecture Structure of lut40142 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40141
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40142
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1: lut40141
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40142
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                , 
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40141
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40142
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1: lut40141
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40142
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0
+                , 
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40133
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40134
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1: lut40133
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40134
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0
+                , 
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40143
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40143 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40143 : ENTITY IS TRUE;
+
+  end lut40143;
+
+  architecture Structure of lut40143 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40144
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40144 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40144 : ENTITY IS TRUE;
+
+  end lut40144;
+
+  architecture Structure of lut40144 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40143
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40144
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1: lut40143
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40144
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0
+                , 
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40145
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40145 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40145 : ENTITY IS TRUE;
+
+  end lut40145;
+
+  architecture Structure of lut40145 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40146
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40146 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40146 : ENTITY IS TRUE;
+
+  end lut40146;
+
+  architecture Structure of lut40146 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40145
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40146
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1: lut40145
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40146
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0
+                , 
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40147
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40147 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40147 : ENTITY IS TRUE;
+
+  end lut40147;
+
+  architecture Structure of lut40147 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40148
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40148 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40148 : ENTITY IS TRUE;
+
+  end lut40148;
+
+  architecture Structure of lut40148 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_648
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_648 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_648";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_648 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_648;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_648 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40147
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40148
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_SLICE_648_K1: lut40147
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1
+                );
+    fifo_colector_inst_fifo40_inst_LUT4_6: lut40148
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0
+                );
+    fifo_colector_inst_fifo40_inst_SLICE_648_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0
+                , 
+                D1=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40149
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40149 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40149 : ENTITY IS TRUE;
+
+  end lut40149;
+
+  architecture Structure of lut40149 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9669")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_649
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_649 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_649";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_649 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_649;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_649 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1: Std_logic;
+
+      signal fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40148
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40149
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_SLICE_649_K1: lut40149
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1
+                );
+    fifo_colector_inst_fifo40_inst_LUT4_9: lut40148
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0
+                );
+    fifo_colector_inst_fifo40_inst_SLICE_649_K0K1MUX: selmux2
+      port map (
+                D0=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0
+                , 
+                D1=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40150
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40150 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40150 : ENTITY IS TRUE;
+
+  end lut40150;
+
+  architecture Structure of lut40150 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40151
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40151 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40151 : ENTITY IS TRUE;
+
+  end lut40151;
+
+  architecture Structure of lut40151 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"3FAE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40150
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40151
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1: lut40150
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40151
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                );
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                , 
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40152
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40152 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40152 : ENTITY IS TRUE;
+
+  end lut40152;
+
+  architecture Structure of lut40152 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40153
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40153 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40153 : ENTITY IS TRUE;
+
+  end lut40153;
+
+  architecture Structure of lut40153 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7F4E")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40152
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40153
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1: lut40152
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40153
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                );
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                , 
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40154
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40154 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40154 : ENTITY IS TRUE;
+
+  end lut40154;
+
+  architecture Structure of lut40154 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40155
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40155 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40155 : ENTITY IS TRUE;
+
+  end lut40155;
+
+  architecture Structure of lut40155 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"74FE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40154
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40155
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1: lut40154
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40155
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                );
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K0K1MUX: selmux2
+      port map (
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0
+                , 
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40156
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40156 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40156 : ENTITY IS TRUE;
+
+  end lut40156;
+
+  architecture Structure of lut40156 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FFFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_653
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_653 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_653";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_653 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_653;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_653 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1: Std_logic;
+
+      signal hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40156
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_SLICE_653_K1: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, 
+                Z=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1
+                );
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11: lut40156
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0
+                );
+    hades_tdc_bundle_inst_SLICE_653_K0K1MUX: selmux2
+      port map (
+                D0=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0
+                , 
+                D1=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1
+                , SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40157
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40157 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40157 : ENTITY IS TRUE;
+
+  end lut40157;
+
+  architecture Structure of lut40157 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40158
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40158 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40158 : ENTITY IS TRUE;
+
+  end lut40158;
+
+  architecture Structure of lut40158 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF20")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_654
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_654 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_654";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_654 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_654;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_654 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40157
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40158
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2: lut40157
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0: lut40158
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40159
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40159 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40159 : ENTITY IS TRUE;
+
+  end lut40159;
+
+  architecture Structure of lut40159 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40160
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40160 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40160 : ENTITY IS TRUE;
+
+  end lut40160;
+
+  architecture Structure of lut40160 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40160
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40159
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40160
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40161
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40161 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40161 : ENTITY IS TRUE;
+
+  end lut40161;
+
+  architecture Structure of lut40161 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"C33C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40161
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40161
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40159
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40162
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40162 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40162 : ENTITY IS TRUE;
+
+  end lut40162;
+
+  architecture Structure of lut40162 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40163
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40163 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40163 : ENTITY IS TRUE;
+
+  end lut40163;
+
+  architecture Structure of lut40163 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9696")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40162
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40163
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40162
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40164
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40164 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40164 : ENTITY IS TRUE;
+
+  end lut40164;
+
+  architecture Structure of lut40164 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40160
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40164
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40160
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40165
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40165 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40165 : ENTITY IS TRUE;
+
+  end lut40165;
+
+  architecture Structure of lut40165 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"A55A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40160
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40165
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40165
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40160
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40166
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40166 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40166 : ENTITY IS TRUE;
+
+  end lut40166;
+
+  architecture Structure of lut40166 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40167
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40167 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40167 : ENTITY IS TRUE;
+
+  end lut40167;
+
+  architecture Structure of lut40167 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9966")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40166
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40167
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40166
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40167
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40160
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40159
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40160
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40168
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40168 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40168 : ENTITY IS TRUE;
+
+  end lut40168;
+
+  architecture Structure of lut40168 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40165
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40168
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40165
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40168
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40169
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40169 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40169 : ENTITY IS TRUE;
+
+  end lut40169;
+
+  architecture Structure of lut40169 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40163
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40169
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40169
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40170
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40170 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40170 : ENTITY IS TRUE;
+
+  end lut40170;
+
+  architecture Structure of lut40170 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40164
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40170
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40170
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40171
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40171 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40171 : ENTITY IS TRUE;
+
+  end lut40171;
+
+  architecture Structure of lut40171 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9966")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40172
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40172 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40172 : ENTITY IS TRUE;
+
+  end lut40172;
+
+  architecture Structure of lut40172 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40171
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40172
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40171
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40172
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40173
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40173 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40173 : ENTITY IS TRUE;
+
+  end lut40173;
+
+  architecture Structure of lut40173 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"A55A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40166
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40173
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40166
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40173
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40168
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40168
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40159
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40174
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40174 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40174 : ENTITY IS TRUE;
+
+  end lut40174;
+
+  architecture Structure of lut40174 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9966")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40174
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40174
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40159
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40175
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40175 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40175 : ENTITY IS TRUE;
+
+  end lut40175;
+
+  architecture Structure of lut40175 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40163
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40175
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40175
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40164
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40164
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40176
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40176 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40176 : ENTITY IS TRUE;
+
+  end lut40176;
+
+  architecture Structure of lut40176 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40161
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40176
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40161
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40176
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40177
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40177 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40177 : ENTITY IS TRUE;
+
+  end lut40177;
+
+  architecture Structure of lut40177 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40178
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40178 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40178 : ENTITY IS TRUE;
+
+  end lut40178;
+
+  architecture Structure of lut40178 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"C33C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40177
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40178
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40177
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40178
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_673
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_673 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_673";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_673 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_673;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_673 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40160
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40175
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_14: lut40160
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_23: lut40175
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_674
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_674 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_674";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_674 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_674;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_674 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40161
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40166
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_15: lut40161
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_LUT4_22: lut40166
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_675
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_675 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_675";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_675 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_675;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_675 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40162
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_19: lut40162
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_21: lut40064
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40179
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40179 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40179 : ENTITY IS TRUE;
+
+  end lut40179;
+
+  architecture Structure of lut40179 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40180
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40180 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40180 : ENTITY IS TRUE;
+
+  end lut40180;
+
+  architecture Structure of lut40180 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"9966")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_676
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_676 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_676";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_676 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_676;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_676 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40179
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40180
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_18: lut40179
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_20: lut40180
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_677
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_677 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_677";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_677 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_677;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_677 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40159
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40164
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_4: lut40164
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_13: lut40159
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_678
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_678 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_678";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_678 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_678;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_678 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40161
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40176
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_5: lut40161
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_LUT4_12: lut40176
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40181
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40181 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40181 : ENTITY IS TRUE;
+
+  end lut40181;
+
+  architecture Structure of lut40181 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_679
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_679 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_679";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_679 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_679;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_679 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40178
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40181
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_8: lut40181
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_10: lut40178
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40182
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40182 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40182 : ENTITY IS TRUE;
+
+  end lut40182;
+
+  architecture Structure of lut40182 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EE22")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_680
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_680 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_680";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_680 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_680;
+
+  architecture Structure of fifo_colector_inst_SLICE_680 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40182
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_in_empty_pmux_0: lut40043
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_in_empty_pmux_u: lut40182
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40183
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40183 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40183 : ENTITY IS TRUE;
+
+  end lut40183;
+
+  architecture Structure of lut40183 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"C000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40184
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40184 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40184 : ENTITY IS TRUE;
+
+  end lut40184;
+
+  architecture Structure of lut40184 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8778")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_681
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_681 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_681";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_681 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_681;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_681 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40183
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40184
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_3: lut40183
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0_RNO_0: lut40184
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40185
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40185 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40185 : ENTITY IS TRUE;
+
+  end lut40185;
+
+  architecture Structure of lut40185 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0030")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40186
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40186 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40186 : ENTITY IS TRUE;
+
+  end lut40186;
+
+  architecture Structure of lut40186 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40185
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40186
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0: lut40185
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c: lut40186
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40187
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40187 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40187 : ENTITY IS TRUE;
+
+  end lut40187;
+
+  architecture Structure of lut40187 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0005")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40188
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40188 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40188 : ENTITY IS TRUE;
+
+  end lut40188;
+
+  architecture Structure of lut40188 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF88")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_683
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_683 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_683";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_683 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_683;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_683 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40187
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40188
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2: lut40187
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_buf_out12: lut40188
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40189
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40189 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40189 : ENTITY IS TRUE;
+
+  end lut40189;
+
+  architecture Structure of lut40189 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40189
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNIOA5C_2: lut40189
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3: lut40189
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40190
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40190 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40190 : ENTITY IS TRUE;
+
+  end lut40190;
+
+  architecture Structure of lut40190 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4242")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40191
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40191 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40191 : ENTITY IS TRUE;
+
+  end lut40191;
+
+  architecture Structure of lut40191 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"2424")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40190
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40191
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40190
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40191
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40192
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40192 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40192 : ENTITY IS TRUE;
+
+  end lut40192;
+
+  architecture Structure of lut40192 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8811")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40193
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40193 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40193 : ENTITY IS TRUE;
+
+  end lut40193;
+
+  architecture Structure of lut40193 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4422")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40192
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40193
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40192
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40193
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40194
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40194 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40194 : ENTITY IS TRUE;
+
+  end lut40194;
+
+  architecture Structure of lut40194 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4422")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40195
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40195 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40195 : ENTITY IS TRUE;
+
+  end lut40195;
+
+  architecture Structure of lut40195 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"2244")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40194
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40195
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40194
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40195
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40196
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40196 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40196 : ENTITY IS TRUE;
+
+  end lut40196;
+
+  architecture Structure of lut40196 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8181")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40197
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40197 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40197 : ENTITY IS TRUE;
+
+  end lut40197;
+
+  architecture Structure of lut40197 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"1818")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40196
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40197
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40196
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40197
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40198
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40198 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40198 : ENTITY IS TRUE;
+
+  end lut40198;
+
+  architecture Structure of lut40198 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4242")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40199
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40199 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40199 : ENTITY IS TRUE;
+
+  end lut40199;
+
+  architecture Structure of lut40199 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"1818")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40198
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40199
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40198
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40199
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40196
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40197
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40196
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40197
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40200
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40200 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40200 : ENTITY IS TRUE;
+
+  end lut40200;
+
+  architecture Structure of lut40200 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"2424")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40201
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40201 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40201 : ENTITY IS TRUE;
+
+  end lut40201;
+
+  architecture Structure of lut40201 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8181")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_691
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_691 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_691";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_691 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_691;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_691 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40200
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40201
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_1: lut40200
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_LUT4_0: lut40201
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40202
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40202 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40202 : ENTITY IS TRUE;
+
+  end lut40202;
+
+  architecture Structure of lut40202 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"500A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40203
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40203 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40203 : ENTITY IS TRUE;
+
+  end lut40203;
+
+  architecture Structure of lut40203 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"05A0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_692
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_692 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_692";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_692 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_692;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_692 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40202
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40203
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_2: lut40202
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_LUT4_3: lut40203
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40204
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40204 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40204 : ENTITY IS TRUE;
+
+  end lut40204;
+
+  architecture Structure of lut40204 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F3FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40205
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40205 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40205 : ENTITY IS TRUE;
+
+  end lut40205;
+
+  architecture Structure of lut40205 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0400")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_693
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_693 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_693";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_693 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_693;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_693 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40204
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40205
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_0_0_o2_0: lut40204
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_un1_hit_i_2_0_a2: lut40205
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40206
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40206 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40206 : ENTITY IS TRUE;
+
+  end lut40206;
+
+  architecture Structure of lut40206 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7F6E")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40207
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40207 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40207 : ENTITY IS TRUE;
+
+  end lut40207;
+
+  architecture Structure of lut40207 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7350")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40206
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40207
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m15_i_1: lut40206
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5: lut40207
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40208
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40208 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40208 : ENTITY IS TRUE;
+
+  end lut40208;
+
+  architecture Structure of lut40208 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"50DC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40209
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40209 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40209 : ENTITY IS TRUE;
+
+  end lut40209;
+
+  architecture Structure of lut40209 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40208
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40209
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1: lut40208
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_3: lut40209
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40210
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40210 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40210 : ENTITY IS TRUE;
+
+  end lut40210;
+
+  architecture Structure of lut40210 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7DFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40211
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40211 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40211 : ENTITY IS TRUE;
+
+  end lut40211;
+
+  architecture Structure of lut40211 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"DD11")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40210
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40211
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1_0: lut40210
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_m3: lut40211
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40212
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40212 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40212 : ENTITY IS TRUE;
+
+  end lut40212;
+
+  architecture Structure of lut40212 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"965A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40213
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40213 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40213 : ENTITY IS TRUE;
+
+  end lut40213;
+
+  architecture Structure of lut40213 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"965A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40212
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40213
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0_RNO: lut40212
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_0_RNO: lut40213
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40214
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40214 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40214 : ENTITY IS TRUE;
+
+  end lut40214;
+
+  architecture Structure of lut40214 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"8800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40215
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40215 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40215 : ENTITY IS TRUE;
+
+  end lut40215;
+
+  architecture Structure of lut40215 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"956A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_698
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_698 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_698";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_698 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_698;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_698 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40214
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40215
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_7: lut40214
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_RNO_0: lut40215
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40216
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40216 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40216 : ENTITY IS TRUE;
+
+  end lut40216;
+
+  architecture Structure of lut40216 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7350")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40217
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40217 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40217 : ENTITY IS TRUE;
+
+  end lut40217;
+
+  architecture Structure of lut40217 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40216
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40217
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1: lut40216
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_3: lut40217
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40218
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40218 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40218 : ENTITY IS TRUE;
+
+  end lut40218;
+
+  architecture Structure of lut40218 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"7FBA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40219
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40219 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40219 : ENTITY IS TRUE;
+
+  end lut40219;
+
+  architecture Structure of lut40219 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F055")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40218
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40219
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1_0: lut40218
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_m3: lut40219
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40220
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40220 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40220 : ENTITY IS TRUE;
+
+  end lut40220;
+
+  architecture Structure of lut40220 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CC00")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40221
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40221 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40221 : ENTITY IS TRUE;
+
+  end lut40221;
+
+  architecture Structure of lut40221 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"A0A0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_701
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_701 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_701";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_701 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_701;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_701 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40220
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40221
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0: lut40220
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0: lut40221
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, C0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40222
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40222 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40222 : ENTITY IS TRUE;
+
+  end lut40222;
+
+  architecture Structure of lut40222 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_702
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_702 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_702";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_702 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_702;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_702 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40222
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_17: lut40222
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    fifo_colector_inst_fifo40_inst_LUT4_16: lut40063
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_703
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_703 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_703";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_703 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_703;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_703 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40170
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_LUT4_11: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    fifo_colector_inst_fifo40_inst_LUT4_7: lut40170
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40223
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40223 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40223 : ENTITY IS TRUE;
+
+  end lut40223;
+
+  architecture Structure of lut40223 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40223
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40223
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40224
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40224 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40224 : ENTITY IS TRUE;
+
+  end lut40224;
+
+  architecture Structure of lut40224 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40224
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40224
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40162
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40059
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40162
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40225
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40225 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40225 : ENTITY IS TRUE;
+
+  end lut40225;
+
+  architecture Structure of lut40225 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"6996")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707"
+        ;
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40225
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40064
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40225
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40224
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40061
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40224
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709"
+        ;
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40181
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40065
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40181
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40226
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40226 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40226 : ENTITY IS TRUE;
+
+  end lut40226;
+
+  architecture Structure of lut40226 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_710
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_710 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_710";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_710 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_710;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_710 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40226
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa_0_a2: lut40226
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    hades_tdc_bundle_inst_hit_valid_pmux_iv_0_m2: lut40046
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40227
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40227 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40227 : ENTITY IS TRUE;
+
+  end lut40227;
+
+  architecture Structure of lut40227 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0F00")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_711
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_SLICE_711";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_SLICE_711;
+
+  architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40227
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_2_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40228
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40228 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40228 : ENTITY IS TRUE;
+
+  end lut40228;
+
+  architecture Structure of lut40228 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5500")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40228
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40228
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40229
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40229 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40229 : ENTITY IS TRUE;
+
+  end lut40229;
+
+  architecture Structure of lut40229 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF0F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40229
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40229
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_714
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_SLICE_714";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_SLICE_714;
+
+  architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40227
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_1_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40228
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40228
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40230
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40230 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40230 : ENTITY IS TRUE;
+
+  end lut40230;
+
+  architecture Structure of lut40230 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"FF33")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40230
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40230
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_717
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_SLICE_717";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_SLICE_717;
+
+  architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40227
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    genblk1_0_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40231
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40231 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40231 : ENTITY IS TRUE;
+
+  end lut40231;
+
+  architecture Structure of lut40231 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4444")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718"
+        ;
+
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40231
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40231
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40232
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40232 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40232 : ENTITY IS TRUE;
+
+  end lut40232;
+
+  architecture Structure of lut40232 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F5F5")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40232
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40232
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40233
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40233 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40233 : ENTITY IS TRUE;
+
+  end lut40233;
+
+  architecture Structure of lut40233 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_720
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_720 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_720";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_720 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_720;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_720 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40233
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_AND2_t19: lut40233
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40234
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40234 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40234 : ENTITY IS TRUE;
+
+  end lut40234;
+
+  architecture Structure of lut40234 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0C0C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_SLICE_721
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_SLICE_721 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_SLICE_721";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_721 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_SLICE_721;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_721 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40234
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_AND2_t20: lut40234
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_colector_inst_SLICE_722
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_SLICE_722 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_SLICE_722";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_722 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_SLICE_722;
+
+  architecture Structure of fifo_colector_inst_SLICE_722 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40228
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_iterator_RNI7U5I_1: lut40228
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40235
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40235 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40235 : ENTITY IS TRUE;
+
+  end lut40235;
+
+  architecture Structure of lut40235 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"00CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_723
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_723 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_723";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_723 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_723;
+
+  architecture Structure of trb_adapter_inst_SLICE_723 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40235
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_LVL1_TRG_DATA_VALI_IN_rising: lut40235
+      port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40236
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40236 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40236 : ENTITY IS TRUE;
+
+  end lut40236;
+
+  architecture Structure of lut40236 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"4444")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity trb_adapter_inst_SLICE_724
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trb_adapter_inst_SLICE_724 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trb_adapter_inst_SLICE_724";
+
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_LSR 	: VitalDelayType := 0 ns;
+      tpw_LSR_posedge	: VitalDelayType := 0 ns;
+      tpw_LSR_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_724 : ENTITY IS TRUE;
+
+  end trb_adapter_inst_SLICE_724;
+
+  architecture Structure of trb_adapter_inst_SLICE_724 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre0026
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40236
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_release_out: lut40236
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    trb_adapter_inst_finished: svmuxregsre0026
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B0_ipd, A0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_LSR          	: x01 := '0';
+    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => LSR_ipd,
+        TestSignalName => "LSR",
+        Period => tperiod_LSR,
+        PulseWidthHigh => tpw_LSR_posedge,
+        PulseWidthLow => tpw_LSR_negedge,
+        PeriodData => periodcheckinfo_LSR,
+        Violation => tviol_LSR_LSR,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40237
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40237 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40237 : ENTITY IS TRUE;
+
+  end lut40237;
+
+  architecture Structure of lut40237 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40237
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_RNI97O31: lut40237
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, 
+      Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40229
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_RNIT1GT_7: lut40229
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40238
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40238 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40238 : ENTITY IS TRUE;
+
+  end lut40238;
+
+  architecture Structure of lut40238 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5D0C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40238
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0: lut40238
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40239
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40239 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40239 : ENTITY IS TRUE;
+
+  end lut40239;
+
+  architecture Structure of lut40239 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0ACE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40239
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i_0: lut40239
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40240
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40240 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40240 : ENTITY IS TRUE;
+
+  end lut40240;
+
+  architecture Structure of lut40240 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"AF05")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 : ENTITY IS TRUE;
+
+
+    end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40240
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i_m3: lut40240
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40241
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40241 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40241 : ENTITY IS TRUE;
+
+  end lut40241;
+
+  architecture Structure of lut40241 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"CFCF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40241
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_RNIB4EQ_7: lut40241
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40227
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_RNI8UMR: lut40227
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40242
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40242 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40242 : ENTITY IS TRUE;
+
+  end lut40242;
+
+  architecture Structure of lut40242 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"50DC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+
+  -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+
+    entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40242
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40242
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40243
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40243 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40243 : ENTITY IS TRUE;
+
+  end lut40243;
+
+  architecture Structure of lut40243 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"EFCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40243
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast_RNI999V: lut40243
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40244
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40244 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40244 : ENTITY IS TRUE;
+
+  end lut40244;
+
+  architecture Structure of lut40244 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"F3F3")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734"
+        ;
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40244
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_RNI3HPF_7: lut40244
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40238
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40238
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40245
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40245 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40245 : ENTITY IS TRUE;
+
+  end lut40245;
+
+  architecture Structure of lut40245 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"AEAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40245
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast_RNI5DQ71: lut40245
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, 
+      F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40188
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2: lut40188
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40115
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2: lut40115
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40246
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40246 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40246 : ENTITY IS TRUE;
+
+  end lut40246;
+
+  architecture Structure of lut40246 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739"
+        ;
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739;
+
+
+    architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    component lut40246
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNICU4C_3: lut40246
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_740
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_740 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_740";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_740 : ENTITY IS TRUE;
+
+  end SLICE_740;
+
+  architecture Structure of SLICE_740 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component svmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40233
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa_0_a2: lut40233
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    reset_dl_2: svmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, CLK_dly, F0_out, Q0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40247
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40247 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40247 : ENTITY IS TRUE;
+
+  end lut40247;
+
+  architecture Structure of lut40247 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"0505")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity hades_tdc_bundle_inst_SLICE_741
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_tdc_bundle_inst_SLICE_741 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_tdc_bundle_inst_SLICE_741";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_741 : ENTITY IS TRUE;
+
+  end hades_tdc_bundle_inst_SLICE_741;
+
+  architecture Structure of hades_tdc_bundle_inst_SLICE_741 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40247
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0: lut40247
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity pll0inst_SLICE_742
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity pll0inst_SLICE_742 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "pll0inst_SLICE_742");
+
+    port (F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF pll0inst_SLICE_742 : ENTITY IS TRUE;
+
+  end pll0inst_SLICE_742;
+
+  architecture Structure of pll0inst_SLICE_742 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    pll0inst_GND: lut40093
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (F0_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0 	<= F0_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_743
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_743 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_743";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_743 : ENTITY IS TRUE;
+
+  end SLICE_743;
+
+  architecture Structure of SLICE_743 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_lvl1_pad_RNINMH5: lut40081
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_744
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_744 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_744";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_744 : ENTITY IS TRUE;
+
+  end SLICE_744;
+
+  architecture Structure of SLICE_744 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trig_pad_RNII4FF_0: lut40081
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_745
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_745 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_745";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_745 : ENTITY IS TRUE;
+
+  end SLICE_745;
+
+  architecture Structure of SLICE_745 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trig_pad_RNIJ5FF_1: lut40081
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_746
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_746 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_746";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_746 : ENTITY IS TRUE;
+
+  end SLICE_746;
+
+  architecture Structure of SLICE_746 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    trig_pad_RNIK6FF_2: lut40081
+      port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40248
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity lut40248 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40248 : ENTITY IS TRUE;
+
+  end lut40248;
+
+  architecture Structure of lut40248 is
+  begin
+    INST10: ROM16X1A
+      generic map (initval => X"5555")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_747
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity SLICE_747 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_747";
+
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (A0: in Std_logic; F0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_747 : ENTITY IS TRUE;
+
+  end SLICE_747;
+
+  architecture Structure of SLICE_747 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40248
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    hades_trig_pad_RNIE1B4: lut40248
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A0_ipd, F0_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity sapiobuf
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity sapiobuf is
+    port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF sapiobuf : ENTITY IS TRUE;
+
+  end sapiobuf;
+
+  architecture Structure of sapiobuf is
+  begin
+    INST5: OBZ
+      port map (I=>I, T=>T, O=>PAD);
+  end Structure;
+
+-- entity hades_raw_valid_vect_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_raw_valid_vect_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_raw_valid_vect_0_B");
+
+    port (hadesrawvalidvect0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_raw_valid_vect_0_B : ENTITY IS TRUE;
+
+  end hades_raw_valid_vect_0_B;
+
+  architecture Structure of hades_raw_valid_vect_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesrawvalidvect0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component sapiobuf
+      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_raw_valid_vect_pad_0: sapiobuf
+      port map (I=>GNDI, T=>VCCI, PAD=>hadesrawvalidvect0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesrawvalidvect0_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesrawvalidvect0 	<= hadesrawvalidvect0_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity sapiobuf0249
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity sapiobuf0249 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF sapiobuf0249 : ENTITY IS TRUE;
+
+  end sapiobuf0249;
+
+  architecture Structure of sapiobuf0249 is
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity fifo_data_out_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_0_B : ENTITY IS TRUE;
+
+  end fifo_data_out_0_B;
+
+  architecture Structure of fifo_data_out_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout0_out)
+    VARIABLE fifodataout0_zd         	: std_logic := 'X';
+    VARIABLE fifodataout0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout0_zd 	:= fifodataout0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout0, OutSignalName => "fifodataout0", OutTemp => fifodataout0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout0,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity sapiobuf0250
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity sapiobuf0250 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF sapiobuf0250 : ENTITY IS TRUE;
+
+  end sapiobuf0250;
+
+  architecture Structure of sapiobuf0250 is
+  begin
+    INST1: IB
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity clkB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity clkB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "clkB";
+
+      tipd_clkS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_clkS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_clkS 	: VitalDelayType := 0 ns;
+      tpw_clkS_posedge	: VitalDelayType := 0 ns;
+      tpw_clkS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; clkS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF clkB : ENTITY IS TRUE;
+
+  end clkB;
+
+  architecture Structure of clkB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal clkS_ipd 	: std_logic := 'X';
+
+    component sapiobuf0250
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    clk_pad: sapiobuf0250
+      port map (Z=>PADDI_out, PAD=>clkS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(clkS_ipd, clkS, tipd_clkS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, clkS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_clkS_clkS          	: x01 := '0';
+    VARIABLE periodcheckinfo_clkS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => clkS_ipd,
+        TestSignalName => "clkS",
+        Period => tperiod_clkS,
+        PulseWidthHigh => tpw_clkS_posedge,
+        PulseWidthLow => tpw_clkS_negedge,
+        PeriodData => periodcheckinfo_clkS,
+        Violation => tviol_clkS_clkS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => clkS_ipd'last_event,
+                           PathDelay => tpd_clkS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_validB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_validB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_validB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufvalid	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufvalid: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_validB : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_validB;
+
+  architecture Structure of hades_drop_cmp_buf_validB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufvalid_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_valid_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufvalid_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufvalid_out)
+    VARIABLE hadesdropcmpbufvalid_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufvalid_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufvalid_zd 	:= hadesdropcmpbufvalid_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufvalid, OutSignalName => "hadesdropcmpbufvalid", OutTemp => hadesdropcmpbufvalid_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufvalid,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufvalid_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_11_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_11_B");
+
+    port (hadesdropcmpbufcoarse11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_11_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_11_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdropcmpbufcoarse11_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_11: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdropcmpbufcoarse11_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdropcmpbufcoarse11_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse11 	<= hadesdropcmpbufcoarse11_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_10_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_10_B");
+
+    port (hadesdropcmpbufcoarse10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_10_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_10_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdropcmpbufcoarse10_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_10: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdropcmpbufcoarse10_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdropcmpbufcoarse10_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse10 	<= hadesdropcmpbufcoarse10_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_9_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse9	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_9_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_9_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse9_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_9: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse9_out)
+    VARIABLE hadesdropcmpbufcoarse9_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse9_zd 	:= hadesdropcmpbufcoarse9_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse9, OutSignalName => "hadesdropcmpbufcoarse9", OutTemp => hadesdropcmpbufcoarse9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse9,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_8_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_8_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse8_out)
+    VARIABLE hadesdropcmpbufcoarse8_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse8_zd 	:= hadesdropcmpbufcoarse8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse8, OutSignalName => "hadesdropcmpbufcoarse8", OutTemp => hadesdropcmpbufcoarse8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse8,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_7_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_7_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse7_out)
+    VARIABLE hadesdropcmpbufcoarse7_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse7_zd 	:= hadesdropcmpbufcoarse7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse7, OutSignalName => "hadesdropcmpbufcoarse7", OutTemp => hadesdropcmpbufcoarse7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse7,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_6_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_6_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse6_out)
+    VARIABLE hadesdropcmpbufcoarse6_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse6_zd 	:= hadesdropcmpbufcoarse6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse6, OutSignalName => "hadesdropcmpbufcoarse6", OutTemp => hadesdropcmpbufcoarse6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse6,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_5_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_5_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse5_out)
+    VARIABLE hadesdropcmpbufcoarse5_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse5_zd 	:= hadesdropcmpbufcoarse5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse5, OutSignalName => "hadesdropcmpbufcoarse5", OutTemp => hadesdropcmpbufcoarse5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse5,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_4_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_4_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse4_out)
+    VARIABLE hadesdropcmpbufcoarse4_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse4_zd 	:= hadesdropcmpbufcoarse4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse4, OutSignalName => "hadesdropcmpbufcoarse4", OutTemp => hadesdropcmpbufcoarse4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse4,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_3_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_3_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse3_out)
+    VARIABLE hadesdropcmpbufcoarse3_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse3_zd 	:= hadesdropcmpbufcoarse3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse3, OutSignalName => "hadesdropcmpbufcoarse3", OutTemp => hadesdropcmpbufcoarse3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse3,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_2_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_2_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse2_out)
+    VARIABLE hadesdropcmpbufcoarse2_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse2_zd 	:= hadesdropcmpbufcoarse2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse2, OutSignalName => "hadesdropcmpbufcoarse2", OutTemp => hadesdropcmpbufcoarse2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_1_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_1_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse1_out)
+    VARIABLE hadesdropcmpbufcoarse1_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse1_zd 	:= hadesdropcmpbufcoarse1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse1, OutSignalName => "hadesdropcmpbufcoarse1", OutTemp => hadesdropcmpbufcoarse1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_coarse_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_coarse_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_coarse_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbufcoarse0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbufcoarse0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_0_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_coarse_0_B;
+
+  architecture Structure of hades_drop_cmp_buf_coarse_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbufcoarse0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_coarse_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse0_out)
+    VARIABLE hadesdropcmpbufcoarse0_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbufcoarse0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbufcoarse0_zd 	:= hadesdropcmpbufcoarse0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbufcoarse0, OutSignalName => "hadesdropcmpbufcoarse0", OutTemp => hadesdropcmpbufcoarse0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbufcoarse0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbufcoarse0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_11_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_11_B");
+
+    port (hadesdropcmpbuf11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_11_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_11_B;
+
+  architecture Structure of hades_drop_cmp_buf_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdropcmpbuf11_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_11: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdropcmpbuf11_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdropcmpbuf11_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf11 	<= hadesdropcmpbuf11_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_10_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_10_B");
+
+    port (hadesdropcmpbuf10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_10_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_10_B;
+
+  architecture Structure of hades_drop_cmp_buf_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdropcmpbuf10_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_10: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdropcmpbuf10_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdropcmpbuf10_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf10 	<= hadesdropcmpbuf10_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_9_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_9_B");
+
+    port (hadesdropcmpbuf9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_9_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_9_B;
+
+  architecture Structure of hades_drop_cmp_buf_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdropcmpbuf9_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_9: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdropcmpbuf9_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdropcmpbuf9_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf9 	<= hadesdropcmpbuf9_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_8_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_8_B;
+
+  architecture Structure of hades_drop_cmp_buf_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf8_out)
+    VARIABLE hadesdropcmpbuf8_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf8_zd 	:= hadesdropcmpbuf8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf8, OutSignalName => "hadesdropcmpbuf8", OutTemp => hadesdropcmpbuf8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf8,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_7_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_7_B;
+
+  architecture Structure of hades_drop_cmp_buf_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf7_out)
+    VARIABLE hadesdropcmpbuf7_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf7_zd 	:= hadesdropcmpbuf7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf7, OutSignalName => "hadesdropcmpbuf7", OutTemp => hadesdropcmpbuf7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf7,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_6_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_6_B;
+
+  architecture Structure of hades_drop_cmp_buf_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf6_out)
+    VARIABLE hadesdropcmpbuf6_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf6_zd 	:= hadesdropcmpbuf6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf6, OutSignalName => "hadesdropcmpbuf6", OutTemp => hadesdropcmpbuf6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf6,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_5_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_5_B;
+
+  architecture Structure of hades_drop_cmp_buf_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf5_out)
+    VARIABLE hadesdropcmpbuf5_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf5_zd 	:= hadesdropcmpbuf5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf5, OutSignalName => "hadesdropcmpbuf5", OutTemp => hadesdropcmpbuf5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf5,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_4_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_4_B;
+
+  architecture Structure of hades_drop_cmp_buf_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf4_out)
+    VARIABLE hadesdropcmpbuf4_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf4_zd 	:= hadesdropcmpbuf4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf4, OutSignalName => "hadesdropcmpbuf4", OutTemp => hadesdropcmpbuf4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf4,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_3_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_3_B;
+
+  architecture Structure of hades_drop_cmp_buf_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf3_out)
+    VARIABLE hadesdropcmpbuf3_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf3_zd 	:= hadesdropcmpbuf3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf3, OutSignalName => "hadesdropcmpbuf3", OutTemp => hadesdropcmpbuf3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf3,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_2_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_2_B;
+
+  architecture Structure of hades_drop_cmp_buf_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf2_out)
+    VARIABLE hadesdropcmpbuf2_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf2_zd 	:= hadesdropcmpbuf2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf2, OutSignalName => "hadesdropcmpbuf2", OutTemp => hadesdropcmpbuf2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_1_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_1_B;
+
+  architecture Structure of hades_drop_cmp_buf_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf1_out)
+    VARIABLE hadesdropcmpbuf1_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf1_zd 	:= hadesdropcmpbuf1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf1, OutSignalName => "hadesdropcmpbuf1", OutTemp => hadesdropcmpbuf1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_drop_cmp_buf_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_drop_cmp_buf_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_drop_cmp_buf_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdropcmpbuf0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdropcmpbuf0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_0_B : ENTITY IS TRUE;
+
+  end hades_drop_cmp_buf_0_B;
+
+  architecture Structure of hades_drop_cmp_buf_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdropcmpbuf0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_drop_cmp_buf_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf0_out)
+    VARIABLE hadesdropcmpbuf0_zd         	: std_logic := 'X';
+    VARIABLE hadesdropcmpbuf0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdropcmpbuf0_zd 	:= hadesdropcmpbuf0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdropcmpbuf0, OutSignalName => "hadesdropcmpbuf0", OutTemp => hadesdropcmpbuf0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdropcmpbuf0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdropcmpbuf0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_8_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_8_B;
+
+  architecture Structure of hades_dbg2_coarse_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse8_out)
+    VARIABLE hadesdbg2coarse8_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse8_zd 	:= hadesdbg2coarse8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse8, OutSignalName => "hadesdbg2coarse8", OutTemp => hadesdbg2coarse8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse8,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_7_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_7_B;
+
+  architecture Structure of hades_dbg2_coarse_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse7_out)
+    VARIABLE hadesdbg2coarse7_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse7_zd 	:= hadesdbg2coarse7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse7, OutSignalName => "hadesdbg2coarse7", OutTemp => hadesdbg2coarse7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse7,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_6_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_6_B;
+
+  architecture Structure of hades_dbg2_coarse_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse6_out)
+    VARIABLE hadesdbg2coarse6_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse6_zd 	:= hadesdbg2coarse6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse6, OutSignalName => "hadesdbg2coarse6", OutTemp => hadesdbg2coarse6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse6,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_5_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_5_B;
+
+  architecture Structure of hades_dbg2_coarse_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse5_out)
+    VARIABLE hadesdbg2coarse5_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse5_zd 	:= hadesdbg2coarse5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse5, OutSignalName => "hadesdbg2coarse5", OutTemp => hadesdbg2coarse5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse5,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_4_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_4_B;
+
+  architecture Structure of hades_dbg2_coarse_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse4_out)
+    VARIABLE hadesdbg2coarse4_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse4_zd 	:= hadesdbg2coarse4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse4, OutSignalName => "hadesdbg2coarse4", OutTemp => hadesdbg2coarse4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse4,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_3_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_3_B;
+
+  architecture Structure of hades_dbg2_coarse_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse3_out)
+    VARIABLE hadesdbg2coarse3_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse3_zd 	:= hadesdbg2coarse3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse3, OutSignalName => "hadesdbg2coarse3", OutTemp => hadesdbg2coarse3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse3,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_2_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_2_B;
+
+  architecture Structure of hades_dbg2_coarse_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse2_out)
+    VARIABLE hadesdbg2coarse2_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse2_zd 	:= hadesdbg2coarse2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse2, OutSignalName => "hadesdbg2coarse2", OutTemp => hadesdbg2coarse2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_1_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_1_B;
+
+  architecture Structure of hades_dbg2_coarse_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse1_out)
+    VARIABLE hadesdbg2coarse1_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse1_zd 	:= hadesdbg2coarse1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse1, OutSignalName => "hadesdbg2coarse1", OutTemp => hadesdbg2coarse1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_coarse_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_coarse_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_coarse_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2coarse0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2coarse0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_0_B : ENTITY IS TRUE;
+
+  end hades_dbg2_coarse_0_B;
+
+  architecture Structure of hades_dbg2_coarse_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2coarse0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_coarse_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse0_out)
+    VARIABLE hadesdbg2coarse0_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2coarse0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2coarse0_zd 	:= hadesdbg2coarse0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2coarse0, OutSignalName => "hadesdbg2coarse0", OutTemp => hadesdbg2coarse0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2coarse0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2coarse0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_31_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_31_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_31_B");
+
+    port (hadesdbg2out31: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_31_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_31_B;
+
+  architecture Structure of hades_dbg2_out_31_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out31_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_31: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out31_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out31_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out31 	<= hadesdbg2out31_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_30_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_30_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_30_B");
+
+    port (hadesdbg2out30: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_30_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_30_B;
+
+  architecture Structure of hades_dbg2_out_30_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out30_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_30: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out30_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out30_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out30 	<= hadesdbg2out30_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_29_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_29_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_29_B");
+
+    port (hadesdbg2out29: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_29_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_29_B;
+
+  architecture Structure of hades_dbg2_out_29_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out29_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_29: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out29_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out29_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out29 	<= hadesdbg2out29_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_28_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_28_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_28_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out28	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out28: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_28_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_28_B;
+
+  architecture Structure of hades_dbg2_out_28_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out28_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_28: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out28_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out28_out)
+    VARIABLE hadesdbg2out28_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out28_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out28_zd 	:= hadesdbg2out28_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out28, OutSignalName => "hadesdbg2out28", OutTemp => hadesdbg2out28_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out28,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out28_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mfflsre
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity mfflsre is
+    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+          LSR: in Std_logic; Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE;
+
+  end mfflsre;
+
+  architecture Structure of mfflsre is
+  begin
+    INST01: FD1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity hades_dbg2_out_28_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_28_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_28_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_28_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_28_MGIOL;
+
+  architecture Structure of hades_dbg2_out_28_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_23: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_27_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_27_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_27_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out27	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out27: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_27_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_27_B;
+
+  architecture Structure of hades_dbg2_out_27_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out27_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_27: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out27_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out27_out)
+    VARIABLE hadesdbg2out27_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out27_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out27_zd 	:= hadesdbg2out27_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out27, OutSignalName => "hadesdbg2out27", OutTemp => hadesdbg2out27_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out27,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out27_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_27_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_27_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_27_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_27_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_27_MGIOL;
+
+  architecture Structure of hades_dbg2_out_27_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_22: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_26_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_26_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_26_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out26	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out26: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_26_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_26_B;
+
+  architecture Structure of hades_dbg2_out_26_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out26_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_26: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out26_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out26_out)
+    VARIABLE hadesdbg2out26_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out26_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out26_zd 	:= hadesdbg2out26_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out26, OutSignalName => "hadesdbg2out26", OutTemp => hadesdbg2out26_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out26,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out26_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_26_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_26_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_26_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_26_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_26_MGIOL;
+
+  architecture Structure of hades_dbg2_out_26_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_21: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_25_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_25_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_25_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out25	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out25: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_25_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_25_B;
+
+  architecture Structure of hades_dbg2_out_25_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out25_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_25: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out25_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out25_out)
+    VARIABLE hadesdbg2out25_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out25_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out25_zd 	:= hadesdbg2out25_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out25, OutSignalName => "hadesdbg2out25", OutTemp => hadesdbg2out25_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out25,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out25_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_25_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_25_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_25_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_25_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_25_MGIOL;
+
+  architecture Structure of hades_dbg2_out_25_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_20: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_24_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_24_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_24_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out24	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out24: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_24_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_24_B;
+
+  architecture Structure of hades_dbg2_out_24_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out24_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_24: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out24_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out24_out)
+    VARIABLE hadesdbg2out24_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out24_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out24_zd 	:= hadesdbg2out24_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out24, OutSignalName => "hadesdbg2out24", OutTemp => hadesdbg2out24_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out24,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out24_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_24_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_24_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_24_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_24_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_24_MGIOL;
+
+  architecture Structure of hades_dbg2_out_24_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_19: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_23_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_23_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_23_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out23	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out23: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_23_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_23_B;
+
+  architecture Structure of hades_dbg2_out_23_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out23_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_23: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out23_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out23_out)
+    VARIABLE hadesdbg2out23_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out23_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out23_zd 	:= hadesdbg2out23_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out23, OutSignalName => "hadesdbg2out23", OutTemp => hadesdbg2out23_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out23,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out23_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_23_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_23_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_23_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_23_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_23_MGIOL;
+
+  architecture Structure of hades_dbg2_out_23_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_18: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_22_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_22_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_22_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out22	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out22: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_22_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_22_B;
+
+  architecture Structure of hades_dbg2_out_22_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out22_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_22: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out22_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out22_out)
+    VARIABLE hadesdbg2out22_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out22_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out22_zd 	:= hadesdbg2out22_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out22, OutSignalName => "hadesdbg2out22", OutTemp => hadesdbg2out22_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out22,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out22_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_22_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_22_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_22_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_22_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_22_MGIOL;
+
+  architecture Structure of hades_dbg2_out_22_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_17: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_21_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_21_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_21_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out21	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out21: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_21_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_21_B;
+
+  architecture Structure of hades_dbg2_out_21_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out21_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_21: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out21_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out21_out)
+    VARIABLE hadesdbg2out21_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out21_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out21_zd 	:= hadesdbg2out21_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out21, OutSignalName => "hadesdbg2out21", OutTemp => hadesdbg2out21_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out21,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out21_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_21_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_21_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_21_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_21_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_21_MGIOL;
+
+  architecture Structure of hades_dbg2_out_21_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_16: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_20_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_20_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_20_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out20	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out20: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_20_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_20_B;
+
+  architecture Structure of hades_dbg2_out_20_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out20_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_20: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out20_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out20_out)
+    VARIABLE hadesdbg2out20_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out20_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out20_zd 	:= hadesdbg2out20_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out20, OutSignalName => "hadesdbg2out20", OutTemp => hadesdbg2out20_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out20,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out20_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_20_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_20_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_20_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_20_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_20_MGIOL;
+
+  architecture Structure of hades_dbg2_out_20_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_15: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_19_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_19_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_19_B");
+
+    port (hadesdbg2out19: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_19_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_19_B;
+
+  architecture Structure of hades_dbg2_out_19_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out19_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_19: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out19_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out19_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out19 	<= hadesdbg2out19_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_18_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_18_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_18_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out18	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out18: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_18_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_18_B;
+
+  architecture Structure of hades_dbg2_out_18_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out18_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_18: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out18_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out18_out)
+    VARIABLE hadesdbg2out18_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out18_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out18_zd 	:= hadesdbg2out18_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out18, OutSignalName => "hadesdbg2out18", OutTemp => hadesdbg2out18_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out18,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out18_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_18_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_18_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_18_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_18_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_18_MGIOL;
+
+  architecture Structure of hades_dbg2_out_18_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_14: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_17_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_17_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_17_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out17	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out17: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_17_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_17_B;
+
+  architecture Structure of hades_dbg2_out_17_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out17_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_17: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out17_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out17_out)
+    VARIABLE hadesdbg2out17_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out17_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out17_zd 	:= hadesdbg2out17_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out17, OutSignalName => "hadesdbg2out17", OutTemp => hadesdbg2out17_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out17,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out17_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_17_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_17_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_17_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_17_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_17_MGIOL;
+
+  architecture Structure of hades_dbg2_out_17_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_13: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_16_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_16_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_16_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out16	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out16: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_16_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_16_B;
+
+  architecture Structure of hades_dbg2_out_16_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out16_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_16: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out16_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out16_out)
+    VARIABLE hadesdbg2out16_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out16_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out16_zd 	:= hadesdbg2out16_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out16, OutSignalName => "hadesdbg2out16", OutTemp => hadesdbg2out16_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out16,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out16_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_16_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_16_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_16_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_16_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_16_MGIOL;
+
+  architecture Structure of hades_dbg2_out_16_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_12: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_15_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_15_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_15_B");
+
+    port (hadesdbg2out15: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_15_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_15_B;
+
+  architecture Structure of hades_dbg2_out_15_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out15_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_15: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out15_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out15_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out15 	<= hadesdbg2out15_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_14_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_14_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_14_B");
+
+    port (hadesdbg2out14: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_14_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_14_B;
+
+  architecture Structure of hades_dbg2_out_14_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out14_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_14: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out14_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out14_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out14 	<= hadesdbg2out14_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_13_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_13_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_13_B");
+
+    port (hadesdbg2out13: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_13_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_13_B;
+
+  architecture Structure of hades_dbg2_out_13_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out13_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_13: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out13_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out13_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out13 	<= hadesdbg2out13_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_12_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_12_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_12_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out12	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out12: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_12_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_12_B;
+
+  architecture Structure of hades_dbg2_out_12_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out12_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_12: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out12_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out12_out)
+    VARIABLE hadesdbg2out12_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out12_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out12_zd 	:= hadesdbg2out12_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out12, OutSignalName => "hadesdbg2out12", OutTemp => hadesdbg2out12_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out12,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out12_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_11_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out11	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_11_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_11_B;
+
+  architecture Structure of hades_dbg2_out_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out11_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_11: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out11_out)
+    VARIABLE hadesdbg2out11_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out11_zd 	:= hadesdbg2out11_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out11, OutSignalName => "hadesdbg2out11", OutTemp => hadesdbg2out11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out11,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_10_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out10	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_10_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_10_B;
+
+  architecture Structure of hades_dbg2_out_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out10_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_10: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out10_out)
+    VARIABLE hadesdbg2out10_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out10_zd 	:= hadesdbg2out10_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out10, OutSignalName => "hadesdbg2out10", OutTemp => hadesdbg2out10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out10,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_9_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out9	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_9_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_9_B;
+
+  architecture Structure of hades_dbg2_out_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out9_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_9: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out9_out)
+    VARIABLE hadesdbg2out9_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out9_zd 	:= hadesdbg2out9_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out9, OutSignalName => "hadesdbg2out9", OutTemp => hadesdbg2out9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out9,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_8_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_8_B;
+
+  architecture Structure of hades_dbg2_out_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out8_out)
+    VARIABLE hadesdbg2out8_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out8_zd 	:= hadesdbg2out8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out8, OutSignalName => "hadesdbg2out8", OutTemp => hadesdbg2out8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out8,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_7_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_7_B;
+
+  architecture Structure of hades_dbg2_out_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out7_out)
+    VARIABLE hadesdbg2out7_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out7_zd 	:= hadesdbg2out7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out7, OutSignalName => "hadesdbg2out7", OutTemp => hadesdbg2out7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out7,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_6_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_6_B;
+
+  architecture Structure of hades_dbg2_out_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out6_out)
+    VARIABLE hadesdbg2out6_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out6_zd 	:= hadesdbg2out6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out6, OutSignalName => "hadesdbg2out6", OutTemp => hadesdbg2out6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out6,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_5_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_5_B;
+
+  architecture Structure of hades_dbg2_out_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out5_out)
+    VARIABLE hadesdbg2out5_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out5_zd 	:= hadesdbg2out5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out5, OutSignalName => "hadesdbg2out5", OutTemp => hadesdbg2out5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out5,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdbg2out4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdbg2out4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_4_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_4_B;
+
+  architecture Structure of hades_dbg2_out_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdbg2out4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out4_out)
+    VARIABLE hadesdbg2out4_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out4_zd 	:= hadesdbg2out4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out4, OutSignalName => "hadesdbg2out4", OutTemp => hadesdbg2out4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdbg2out4,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_3_B");
+
+    port (hadesdbg2out3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_3_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_3_B;
+
+  architecture Structure of hades_dbg2_out_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesdbg2out3_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_3: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesdbg2out3_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesdbg2out3_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out3 	<= hadesdbg2out3_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_2_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_2_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_2_B;
+
+  architecture Structure of hades_dbg2_out_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_2: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out2_out)
+    VARIABLE hadesdbg2out2_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out2_zd 	:= hadesdbg2out2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out2, OutSignalName => "hadesdbg2out2", OutTemp => hadesdbg2out2_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_2_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_2_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_2_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_2_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_2_MGIOL;
+
+  architecture Structure of hades_dbg2_out_2_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_2: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_1_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_1_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_1_B;
+
+  architecture Structure of hades_dbg2_out_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_1: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out1_out)
+    VARIABLE hadesdbg2out1_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out1_zd 	:= hadesdbg2out1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out1, OutSignalName => "hadesdbg2out1", OutTemp => hadesdbg2out1_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_1_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_1_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_1_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_1_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_1_MGIOL;
+
+  architecture Structure of hades_dbg2_out_1_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_1: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_0_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesdbg2out0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesdbg2out0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_0_B : ENTITY IS TRUE;
+
+  end hades_dbg2_out_0_B;
+
+  architecture Structure of hades_dbg2_out_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesdbg2out0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_dbg2_out_pad_0: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesdbg2out0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out0_out)
+    VARIABLE hadesdbg2out0_zd         	: std_logic := 'X';
+    VARIABLE hadesdbg2out0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdbg2out0_zd 	:= hadesdbg2out0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdbg2out0, OutSignalName => "hadesdbg2out0", OutTemp => hadesdbg2out0_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesdbg2out0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdbg2out0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_dbg2_out_0_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_dbg2_out_0_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_dbg2_out_0_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_dbg2_out_0_MGIOL : ENTITY IS TRUE;
+
+  end hades_dbg2_out_0_MGIOL;
+
+  architecture Structure of hades_dbg2_out_0_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hitbuffer_1_io_0: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_drop_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_drop_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_drop_3_B");
+
+    port (hadesbufdrop3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_drop_3_B : ENTITY IS TRUE;
+
+  end hades_buf_drop_3_B;
+
+  architecture Structure of hades_buf_drop_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesbufdrop3_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_drop_pad_3: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesbufdrop3_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesbufdrop3_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufdrop3 	<= hadesbufdrop3_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_drop_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_drop_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_drop_2_B");
+
+    port (hadesbufdrop2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_drop_2_B : ENTITY IS TRUE;
+
+  end hades_buf_drop_2_B;
+
+  architecture Structure of hades_buf_drop_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesbufdrop2_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_drop_pad_2: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesbufdrop2_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesbufdrop2_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufdrop2 	<= hadesbufdrop2_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_drop_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_drop_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_drop_1_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesbufdrop1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesbufdrop1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_drop_1_B : ENTITY IS TRUE;
+
+  end hades_buf_drop_1_B;
+
+  architecture Structure of hades_buf_drop_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesbufdrop1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_drop_pad_1: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesbufdrop1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesbufdrop1_out)
+    VARIABLE hadesbufdrop1_zd         	: std_logic := 'X';
+    VARIABLE hadesbufdrop1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufdrop1_zd 	:= hadesbufdrop1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesbufdrop1, OutSignalName => "hadesbufdrop1", OutTemp => hadesbufdrop1_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesbufdrop1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesbufdrop1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mfflsre0251
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity mfflsre0251 is
+    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+          LSR: in Std_logic; Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mfflsre0251 : ENTITY IS TRUE;
+
+  end mfflsre0251;
+
+  architecture Structure of mfflsre0251 is
+  begin
+    INST01: FD1P3IX
+      generic map (GSR => "DISABLED")
+      port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity hades_buf_drop_1_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_drop_1_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_drop_1_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_drop_1_MGIOL : ENTITY IS TRUE;
+
+  end hades_buf_drop_1_MGIOL;
+
+  architecture Structure of hades_buf_drop_1_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_buf_drop_1io_1: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_drop_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_drop_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_drop_0_B");
+
+    port (hadesbufdrop0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_drop_0_B : ENTITY IS TRUE;
+
+  end hades_buf_drop_0_B;
+
+  architecture Structure of hades_buf_drop_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesbufdrop0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_drop_pad_0: sapiobuf0249
+      port map (I=>GNDI, PAD=>hadesbufdrop0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesbufdrop0_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufdrop0 	<= hadesbufdrop0_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_invalid_dl_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_invalid_dl_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_invalid_dl_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesinvaliddl3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesinvaliddl3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_invalid_dl_3_B : ENTITY IS TRUE;
+
+  end hades_invalid_dl_3_B;
+
+  architecture Structure of hades_invalid_dl_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesinvaliddl3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_invalid_dl_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesinvaliddl3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl3_out)
+    VARIABLE hadesinvaliddl3_zd         	: std_logic := 'X';
+    VARIABLE hadesinvaliddl3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesinvaliddl3_zd 	:= hadesinvaliddl3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesinvaliddl3, OutSignalName => "hadesinvaliddl3", OutTemp => hadesinvaliddl3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesinvaliddl3,
+                           PathCondition => TRUE)),
+      GlitchData => hadesinvaliddl3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_invalid_dl_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_invalid_dl_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_invalid_dl_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesinvaliddl2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesinvaliddl2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_invalid_dl_2_B : ENTITY IS TRUE;
+
+  end hades_invalid_dl_2_B;
+
+  architecture Structure of hades_invalid_dl_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesinvaliddl2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_invalid_dl_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesinvaliddl2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl2_out)
+    VARIABLE hadesinvaliddl2_zd         	: std_logic := 'X';
+    VARIABLE hadesinvaliddl2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesinvaliddl2_zd 	:= hadesinvaliddl2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesinvaliddl2, OutSignalName => "hadesinvaliddl2", OutTemp => hadesinvaliddl2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesinvaliddl2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesinvaliddl2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_invalid_dl_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_invalid_dl_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_invalid_dl_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesinvaliddl1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesinvaliddl1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_invalid_dl_1_B : ENTITY IS TRUE;
+
+  end hades_invalid_dl_1_B;
+
+  architecture Structure of hades_invalid_dl_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesinvaliddl1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_invalid_dl_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesinvaliddl1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl1_out)
+    VARIABLE hadesinvaliddl1_zd         	: std_logic := 'X';
+    VARIABLE hadesinvaliddl1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesinvaliddl1_zd 	:= hadesinvaliddl1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesinvaliddl1, OutSignalName => "hadesinvaliddl1", OutTemp => hadesinvaliddl1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesinvaliddl1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesinvaliddl1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_invalid_dl_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_invalid_dl_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_invalid_dl_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesinvaliddl0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesinvaliddl0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_invalid_dl_0_B : ENTITY IS TRUE;
+
+  end hades_invalid_dl_0_B;
+
+  architecture Structure of hades_invalid_dl_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesinvaliddl0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_invalid_dl_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesinvaliddl0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl0_out)
+    VARIABLE hadesinvaliddl0_zd         	: std_logic := 'X';
+    VARIABLE hadesinvaliddl0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesinvaliddl0_zd 	:= hadesinvaliddl0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesinvaliddl0, OutSignalName => "hadesinvaliddl0", OutTemp => hadesinvaliddl0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesinvaliddl0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesinvaliddl0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_discardB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_discardB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_discardB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesdiscard	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesdiscard: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_discardB : ENTITY IS TRUE;
+
+  end hades_discardB;
+
+  architecture Structure of hades_discardB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesdiscard_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_discard_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesdiscard_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesdiscard_out)
+    VARIABLE hadesdiscard_zd         	: std_logic := 'X';
+    VARIABLE hadesdiscard_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesdiscard_zd 	:= hadesdiscard_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesdiscard, OutSignalName => "hadesdiscard", OutTemp => hadesdiscard_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesdiscard,
+                           PathCondition => TRUE)),
+      GlitchData => hadesdiscard_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_valid_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_valid_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_valid_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitvalid3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitvalid3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_valid_3_B : ENTITY IS TRUE;
+
+  end hades_hit_valid_3_B;
+
+  architecture Structure of hades_hit_valid_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitvalid3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_valid_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitvalid3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid3_out)
+    VARIABLE hadeshitvalid3_zd         	: std_logic := 'X';
+    VARIABLE hadeshitvalid3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitvalid3_zd 	:= hadeshitvalid3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitvalid3, OutSignalName => "hadeshitvalid3", OutTemp => hadeshitvalid3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitvalid3,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitvalid3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_valid_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_valid_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_valid_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitvalid2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitvalid2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_valid_2_B : ENTITY IS TRUE;
+
+  end hades_hit_valid_2_B;
+
+  architecture Structure of hades_hit_valid_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitvalid2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_valid_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitvalid2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid2_out)
+    VARIABLE hadeshitvalid2_zd         	: std_logic := 'X';
+    VARIABLE hadeshitvalid2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitvalid2_zd 	:= hadeshitvalid2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitvalid2, OutSignalName => "hadeshitvalid2", OutTemp => hadeshitvalid2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitvalid2,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitvalid2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_valid_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_valid_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_valid_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitvalid1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitvalid1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_valid_1_B : ENTITY IS TRUE;
+
+  end hades_hit_valid_1_B;
+
+  architecture Structure of hades_hit_valid_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitvalid1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_valid_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitvalid1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid1_out)
+    VARIABLE hadeshitvalid1_zd         	: std_logic := 'X';
+    VARIABLE hadeshitvalid1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitvalid1_zd 	:= hadeshitvalid1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitvalid1, OutSignalName => "hadeshitvalid1", OutTemp => hadeshitvalid1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitvalid1,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitvalid1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_valid_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_valid_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_valid_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitvalid0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitvalid0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_valid_0_B : ENTITY IS TRUE;
+
+  end hades_hit_valid_0_B;
+
+  architecture Structure of hades_hit_valid_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitvalid0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_valid_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitvalid0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid0_out)
+    VARIABLE hadeshitvalid0_zd         	: std_logic := 'X';
+    VARIABLE hadeshitvalid0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitvalid0_zd 	:= hadeshitvalid0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitvalid0, OutSignalName => "hadeshitvalid0", OutTemp => hadeshitvalid0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitvalid0,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitvalid0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_out_i_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_out_i_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_out_i_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitouti3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitouti3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_out_i_3_B : ENTITY IS TRUE;
+
+  end hades_hit_out_i_3_B;
+
+  architecture Structure of hades_hit_out_i_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitouti3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_out_i_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitouti3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti3_out)
+    VARIABLE hadeshitouti3_zd         	: std_logic := 'X';
+    VARIABLE hadeshitouti3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitouti3_zd 	:= hadeshitouti3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitouti3, OutSignalName => "hadeshitouti3", OutTemp => hadeshitouti3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitouti3,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitouti3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_out_i_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_out_i_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_out_i_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitouti2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitouti2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_out_i_2_B : ENTITY IS TRUE;
+
+  end hades_hit_out_i_2_B;
+
+  architecture Structure of hades_hit_out_i_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitouti2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_out_i_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitouti2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti2_out)
+    VARIABLE hadeshitouti2_zd         	: std_logic := 'X';
+    VARIABLE hadeshitouti2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitouti2_zd 	:= hadeshitouti2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitouti2, OutSignalName => "hadeshitouti2", OutTemp => hadeshitouti2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitouti2,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitouti2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_out_i_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_out_i_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_out_i_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitouti1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitouti1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_out_i_1_B : ENTITY IS TRUE;
+
+  end hades_hit_out_i_1_B;
+
+  architecture Structure of hades_hit_out_i_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitouti1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_out_i_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitouti1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti1_out)
+    VARIABLE hadeshitouti1_zd         	: std_logic := 'X';
+    VARIABLE hadeshitouti1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitouti1_zd 	:= hadeshitouti1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitouti1, OutSignalName => "hadeshitouti1", OutTemp => hadeshitouti1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitouti1,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitouti1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_hit_out_i_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_hit_out_i_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_hit_out_i_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeshitouti0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeshitouti0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_hit_out_i_0_B : ENTITY IS TRUE;
+
+  end hades_hit_out_i_0_B;
+
+  architecture Structure of hades_hit_out_i_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeshitouti0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_hit_out_i_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeshitouti0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti0_out)
+    VARIABLE hadeshitouti0_zd         	: std_logic := 'X';
+    VARIABLE hadeshitouti0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeshitouti0_zd 	:= hadeshitouti0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeshitouti0, OutSignalName => "hadeshitouti0", OutTemp => hadeshitouti0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeshitouti0,
+                           PathCondition => TRUE)),
+      GlitchData => hadeshitouti0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_finishedB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_finishedB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_finishedB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesbuffinished	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesbuffinished: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_finishedB : ENTITY IS TRUE;
+
+  end hades_buf_finishedB;
+
+  architecture Structure of hades_buf_finishedB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesbuffinished_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_finished_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesbuffinished_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesbuffinished_out)
+    VARIABLE hadesbuffinished_zd         	: std_logic := 'X';
+    VARIABLE hadesbuffinished_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbuffinished_zd 	:= hadesbuffinished_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesbuffinished, OutSignalName => "hadesbuffinished", OutTemp => hadesbuffinished_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesbuffinished,
+                           PathCondition => TRUE)),
+      GlitchData => hadesbuffinished_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_releaseB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_releaseB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_releaseB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesbufrelease	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesbufrelease: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_releaseB : ENTITY IS TRUE;
+
+  end hades_buf_releaseB;
+
+  architecture Structure of hades_buf_releaseB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesbufrelease_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_release_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesbufrelease_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesbufrelease_out)
+    VARIABLE hadesbufrelease_zd         	: std_logic := 'X';
+    VARIABLE hadesbufrelease_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufrelease_zd 	:= hadesbufrelease_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesbufrelease, OutSignalName => "hadesbufrelease", OutTemp => hadesbufrelease_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesbufrelease,
+                           PathCondition => TRUE)),
+      GlitchData => hadesbufrelease_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_out_validB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_out_validB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_out_validB";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesbufoutvalid	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesbufoutvalid: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_out_validB : ENTITY IS TRUE;
+
+  end hades_buf_out_validB;
+
+  architecture Structure of hades_buf_out_validB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesbufoutvalid_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_buf_out_valid_pad: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesbufoutvalid_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesbufoutvalid_out)
+    VARIABLE hadesbufoutvalid_zd         	: std_logic := 'X';
+    VARIABLE hadesbufoutvalid_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesbufoutvalid_zd 	:= hadesbufoutvalid_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesbufoutvalid, OutSignalName => "hadesbufoutvalid", OutTemp => hadesbufoutvalid_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesbufoutvalid,
+                           PathCondition => TRUE)),
+      GlitchData => hadesbufoutvalid_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_buf_out_valid_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_buf_out_valid_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_buf_out_valid_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_buf_out_valid_MGIOL : ENTITY IS TRUE;
+
+  end hades_buf_out_valid_MGIOL;
+
+  architecture Structure of hades_buf_out_valid_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_buf_out_validio: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_window_endB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_window_endB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_window_endB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadeswindowend	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadeswindowend: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_window_endB : ENTITY IS TRUE;
+
+  end hades_window_endB;
+
+  architecture Structure of hades_window_endB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadeswindowend_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_window_end_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadeswindowend_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadeswindowend_out)
+    VARIABLE hadeswindowend_zd         	: std_logic := 'X';
+    VARIABLE hadeswindowend_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadeswindowend_zd 	:= hadeswindowend_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadeswindowend, OutSignalName => "hadeswindowend", OutTemp => hadeswindowend_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadeswindowend,
+                           PathCondition => TRUE)),
+      GlitchData => hadeswindowend_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_validB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_validB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_validB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_hadesoffsetvalid	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; hadesoffsetvalid: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_validB : ENTITY IS TRUE;
+
+  end hades_offset_validB;
+
+  architecture Structure of hades_offset_validB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal hadesoffsetvalid_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_valid_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>hadesoffsetvalid_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, hadesoffsetvalid_out)
+    VARIABLE hadesoffsetvalid_zd         	: std_logic := 'X';
+    VARIABLE hadesoffsetvalid_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffsetvalid_zd 	:= hadesoffsetvalid_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffsetvalid, OutSignalName => "hadesoffsetvalid", OutTemp => hadesoffsetvalid_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_hadesoffsetvalid,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffsetvalid_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_8_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_8_B : ENTITY IS TRUE;
+
+  end hades_offset_8_B;
+
+  architecture Structure of hades_offset_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_8: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset8_out)
+    VARIABLE hadesoffset8_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset8_zd 	:= hadesoffset8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset8, OutSignalName => "hadesoffset8", OutTemp => hadesoffset8_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset8,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_8_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_8_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_8_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_8_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_8_MGIOL;
+
+  architecture Structure of hades_offset_8_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_7_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_7_B : ENTITY IS TRUE;
+
+  end hades_offset_7_B;
+
+  architecture Structure of hades_offset_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_7: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset7_out)
+    VARIABLE hadesoffset7_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset7_zd 	:= hadesoffset7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset7, OutSignalName => "hadesoffset7", OutTemp => hadesoffset7_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset7,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_7_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_7_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_7_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_7_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_7_MGIOL;
+
+  architecture Structure of hades_offset_7_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_6_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_6_B : ENTITY IS TRUE;
+
+  end hades_offset_6_B;
+
+  architecture Structure of hades_offset_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_6: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset6_out)
+    VARIABLE hadesoffset6_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset6_zd 	:= hadesoffset6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset6, OutSignalName => "hadesoffset6", OutTemp => hadesoffset6_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset6,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_6_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_6_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_6_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_6_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_6_MGIOL;
+
+  architecture Structure of hades_offset_6_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_5_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_5_B : ENTITY IS TRUE;
+
+  end hades_offset_5_B;
+
+  architecture Structure of hades_offset_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_5: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset5_out)
+    VARIABLE hadesoffset5_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset5_zd 	:= hadesoffset5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset5, OutSignalName => "hadesoffset5", OutTemp => hadesoffset5_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset5,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_5_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_5_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_5_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_5_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_5_MGIOL;
+
+  architecture Structure of hades_offset_5_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_4_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_4_B : ENTITY IS TRUE;
+
+  end hades_offset_4_B;
+
+  architecture Structure of hades_offset_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_4: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset4_out)
+    VARIABLE hadesoffset4_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset4_zd 	:= hadesoffset4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset4, OutSignalName => "hadesoffset4", OutTemp => hadesoffset4_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset4,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_4_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_4_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_4_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_4_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_4_MGIOL;
+
+  architecture Structure of hades_offset_4_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_3_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_3_B : ENTITY IS TRUE;
+
+  end hades_offset_3_B;
+
+  architecture Structure of hades_offset_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_3: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset3_out)
+    VARIABLE hadesoffset3_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset3_zd 	:= hadesoffset3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset3, OutSignalName => "hadesoffset3", OutTemp => hadesoffset3_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset3,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_3_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_3_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_3_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_3_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_3_MGIOL;
+
+  architecture Structure of hades_offset_3_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_2_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_2_B : ENTITY IS TRUE;
+
+  end hades_offset_2_B;
+
+  architecture Structure of hades_offset_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_2: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset2_out)
+    VARIABLE hadesoffset2_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset2_zd 	:= hadesoffset2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset2, OutSignalName => "hadesoffset2", OutTemp => hadesoffset2_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset2,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_2_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_2_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_2_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_2_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_2_MGIOL;
+
+  architecture Structure of hades_offset_2_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_1_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_1_B : ENTITY IS TRUE;
+
+  end hades_offset_1_B;
+
+  architecture Structure of hades_offset_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_1: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset1_out)
+    VARIABLE hadesoffset1_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset1_zd 	:= hadesoffset1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset1, OutSignalName => "hadesoffset1", OutTemp => hadesoffset1_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset1,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_1_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_1_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_1_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_1_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_1_MGIOL;
+
+  architecture Structure of hades_offset_1_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_0_B";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesoffset0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesoffset0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_0_B : ENTITY IS TRUE;
+
+  end hades_offset_0_B;
+
+  architecture Structure of hades_offset_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesoffset0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_offset_pad_0: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesoffset0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset0_out)
+    VARIABLE hadesoffset0_zd         	: std_logic := 'X';
+    VARIABLE hadesoffset0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesoffset0_zd 	:= hadesoffset0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesoffset0, OutSignalName => "hadesoffset0", OutTemp => hadesoffset0_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesoffset0,
+                           PathCondition => TRUE)),
+      GlitchData => hadesoffset0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_offset_0_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_offset_0_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_offset_0_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_offset_0_MGIOL : ENTITY IS TRUE;
+
+  end hades_offset_0_MGIOL;
+
+  architecture Structure of hades_offset_0_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity sapiobuf0252
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity sapiobuf0252 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF sapiobuf0252 : ENTITY IS TRUE;
+
+  end sapiobuf0252;
+
+  architecture Structure of sapiobuf0252 is
+  begin
+    INST1: IBPD
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity hades_lvl1_invalidB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_lvl1_invalidB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_lvl1_invalidB";
+
+      tipd_hadeslvl1invalid  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_hadeslvl1invalid_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_hadeslvl1invalid 	: VitalDelayType := 0 ns;
+      tpw_hadeslvl1invalid_posedge	: VitalDelayType := 0 ns;
+      tpw_hadeslvl1invalid_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; hadeslvl1invalid: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_lvl1_invalidB : ENTITY IS TRUE;
+
+  end hades_lvl1_invalidB;
+
+  architecture Structure of hades_lvl1_invalidB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal hadeslvl1invalid_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    hades_lvl1_invalid_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>hadeslvl1invalid_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(hadeslvl1invalid_ipd, hadeslvl1invalid, tipd_hadeslvl1invalid);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, hadeslvl1invalid_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_hadeslvl1invalid_hadeslvl1invalid          	: x01 := '0';
+    VARIABLE periodcheckinfo_hadeslvl1invalid	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => hadeslvl1invalid_ipd,
+        TestSignalName => "hadeslvl1invalid",
+        Period => tperiod_hadeslvl1invalid,
+        PulseWidthHigh => tpw_hadeslvl1invalid_posedge,
+        PulseWidthLow => tpw_hadeslvl1invalid_negedge,
+        PeriodData => periodcheckinfo_hadeslvl1invalid,
+        Violation => tviol_hadeslvl1invalid_hadeslvl1invalid,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => hadeslvl1invalid_ipd'last_event,
+                           PathDelay => tpd_hadeslvl1invalid_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity smuxlregsre
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity smuxlregsre is
+    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+          LSR: in Std_logic; Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE;
+
+  end smuxlregsre;
+
+  architecture Structure of smuxlregsre is
+  begin
+    INST01: IFS1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity hades_lvl1_invalid_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_lvl1_invalid_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_lvl1_invalid_MGIOL";
+
+      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_INFF	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_lvl1_invalid_MGIOL : ENTITY IS TRUE;
+
+  end hades_lvl1_invalid_MGIOL;
+
+  architecture Structure of hades_lvl1_invalid_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI_ipd 	: std_logic := 'X';
+    signal DI_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal INFF_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component smuxlregsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0: smuxlregsre
+      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI_ipd, DI, tipd_DI);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out)
+    VARIABLE INFF_zd         	: std_logic := 'X';
+    VARIABLE INFF_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI_CLK       	: x01 := '0';
+    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI_dly,
+        TestSignalName => "DI",
+        TestDelay => tisd_DI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI_CLK_noedge_posedge,
+        SetupLow => tsetup_DI_CLK_noedge_posedge,
+        HoldHigh => thold_DI_CLK_noedge_posedge,
+        HoldLow => thold_DI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI_CLK_TimingDatash,
+        Violation => tviol_DI_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    INFF_zd 	:= INFF_out;
+
+    VitalPathDelay01 (
+      OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_INFF,
+                           PathCondition => TRUE)),
+      GlitchData => INFF_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_lvl1B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_lvl1B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_lvl1B";
+
+      tipd_hadeslvl1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_hadeslvl1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_hadeslvl1 	: VitalDelayType := 0 ns;
+      tpw_hadeslvl1_posedge	: VitalDelayType := 0 ns;
+      tpw_hadeslvl1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; hadeslvl1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_lvl1B : ENTITY IS TRUE;
+
+  end hades_lvl1B;
+
+  architecture Structure of hades_lvl1B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal hadeslvl1_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    hades_lvl1_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>hadeslvl1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(hadeslvl1_ipd, hadeslvl1, tipd_hadeslvl1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, hadeslvl1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_hadeslvl1_hadeslvl1          	: x01 := '0';
+    VARIABLE periodcheckinfo_hadeslvl1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => hadeslvl1_ipd,
+        TestSignalName => "hadeslvl1",
+        Period => tperiod_hadeslvl1,
+        PulseWidthHigh => tpw_hadeslvl1_posedge,
+        PulseWidthLow => tpw_hadeslvl1_negedge,
+        PeriodData => periodcheckinfo_hadeslvl1,
+        Violation => tviol_hadeslvl1_hadeslvl1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => hadeslvl1_ipd'last_event,
+                           PathDelay => tpd_hadeslvl1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_lvl1_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_lvl1_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_lvl1_MGIOL";
+
+      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_INFF	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_lvl1_MGIOL : ENTITY IS TRUE;
+
+  end hades_lvl1_MGIOL;
+
+  architecture Structure of hades_lvl1_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI_ipd 	: std_logic := 'X';
+    signal DI_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal INFF_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component smuxlregsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0: smuxlregsre
+      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI_ipd, DI, tipd_DI);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out)
+    VARIABLE INFF_zd         	: std_logic := 'X';
+    VARIABLE INFF_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI_CLK       	: x01 := '0';
+    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI_dly,
+        TestSignalName => "DI",
+        TestDelay => tisd_DI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI_CLK_noedge_posedge,
+        SetupLow => tsetup_DI_CLK_noedge_posedge,
+        HoldHigh => thold_DI_CLK_noedge_posedge,
+        HoldLow => thold_DI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI_CLK_TimingDatash,
+        Violation => tviol_DI_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    INFF_zd 	:= INFF_out;
+
+    VitalPathDelay01 (
+      OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_INFF,
+                           PathCondition => TRUE)),
+      GlitchData => INFF_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_raw_valid_vect_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_raw_valid_vect_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_raw_valid_vect_1_B");
+
+    port (hadesrawvalidvect1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_raw_valid_vect_1_B : ENTITY IS TRUE;
+
+  end hades_raw_valid_vect_1_B;
+
+  architecture Structure of hades_raw_valid_vect_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal hadesrawvalidvect1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component sapiobuf
+      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_raw_valid_vect_pad_1: sapiobuf
+      port map (I=>GNDI, T=>VCCI, PAD=>hadesrawvalidvect1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+    END BLOCK;
+
+    VitalBehavior : PROCESS (hadesrawvalidvect1_out)
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesrawvalidvect1 	<= hadesrawvalidvect1_out;
+
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_raw_out_validB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_raw_out_validB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_raw_out_validB";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_hadesrawoutvalid	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; hadesrawoutvalid: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_raw_out_validB : ENTITY IS TRUE;
+
+  end hades_raw_out_validB;
+
+  architecture Structure of hades_raw_out_validB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal hadesrawoutvalid_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    hades_raw_out_valid_pad: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>hadesrawoutvalid_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, hadesrawoutvalid_out)
+    VARIABLE hadesrawoutvalid_zd         	: std_logic := 'X';
+    VARIABLE hadesrawoutvalid_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    hadesrawoutvalid_zd 	:= hadesrawoutvalid_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => hadesrawoutvalid, OutSignalName => "hadesrawoutvalid", OutTemp => hadesrawoutvalid_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_hadesrawoutvalid,
+                           PathCondition => TRUE)),
+      GlitchData => hadesrawoutvalid_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_raw_out_valid_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_raw_out_valid_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_raw_out_valid_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_raw_out_valid_MGIOL : ENTITY IS TRUE;
+
+  end hades_raw_out_valid_MGIOL;
+
+  architecture Structure of hades_raw_out_valid_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component mfflsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    hades_tdc_bundle_inst_referenced_out_validio: mfflsre
+      port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, 
+                Q=>IOLDO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity hades_trigB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity hades_trigB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "hades_trigB";
+
+      tipd_hadestrig  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_hadestrig_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_hadestrig 	: VitalDelayType := 0 ns;
+      tpw_hadestrig_posedge	: VitalDelayType := 0 ns;
+      tpw_hadestrig_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; hadestrig: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF hades_trigB : ENTITY IS TRUE;
+
+  end hades_trigB;
+
+  architecture Structure of hades_trigB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal hadestrig_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    hades_trig_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>hadestrig_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(hadestrig_ipd, hadestrig, tipd_hadestrig);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, hadestrig_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_hadestrig_hadestrig          	: x01 := '0';
+    VARIABLE periodcheckinfo_hadestrig	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => hadestrig_ipd,
+        TestSignalName => "hadestrig",
+        Period => tperiod_hadestrig,
+        PulseWidthHigh => tpw_hadestrig_posedge,
+        PulseWidthLow => tpw_hadestrig_negedge,
+        PeriodData => periodcheckinfo_hadestrig,
+        Violation => tviol_hadestrig_hadestrig,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => hadestrig_ipd'last_event,
+                           PathDelay => tpd_hadestrig_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity release_outB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity release_outB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "release_outB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_releaseout	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; releaseout: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF release_outB : ENTITY IS TRUE;
+
+  end release_outB;
+
+  architecture Structure of release_outB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal releaseout_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    release_out_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>releaseout_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, releaseout_out)
+    VARIABLE releaseout_zd         	: std_logic := 'X';
+    VARIABLE releaseout_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    releaseout_zd 	:= releaseout_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => releaseout, OutSignalName => "releaseout", OutTemp => releaseout_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_releaseout,
+                           PathCondition => TRUE)),
+      GlitchData => releaseout_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity finishedB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity finishedB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "finishedB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_finishedS	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; finishedS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF finishedB : ENTITY IS TRUE;
+
+  end finishedB;
+
+  architecture Structure of finishedB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal finishedS_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    finished_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>finishedS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, finishedS_out)
+    VARIABLE finishedS_zd         	: std_logic := 'X';
+    VARIABLE finishedS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    finishedS_zd 	:= finishedS_out;
+
+    VitalPathDelay01 (
+      OutSignal => finishedS, OutSignalName => "finishedS", OutTemp => finishedS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_finishedS,
+                           PathCondition => TRUE)),
+      GlitchData => finishedS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity last_buf_emptyB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity last_buf_emptyB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "last_buf_emptyB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_lastbufempty	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; lastbufempty: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF last_buf_emptyB : ENTITY IS TRUE;
+
+  end last_buf_emptyB;
+
+  architecture Structure of last_buf_emptyB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal lastbufempty_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    last_buf_empty_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>lastbufempty_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, lastbufempty_out)
+    VARIABLE lastbufempty_zd         	: std_logic := 'X';
+    VARIABLE lastbufempty_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    lastbufempty_zd 	:= lastbufempty_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => lastbufempty, OutSignalName => "lastbufempty", OutTemp => lastbufempty_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_lastbufempty,
+                           PathCondition => TRUE)),
+      GlitchData => lastbufempty_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity discardB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity discardB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "discardB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_discardS	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; discardS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF discardB : ENTITY IS TRUE;
+
+  end discardB;
+
+  architecture Structure of discardB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal discardS_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    discard_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>discardS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, discardS_out)
+    VARIABLE discardS_zd         	: std_logic := 'X';
+    VARIABLE discardS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    discardS_zd 	:= discardS_out;
+
+    VitalPathDelay01 (
+      OutSignal => discardS, OutSignalName => "discardS", OutTemp => discardS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_discardS,
+                           PathCondition => TRUE)),
+      GlitchData => discardS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity burstB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity burstB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "burstB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_burstS	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; burstS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF burstB : ENTITY IS TRUE;
+
+  end burstB;
+
+  architecture Structure of burstB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal burstS_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    burst_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>burstS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, burstS_out)
+    VARIABLE burstS_zd         	: std_logic := 'X';
+    VARIABLE burstS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    burstS_zd 	:= burstS_out;
+
+    VitalPathDelay01 (
+      OutSignal => burstS, OutSignalName => "burstS", OutTemp => burstS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_burstS,
+                           PathCondition => TRUE)),
+      GlitchData => burstS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity LVL1_TRG_DATA_VALI_IN_risingB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity LVL1_TRG_DATA_VALI_IN_risingB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LVL1_TRG_DATA_VALI_IN_risingB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_LVL1TRGDATAVALIINrising	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; LVL1TRGDATAVALIINrising: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALI_IN_risingB : ENTITY IS TRUE;
+
+  end LVL1_TRG_DATA_VALI_IN_risingB;
+
+  architecture Structure of LVL1_TRG_DATA_VALI_IN_risingB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal LVL1TRGDATAVALIINrising_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    LVL1_TRG_DATA_VALI_IN_rising_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>LVL1TRGDATAVALIINrising_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, LVL1TRGDATAVALIINrising_out)
+    VARIABLE LVL1TRGDATAVALIINrising_zd         	: std_logic := 'X';
+    VARIABLE LVL1TRGDATAVALIINrising_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    LVL1TRGDATAVALIINrising_zd 	:= LVL1TRGDATAVALIINrising_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => LVL1TRGDATAVALIINrising, OutSignalName => "LVL1TRGDATAVALIINrising", OutTemp => LVL1TRGDATAVALIINrising_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_LVL1TRGDATAVALIINrising,
+                           PathCondition => TRUE)),
+      GlitchData => LVL1TRGDATAVALIINrising_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_TRG_RELEASE_OUTB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_TRG_RELEASE_OUTB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_TRG_RELEASE_OUTB";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_FEETRGRELEASEOUT	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; FEETRGRELEASEOUT: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_TRG_RELEASE_OUTB : ENTITY IS TRUE;
+
+  end FEE_TRG_RELEASE_OUTB;
+
+  architecture Structure of FEE_TRG_RELEASE_OUTB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal FEETRGRELEASEOUT_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_TRG_RELEASE_OUT_pad: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>FEETRGRELEASEOUT_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, FEETRGRELEASEOUT_out)
+    VARIABLE FEETRGRELEASEOUT_zd         	: std_logic := 'X';
+    VARIABLE FEETRGRELEASEOUT_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEETRGRELEASEOUT_zd 	:= FEETRGRELEASEOUT_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEETRGRELEASEOUT, OutSignalName => "FEETRGRELEASEOUT", OutTemp => FEETRGRELEASEOUT_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_FEETRGRELEASEOUT,
+                           PathCondition => TRUE)),
+      GlitchData => FEETRGRELEASEOUT_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_TRG_RELEASE_OUT_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_TRG_RELEASE_OUT_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_TRG_RELEASE_OUT_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_TRG_RELEASE_OUT_MGIOL : ENTITY IS TRUE;
+
+  end FEE_TRG_RELEASE_OUT_MGIOL;
+
+  architecture Structure of FEE_TRG_RELEASE_OUT_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_FEE_TRG_RELEASE_OUTio: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATAFINISHED_OUTB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATAFINISHED_OUTB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATAFINISHED_OUTB";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_FEEDATAFINISHEDOUT	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; FEEDATAFINISHEDOUT: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATAFINISHED_OUTB : ENTITY IS TRUE;
+
+  end FEE_DATAFINISHED_OUTB;
+
+  architecture Structure of FEE_DATAFINISHED_OUTB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal FEEDATAFINISHEDOUT_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATAFINISHED_OUT_pad: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>FEEDATAFINISHEDOUT_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, FEEDATAFINISHEDOUT_out)
+    VARIABLE FEEDATAFINISHEDOUT_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAFINISHEDOUT_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAFINISHEDOUT_zd 	:= FEEDATAFINISHEDOUT_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAFINISHEDOUT, OutSignalName => "FEEDATAFINISHEDOUT", OutTemp => FEEDATAFINISHEDOUT_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_FEEDATAFINISHEDOUT,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAFINISHEDOUT_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATAFINISHED_OUT_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATAFINISHED_OUT_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATAFINISHED_OUT_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATAFINISHED_OUT_MGIOL : ENTITY IS TRUE;
+
+  end FEE_DATAFINISHED_OUT_MGIOL;
+
+  architecture Structure of FEE_DATAFINISHED_OUT_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_FEE_DATAFINISHED_OUTio: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_WRITE_OUTB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_WRITE_OUTB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_WRITE_OUTB";
+
+      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_IOLDO_FEEDATAWRITEOUT	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (IOLDO: in Std_logic; FEEDATAWRITEOUT: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_WRITE_OUTB : ENTITY IS TRUE;
+
+  end FEE_DATA_WRITE_OUTB;
+
+  architecture Structure of FEE_DATA_WRITE_OUTB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_ipd 	: std_logic := 'X';
+    signal FEEDATAWRITEOUT_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_WRITE_OUT_pad: sapiobuf0249
+      port map (I=>IOLDO_ipd, PAD=>FEEDATAWRITEOUT_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_ipd, FEEDATAWRITEOUT_out)
+    VARIABLE FEEDATAWRITEOUT_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAWRITEOUT_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAWRITEOUT_zd 	:= FEEDATAWRITEOUT_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAWRITEOUT, OutSignalName => "FEEDATAWRITEOUT", OutTemp => FEEDATAWRITEOUT_zd,
+      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
+                           PathDelay => tpd_IOLDO_FEEDATAWRITEOUT,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAWRITEOUT_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_WRITE_OUT_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_WRITE_OUT_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_WRITE_OUT_MGIOL";
+
+      tipd_TXDATA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_TXDATA0_CLK	: VitalDelayType := 0 ns;
+      tsetup_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_TXDATA0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_WRITE_OUT_MGIOL : ENTITY IS TRUE;
+
+  end FEE_DATA_WRITE_OUT_MGIOL;
+
+  architecture Structure of FEE_DATA_WRITE_OUT_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal IOLDO_out 	: std_logic := 'X';
+    signal TXDATA0_ipd 	: std_logic := 'X';
+    signal TXDATA0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component mfflsre0251
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_FEE_DATA_WRITE_OUTio: mfflsre0251
+      port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, 
+                Q=>IOLDO_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly)
+    VARIABLE IOLDO_zd         	: std_logic := 'X';
+    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_TXDATA0_CLK       	: x01 := '0';
+    VARIABLE TXDATA0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => TXDATA0_dly,
+        TestSignalName => "TXDATA0",
+        TestDelay => tisd_TXDATA0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge,
+        SetupLow => tsetup_TXDATA0_CLK_noedge_posedge,
+        HoldHigh => thold_TXDATA0_CLK_noedge_posedge,
+        HoldLow => thold_TXDATA0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => TXDATA0_CLK_TimingDatash,
+        Violation => tviol_TXDATA0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    IOLDO_zd 	:= IOLDO_out;
+
+    VitalPathDelay01 (
+      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_IOLDO,
+                           PathCondition => TRUE)),
+      GlitchData => IOLDO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_31_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_31_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_31_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT31	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT31: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_31_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_31_B;
+
+  architecture Structure of FEE_DATA_OUT_31_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT31_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_31: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT31_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT31_out)
+    VARIABLE FEEDATAOUT31_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT31_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT31_zd 	:= FEEDATAOUT31_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT31, OutSignalName => "FEEDATAOUT31", OutTemp => FEEDATAOUT31_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT31,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT31_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_30_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_30_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_30_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT30	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT30: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_30_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_30_B;
+
+  architecture Structure of FEE_DATA_OUT_30_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT30_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_30: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT30_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT30_out)
+    VARIABLE FEEDATAOUT30_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT30_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT30_zd 	:= FEEDATAOUT30_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT30, OutSignalName => "FEEDATAOUT30", OutTemp => FEEDATAOUT30_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT30,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT30_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_29_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_29_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_29_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT29	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT29: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_29_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_29_B;
+
+  architecture Structure of FEE_DATA_OUT_29_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT29_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_29: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT29_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT29_out)
+    VARIABLE FEEDATAOUT29_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT29_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT29_zd 	:= FEEDATAOUT29_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT29, OutSignalName => "FEEDATAOUT29", OutTemp => FEEDATAOUT29_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT29,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT29_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_28_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_28_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_28_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT28	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT28: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_28_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_28_B;
+
+  architecture Structure of FEE_DATA_OUT_28_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT28_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_28: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT28_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT28_out)
+    VARIABLE FEEDATAOUT28_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT28_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT28_zd 	:= FEEDATAOUT28_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT28, OutSignalName => "FEEDATAOUT28", OutTemp => FEEDATAOUT28_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT28,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT28_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_27_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_27_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_27_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT27	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT27: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_27_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_27_B;
+
+  architecture Structure of FEE_DATA_OUT_27_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT27_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_27: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT27_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT27_out)
+    VARIABLE FEEDATAOUT27_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT27_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT27_zd 	:= FEEDATAOUT27_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT27, OutSignalName => "FEEDATAOUT27", OutTemp => FEEDATAOUT27_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT27,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT27_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_26_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_26_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_26_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT26	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT26: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_26_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_26_B;
+
+  architecture Structure of FEE_DATA_OUT_26_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT26_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_26: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT26_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT26_out)
+    VARIABLE FEEDATAOUT26_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT26_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT26_zd 	:= FEEDATAOUT26_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT26, OutSignalName => "FEEDATAOUT26", OutTemp => FEEDATAOUT26_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT26,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT26_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_25_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_25_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_25_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT25	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT25: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_25_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_25_B;
+
+  architecture Structure of FEE_DATA_OUT_25_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT25_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_25: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT25_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT25_out)
+    VARIABLE FEEDATAOUT25_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT25_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT25_zd 	:= FEEDATAOUT25_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT25, OutSignalName => "FEEDATAOUT25", OutTemp => FEEDATAOUT25_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT25,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT25_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_24_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_24_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_24_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT24	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT24: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_24_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_24_B;
+
+  architecture Structure of FEE_DATA_OUT_24_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT24_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_24: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT24_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT24_out)
+    VARIABLE FEEDATAOUT24_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT24_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT24_zd 	:= FEEDATAOUT24_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT24, OutSignalName => "FEEDATAOUT24", OutTemp => FEEDATAOUT24_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT24,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT24_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_23_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_23_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_23_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT23	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT23: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_23_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_23_B;
+
+  architecture Structure of FEE_DATA_OUT_23_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT23_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_23: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT23_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT23_out)
+    VARIABLE FEEDATAOUT23_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT23_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT23_zd 	:= FEEDATAOUT23_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT23, OutSignalName => "FEEDATAOUT23", OutTemp => FEEDATAOUT23_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT23,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT23_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_22_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_22_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_22_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT22	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT22: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_22_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_22_B;
+
+  architecture Structure of FEE_DATA_OUT_22_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT22_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_22: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT22_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT22_out)
+    VARIABLE FEEDATAOUT22_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT22_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT22_zd 	:= FEEDATAOUT22_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT22, OutSignalName => "FEEDATAOUT22", OutTemp => FEEDATAOUT22_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT22,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT22_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_21_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_21_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_21_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT21	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT21: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_21_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_21_B;
+
+  architecture Structure of FEE_DATA_OUT_21_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT21_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_21: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT21_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT21_out)
+    VARIABLE FEEDATAOUT21_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT21_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT21_zd 	:= FEEDATAOUT21_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT21, OutSignalName => "FEEDATAOUT21", OutTemp => FEEDATAOUT21_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT21,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT21_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_20_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_20_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_20_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT20	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT20: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_20_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_20_B;
+
+  architecture Structure of FEE_DATA_OUT_20_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT20_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_20: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT20_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT20_out)
+    VARIABLE FEEDATAOUT20_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT20_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT20_zd 	:= FEEDATAOUT20_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT20, OutSignalName => "FEEDATAOUT20", OutTemp => FEEDATAOUT20_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT20,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT20_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_19_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_19_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_19_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT19	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT19: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_19_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_19_B;
+
+  architecture Structure of FEE_DATA_OUT_19_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT19_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_19: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT19_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT19_out)
+    VARIABLE FEEDATAOUT19_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT19_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT19_zd 	:= FEEDATAOUT19_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT19, OutSignalName => "FEEDATAOUT19", OutTemp => FEEDATAOUT19_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT19,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT19_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_18_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_18_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_18_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT18	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT18: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_18_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_18_B;
+
+  architecture Structure of FEE_DATA_OUT_18_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT18_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_18: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT18_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT18_out)
+    VARIABLE FEEDATAOUT18_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT18_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT18_zd 	:= FEEDATAOUT18_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT18, OutSignalName => "FEEDATAOUT18", OutTemp => FEEDATAOUT18_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT18,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT18_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_17_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_17_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_17_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT17	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT17: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_17_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_17_B;
+
+  architecture Structure of FEE_DATA_OUT_17_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT17_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_17: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT17_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT17_out)
+    VARIABLE FEEDATAOUT17_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT17_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT17_zd 	:= FEEDATAOUT17_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT17, OutSignalName => "FEEDATAOUT17", OutTemp => FEEDATAOUT17_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT17,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT17_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_16_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_16_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_16_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT16	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT16: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_16_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_16_B;
+
+  architecture Structure of FEE_DATA_OUT_16_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT16_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_16: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT16_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT16_out)
+    VARIABLE FEEDATAOUT16_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT16_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT16_zd 	:= FEEDATAOUT16_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT16, OutSignalName => "FEEDATAOUT16", OutTemp => FEEDATAOUT16_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT16,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT16_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_15_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_15_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_15_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT15	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT15: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_15_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_15_B;
+
+  architecture Structure of FEE_DATA_OUT_15_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT15_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_15: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT15_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT15_out)
+    VARIABLE FEEDATAOUT15_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT15_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT15_zd 	:= FEEDATAOUT15_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT15, OutSignalName => "FEEDATAOUT15", OutTemp => FEEDATAOUT15_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT15,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT15_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_14_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_14_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_14_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT14	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT14: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_14_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_14_B;
+
+  architecture Structure of FEE_DATA_OUT_14_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT14_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_14: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT14_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT14_out)
+    VARIABLE FEEDATAOUT14_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT14_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT14_zd 	:= FEEDATAOUT14_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT14, OutSignalName => "FEEDATAOUT14", OutTemp => FEEDATAOUT14_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT14,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT14_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_13_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_13_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_13_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT13	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT13: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_13_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_13_B;
+
+  architecture Structure of FEE_DATA_OUT_13_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT13_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_13: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT13_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT13_out)
+    VARIABLE FEEDATAOUT13_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT13_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT13_zd 	:= FEEDATAOUT13_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT13, OutSignalName => "FEEDATAOUT13", OutTemp => FEEDATAOUT13_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT13,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT13_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_12_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_12_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_12_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT12	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT12: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_12_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_12_B;
+
+  architecture Structure of FEE_DATA_OUT_12_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT12_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_12: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT12_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT12_out)
+    VARIABLE FEEDATAOUT12_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT12_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT12_zd 	:= FEEDATAOUT12_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT12, OutSignalName => "FEEDATAOUT12", OutTemp => FEEDATAOUT12_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT12,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT12_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_11_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT11	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_11_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_11_B;
+
+  architecture Structure of FEE_DATA_OUT_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT11_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_11: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT11_out)
+    VARIABLE FEEDATAOUT11_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT11_zd 	:= FEEDATAOUT11_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT11, OutSignalName => "FEEDATAOUT11", OutTemp => FEEDATAOUT11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT11,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_10_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT10	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_10_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_10_B;
+
+  architecture Structure of FEE_DATA_OUT_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT10_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_10: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT10_out)
+    VARIABLE FEEDATAOUT10_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT10_zd 	:= FEEDATAOUT10_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT10, OutSignalName => "FEEDATAOUT10", OutTemp => FEEDATAOUT10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT10,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_9_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT9	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_9_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_9_B;
+
+  architecture Structure of FEE_DATA_OUT_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT9_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_9: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT9_out)
+    VARIABLE FEEDATAOUT9_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT9_zd 	:= FEEDATAOUT9_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT9, OutSignalName => "FEEDATAOUT9", OutTemp => FEEDATAOUT9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT9,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_8_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_8_B;
+
+  architecture Structure of FEE_DATA_OUT_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT8_out)
+    VARIABLE FEEDATAOUT8_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT8_zd 	:= FEEDATAOUT8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT8, OutSignalName => "FEEDATAOUT8", OutTemp => FEEDATAOUT8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT8,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_7_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_7_B;
+
+  architecture Structure of FEE_DATA_OUT_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT7_out)
+    VARIABLE FEEDATAOUT7_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT7_zd 	:= FEEDATAOUT7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT7, OutSignalName => "FEEDATAOUT7", OutTemp => FEEDATAOUT7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT7,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_6_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_6_B;
+
+  architecture Structure of FEE_DATA_OUT_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT6_out)
+    VARIABLE FEEDATAOUT6_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT6_zd 	:= FEEDATAOUT6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT6, OutSignalName => "FEEDATAOUT6", OutTemp => FEEDATAOUT6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT6,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_5_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_5_B;
+
+  architecture Structure of FEE_DATA_OUT_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT5_out)
+    VARIABLE FEEDATAOUT5_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT5_zd 	:= FEEDATAOUT5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT5, OutSignalName => "FEEDATAOUT5", OutTemp => FEEDATAOUT5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT5,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_4_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_4_B;
+
+  architecture Structure of FEE_DATA_OUT_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT4_out)
+    VARIABLE FEEDATAOUT4_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT4_zd 	:= FEEDATAOUT4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT4, OutSignalName => "FEEDATAOUT4", OutTemp => FEEDATAOUT4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT4,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_3_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_3_B;
+
+  architecture Structure of FEE_DATA_OUT_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT3_out)
+    VARIABLE FEEDATAOUT3_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT3_zd 	:= FEEDATAOUT3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT3, OutSignalName => "FEEDATAOUT3", OutTemp => FEEDATAOUT3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT3,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_2_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_2_B;
+
+  architecture Structure of FEE_DATA_OUT_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT2_out)
+    VARIABLE FEEDATAOUT2_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT2_zd 	:= FEEDATAOUT2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT2, OutSignalName => "FEEDATAOUT2", OutTemp => FEEDATAOUT2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT2,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_1_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_1_B;
+
+  architecture Structure of FEE_DATA_OUT_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT1_out)
+    VARIABLE FEEDATAOUT1_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT1_zd 	:= FEEDATAOUT1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT1, OutSignalName => "FEEDATAOUT1", OutTemp => FEEDATAOUT1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT1,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity FEE_DATA_OUT_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity FEE_DATA_OUT_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "FEE_DATA_OUT_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_FEEDATAOUT0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; FEEDATAOUT0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_0_B : ENTITY IS TRUE;
+
+  end FEE_DATA_OUT_0_B;
+
+  architecture Structure of FEE_DATA_OUT_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal FEEDATAOUT0_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    FEE_DATA_OUT_pad_0: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>FEEDATAOUT0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT0_out)
+    VARIABLE FEEDATAOUT0_zd         	: std_logic := 'X';
+    VARIABLE FEEDATAOUT0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    FEEDATAOUT0_zd 	:= FEEDATAOUT0_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => FEEDATAOUT0, OutSignalName => "FEEDATAOUT0", OutTemp => FEEDATAOUT0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_FEEDATAOUT0,
+                           PathCondition => TRUE)),
+      GlitchData => FEEDATAOUT0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity LVL1_INVALID_TRG_INB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity LVL1_INVALID_TRG_INB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LVL1_INVALID_TRG_INB";
+
+      tipd_LVL1INVALIDTRGIN  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_LVL1INVALIDTRGIN_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LVL1INVALIDTRGIN 	: VitalDelayType := 0 ns;
+      tpw_LVL1INVALIDTRGIN_posedge	: VitalDelayType := 0 ns;
+      tpw_LVL1INVALIDTRGIN_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; LVL1INVALIDTRGIN: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LVL1_INVALID_TRG_INB : ENTITY IS TRUE;
+
+  end LVL1_INVALID_TRG_INB;
+
+  architecture Structure of LVL1_INVALID_TRG_INB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal LVL1INVALIDTRGIN_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    LVL1_INVALID_TRG_IN_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>LVL1INVALIDTRGIN_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(LVL1INVALIDTRGIN_ipd, LVL1INVALIDTRGIN, tipd_LVL1INVALIDTRGIN);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, LVL1INVALIDTRGIN_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_LVL1INVALIDTRGIN_LVL1INVALIDTRGIN          	: x01 := '0';
+    VARIABLE periodcheckinfo_LVL1INVALIDTRGIN	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => LVL1INVALIDTRGIN_ipd,
+        TestSignalName => "LVL1INVALIDTRGIN",
+        Period => tperiod_LVL1INVALIDTRGIN,
+        PulseWidthHigh => tpw_LVL1INVALIDTRGIN_posedge,
+        PulseWidthLow => tpw_LVL1INVALIDTRGIN_negedge,
+        PeriodData => periodcheckinfo_LVL1INVALIDTRGIN,
+        Violation => tviol_LVL1INVALIDTRGIN_LVL1INVALIDTRGIN,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => LVL1INVALIDTRGIN_ipd'last_event,
+                           PathDelay => tpd_LVL1INVALIDTRGIN_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity LVL1_INVALID_TRG_IN_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity LVL1_INVALID_TRG_IN_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LVL1_INVALID_TRG_IN_MGIOL";
+
+      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_INFF	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LVL1_INVALID_TRG_IN_MGIOL : ENTITY IS TRUE;
+
+  end LVL1_INVALID_TRG_IN_MGIOL;
+
+  architecture Structure of LVL1_INVALID_TRG_IN_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI_ipd 	: std_logic := 'X';
+    signal DI_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal INFF_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component smuxlregsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0: smuxlregsre
+      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI_ipd, DI, tipd_DI);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out)
+    VARIABLE INFF_zd         	: std_logic := 'X';
+    VARIABLE INFF_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI_CLK       	: x01 := '0';
+    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI_dly,
+        TestSignalName => "DI",
+        TestDelay => tisd_DI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI_CLK_noedge_posedge,
+        SetupLow => tsetup_DI_CLK_noedge_posedge,
+        HoldHigh => thold_DI_CLK_noedge_posedge,
+        HoldLow => thold_DI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI_CLK_TimingDatash,
+        Violation => tviol_DI_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    INFF_zd 	:= INFF_out;
+
+    VitalPathDelay01 (
+      OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_INFF,
+                           PathCondition => TRUE)),
+      GlitchData => INFF_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity LVL1_TRG_DATA_VALID_INB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity LVL1_TRG_DATA_VALID_INB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LVL1_TRG_DATA_VALID_INB";
+
+      tipd_LVL1TRGDATAVALIDIN  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_LVL1TRGDATAVALIDIN_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_LVL1TRGDATAVALIDIN 	: VitalDelayType := 0 ns;
+      tpw_LVL1TRGDATAVALIDIN_posedge	: VitalDelayType := 0 ns;
+      tpw_LVL1TRGDATAVALIDIN_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; LVL1TRGDATAVALIDIN: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALID_INB : ENTITY IS TRUE;
+
+  end LVL1_TRG_DATA_VALID_INB;
+
+  architecture Structure of LVL1_TRG_DATA_VALID_INB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal LVL1TRGDATAVALIDIN_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    LVL1_TRG_DATA_VALID_IN_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>LVL1TRGDATAVALIDIN_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+
+        VitalWireDelay(LVL1TRGDATAVALIDIN_ipd, LVL1TRGDATAVALIDIN, tipd_LVL1TRGDATAVALIDIN);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, LVL1TRGDATAVALIDIN_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_LVL1TRGDATAVALIDIN_LVL1TRGDATAVALIDIN          	: x01 := '0';
+    VARIABLE periodcheckinfo_LVL1TRGDATAVALIDIN	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => LVL1TRGDATAVALIDIN_ipd,
+        TestSignalName => "LVL1TRGDATAVALIDIN",
+        Period => tperiod_LVL1TRGDATAVALIDIN,
+        PulseWidthHigh => tpw_LVL1TRGDATAVALIDIN_posedge,
+        PulseWidthLow => tpw_LVL1TRGDATAVALIDIN_negedge,
+        PeriodData => periodcheckinfo_LVL1TRGDATAVALIDIN,
+        Violation => tviol_LVL1TRGDATAVALIDIN_LVL1TRGDATAVALIDIN,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (
+        0 => (InputChangeTime => LVL1TRGDATAVALIDIN_ipd'last_event,
+                           PathDelay => tpd_LVL1TRGDATAVALIDIN_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity LVL1_TRG_DATA_VALID_IN_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity LVL1_TRG_DATA_VALID_IN_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LVL1_TRG_DATA_VALID_IN_MGIOL";
+
+      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_INFF	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALID_IN_MGIOL : ENTITY IS TRUE;
+
+  end LVL1_TRG_DATA_VALID_IN_MGIOL;
+
+  architecture Structure of LVL1_TRG_DATA_VALID_IN_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI_ipd 	: std_logic := 'X';
+    signal DI_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal INFF_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component smuxlregsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0: smuxlregsre
+      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI_ipd, DI, tipd_DI);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out)
+    VARIABLE INFF_zd         	: std_logic := 'X';
+    VARIABLE INFF_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI_CLK       	: x01 := '0';
+    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI_dly,
+        TestSignalName => "DI",
+        TestDelay => tisd_DI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI_CLK_noedge_posedge,
+        SetupLow => tsetup_DI_CLK_noedge_posedge,
+        HoldHigh => thold_DI_CLK_noedge_posedge,
+        HoldLow => thold_DI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI_CLK_TimingDatash,
+        Violation => tviol_DI_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    INFF_zd 	:= INFF_out;
+
+    VitalPathDelay01 (
+      OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_INFF,
+                           PathCondition => TRUE)),
+      GlitchData => INFF_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_empty1B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_empty1B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_empty1B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifoempty1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifoempty1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_empty1B : ENTITY IS TRUE;
+
+  end fifo_empty1B;
+
+  architecture Structure of fifo_empty1B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifoempty1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_empty1_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifoempty1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifoempty1_out)
+    VARIABLE fifoempty1_zd         	: std_logic := 'X';
+    VARIABLE fifoempty1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifoempty1_zd 	:= fifoempty1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifoempty1, OutSignalName => "fifoempty1", OutTemp => fifoempty1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifoempty1,
+                           PathCondition => TRUE)),
+      GlitchData => fifoempty1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_rdenB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_rdenB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_rdenB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fiforden	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fiforden: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_rdenB : ENTITY IS TRUE;
+
+  end fifo_rdenB;
+
+  architecture Structure of fifo_rdenB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fiforden_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_rden_pad: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fiforden_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fiforden_out)
+    VARIABLE fiforden_zd         	: std_logic := 'X';
+    VARIABLE fiforden_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fiforden_zd 	:= fiforden_out;
+
+    VitalPathDelay01 (
+      OutSignal => fiforden, OutSignalName => "fiforden", OutTemp => fiforden_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fiforden,
+                           PathCondition => TRUE)),
+      GlitchData => fiforden_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_31_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_31_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_31_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout31	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout31: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_31_B : ENTITY IS TRUE;
+
+  end fifo_data_out_31_B;
+
+  architecture Structure of fifo_data_out_31_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout31_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_31: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout31_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout31_out)
+    VARIABLE fifodataout31_zd         	: std_logic := 'X';
+    VARIABLE fifodataout31_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout31_zd 	:= fifodataout31_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout31, OutSignalName => "fifodataout31", OutTemp => fifodataout31_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout31,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout31_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_30_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_30_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_30_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout30	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout30: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_30_B : ENTITY IS TRUE;
+
+  end fifo_data_out_30_B;
+
+  architecture Structure of fifo_data_out_30_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout30_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_30: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout30_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout30_out)
+    VARIABLE fifodataout30_zd         	: std_logic := 'X';
+    VARIABLE fifodataout30_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout30_zd 	:= fifodataout30_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout30, OutSignalName => "fifodataout30", OutTemp => fifodataout30_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout30,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout30_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_29_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_29_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_29_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout29	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout29: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_29_B : ENTITY IS TRUE;
+
+  end fifo_data_out_29_B;
+
+  architecture Structure of fifo_data_out_29_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout29_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_29: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout29_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout29_out)
+    VARIABLE fifodataout29_zd         	: std_logic := 'X';
+    VARIABLE fifodataout29_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout29_zd 	:= fifodataout29_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout29, OutSignalName => "fifodataout29", OutTemp => fifodataout29_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout29,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout29_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_28_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_28_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_28_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout28	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout28: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_28_B : ENTITY IS TRUE;
+
+  end fifo_data_out_28_B;
+
+  architecture Structure of fifo_data_out_28_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout28_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_28: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout28_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout28_out)
+    VARIABLE fifodataout28_zd         	: std_logic := 'X';
+    VARIABLE fifodataout28_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout28_zd 	:= fifodataout28_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout28, OutSignalName => "fifodataout28", OutTemp => fifodataout28_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout28,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout28_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_27_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_27_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_27_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout27	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout27: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_27_B : ENTITY IS TRUE;
+
+  end fifo_data_out_27_B;
+
+  architecture Structure of fifo_data_out_27_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout27_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_27: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout27_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout27_out)
+    VARIABLE fifodataout27_zd         	: std_logic := 'X';
+    VARIABLE fifodataout27_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout27_zd 	:= fifodataout27_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout27, OutSignalName => "fifodataout27", OutTemp => fifodataout27_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout27,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout27_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_26_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_26_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_26_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout26	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout26: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_26_B : ENTITY IS TRUE;
+
+  end fifo_data_out_26_B;
+
+  architecture Structure of fifo_data_out_26_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout26_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_26: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout26_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout26_out)
+    VARIABLE fifodataout26_zd         	: std_logic := 'X';
+    VARIABLE fifodataout26_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout26_zd 	:= fifodataout26_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout26, OutSignalName => "fifodataout26", OutTemp => fifodataout26_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout26,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout26_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_25_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_25_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_25_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout25	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout25: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_25_B : ENTITY IS TRUE;
+
+  end fifo_data_out_25_B;
+
+  architecture Structure of fifo_data_out_25_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout25_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_25: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout25_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout25_out)
+    VARIABLE fifodataout25_zd         	: std_logic := 'X';
+    VARIABLE fifodataout25_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout25_zd 	:= fifodataout25_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout25, OutSignalName => "fifodataout25", OutTemp => fifodataout25_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout25,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout25_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_24_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_24_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_24_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout24	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout24: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_24_B : ENTITY IS TRUE;
+
+  end fifo_data_out_24_B;
+
+  architecture Structure of fifo_data_out_24_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout24_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_24: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout24_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout24_out)
+    VARIABLE fifodataout24_zd         	: std_logic := 'X';
+    VARIABLE fifodataout24_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout24_zd 	:= fifodataout24_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout24, OutSignalName => "fifodataout24", OutTemp => fifodataout24_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout24,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout24_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_23_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_23_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_23_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout23	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout23: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_23_B : ENTITY IS TRUE;
+
+  end fifo_data_out_23_B;
+
+  architecture Structure of fifo_data_out_23_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout23_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_23: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout23_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout23_out)
+    VARIABLE fifodataout23_zd         	: std_logic := 'X';
+    VARIABLE fifodataout23_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout23_zd 	:= fifodataout23_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout23, OutSignalName => "fifodataout23", OutTemp => fifodataout23_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout23,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout23_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_22_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_22_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_22_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout22	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout22: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_22_B : ENTITY IS TRUE;
+
+  end fifo_data_out_22_B;
+
+  architecture Structure of fifo_data_out_22_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout22_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_22: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout22_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout22_out)
+    VARIABLE fifodataout22_zd         	: std_logic := 'X';
+    VARIABLE fifodataout22_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout22_zd 	:= fifodataout22_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout22, OutSignalName => "fifodataout22", OutTemp => fifodataout22_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout22,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout22_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_21_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_21_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_21_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout21	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout21: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_21_B : ENTITY IS TRUE;
+
+  end fifo_data_out_21_B;
+
+  architecture Structure of fifo_data_out_21_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout21_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_21: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout21_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout21_out)
+    VARIABLE fifodataout21_zd         	: std_logic := 'X';
+    VARIABLE fifodataout21_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout21_zd 	:= fifodataout21_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout21, OutSignalName => "fifodataout21", OutTemp => fifodataout21_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout21,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout21_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_20_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_20_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_20_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout20	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout20: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_20_B : ENTITY IS TRUE;
+
+  end fifo_data_out_20_B;
+
+  architecture Structure of fifo_data_out_20_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout20_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_20: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout20_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout20_out)
+    VARIABLE fifodataout20_zd         	: std_logic := 'X';
+    VARIABLE fifodataout20_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout20_zd 	:= fifodataout20_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout20, OutSignalName => "fifodataout20", OutTemp => fifodataout20_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout20,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout20_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_19_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_19_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_19_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout19	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout19: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_19_B : ENTITY IS TRUE;
+
+  end fifo_data_out_19_B;
+
+  architecture Structure of fifo_data_out_19_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout19_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_19: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout19_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout19_out)
+    VARIABLE fifodataout19_zd         	: std_logic := 'X';
+    VARIABLE fifodataout19_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout19_zd 	:= fifodataout19_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout19, OutSignalName => "fifodataout19", OutTemp => fifodataout19_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout19,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout19_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_18_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_18_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_18_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout18	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout18: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_18_B : ENTITY IS TRUE;
+
+  end fifo_data_out_18_B;
+
+  architecture Structure of fifo_data_out_18_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout18_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_18: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout18_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout18_out)
+    VARIABLE fifodataout18_zd         	: std_logic := 'X';
+    VARIABLE fifodataout18_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout18_zd 	:= fifodataout18_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout18, OutSignalName => "fifodataout18", OutTemp => fifodataout18_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout18,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout18_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_17_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_17_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_17_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout17	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout17: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_17_B : ENTITY IS TRUE;
+
+  end fifo_data_out_17_B;
+
+  architecture Structure of fifo_data_out_17_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout17_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_17: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout17_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout17_out)
+    VARIABLE fifodataout17_zd         	: std_logic := 'X';
+    VARIABLE fifodataout17_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout17_zd 	:= fifodataout17_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout17, OutSignalName => "fifodataout17", OutTemp => fifodataout17_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout17,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout17_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_16_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_16_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_16_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout16	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout16: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_16_B : ENTITY IS TRUE;
+
+  end fifo_data_out_16_B;
+
+  architecture Structure of fifo_data_out_16_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout16_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_16: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout16_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout16_out)
+    VARIABLE fifodataout16_zd         	: std_logic := 'X';
+    VARIABLE fifodataout16_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout16_zd 	:= fifodataout16_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout16, OutSignalName => "fifodataout16", OutTemp => fifodataout16_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout16,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout16_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_15_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_15_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_15_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout15	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout15: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_15_B : ENTITY IS TRUE;
+
+  end fifo_data_out_15_B;
+
+  architecture Structure of fifo_data_out_15_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout15_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_15: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout15_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout15_out)
+    VARIABLE fifodataout15_zd         	: std_logic := 'X';
+    VARIABLE fifodataout15_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout15_zd 	:= fifodataout15_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout15, OutSignalName => "fifodataout15", OutTemp => fifodataout15_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout15,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout15_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_14_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_14_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_14_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout14	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout14: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_14_B : ENTITY IS TRUE;
+
+  end fifo_data_out_14_B;
+
+  architecture Structure of fifo_data_out_14_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout14_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_14: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout14_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout14_out)
+    VARIABLE fifodataout14_zd         	: std_logic := 'X';
+    VARIABLE fifodataout14_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout14_zd 	:= fifodataout14_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout14, OutSignalName => "fifodataout14", OutTemp => fifodataout14_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout14,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout14_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_13_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_13_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_13_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout13	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout13: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_13_B : ENTITY IS TRUE;
+
+  end fifo_data_out_13_B;
+
+  architecture Structure of fifo_data_out_13_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout13_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_13: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout13_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout13_out)
+    VARIABLE fifodataout13_zd         	: std_logic := 'X';
+    VARIABLE fifodataout13_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout13_zd 	:= fifodataout13_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout13, OutSignalName => "fifodataout13", OutTemp => fifodataout13_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout13,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout13_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_12_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_12_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_12_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout12	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout12: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_12_B : ENTITY IS TRUE;
+
+  end fifo_data_out_12_B;
+
+  architecture Structure of fifo_data_out_12_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout12_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_12: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout12_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout12_out)
+    VARIABLE fifodataout12_zd         	: std_logic := 'X';
+    VARIABLE fifodataout12_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout12_zd 	:= fifodataout12_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout12, OutSignalName => "fifodataout12", OutTemp => fifodataout12_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout12,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout12_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_11_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout11	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_11_B : ENTITY IS TRUE;
+
+  end fifo_data_out_11_B;
+
+  architecture Structure of fifo_data_out_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout11_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_11: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout11_out)
+    VARIABLE fifodataout11_zd         	: std_logic := 'X';
+    VARIABLE fifodataout11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout11_zd 	:= fifodataout11_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout11, OutSignalName => "fifodataout11", OutTemp => fifodataout11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout11,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_10_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout10	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_10_B : ENTITY IS TRUE;
+
+  end fifo_data_out_10_B;
+
+  architecture Structure of fifo_data_out_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout10_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_10: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout10_out)
+    VARIABLE fifodataout10_zd         	: std_logic := 'X';
+    VARIABLE fifodataout10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout10_zd 	:= fifodataout10_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout10, OutSignalName => "fifodataout10", OutTemp => fifodataout10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout10,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_9_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout9	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_9_B : ENTITY IS TRUE;
+
+  end fifo_data_out_9_B;
+
+  architecture Structure of fifo_data_out_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout9_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_9: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout9_out)
+    VARIABLE fifodataout9_zd         	: std_logic := 'X';
+    VARIABLE fifodataout9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout9_zd 	:= fifodataout9_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout9, OutSignalName => "fifodataout9", OutTemp => fifodataout9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout9,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_8_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout8	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_8_B : ENTITY IS TRUE;
+
+  end fifo_data_out_8_B;
+
+  architecture Structure of fifo_data_out_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout8_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_8: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout8_out)
+    VARIABLE fifodataout8_zd         	: std_logic := 'X';
+    VARIABLE fifodataout8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout8_zd 	:= fifodataout8_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout8, OutSignalName => "fifodataout8", OutTemp => fifodataout8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout8,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_7_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout7	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_7_B : ENTITY IS TRUE;
+
+  end fifo_data_out_7_B;
+
+  architecture Structure of fifo_data_out_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout7_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_7: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout7_out)
+    VARIABLE fifodataout7_zd         	: std_logic := 'X';
+    VARIABLE fifodataout7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout7_zd 	:= fifodataout7_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout7, OutSignalName => "fifodataout7", OutTemp => fifodataout7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout7,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_6_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout6	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_6_B : ENTITY IS TRUE;
+
+  end fifo_data_out_6_B;
+
+  architecture Structure of fifo_data_out_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout6_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_6: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout6_out)
+    VARIABLE fifodataout6_zd         	: std_logic := 'X';
+    VARIABLE fifodataout6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout6_zd 	:= fifodataout6_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout6, OutSignalName => "fifodataout6", OutTemp => fifodataout6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout6,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_5_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout5	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_5_B : ENTITY IS TRUE;
+
+  end fifo_data_out_5_B;
+
+  architecture Structure of fifo_data_out_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout5_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_5: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout5_out)
+    VARIABLE fifodataout5_zd         	: std_logic := 'X';
+    VARIABLE fifodataout5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout5_zd 	:= fifodataout5_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout5, OutSignalName => "fifodataout5", OutTemp => fifodataout5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout5,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_4_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout4	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_4_B : ENTITY IS TRUE;
+
+  end fifo_data_out_4_B;
+
+  architecture Structure of fifo_data_out_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout4_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_4: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout4_out)
+    VARIABLE fifodataout4_zd         	: std_logic := 'X';
+    VARIABLE fifodataout4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout4_zd 	:= fifodataout4_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout4, OutSignalName => "fifodataout4", OutTemp => fifodataout4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout4,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_3_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout3	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_3_B : ENTITY IS TRUE;
+
+  end fifo_data_out_3_B;
+
+  architecture Structure of fifo_data_out_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout3_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_3: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout3_out)
+    VARIABLE fifodataout3_zd         	: std_logic := 'X';
+    VARIABLE fifodataout3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout3_zd 	:= fifodataout3_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout3, OutSignalName => "fifodataout3", OutTemp => fifodataout3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout3,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout2	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_2_B : ENTITY IS TRUE;
+
+  end fifo_data_out_2_B;
+
+  architecture Structure of fifo_data_out_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout2_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_2: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout2_out)
+    VARIABLE fifodataout2_zd         	: std_logic := 'X';
+    VARIABLE fifodataout2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout2_zd 	:= fifodataout2_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout2, OutSignalName => "fifodataout2", OutTemp => fifodataout2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout2,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity fifo_data_out_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_data_out_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_data_out_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_fifodataout1	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; fifodataout1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF fifo_data_out_1_B : ENTITY IS TRUE;
+
+  end fifo_data_out_1_B;
+
+  architecture Structure of fifo_data_out_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal fifodataout1_out 	: std_logic := 'X';
+
+    component sapiobuf0249
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    fifo_data_out_pad_1: sapiobuf0249
+      port map (I=>PADDO_ipd, PAD=>fifodataout1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, fifodataout1_out)
+    VARIABLE fifodataout1_zd         	: std_logic := 'X';
+    VARIABLE fifodataout1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    fifodataout1_zd 	:= fifodataout1_out;
+
+    VitalPathDelay01 (
+
+        OutSignal => fifodataout1, OutSignalName => "fifodataout1", OutTemp => fifodataout1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_fifodataout1,
+                           PathCondition => TRUE)),
+      GlitchData => fifodataout1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trig_2_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trig_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trig_2_B";
+
+      tipd_trig2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_trig2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_trig2 	: VitalDelayType := 0 ns;
+      tpw_trig2_posedge	: VitalDelayType := 0 ns;
+      tpw_trig2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; trig2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trig_2_B : ENTITY IS TRUE;
+
+  end trig_2_B;
+
+  architecture Structure of trig_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal trig2_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    trig_pad_2: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>trig2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(trig2_ipd, trig2, tipd_trig2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, trig2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_trig2_trig2          	: x01 := '0';
+    VARIABLE periodcheckinfo_trig2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => trig2_ipd,
+        TestSignalName => "trig2",
+        Period => tperiod_trig2,
+        PulseWidthHigh => tpw_trig2_posedge,
+        PulseWidthLow => tpw_trig2_negedge,
+        PeriodData => periodcheckinfo_trig2,
+        Violation => tviol_trig2_trig2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => trig2_ipd'last_event,
+                           PathDelay => tpd_trig2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trig_1_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trig_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trig_1_B";
+
+      tipd_trig1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_trig1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_trig1 	: VitalDelayType := 0 ns;
+      tpw_trig1_posedge	: VitalDelayType := 0 ns;
+      tpw_trig1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; trig1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trig_1_B : ENTITY IS TRUE;
+
+  end trig_1_B;
+
+  architecture Structure of trig_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal trig1_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    trig_pad_1: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>trig1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(trig1_ipd, trig1, tipd_trig1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, trig1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_trig1_trig1          	: x01 := '0';
+    VARIABLE periodcheckinfo_trig1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => trig1_ipd,
+        TestSignalName => "trig1",
+        Period => tperiod_trig1,
+        PulseWidthHigh => tpw_trig1_posedge,
+        PulseWidthLow => tpw_trig1_negedge,
+        PeriodData => periodcheckinfo_trig1,
+        Violation => tviol_trig1_trig1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => trig1_ipd'last_event,
+                           PathDelay => tpd_trig1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity trig_0_B
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity trig_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "trig_0_B";
+
+      tipd_trig0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_trig0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_trig0 	: VitalDelayType := 0 ns;
+      tpw_trig0_posedge	: VitalDelayType := 0 ns;
+      tpw_trig0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; trig0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF trig_0_B : ENTITY IS TRUE;
+
+  end trig_0_B;
+
+  architecture Structure of trig_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal trig0_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    trig_pad_0: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>trig0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(trig0_ipd, trig0, tipd_trig0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, trig0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_trig0_trig0          	: x01 := '0';
+    VARIABLE periodcheckinfo_trig0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => trig0_ipd,
+        TestSignalName => "trig0",
+        Period => tperiod_trig0,
+        PulseWidthHigh => tpw_trig0_posedge,
+        PulseWidthLow => tpw_trig0_negedge,
+        PeriodData => periodcheckinfo_trig0,
+        Violation => tviol_trig0_trig0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => trig0_ipd'last_event,
+                           PathDelay => tpd_trig0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity reset_dcB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity reset_dcB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "reset_dcB";
+
+      tipd_resetdc  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_resetdc_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_resetdc 	: VitalDelayType := 0 ns;
+      tpw_resetdc_posedge	: VitalDelayType := 0 ns;
+      tpw_resetdc_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; resetdc: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF reset_dcB : ENTITY IS TRUE;
+
+  end reset_dcB;
+
+  architecture Structure of reset_dcB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal resetdc_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    reset_dc_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>resetdc_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(resetdc_ipd, resetdc, tipd_resetdc);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, resetdc_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_resetdc_resetdc          	: x01 := '0';
+    VARIABLE periodcheckinfo_resetdc	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => resetdc_ipd,
+        TestSignalName => "resetdc",
+        Period => tperiod_resetdc,
+        PulseWidthHigh => tpw_resetdc_posedge,
+        PulseWidthLow => tpw_resetdc_negedge,
+        PeriodData => periodcheckinfo_resetdc,
+        Violation => tviol_resetdc_resetdc,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => resetdc_ipd'last_event,
+                           PathDelay => tpd_resetdc_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity reset_dc_MGIOL
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity reset_dc_MGIOL is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "reset_dc_MGIOL";
+
+      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_INFF	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF reset_dc_MGIOL : ENTITY IS TRUE;
+
+  end reset_dc_MGIOL;
+
+  architecture Structure of reset_dc_MGIOL is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DI_ipd 	: std_logic := 'X';
+    signal DI_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal INFF_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component smuxlregsre
+      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
+            LSR: in Std_logic; Q: out Std_logic);
+    end component;
+  begin
+    reset_dl_0io_1: smuxlregsre
+      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DI_ipd, DI, tipd_DI);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out)
+    VARIABLE INFF_zd         	: std_logic := 'X';
+    VARIABLE INFF_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI_CLK       	: x01 := '0';
+    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI_dly,
+        TestSignalName => "DI",
+        TestDelay => tisd_DI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI_CLK_noedge_posedge,
+        SetupLow => tsetup_DI_CLK_noedge_posedge,
+        HoldHigh => thold_DI_CLK_noedge_posedge,
+        HoldLow => thold_DI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI_CLK_TimingDatash,
+        Violation => tviol_DI_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    INFF_zd 	:= INFF_out;
+
+    VitalPathDelay01 (
+      OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_INFF,
+                           PathCondition => TRUE)),
+      GlitchData => INFF_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity rd_clkB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity rd_clkB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "rd_clkB";
+
+      tipd_rdclk  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_rdclk_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_rdclk 	: VitalDelayType := 0 ns;
+      tpw_rdclk_posedge	: VitalDelayType := 0 ns;
+      tpw_rdclk_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; rdclk: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF rd_clkB : ENTITY IS TRUE;
+
+  end rd_clkB;
+
+  architecture Structure of rd_clkB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal rdclk_ipd 	: std_logic := 'X';
+
+    component sapiobuf0252
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    rd_clk_pad: sapiobuf0252
+      port map (Z=>PADDI_out, PAD=>rdclk_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(rdclk_ipd, rdclk, tipd_rdclk);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, rdclk_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_rdclk_rdclk          	: x01 := '0';
+    VARIABLE periodcheckinfo_rdclk	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => rdclk_ipd,
+        TestSignalName => "rdclk",
+        Period => tperiod_rdclk,
+        PulseWidthHigh => tpw_rdclk_posedge,
+        PulseWidthLow => tpw_rdclk_negedge,
+        PeriodData => periodcheckinfo_rdclk,
+        Violation => tviol_rdclk_rdclk,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => rdclk_ipd'last_event,
+                           PathDelay => tpd_rdclk_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity PDPW16KDB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity PDPW16KDB is
+    port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+          CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+          OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+          CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+          BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+          BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+          DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+          DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+          DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+          DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+          DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+          DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+          DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+          DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+          DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+          DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+          DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+          DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+          ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+          ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+          ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+          ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+          ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+          ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+          ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+          DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+          DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+          DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+          DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+          DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+          DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+          DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+          DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+          DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+          DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+          DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+          DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PDPW16KDB : ENTITY IS TRUE;
+
+  end PDPW16KDB;
+
+  architecture Structure of PDPW16KDB is
+  begin
+    INST10: PDPW16KD
+      generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", 
+                   CSDECODE_W => "0b001", DATA_WIDTH_R => 36, 
+                   DATA_WIDTH_W => 36, GSR => "DISABLED", 
+                   INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , INIT_DATA => "STATIC", REGMODE => "NOREG", 
+                   RESETMODE => "SYNC")
+      port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, 
+                DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, 
+                DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, 
+                DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, 
+                DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, 
+                DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, 
+                DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, 
+                ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, 
+                ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, 
+                BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, 
+                CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, 
+                ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, 
+                ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, 
+                ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, 
+                CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, 
+                DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, 
+                DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, 
+                DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, 
+                DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, 
+                DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, 
+                DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, 
+                DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35);
+  end Structure;
+
+-- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0"
+        ;
+
+      tipd_DIA15  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_OCEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA17	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA16	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA15	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA14	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA13	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA12	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA11	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA10	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA9	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA8	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA7	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA6	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA5	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB5	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLKA	: VitalDelayType := 0 ns;
+      tisd_DIA15_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEA_CLKA	: VitalDelayType := 0 ns;
+      tsetup_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      ticd_CLKB	: VitalDelayType := 0 ns;
+      tisd_OCEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB5_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB6_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB7_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB8_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB9_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB10_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB11_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB12_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB13_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLKA 	: VitalDelayType := 0 ns;
+      tpw_CLKA_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKA_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLKB 	: VitalDelayType := 0 ns;
+      tpw_CLKB_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKB_negedge	: VitalDelayType := 0 ns);
+
+    port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+          DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+          ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+          ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+          ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+          DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+          DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+          DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+          DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+          DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+          DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+          CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+          CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+          DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+          DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+          ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+          ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+          ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+          DIB9: in Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE;
+
+  end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0;
+
+
+    architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DIA15_ipd 	: std_logic := 'X';
+    signal DIA15_dly 	: std_logic := 'X';
+    signal DIA13_ipd 	: std_logic := 'X';
+    signal DIA13_dly 	: std_logic := 'X';
+    signal DIA12_ipd 	: std_logic := 'X';
+    signal DIA12_dly 	: std_logic := 'X';
+    signal DIA11_ipd 	: std_logic := 'X';
+    signal DIA11_dly 	: std_logic := 'X';
+    signal DIA9_ipd 	: std_logic := 'X';
+    signal DIA9_dly 	: std_logic := 'X';
+    signal ADA13_ipd 	: std_logic := 'X';
+    signal ADA13_dly 	: std_logic := 'X';
+    signal ADA12_ipd 	: std_logic := 'X';
+    signal ADA12_dly 	: std_logic := 'X';
+    signal ADA11_ipd 	: std_logic := 'X';
+    signal ADA11_dly 	: std_logic := 'X';
+    signal ADA10_ipd 	: std_logic := 'X';
+    signal ADA10_dly 	: std_logic := 'X';
+    signal ADA9_ipd 	: std_logic := 'X';
+    signal ADA9_dly 	: std_logic := 'X';
+    signal ADA8_ipd 	: std_logic := 'X';
+    signal ADA8_dly 	: std_logic := 'X';
+    signal ADA7_ipd 	: std_logic := 'X';
+    signal ADA7_dly 	: std_logic := 'X';
+    signal ADA6_ipd 	: std_logic := 'X';
+    signal ADA6_dly 	: std_logic := 'X';
+    signal ADA5_ipd 	: std_logic := 'X';
+    signal ADA5_dly 	: std_logic := 'X';
+    signal DOA17_out 	: std_logic := 'X';
+    signal DOA16_out 	: std_logic := 'X';
+    signal DOA15_out 	: std_logic := 'X';
+    signal DOA14_out 	: std_logic := 'X';
+    signal DOA13_out 	: std_logic := 'X';
+    signal DOA12_out 	: std_logic := 'X';
+    signal DOA11_out 	: std_logic := 'X';
+    signal DOA10_out 	: std_logic := 'X';
+    signal DOA9_out 	: std_logic := 'X';
+    signal DOA8_out 	: std_logic := 'X';
+    signal DOA7_out 	: std_logic := 'X';
+    signal DOA6_out 	: std_logic := 'X';
+    signal DOA5_out 	: std_logic := 'X';
+    signal DOA4_out 	: std_logic := 'X';
+    signal DOA3_out 	: std_logic := 'X';
+    signal DOA2_out 	: std_logic := 'X';
+    signal DOA1_out 	: std_logic := 'X';
+    signal DOA0_out 	: std_logic := 'X';
+    signal CEA_ipd 	: std_logic := 'X';
+    signal CEA_dly 	: std_logic := 'X';
+    signal CLKA_ipd 	: std_logic := 'X';
+    signal CLKA_dly 	: std_logic := 'X';
+    signal CLKB_ipd 	: std_logic := 'X';
+    signal CLKB_dly 	: std_logic := 'X';
+    signal OCEB_ipd 	: std_logic := 'X';
+    signal OCEB_dly 	: std_logic := 'X';
+    signal CEB_ipd 	: std_logic := 'X';
+    signal CEB_dly 	: std_logic := 'X';
+    signal DOB0_out 	: std_logic := 'X';
+    signal DOB1_out 	: std_logic := 'X';
+    signal DOB2_out 	: std_logic := 'X';
+    signal DOB3_out 	: std_logic := 'X';
+    signal DOB4_out 	: std_logic := 'X';
+    signal DOB5_out 	: std_logic := 'X';
+    signal ADB5_ipd 	: std_logic := 'X';
+    signal ADB5_dly 	: std_logic := 'X';
+    signal ADB6_ipd 	: std_logic := 'X';
+    signal ADB6_dly 	: std_logic := 'X';
+    signal ADB7_ipd 	: std_logic := 'X';
+    signal ADB7_dly 	: std_logic := 'X';
+    signal ADB8_ipd 	: std_logic := 'X';
+    signal ADB8_dly 	: std_logic := 'X';
+    signal ADB9_ipd 	: std_logic := 'X';
+    signal ADB9_dly 	: std_logic := 'X';
+    signal ADB10_ipd 	: std_logic := 'X';
+    signal ADB10_dly 	: std_logic := 'X';
+    signal ADB11_ipd 	: std_logic := 'X';
+    signal ADB11_dly 	: std_logic := 'X';
+    signal ADB12_ipd 	: std_logic := 'X';
+    signal ADB12_dly 	: std_logic := 'X';
+    signal ADB13_ipd 	: std_logic := 'X';
+    signal ADB13_dly 	: std_logic := 'X';
+    signal DIB6_ipd 	: std_logic := 'X';
+    signal DIB6_dly 	: std_logic := 'X';
+    signal DIB8_ipd 	: std_logic := 'X';
+    signal DIB8_dly 	: std_logic := 'X';
+    signal DIB9_ipd 	: std_logic := 'X';
+    signal DIB9_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component PDPW16KDB
+      port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+            CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+            OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+            CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+            BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+            BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+            DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+            DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+            DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+            DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+            DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+            DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+            DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+            DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+            DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+            DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+            DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+            DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+            ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+            ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+            ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+            ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+            ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+            ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+            ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+            DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+            DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+            DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+            DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+            DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+            DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+            DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+            DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+            DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+            DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+            DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+            DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KDB
+      port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, 
+                CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, 
+                CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, 
+                BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, 
+                DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, 
+                DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, 
+                DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, 
+                DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, 
+                DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, 
+                DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, 
+                DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, 
+                DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, 
+                ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, 
+                ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, 
+                ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, 
+                ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, 
+                ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, 
+                ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, 
+                ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, 
+                DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, 
+                DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, 
+                DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, 
+                DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, 
+                DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, 
+                DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, 
+                DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, 
+                DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, 
+                DO34=>DOA16_out, DO35=>DOA17_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15);
+      VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13);
+      VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12);
+      VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11);
+      VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9);
+      VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13);
+      VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12);
+      VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11);
+      VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10);
+      VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9);
+      VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8);
+      VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7);
+      VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6);
+      VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5);
+      VitalWireDelay(CEA_ipd, CEA, tipd_CEA);
+      VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA);
+      VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB);
+      VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB);
+      VitalWireDelay(CEB_ipd, CEB, tipd_CEB);
+      VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5);
+      VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6);
+      VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7);
+      VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8);
+      VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9);
+      VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10);
+      VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11);
+      VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12);
+      VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13);
+      VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6);
+      VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8);
+      VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA);
+      VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA);
+      VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA);
+      VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA);
+      VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA);
+      VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA);
+      VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA);
+      VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA);
+      VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA);
+      VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA);
+      VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA);
+      VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA);
+      VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA);
+      VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA);
+      VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA);
+      VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA);
+      VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB);
+      VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB);
+      VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB);
+      VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB);
+      VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB);
+      VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB);
+      VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB);
+      VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB);
+      VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB);
+      VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB);
+      VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB);
+      VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB);
+      VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA);
+      VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA);
+      VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, 
+      DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, 
+      ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, 
+      DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, 
+      DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, 
+      CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, 
+      DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, 
+      ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, 
+      DIB8_dly, DIB9_dly)
+    VARIABLE DOA17_zd         	: std_logic := 'X';
+    VARIABLE DOA17_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA16_zd         	: std_logic := 'X';
+    VARIABLE DOA16_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA15_zd         	: std_logic := 'X';
+    VARIABLE DOA15_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA14_zd         	: std_logic := 'X';
+    VARIABLE DOA14_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA13_zd         	: std_logic := 'X';
+    VARIABLE DOA13_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA12_zd         	: std_logic := 'X';
+    VARIABLE DOA12_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA11_zd         	: std_logic := 'X';
+    VARIABLE DOA11_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA10_zd         	: std_logic := 'X';
+    VARIABLE DOA10_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA9_zd         	: std_logic := 'X';
+    VARIABLE DOA9_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA8_zd         	: std_logic := 'X';
+    VARIABLE DOA8_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA7_zd         	: std_logic := 'X';
+    VARIABLE DOA7_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA6_zd         	: std_logic := 'X';
+    VARIABLE DOA6_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA5_zd         	: std_logic := 'X';
+    VARIABLE DOA5_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA4_zd         	: std_logic := 'X';
+    VARIABLE DOA4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA3_zd         	: std_logic := 'X';
+    VARIABLE DOA3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA2_zd         	: std_logic := 'X';
+    VARIABLE DOA2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA1_zd         	: std_logic := 'X';
+    VARIABLE DOA1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA0_zd         	: std_logic := 'X';
+    VARIABLE DOA0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB0_zd         	: std_logic := 'X';
+    VARIABLE DOB0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB1_zd         	: std_logic := 'X';
+    VARIABLE DOB1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB2_zd         	: std_logic := 'X';
+    VARIABLE DOB2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB3_zd         	: std_logic := 'X';
+    VARIABLE DOB3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB4_zd         	: std_logic := 'X';
+    VARIABLE DOB4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB5_zd         	: std_logic := 'X';
+    VARIABLE DOB5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DIA15_CLKA       	: x01 := '0';
+    VARIABLE DIA15_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA13_CLKA       	: x01 := '0';
+    VARIABLE DIA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA12_CLKA       	: x01 := '0';
+    VARIABLE DIA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA11_CLKA       	: x01 := '0';
+    VARIABLE DIA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA9_CLKA       	: x01 := '0';
+    VARIABLE DIA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA13_CLKA       	: x01 := '0';
+    VARIABLE ADA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA12_CLKA       	: x01 := '0';
+    VARIABLE ADA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA11_CLKA       	: x01 := '0';
+    VARIABLE ADA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA10_CLKA       	: x01 := '0';
+    VARIABLE ADA10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA9_CLKA       	: x01 := '0';
+    VARIABLE ADA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA8_CLKA       	: x01 := '0';
+    VARIABLE ADA8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA7_CLKA       	: x01 := '0';
+    VARIABLE ADA7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA6_CLKA       	: x01 := '0';
+    VARIABLE ADA6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA5_CLKA       	: x01 := '0';
+    VARIABLE ADA5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEA_CLKA       	: x01 := '0';
+    VARIABLE CEA_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_OCEB_CLKB       	: x01 := '0';
+    VARIABLE OCEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEB_CLKB       	: x01 := '0';
+    VARIABLE CEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB5_CLKB       	: x01 := '0';
+    VARIABLE ADB5_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB6_CLKB       	: x01 := '0';
+    VARIABLE ADB6_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB7_CLKB       	: x01 := '0';
+    VARIABLE ADB7_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB8_CLKB       	: x01 := '0';
+    VARIABLE ADB8_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB9_CLKB       	: x01 := '0';
+    VARIABLE ADB9_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB10_CLKB       	: x01 := '0';
+    VARIABLE ADB10_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB11_CLKB       	: x01 := '0';
+    VARIABLE ADB11_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB12_CLKB       	: x01 := '0';
+    VARIABLE ADB12_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB13_CLKB       	: x01 := '0';
+    VARIABLE ADB13_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB6_CLKA       	: x01 := '0';
+    VARIABLE DIB6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB8_CLKA       	: x01 := '0';
+    VARIABLE DIB8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB9_CLKA       	: x01 := '0';
+    VARIABLE DIB9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLKA_CLKA          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKA	: VitalPeriodDataType;
+    VARIABLE tviol_CLKB_CLKB          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKB	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DIA15_dly,
+        TestSignalName => "DIA15",
+        TestDelay => tisd_DIA15_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA15_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA15_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA15_CLKA_noedge_posedge,
+        HoldLow => thold_DIA15_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA15_CLKA_TimingDatash,
+        Violation => tviol_DIA15_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA13_dly,
+        TestSignalName => "DIA13",
+        TestDelay => tisd_DIA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA13_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA13_CLKA_noedge_posedge,
+        HoldLow => thold_DIA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA13_CLKA_TimingDatash,
+        Violation => tviol_DIA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA12_dly,
+        TestSignalName => "DIA12",
+        TestDelay => tisd_DIA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA12_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA12_CLKA_noedge_posedge,
+        HoldLow => thold_DIA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA12_CLKA_TimingDatash,
+        Violation => tviol_DIA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA11_dly,
+        TestSignalName => "DIA11",
+        TestDelay => tisd_DIA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA11_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA11_CLKA_noedge_posedge,
+        HoldLow => thold_DIA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA11_CLKA_TimingDatash,
+        Violation => tviol_DIA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA9_dly,
+        TestSignalName => "DIA9",
+        TestDelay => tisd_DIA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA9_CLKA_noedge_posedge,
+        HoldLow => thold_DIA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA9_CLKA_TimingDatash,
+        Violation => tviol_DIA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA13_dly,
+        TestSignalName => "ADA13",
+        TestDelay => tisd_ADA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA13_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA13_CLKA_noedge_posedge,
+        HoldLow => thold_ADA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA13_CLKA_TimingDatash,
+        Violation => tviol_ADA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA12_dly,
+        TestSignalName => "ADA12",
+        TestDelay => tisd_ADA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA12_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA12_CLKA_noedge_posedge,
+        HoldLow => thold_ADA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA12_CLKA_TimingDatash,
+        Violation => tviol_ADA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA11_dly,
+        TestSignalName => "ADA11",
+        TestDelay => tisd_ADA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA11_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA11_CLKA_noedge_posedge,
+        HoldLow => thold_ADA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA11_CLKA_TimingDatash,
+        Violation => tviol_ADA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA10_dly,
+        TestSignalName => "ADA10",
+        TestDelay => tisd_ADA10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA10_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA10_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA10_CLKA_noedge_posedge,
+        HoldLow => thold_ADA10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA10_CLKA_TimingDatash,
+        Violation => tviol_ADA10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA9_dly,
+        TestSignalName => "ADA9",
+        TestDelay => tisd_ADA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA9_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA9_CLKA_noedge_posedge,
+        HoldLow => thold_ADA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA9_CLKA_TimingDatash,
+        Violation => tviol_ADA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA8_dly,
+        TestSignalName => "ADA8",
+        TestDelay => tisd_ADA8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA8_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA8_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA8_CLKA_noedge_posedge,
+        HoldLow => thold_ADA8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA8_CLKA_TimingDatash,
+        Violation => tviol_ADA8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA7_dly,
+        TestSignalName => "ADA7",
+        TestDelay => tisd_ADA7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA7_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA7_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA7_CLKA_noedge_posedge,
+        HoldLow => thold_ADA7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA7_CLKA_TimingDatash,
+        Violation => tviol_ADA7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA6_dly,
+        TestSignalName => "ADA6",
+        TestDelay => tisd_ADA6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA6_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA6_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA6_CLKA_noedge_posedge,
+        HoldLow => thold_ADA6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA6_CLKA_TimingDatash,
+        Violation => tviol_ADA6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA5_dly,
+        TestSignalName => "ADA5",
+        TestDelay => tisd_ADA5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA5_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA5_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA5_CLKA_noedge_posedge,
+        HoldLow => thold_ADA5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA5_CLKA_TimingDatash,
+        Violation => tviol_ADA5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEA_dly,
+        TestSignalName => "CEA",
+        TestDelay => tisd_CEA_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_CEA_CLKA_noedge_posedge,
+        SetupLow => tsetup_CEA_CLKA_noedge_posedge,
+        HoldHigh => thold_CEA_CLKA_noedge_posedge,
+        HoldLow => thold_CEA_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEA_CLKA_TimingDatash,
+        Violation => tviol_CEA_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => OCEB_dly,
+        TestSignalName => "OCEB",
+        TestDelay => tisd_OCEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_OCEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_OCEB_CLKB_noedge_posedge,
+        HoldHigh => thold_OCEB_CLKB_noedge_posedge,
+        HoldLow => thold_OCEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => OCEB_CLKB_TimingDatash,
+        Violation => tviol_OCEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEB_dly,
+        TestSignalName => "CEB",
+        TestDelay => tisd_CEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_CEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_CEB_CLKB_noedge_posedge,
+        HoldHigh => thold_CEB_CLKB_noedge_posedge,
+        HoldLow => thold_CEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEB_CLKB_TimingDatash,
+        Violation => tviol_CEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB5_dly,
+        TestSignalName => "ADB5",
+        TestDelay => tisd_ADB5_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB5_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB5_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB5_CLKB_noedge_posedge,
+        HoldLow => thold_ADB5_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB5_CLKB_TimingDatash,
+        Violation => tviol_ADB5_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB6_dly,
+        TestSignalName => "ADB6",
+        TestDelay => tisd_ADB6_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB6_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB6_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB6_CLKB_noedge_posedge,
+        HoldLow => thold_ADB6_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB6_CLKB_TimingDatash,
+        Violation => tviol_ADB6_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB7_dly,
+        TestSignalName => "ADB7",
+        TestDelay => tisd_ADB7_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB7_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB7_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB7_CLKB_noedge_posedge,
+        HoldLow => thold_ADB7_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB7_CLKB_TimingDatash,
+        Violation => tviol_ADB7_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB8_dly,
+        TestSignalName => "ADB8",
+        TestDelay => tisd_ADB8_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB8_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB8_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB8_CLKB_noedge_posedge,
+        HoldLow => thold_ADB8_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB8_CLKB_TimingDatash,
+        Violation => tviol_ADB8_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB9_dly,
+        TestSignalName => "ADB9",
+        TestDelay => tisd_ADB9_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB9_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB9_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB9_CLKB_noedge_posedge,
+        HoldLow => thold_ADB9_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB9_CLKB_TimingDatash,
+        Violation => tviol_ADB9_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB10_dly,
+        TestSignalName => "ADB10",
+        TestDelay => tisd_ADB10_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB10_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB10_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB10_CLKB_noedge_posedge,
+        HoldLow => thold_ADB10_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB10_CLKB_TimingDatash,
+        Violation => tviol_ADB10_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB11_dly,
+        TestSignalName => "ADB11",
+        TestDelay => tisd_ADB11_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB11_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB11_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB11_CLKB_noedge_posedge,
+        HoldLow => thold_ADB11_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB11_CLKB_TimingDatash,
+        Violation => tviol_ADB11_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB12_dly,
+        TestSignalName => "ADB12",
+        TestDelay => tisd_ADB12_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB12_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB12_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB12_CLKB_noedge_posedge,
+        HoldLow => thold_ADB12_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB12_CLKB_TimingDatash,
+        Violation => tviol_ADB12_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB13_dly,
+        TestSignalName => "ADB13",
+        TestDelay => tisd_ADB13_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB13_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB13_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB13_CLKB_noedge_posedge,
+        HoldLow => thold_ADB13_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB13_CLKB_TimingDatash,
+        Violation => tviol_ADB13_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB6_dly,
+        TestSignalName => "DIB6",
+        TestDelay => tisd_DIB6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB6_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB6_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB6_CLKA_noedge_posedge,
+        HoldLow => thold_DIB6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB6_CLKA_TimingDatash,
+        Violation => tviol_DIB6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB8_dly,
+        TestSignalName => "DIB8",
+        TestDelay => tisd_DIB8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB8_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB8_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB8_CLKA_noedge_posedge,
+        HoldLow => thold_DIB8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB8_CLKA_TimingDatash,
+        Violation => tviol_DIB8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB9_dly,
+        TestSignalName => "DIB9",
+        TestDelay => tisd_DIB9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB9_CLKA_noedge_posedge,
+        HoldLow => thold_DIB9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB9_CLKA_TimingDatash,
+        Violation => tviol_DIB9_CLKA,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKA_ipd,
+        TestSignalName => "CLKA",
+        Period => tperiod_CLKA,
+        PulseWidthHigh => tpw_CLKA_posedge,
+        PulseWidthLow => tpw_CLKA_negedge,
+        PeriodData => periodcheckinfo_CLKA,
+        Violation => tviol_CLKA_CLKA,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKB_ipd,
+        TestSignalName => "CLKB",
+        Period => tperiod_CLKB,
+        PulseWidthHigh => tpw_CLKB_posedge,
+        PulseWidthLow => tpw_CLKB_negedge,
+        PeriodData => periodcheckinfo_CLKB,
+        Violation => tviol_CLKB_CLKB,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    DOA17_zd 	:= DOA17_out;
+    DOA16_zd 	:= DOA16_out;
+    DOA15_zd 	:= DOA15_out;
+    DOA14_zd 	:= DOA14_out;
+    DOA13_zd 	:= DOA13_out;
+    DOA12_zd 	:= DOA12_out;
+    DOA11_zd 	:= DOA11_out;
+    DOA10_zd 	:= DOA10_out;
+    DOA9_zd 	:= DOA9_out;
+    DOA8_zd 	:= DOA8_out;
+    DOA7_zd 	:= DOA7_out;
+    DOA6_zd 	:= DOA6_out;
+    DOA5_zd 	:= DOA5_out;
+    DOA4_zd 	:= DOA4_out;
+    DOA3_zd 	:= DOA3_out;
+    DOA2_zd 	:= DOA2_out;
+    DOA1_zd 	:= DOA1_out;
+    DOA0_zd 	:= DOA0_out;
+    DOB0_zd 	:= DOB0_out;
+    DOB1_zd 	:= DOB1_out;
+    DOB2_zd 	:= DOB2_out;
+    DOB3_zd 	:= DOB3_out;
+    DOB4_zd 	:= DOB4_out;
+    DOB5_zd 	:= DOB5_out;
+
+    VitalPathDelay01 (
+      OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA17,
+                           PathCondition => TRUE)),
+      GlitchData => DOA17_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA16,
+                           PathCondition => TRUE)),
+      GlitchData => DOA16_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA15,
+                           PathCondition => TRUE)),
+      GlitchData => DOA15_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA14,
+                           PathCondition => TRUE)),
+      GlitchData => DOA14_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA13,
+                           PathCondition => TRUE)),
+      GlitchData => DOA13_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA12,
+                           PathCondition => TRUE)),
+      GlitchData => DOA12_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA11,
+                           PathCondition => TRUE)),
+      GlitchData => DOA11_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA10,
+                           PathCondition => TRUE)),
+      GlitchData => DOA10_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA9,
+                           PathCondition => TRUE)),
+      GlitchData => DOA9_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA8,
+                           PathCondition => TRUE)),
+      GlitchData => DOA8_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA7,
+                           PathCondition => TRUE)),
+      GlitchData => DOA7_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA6,
+                           PathCondition => TRUE)),
+      GlitchData => DOA6_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA5,
+                           PathCondition => TRUE)),
+      GlitchData => DOA5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA4,
+                           PathCondition => TRUE)),
+      GlitchData => DOA4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA3,
+                           PathCondition => TRUE)),
+      GlitchData => DOA3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA2,
+                           PathCondition => TRUE)),
+      GlitchData => DOA2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA1,
+                           PathCondition => TRUE)),
+      GlitchData => DOA1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA0,
+                           PathCondition => TRUE)),
+      GlitchData => DOA0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB0,
+                           PathCondition => TRUE)),
+      GlitchData => DOB0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB1,
+                           PathCondition => TRUE)),
+      GlitchData => DOB1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB2,
+                           PathCondition => TRUE)),
+      GlitchData => DOB2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB3,
+                           PathCondition => TRUE)),
+      GlitchData => DOB3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB4,
+                           PathCondition => TRUE)),
+      GlitchData => DOB4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB5,
+                           PathCondition => TRUE)),
+      GlitchData => DOB5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity PDPW16KD0253
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity PDPW16KD0253 is
+    port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+          CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+          OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+          CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+          BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+          BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+          DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+          DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+          DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+          DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+          DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+          DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+          DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+          DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+          DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+          DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+          DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+          DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+          ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+          ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+          ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+          ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+          ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+          ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+          ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+          DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+          DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+          DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+          DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+          DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+          DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+          DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+          DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+          DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+          DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+          DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+          DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PDPW16KD0253 : ENTITY IS TRUE;
+
+  end PDPW16KD0253;
+
+  architecture Structure of PDPW16KD0253 is
+  begin
+    INST10: PDPW16KD
+      generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", 
+                   CSDECODE_W => "0b001", DATA_WIDTH_R => 36, 
+                   DATA_WIDTH_W => 36, GSR => "DISABLED", 
+                   INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , INIT_DATA => "STATIC", REGMODE => "NOREG", 
+                   RESETMODE => "SYNC")
+      port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, 
+                DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, 
+                DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, 
+                DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, 
+                DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, 
+                DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, 
+                DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, 
+                ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, 
+                ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, 
+                BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, 
+                CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, 
+                ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, 
+                ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, 
+                ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, 
+                CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, 
+                DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, 
+                DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, 
+                DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, 
+                DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, 
+                DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, 
+                DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, 
+                DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35);
+  end Structure;
+
+-- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0"
+        ;
+
+      tipd_DIA15  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_OCEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA17	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA16	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA15	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA14	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA13	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA12	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA11	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA10	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA9	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA8	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA7	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA6	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA5	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB5	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLKA	: VitalDelayType := 0 ns;
+      tisd_DIA15_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEA_CLKA	: VitalDelayType := 0 ns;
+      tsetup_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      ticd_CLKB	: VitalDelayType := 0 ns;
+      tisd_OCEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB5_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB6_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB7_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB8_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB9_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB10_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB11_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB12_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB13_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLKA 	: VitalDelayType := 0 ns;
+      tpw_CLKA_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKA_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLKB 	: VitalDelayType := 0 ns;
+      tpw_CLKB_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKB_negedge	: VitalDelayType := 0 ns);
+
+    port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+          DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+          ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+          ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+          ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+          DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+          DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+          DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+          DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+          DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+          DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+          CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+          CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+          DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+          DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+          ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+          ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+          ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+          DIB9: in Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE;
+
+  end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0;
+
+
+    architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DIA15_ipd 	: std_logic := 'X';
+    signal DIA15_dly 	: std_logic := 'X';
+    signal DIA13_ipd 	: std_logic := 'X';
+    signal DIA13_dly 	: std_logic := 'X';
+    signal DIA12_ipd 	: std_logic := 'X';
+    signal DIA12_dly 	: std_logic := 'X';
+    signal DIA11_ipd 	: std_logic := 'X';
+    signal DIA11_dly 	: std_logic := 'X';
+    signal DIA9_ipd 	: std_logic := 'X';
+    signal DIA9_dly 	: std_logic := 'X';
+    signal ADA13_ipd 	: std_logic := 'X';
+    signal ADA13_dly 	: std_logic := 'X';
+    signal ADA12_ipd 	: std_logic := 'X';
+    signal ADA12_dly 	: std_logic := 'X';
+    signal ADA11_ipd 	: std_logic := 'X';
+    signal ADA11_dly 	: std_logic := 'X';
+    signal ADA10_ipd 	: std_logic := 'X';
+    signal ADA10_dly 	: std_logic := 'X';
+    signal ADA9_ipd 	: std_logic := 'X';
+    signal ADA9_dly 	: std_logic := 'X';
+    signal ADA8_ipd 	: std_logic := 'X';
+    signal ADA8_dly 	: std_logic := 'X';
+    signal ADA7_ipd 	: std_logic := 'X';
+    signal ADA7_dly 	: std_logic := 'X';
+    signal ADA6_ipd 	: std_logic := 'X';
+    signal ADA6_dly 	: std_logic := 'X';
+    signal ADA5_ipd 	: std_logic := 'X';
+    signal ADA5_dly 	: std_logic := 'X';
+    signal DOA17_out 	: std_logic := 'X';
+    signal DOA16_out 	: std_logic := 'X';
+    signal DOA15_out 	: std_logic := 'X';
+    signal DOA14_out 	: std_logic := 'X';
+    signal DOA13_out 	: std_logic := 'X';
+    signal DOA12_out 	: std_logic := 'X';
+    signal DOA11_out 	: std_logic := 'X';
+    signal DOA10_out 	: std_logic := 'X';
+    signal DOA9_out 	: std_logic := 'X';
+    signal DOA8_out 	: std_logic := 'X';
+    signal DOA7_out 	: std_logic := 'X';
+    signal DOA6_out 	: std_logic := 'X';
+    signal DOA5_out 	: std_logic := 'X';
+    signal DOA4_out 	: std_logic := 'X';
+    signal DOA3_out 	: std_logic := 'X';
+    signal DOA2_out 	: std_logic := 'X';
+    signal DOA1_out 	: std_logic := 'X';
+    signal DOA0_out 	: std_logic := 'X';
+    signal CEA_ipd 	: std_logic := 'X';
+    signal CEA_dly 	: std_logic := 'X';
+    signal CLKA_ipd 	: std_logic := 'X';
+    signal CLKA_dly 	: std_logic := 'X';
+    signal CLKB_ipd 	: std_logic := 'X';
+    signal CLKB_dly 	: std_logic := 'X';
+    signal OCEB_ipd 	: std_logic := 'X';
+    signal OCEB_dly 	: std_logic := 'X';
+    signal CEB_ipd 	: std_logic := 'X';
+    signal CEB_dly 	: std_logic := 'X';
+    signal DOB0_out 	: std_logic := 'X';
+    signal DOB1_out 	: std_logic := 'X';
+    signal DOB2_out 	: std_logic := 'X';
+    signal DOB3_out 	: std_logic := 'X';
+    signal DOB4_out 	: std_logic := 'X';
+    signal DOB5_out 	: std_logic := 'X';
+    signal ADB5_ipd 	: std_logic := 'X';
+    signal ADB5_dly 	: std_logic := 'X';
+    signal ADB6_ipd 	: std_logic := 'X';
+    signal ADB6_dly 	: std_logic := 'X';
+    signal ADB7_ipd 	: std_logic := 'X';
+    signal ADB7_dly 	: std_logic := 'X';
+    signal ADB8_ipd 	: std_logic := 'X';
+    signal ADB8_dly 	: std_logic := 'X';
+    signal ADB9_ipd 	: std_logic := 'X';
+    signal ADB9_dly 	: std_logic := 'X';
+    signal ADB10_ipd 	: std_logic := 'X';
+    signal ADB10_dly 	: std_logic := 'X';
+    signal ADB11_ipd 	: std_logic := 'X';
+    signal ADB11_dly 	: std_logic := 'X';
+    signal ADB12_ipd 	: std_logic := 'X';
+    signal ADB12_dly 	: std_logic := 'X';
+    signal ADB13_ipd 	: std_logic := 'X';
+    signal ADB13_dly 	: std_logic := 'X';
+    signal DIB6_ipd 	: std_logic := 'X';
+    signal DIB6_dly 	: std_logic := 'X';
+    signal DIB8_ipd 	: std_logic := 'X';
+    signal DIB8_dly 	: std_logic := 'X';
+    signal DIB9_ipd 	: std_logic := 'X';
+    signal DIB9_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component PDPW16KD0253
+      port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+            CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+            OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+            CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+            BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+            BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+            DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+            DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+            DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+            DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+            DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+            DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+            DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+            DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+            DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+            DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+            DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+            DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+            ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+            ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+            ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+            ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+            ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+            ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+            ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+            DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+            DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+            DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+            DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+            DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+            DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+            DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+            DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+            DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+            DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+            DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+            DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+    end component;
+  begin
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KD0253
+      port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, 
+                CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, 
+                CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, 
+                BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, 
+                DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, 
+                DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, 
+                DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, 
+                DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, 
+                DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, 
+                DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, 
+                DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, 
+                DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, 
+                ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, 
+                ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, 
+                ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, 
+                ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, 
+                ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, 
+                ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, 
+                ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, 
+                DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, 
+                DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, 
+                DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, 
+                DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, 
+                DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, 
+                DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, 
+                DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, 
+                DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, 
+                DO34=>DOA16_out, DO35=>DOA17_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15);
+      VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13);
+      VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12);
+      VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11);
+      VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9);
+      VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13);
+      VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12);
+      VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11);
+      VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10);
+      VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9);
+      VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8);
+      VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7);
+      VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6);
+      VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5);
+      VitalWireDelay(CEA_ipd, CEA, tipd_CEA);
+      VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA);
+      VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB);
+      VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB);
+      VitalWireDelay(CEB_ipd, CEB, tipd_CEB);
+      VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5);
+      VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6);
+      VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7);
+      VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8);
+      VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9);
+      VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10);
+      VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11);
+      VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12);
+      VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13);
+      VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6);
+      VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8);
+      VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA);
+      VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA);
+      VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA);
+      VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA);
+      VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA);
+      VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA);
+      VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA);
+      VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA);
+      VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA);
+      VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA);
+      VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA);
+      VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA);
+      VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA);
+      VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA);
+      VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA);
+      VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA);
+      VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB);
+      VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB);
+      VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB);
+      VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB);
+      VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB);
+      VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB);
+      VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB);
+      VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB);
+      VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB);
+      VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB);
+      VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB);
+      VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB);
+      VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA);
+      VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA);
+      VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, 
+      DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, 
+      ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, 
+      DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, 
+      DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, 
+      CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, 
+      DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, 
+      ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, 
+      DIB8_dly, DIB9_dly)
+    VARIABLE DOA17_zd         	: std_logic := 'X';
+    VARIABLE DOA17_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA16_zd         	: std_logic := 'X';
+    VARIABLE DOA16_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA15_zd         	: std_logic := 'X';
+    VARIABLE DOA15_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA14_zd         	: std_logic := 'X';
+    VARIABLE DOA14_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA13_zd         	: std_logic := 'X';
+    VARIABLE DOA13_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA12_zd         	: std_logic := 'X';
+    VARIABLE DOA12_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA11_zd         	: std_logic := 'X';
+    VARIABLE DOA11_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA10_zd         	: std_logic := 'X';
+    VARIABLE DOA10_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA9_zd         	: std_logic := 'X';
+    VARIABLE DOA9_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA8_zd         	: std_logic := 'X';
+    VARIABLE DOA8_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA7_zd         	: std_logic := 'X';
+    VARIABLE DOA7_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA6_zd         	: std_logic := 'X';
+    VARIABLE DOA6_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA5_zd         	: std_logic := 'X';
+    VARIABLE DOA5_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA4_zd         	: std_logic := 'X';
+    VARIABLE DOA4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA3_zd         	: std_logic := 'X';
+    VARIABLE DOA3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA2_zd         	: std_logic := 'X';
+    VARIABLE DOA2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA1_zd         	: std_logic := 'X';
+    VARIABLE DOA1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA0_zd         	: std_logic := 'X';
+    VARIABLE DOA0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB0_zd         	: std_logic := 'X';
+    VARIABLE DOB0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB1_zd         	: std_logic := 'X';
+    VARIABLE DOB1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB2_zd         	: std_logic := 'X';
+    VARIABLE DOB2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB3_zd         	: std_logic := 'X';
+    VARIABLE DOB3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB4_zd         	: std_logic := 'X';
+    VARIABLE DOB4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB5_zd         	: std_logic := 'X';
+    VARIABLE DOB5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DIA15_CLKA       	: x01 := '0';
+    VARIABLE DIA15_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA13_CLKA       	: x01 := '0';
+    VARIABLE DIA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA12_CLKA       	: x01 := '0';
+    VARIABLE DIA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA11_CLKA       	: x01 := '0';
+    VARIABLE DIA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA9_CLKA       	: x01 := '0';
+    VARIABLE DIA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA13_CLKA       	: x01 := '0';
+    VARIABLE ADA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA12_CLKA       	: x01 := '0';
+    VARIABLE ADA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA11_CLKA       	: x01 := '0';
+    VARIABLE ADA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA10_CLKA       	: x01 := '0';
+    VARIABLE ADA10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA9_CLKA       	: x01 := '0';
+    VARIABLE ADA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA8_CLKA       	: x01 := '0';
+    VARIABLE ADA8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA7_CLKA       	: x01 := '0';
+    VARIABLE ADA7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA6_CLKA       	: x01 := '0';
+    VARIABLE ADA6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA5_CLKA       	: x01 := '0';
+    VARIABLE ADA5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEA_CLKA       	: x01 := '0';
+    VARIABLE CEA_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_OCEB_CLKB       	: x01 := '0';
+    VARIABLE OCEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEB_CLKB       	: x01 := '0';
+    VARIABLE CEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB5_CLKB       	: x01 := '0';
+    VARIABLE ADB5_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB6_CLKB       	: x01 := '0';
+    VARIABLE ADB6_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB7_CLKB       	: x01 := '0';
+    VARIABLE ADB7_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB8_CLKB       	: x01 := '0';
+    VARIABLE ADB8_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB9_CLKB       	: x01 := '0';
+    VARIABLE ADB9_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB10_CLKB       	: x01 := '0';
+    VARIABLE ADB10_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB11_CLKB       	: x01 := '0';
+    VARIABLE ADB11_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB12_CLKB       	: x01 := '0';
+    VARIABLE ADB12_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB13_CLKB       	: x01 := '0';
+    VARIABLE ADB13_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB6_CLKA       	: x01 := '0';
+    VARIABLE DIB6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB8_CLKA       	: x01 := '0';
+    VARIABLE DIB8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB9_CLKA       	: x01 := '0';
+    VARIABLE DIB9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLKA_CLKA          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKA	: VitalPeriodDataType;
+    VARIABLE tviol_CLKB_CLKB          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKB	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DIA15_dly,
+        TestSignalName => "DIA15",
+        TestDelay => tisd_DIA15_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA15_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA15_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA15_CLKA_noedge_posedge,
+        HoldLow => thold_DIA15_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA15_CLKA_TimingDatash,
+        Violation => tviol_DIA15_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA13_dly,
+        TestSignalName => "DIA13",
+        TestDelay => tisd_DIA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA13_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA13_CLKA_noedge_posedge,
+        HoldLow => thold_DIA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA13_CLKA_TimingDatash,
+        Violation => tviol_DIA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA12_dly,
+        TestSignalName => "DIA12",
+        TestDelay => tisd_DIA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA12_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA12_CLKA_noedge_posedge,
+        HoldLow => thold_DIA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA12_CLKA_TimingDatash,
+        Violation => tviol_DIA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA11_dly,
+        TestSignalName => "DIA11",
+        TestDelay => tisd_DIA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA11_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA11_CLKA_noedge_posedge,
+        HoldLow => thold_DIA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA11_CLKA_TimingDatash,
+        Violation => tviol_DIA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA9_dly,
+        TestSignalName => "DIA9",
+        TestDelay => tisd_DIA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA9_CLKA_noedge_posedge,
+        HoldLow => thold_DIA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA9_CLKA_TimingDatash,
+        Violation => tviol_DIA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA13_dly,
+        TestSignalName => "ADA13",
+        TestDelay => tisd_ADA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA13_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA13_CLKA_noedge_posedge,
+        HoldLow => thold_ADA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA13_CLKA_TimingDatash,
+        Violation => tviol_ADA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA12_dly,
+        TestSignalName => "ADA12",
+        TestDelay => tisd_ADA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA12_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA12_CLKA_noedge_posedge,
+        HoldLow => thold_ADA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA12_CLKA_TimingDatash,
+        Violation => tviol_ADA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA11_dly,
+        TestSignalName => "ADA11",
+        TestDelay => tisd_ADA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA11_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA11_CLKA_noedge_posedge,
+        HoldLow => thold_ADA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA11_CLKA_TimingDatash,
+        Violation => tviol_ADA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA10_dly,
+        TestSignalName => "ADA10",
+        TestDelay => tisd_ADA10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA10_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA10_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA10_CLKA_noedge_posedge,
+        HoldLow => thold_ADA10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA10_CLKA_TimingDatash,
+        Violation => tviol_ADA10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA9_dly,
+        TestSignalName => "ADA9",
+        TestDelay => tisd_ADA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA9_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA9_CLKA_noedge_posedge,
+        HoldLow => thold_ADA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA9_CLKA_TimingDatash,
+        Violation => tviol_ADA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA8_dly,
+        TestSignalName => "ADA8",
+        TestDelay => tisd_ADA8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA8_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA8_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA8_CLKA_noedge_posedge,
+        HoldLow => thold_ADA8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA8_CLKA_TimingDatash,
+        Violation => tviol_ADA8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA7_dly,
+        TestSignalName => "ADA7",
+        TestDelay => tisd_ADA7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA7_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA7_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA7_CLKA_noedge_posedge,
+        HoldLow => thold_ADA7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA7_CLKA_TimingDatash,
+        Violation => tviol_ADA7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA6_dly,
+        TestSignalName => "ADA6",
+        TestDelay => tisd_ADA6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA6_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA6_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA6_CLKA_noedge_posedge,
+        HoldLow => thold_ADA6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA6_CLKA_TimingDatash,
+        Violation => tviol_ADA6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA5_dly,
+        TestSignalName => "ADA5",
+        TestDelay => tisd_ADA5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA5_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA5_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA5_CLKA_noedge_posedge,
+        HoldLow => thold_ADA5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA5_CLKA_TimingDatash,
+        Violation => tviol_ADA5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEA_dly,
+        TestSignalName => "CEA",
+        TestDelay => tisd_CEA_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_CEA_CLKA_noedge_posedge,
+        SetupLow => tsetup_CEA_CLKA_noedge_posedge,
+        HoldHigh => thold_CEA_CLKA_noedge_posedge,
+        HoldLow => thold_CEA_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEA_CLKA_TimingDatash,
+        Violation => tviol_CEA_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => OCEB_dly,
+        TestSignalName => "OCEB",
+        TestDelay => tisd_OCEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_OCEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_OCEB_CLKB_noedge_posedge,
+        HoldHigh => thold_OCEB_CLKB_noedge_posedge,
+        HoldLow => thold_OCEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => OCEB_CLKB_TimingDatash,
+        Violation => tviol_OCEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEB_dly,
+        TestSignalName => "CEB",
+        TestDelay => tisd_CEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_CEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_CEB_CLKB_noedge_posedge,
+        HoldHigh => thold_CEB_CLKB_noedge_posedge,
+        HoldLow => thold_CEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEB_CLKB_TimingDatash,
+        Violation => tviol_CEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB5_dly,
+        TestSignalName => "ADB5",
+        TestDelay => tisd_ADB5_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB5_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB5_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB5_CLKB_noedge_posedge,
+        HoldLow => thold_ADB5_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB5_CLKB_TimingDatash,
+        Violation => tviol_ADB5_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB6_dly,
+        TestSignalName => "ADB6",
+        TestDelay => tisd_ADB6_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB6_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB6_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB6_CLKB_noedge_posedge,
+        HoldLow => thold_ADB6_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB6_CLKB_TimingDatash,
+        Violation => tviol_ADB6_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB7_dly,
+        TestSignalName => "ADB7",
+        TestDelay => tisd_ADB7_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB7_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB7_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB7_CLKB_noedge_posedge,
+        HoldLow => thold_ADB7_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB7_CLKB_TimingDatash,
+        Violation => tviol_ADB7_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB8_dly,
+        TestSignalName => "ADB8",
+        TestDelay => tisd_ADB8_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB8_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB8_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB8_CLKB_noedge_posedge,
+        HoldLow => thold_ADB8_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB8_CLKB_TimingDatash,
+        Violation => tviol_ADB8_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB9_dly,
+        TestSignalName => "ADB9",
+        TestDelay => tisd_ADB9_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB9_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB9_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB9_CLKB_noedge_posedge,
+        HoldLow => thold_ADB9_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB9_CLKB_TimingDatash,
+        Violation => tviol_ADB9_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB10_dly,
+        TestSignalName => "ADB10",
+        TestDelay => tisd_ADB10_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB10_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB10_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB10_CLKB_noedge_posedge,
+        HoldLow => thold_ADB10_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB10_CLKB_TimingDatash,
+        Violation => tviol_ADB10_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB11_dly,
+        TestSignalName => "ADB11",
+        TestDelay => tisd_ADB11_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB11_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB11_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB11_CLKB_noedge_posedge,
+        HoldLow => thold_ADB11_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB11_CLKB_TimingDatash,
+        Violation => tviol_ADB11_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB12_dly,
+        TestSignalName => "ADB12",
+        TestDelay => tisd_ADB12_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB12_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB12_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB12_CLKB_noedge_posedge,
+        HoldLow => thold_ADB12_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB12_CLKB_TimingDatash,
+        Violation => tviol_ADB12_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB13_dly,
+        TestSignalName => "ADB13",
+        TestDelay => tisd_ADB13_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB13_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB13_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB13_CLKB_noedge_posedge,
+        HoldLow => thold_ADB13_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB13_CLKB_TimingDatash,
+        Violation => tviol_ADB13_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB6_dly,
+        TestSignalName => "DIB6",
+        TestDelay => tisd_DIB6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB6_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB6_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB6_CLKA_noedge_posedge,
+        HoldLow => thold_DIB6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB6_CLKA_TimingDatash,
+        Violation => tviol_DIB6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB8_dly,
+        TestSignalName => "DIB8",
+        TestDelay => tisd_DIB8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB8_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB8_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB8_CLKA_noedge_posedge,
+        HoldLow => thold_DIB8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB8_CLKA_TimingDatash,
+        Violation => tviol_DIB8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB9_dly,
+        TestSignalName => "DIB9",
+        TestDelay => tisd_DIB9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB9_CLKA_noedge_posedge,
+        HoldLow => thold_DIB9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB9_CLKA_TimingDatash,
+        Violation => tviol_DIB9_CLKA,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKA_ipd,
+        TestSignalName => "CLKA",
+        Period => tperiod_CLKA,
+        PulseWidthHigh => tpw_CLKA_posedge,
+        PulseWidthLow => tpw_CLKA_negedge,
+        PeriodData => periodcheckinfo_CLKA,
+        Violation => tviol_CLKA_CLKA,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKB_ipd,
+        TestSignalName => "CLKB",
+        Period => tperiod_CLKB,
+        PulseWidthHigh => tpw_CLKB_posedge,
+        PulseWidthLow => tpw_CLKB_negedge,
+        PeriodData => periodcheckinfo_CLKB,
+        Violation => tviol_CLKB_CLKB,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    DOA17_zd 	:= DOA17_out;
+    DOA16_zd 	:= DOA16_out;
+    DOA15_zd 	:= DOA15_out;
+    DOA14_zd 	:= DOA14_out;
+    DOA13_zd 	:= DOA13_out;
+    DOA12_zd 	:= DOA12_out;
+    DOA11_zd 	:= DOA11_out;
+    DOA10_zd 	:= DOA10_out;
+    DOA9_zd 	:= DOA9_out;
+    DOA8_zd 	:= DOA8_out;
+    DOA7_zd 	:= DOA7_out;
+    DOA6_zd 	:= DOA6_out;
+    DOA5_zd 	:= DOA5_out;
+    DOA4_zd 	:= DOA4_out;
+    DOA3_zd 	:= DOA3_out;
+    DOA2_zd 	:= DOA2_out;
+    DOA1_zd 	:= DOA1_out;
+    DOA0_zd 	:= DOA0_out;
+    DOB0_zd 	:= DOB0_out;
+    DOB1_zd 	:= DOB1_out;
+    DOB2_zd 	:= DOB2_out;
+    DOB3_zd 	:= DOB3_out;
+    DOB4_zd 	:= DOB4_out;
+    DOB5_zd 	:= DOB5_out;
+
+    VitalPathDelay01 (
+      OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA17,
+                           PathCondition => TRUE)),
+      GlitchData => DOA17_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA16,
+                           PathCondition => TRUE)),
+      GlitchData => DOA16_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA15,
+                           PathCondition => TRUE)),
+      GlitchData => DOA15_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA14,
+                           PathCondition => TRUE)),
+      GlitchData => DOA14_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA13,
+                           PathCondition => TRUE)),
+      GlitchData => DOA13_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA12,
+                           PathCondition => TRUE)),
+      GlitchData => DOA12_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA11,
+                           PathCondition => TRUE)),
+      GlitchData => DOA11_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA10,
+                           PathCondition => TRUE)),
+      GlitchData => DOA10_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA9,
+                           PathCondition => TRUE)),
+      GlitchData => DOA9_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA8,
+                           PathCondition => TRUE)),
+      GlitchData => DOA8_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA7,
+                           PathCondition => TRUE)),
+      GlitchData => DOA7_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA6,
+                           PathCondition => TRUE)),
+      GlitchData => DOA6_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA5,
+                           PathCondition => TRUE)),
+      GlitchData => DOA5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA4,
+                           PathCondition => TRUE)),
+      GlitchData => DOA4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA3,
+                           PathCondition => TRUE)),
+      GlitchData => DOA3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA2,
+                           PathCondition => TRUE)),
+      GlitchData => DOA2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA1,
+                           PathCondition => TRUE)),
+      GlitchData => DOA1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA0,
+                           PathCondition => TRUE)),
+      GlitchData => DOA0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB0,
+                           PathCondition => TRUE)),
+      GlitchData => DOB0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB1,
+                           PathCondition => TRUE)),
+      GlitchData => DOB1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB2,
+                           PathCondition => TRUE)),
+      GlitchData => DOB2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB3,
+                           PathCondition => TRUE)),
+      GlitchData => DOB3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB4,
+                           PathCondition => TRUE)),
+      GlitchData => DOB4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB5,
+                           PathCondition => TRUE)),
+      GlitchData => DOB5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity PDPW16KD0254
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity PDPW16KD0254 is
+    port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+          CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+          OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+          CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+          BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+          BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+          DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+          DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+          DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+          DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+          DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+          DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+          DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+          DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+          DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+          DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+          DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+          DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+          ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+          ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+          ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+          ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+          ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+          ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+          ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+          DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+          DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+          DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+          DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+          DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+          DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+          DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+          DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+          DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+          DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+          DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+          DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PDPW16KD0254 : ENTITY IS TRUE;
+
+  end PDPW16KD0254;
+
+  architecture Structure of PDPW16KD0254 is
+  begin
+    INST10: PDPW16KD
+      generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", 
+                   CSDECODE_W => "0b001", DATA_WIDTH_R => 36, 
+                   DATA_WIDTH_W => 36, GSR => "DISABLED", 
+                   INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , INIT_DATA => "STATIC", REGMODE => "NOREG", 
+                   RESETMODE => "SYNC")
+      port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, 
+                DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, 
+                DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, 
+                DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, 
+                DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, 
+                DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, 
+                DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, 
+                ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, 
+                ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, 
+                BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, 
+                CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, 
+                ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, 
+                ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, 
+                ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, 
+                CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, 
+                DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, 
+                DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, 
+                DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, 
+                DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, 
+                DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, 
+                DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, 
+                DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35);
+  end Structure;
+
+-- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+
+        InstancePath  	: string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0"
+        ;
+
+      tipd_DIA15  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_OCEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA17	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA16	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA15	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA14	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA13	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA12	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA11	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA10	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA9	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA8	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA7	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA6	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA5	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB5	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLKA	: VitalDelayType := 0 ns;
+      tisd_DIA15_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEA_CLKA	: VitalDelayType := 0 ns;
+      tsetup_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      ticd_CLKB	: VitalDelayType := 0 ns;
+      tisd_OCEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB5_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB6_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB7_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB8_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB9_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB10_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB11_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB12_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB13_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLKA 	: VitalDelayType := 0 ns;
+      tpw_CLKA_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKA_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLKB 	: VitalDelayType := 0 ns;
+      tpw_CLKB_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKB_negedge	: VitalDelayType := 0 ns);
+
+    port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+          DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+          ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+          ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+          ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+          DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+          DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+          DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+          DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+          DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+          DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+          CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+          CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+          DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+          DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+          ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+          ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+          ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+          DIB9: in Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE;
+
+  end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0;
+
+
+    architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DIA15_ipd 	: std_logic := 'X';
+    signal DIA15_dly 	: std_logic := 'X';
+    signal DIA13_ipd 	: std_logic := 'X';
+    signal DIA13_dly 	: std_logic := 'X';
+    signal DIA12_ipd 	: std_logic := 'X';
+    signal DIA12_dly 	: std_logic := 'X';
+    signal DIA11_ipd 	: std_logic := 'X';
+    signal DIA11_dly 	: std_logic := 'X';
+    signal DIA9_ipd 	: std_logic := 'X';
+    signal DIA9_dly 	: std_logic := 'X';
+    signal ADA13_ipd 	: std_logic := 'X';
+    signal ADA13_dly 	: std_logic := 'X';
+    signal ADA12_ipd 	: std_logic := 'X';
+    signal ADA12_dly 	: std_logic := 'X';
+    signal ADA11_ipd 	: std_logic := 'X';
+    signal ADA11_dly 	: std_logic := 'X';
+    signal ADA10_ipd 	: std_logic := 'X';
+    signal ADA10_dly 	: std_logic := 'X';
+    signal ADA9_ipd 	: std_logic := 'X';
+    signal ADA9_dly 	: std_logic := 'X';
+    signal ADA8_ipd 	: std_logic := 'X';
+    signal ADA8_dly 	: std_logic := 'X';
+    signal ADA7_ipd 	: std_logic := 'X';
+    signal ADA7_dly 	: std_logic := 'X';
+    signal ADA6_ipd 	: std_logic := 'X';
+    signal ADA6_dly 	: std_logic := 'X';
+    signal ADA5_ipd 	: std_logic := 'X';
+    signal ADA5_dly 	: std_logic := 'X';
+    signal DOA17_out 	: std_logic := 'X';
+    signal DOA16_out 	: std_logic := 'X';
+    signal DOA15_out 	: std_logic := 'X';
+    signal DOA14_out 	: std_logic := 'X';
+    signal DOA13_out 	: std_logic := 'X';
+    signal DOA12_out 	: std_logic := 'X';
+    signal DOA11_out 	: std_logic := 'X';
+    signal DOA10_out 	: std_logic := 'X';
+    signal DOA9_out 	: std_logic := 'X';
+    signal DOA8_out 	: std_logic := 'X';
+    signal DOA7_out 	: std_logic := 'X';
+    signal DOA6_out 	: std_logic := 'X';
+    signal DOA5_out 	: std_logic := 'X';
+    signal DOA4_out 	: std_logic := 'X';
+    signal DOA3_out 	: std_logic := 'X';
+    signal DOA2_out 	: std_logic := 'X';
+    signal DOA1_out 	: std_logic := 'X';
+    signal DOA0_out 	: std_logic := 'X';
+    signal CEA_ipd 	: std_logic := 'X';
+    signal CEA_dly 	: std_logic := 'X';
+    signal CLKA_ipd 	: std_logic := 'X';
+    signal CLKA_dly 	: std_logic := 'X';
+    signal CLKB_ipd 	: std_logic := 'X';
+    signal CLKB_dly 	: std_logic := 'X';
+    signal OCEB_ipd 	: std_logic := 'X';
+    signal OCEB_dly 	: std_logic := 'X';
+    signal CEB_ipd 	: std_logic := 'X';
+    signal CEB_dly 	: std_logic := 'X';
+    signal DOB0_out 	: std_logic := 'X';
+    signal DOB1_out 	: std_logic := 'X';
+    signal DOB2_out 	: std_logic := 'X';
+    signal DOB3_out 	: std_logic := 'X';
+    signal DOB4_out 	: std_logic := 'X';
+    signal DOB5_out 	: std_logic := 'X';
+    signal ADB5_ipd 	: std_logic := 'X';
+    signal ADB5_dly 	: std_logic := 'X';
+    signal ADB6_ipd 	: std_logic := 'X';
+    signal ADB6_dly 	: std_logic := 'X';
+    signal ADB7_ipd 	: std_logic := 'X';
+    signal ADB7_dly 	: std_logic := 'X';
+    signal ADB8_ipd 	: std_logic := 'X';
+    signal ADB8_dly 	: std_logic := 'X';
+    signal ADB9_ipd 	: std_logic := 'X';
+    signal ADB9_dly 	: std_logic := 'X';
+    signal ADB10_ipd 	: std_logic := 'X';
+    signal ADB10_dly 	: std_logic := 'X';
+    signal ADB11_ipd 	: std_logic := 'X';
+    signal ADB11_dly 	: std_logic := 'X';
+    signal ADB12_ipd 	: std_logic := 'X';
+    signal ADB12_dly 	: std_logic := 'X';
+    signal ADB13_ipd 	: std_logic := 'X';
+    signal ADB13_dly 	: std_logic := 'X';
+    signal DIB6_ipd 	: std_logic := 'X';
+    signal DIB6_dly 	: std_logic := 'X';
+    signal DIB8_ipd 	: std_logic := 'X';
+    signal DIB8_dly 	: std_logic := 'X';
+    signal DIB9_ipd 	: std_logic := 'X';
+    signal DIB9_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component PDPW16KD0254
+      port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+            CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+            OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+            CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+            BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+            BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+            DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+            DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+            DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+            DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+            DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+            DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+            DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+            DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+            DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+            DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+            DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+            DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+            ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+            ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+            ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+            ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+            ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+            ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+            ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+            DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+            DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+            DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+            DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+            DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+            DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+            DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+            DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+            DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+            DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+            DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+            DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+    end component;
+  begin
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KD0254
+      port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, 
+                CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, 
+                CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, 
+                BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, 
+                DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, 
+                DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, 
+                DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, 
+                DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, 
+                DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, 
+                DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, 
+                DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, 
+                DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, 
+                ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, 
+                ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, 
+                ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, 
+                ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, 
+                ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, 
+                ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, 
+                ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, 
+                DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, 
+                DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, 
+                DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, 
+                DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, 
+                DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, 
+                DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, 
+                DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, 
+                DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, 
+                DO34=>DOA16_out, DO35=>DOA17_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15);
+      VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13);
+      VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12);
+      VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11);
+      VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9);
+      VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13);
+      VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12);
+      VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11);
+      VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10);
+      VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9);
+      VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8);
+      VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7);
+      VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6);
+      VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5);
+      VitalWireDelay(CEA_ipd, CEA, tipd_CEA);
+      VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA);
+      VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB);
+      VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB);
+      VitalWireDelay(CEB_ipd, CEB, tipd_CEB);
+      VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5);
+      VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6);
+      VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7);
+      VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8);
+      VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9);
+      VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10);
+      VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11);
+      VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12);
+      VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13);
+      VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6);
+      VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8);
+      VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA);
+      VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA);
+      VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA);
+      VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA);
+      VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA);
+      VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA);
+      VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA);
+      VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA);
+      VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA);
+      VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA);
+      VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA);
+      VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA);
+      VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA);
+      VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA);
+      VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA);
+      VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA);
+      VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB);
+      VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB);
+      VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB);
+      VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB);
+      VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB);
+      VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB);
+      VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB);
+      VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB);
+      VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB);
+      VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB);
+      VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB);
+      VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB);
+      VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA);
+      VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA);
+      VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, 
+      DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, 
+      ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, 
+      DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, 
+      DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, 
+      CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, 
+      DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, 
+      ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, 
+      DIB8_dly, DIB9_dly)
+    VARIABLE DOA17_zd         	: std_logic := 'X';
+    VARIABLE DOA17_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA16_zd         	: std_logic := 'X';
+    VARIABLE DOA16_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA15_zd         	: std_logic := 'X';
+    VARIABLE DOA15_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA14_zd         	: std_logic := 'X';
+    VARIABLE DOA14_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA13_zd         	: std_logic := 'X';
+    VARIABLE DOA13_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA12_zd         	: std_logic := 'X';
+    VARIABLE DOA12_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA11_zd         	: std_logic := 'X';
+    VARIABLE DOA11_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA10_zd         	: std_logic := 'X';
+    VARIABLE DOA10_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA9_zd         	: std_logic := 'X';
+    VARIABLE DOA9_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA8_zd         	: std_logic := 'X';
+    VARIABLE DOA8_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA7_zd         	: std_logic := 'X';
+    VARIABLE DOA7_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA6_zd         	: std_logic := 'X';
+    VARIABLE DOA6_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA5_zd         	: std_logic := 'X';
+    VARIABLE DOA5_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA4_zd         	: std_logic := 'X';
+    VARIABLE DOA4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA3_zd         	: std_logic := 'X';
+    VARIABLE DOA3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA2_zd         	: std_logic := 'X';
+    VARIABLE DOA2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA1_zd         	: std_logic := 'X';
+    VARIABLE DOA1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA0_zd         	: std_logic := 'X';
+    VARIABLE DOA0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB0_zd         	: std_logic := 'X';
+    VARIABLE DOB0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB1_zd         	: std_logic := 'X';
+    VARIABLE DOB1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB2_zd         	: std_logic := 'X';
+    VARIABLE DOB2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB3_zd         	: std_logic := 'X';
+    VARIABLE DOB3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB4_zd         	: std_logic := 'X';
+    VARIABLE DOB4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB5_zd         	: std_logic := 'X';
+    VARIABLE DOB5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DIA15_CLKA       	: x01 := '0';
+    VARIABLE DIA15_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA13_CLKA       	: x01 := '0';
+    VARIABLE DIA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA12_CLKA       	: x01 := '0';
+    VARIABLE DIA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA11_CLKA       	: x01 := '0';
+    VARIABLE DIA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA9_CLKA       	: x01 := '0';
+    VARIABLE DIA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA13_CLKA       	: x01 := '0';
+    VARIABLE ADA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA12_CLKA       	: x01 := '0';
+    VARIABLE ADA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA11_CLKA       	: x01 := '0';
+    VARIABLE ADA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA10_CLKA       	: x01 := '0';
+    VARIABLE ADA10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA9_CLKA       	: x01 := '0';
+    VARIABLE ADA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA8_CLKA       	: x01 := '0';
+    VARIABLE ADA8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA7_CLKA       	: x01 := '0';
+    VARIABLE ADA7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA6_CLKA       	: x01 := '0';
+    VARIABLE ADA6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA5_CLKA       	: x01 := '0';
+    VARIABLE ADA5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEA_CLKA       	: x01 := '0';
+    VARIABLE CEA_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_OCEB_CLKB       	: x01 := '0';
+    VARIABLE OCEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEB_CLKB       	: x01 := '0';
+    VARIABLE CEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB5_CLKB       	: x01 := '0';
+    VARIABLE ADB5_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB6_CLKB       	: x01 := '0';
+    VARIABLE ADB6_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB7_CLKB       	: x01 := '0';
+    VARIABLE ADB7_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB8_CLKB       	: x01 := '0';
+    VARIABLE ADB8_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB9_CLKB       	: x01 := '0';
+    VARIABLE ADB9_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB10_CLKB       	: x01 := '0';
+    VARIABLE ADB10_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB11_CLKB       	: x01 := '0';
+    VARIABLE ADB11_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB12_CLKB       	: x01 := '0';
+    VARIABLE ADB12_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB13_CLKB       	: x01 := '0';
+    VARIABLE ADB13_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB6_CLKA       	: x01 := '0';
+    VARIABLE DIB6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB8_CLKA       	: x01 := '0';
+    VARIABLE DIB8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB9_CLKA       	: x01 := '0';
+    VARIABLE DIB9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLKA_CLKA          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKA	: VitalPeriodDataType;
+    VARIABLE tviol_CLKB_CLKB          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKB	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DIA15_dly,
+        TestSignalName => "DIA15",
+        TestDelay => tisd_DIA15_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA15_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA15_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA15_CLKA_noedge_posedge,
+        HoldLow => thold_DIA15_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA15_CLKA_TimingDatash,
+        Violation => tviol_DIA15_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA13_dly,
+        TestSignalName => "DIA13",
+        TestDelay => tisd_DIA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA13_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA13_CLKA_noedge_posedge,
+        HoldLow => thold_DIA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA13_CLKA_TimingDatash,
+        Violation => tviol_DIA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA12_dly,
+        TestSignalName => "DIA12",
+        TestDelay => tisd_DIA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA12_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA12_CLKA_noedge_posedge,
+        HoldLow => thold_DIA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA12_CLKA_TimingDatash,
+        Violation => tviol_DIA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA11_dly,
+        TestSignalName => "DIA11",
+        TestDelay => tisd_DIA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA11_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA11_CLKA_noedge_posedge,
+        HoldLow => thold_DIA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA11_CLKA_TimingDatash,
+        Violation => tviol_DIA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA9_dly,
+        TestSignalName => "DIA9",
+        TestDelay => tisd_DIA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA9_CLKA_noedge_posedge,
+        HoldLow => thold_DIA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA9_CLKA_TimingDatash,
+        Violation => tviol_DIA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA13_dly,
+        TestSignalName => "ADA13",
+        TestDelay => tisd_ADA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA13_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA13_CLKA_noedge_posedge,
+        HoldLow => thold_ADA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA13_CLKA_TimingDatash,
+        Violation => tviol_ADA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA12_dly,
+        TestSignalName => "ADA12",
+        TestDelay => tisd_ADA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA12_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA12_CLKA_noedge_posedge,
+        HoldLow => thold_ADA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA12_CLKA_TimingDatash,
+        Violation => tviol_ADA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA11_dly,
+        TestSignalName => "ADA11",
+        TestDelay => tisd_ADA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA11_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA11_CLKA_noedge_posedge,
+        HoldLow => thold_ADA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA11_CLKA_TimingDatash,
+        Violation => tviol_ADA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA10_dly,
+        TestSignalName => "ADA10",
+        TestDelay => tisd_ADA10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA10_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA10_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA10_CLKA_noedge_posedge,
+        HoldLow => thold_ADA10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA10_CLKA_TimingDatash,
+        Violation => tviol_ADA10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA9_dly,
+        TestSignalName => "ADA9",
+        TestDelay => tisd_ADA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA9_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA9_CLKA_noedge_posedge,
+        HoldLow => thold_ADA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA9_CLKA_TimingDatash,
+        Violation => tviol_ADA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA8_dly,
+        TestSignalName => "ADA8",
+        TestDelay => tisd_ADA8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA8_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA8_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA8_CLKA_noedge_posedge,
+        HoldLow => thold_ADA8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA8_CLKA_TimingDatash,
+        Violation => tviol_ADA8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA7_dly,
+        TestSignalName => "ADA7",
+        TestDelay => tisd_ADA7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA7_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA7_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA7_CLKA_noedge_posedge,
+        HoldLow => thold_ADA7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA7_CLKA_TimingDatash,
+        Violation => tviol_ADA7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA6_dly,
+        TestSignalName => "ADA6",
+        TestDelay => tisd_ADA6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA6_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA6_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA6_CLKA_noedge_posedge,
+        HoldLow => thold_ADA6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA6_CLKA_TimingDatash,
+        Violation => tviol_ADA6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA5_dly,
+        TestSignalName => "ADA5",
+        TestDelay => tisd_ADA5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA5_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA5_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA5_CLKA_noedge_posedge,
+        HoldLow => thold_ADA5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA5_CLKA_TimingDatash,
+        Violation => tviol_ADA5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEA_dly,
+        TestSignalName => "CEA",
+        TestDelay => tisd_CEA_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_CEA_CLKA_noedge_posedge,
+        SetupLow => tsetup_CEA_CLKA_noedge_posedge,
+        HoldHigh => thold_CEA_CLKA_noedge_posedge,
+        HoldLow => thold_CEA_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEA_CLKA_TimingDatash,
+        Violation => tviol_CEA_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => OCEB_dly,
+        TestSignalName => "OCEB",
+        TestDelay => tisd_OCEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_OCEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_OCEB_CLKB_noedge_posedge,
+        HoldHigh => thold_OCEB_CLKB_noedge_posedge,
+        HoldLow => thold_OCEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => OCEB_CLKB_TimingDatash,
+        Violation => tviol_OCEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEB_dly,
+        TestSignalName => "CEB",
+        TestDelay => tisd_CEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_CEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_CEB_CLKB_noedge_posedge,
+        HoldHigh => thold_CEB_CLKB_noedge_posedge,
+        HoldLow => thold_CEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEB_CLKB_TimingDatash,
+        Violation => tviol_CEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB5_dly,
+        TestSignalName => "ADB5",
+        TestDelay => tisd_ADB5_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB5_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB5_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB5_CLKB_noedge_posedge,
+        HoldLow => thold_ADB5_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB5_CLKB_TimingDatash,
+        Violation => tviol_ADB5_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB6_dly,
+        TestSignalName => "ADB6",
+        TestDelay => tisd_ADB6_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB6_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB6_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB6_CLKB_noedge_posedge,
+        HoldLow => thold_ADB6_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB6_CLKB_TimingDatash,
+        Violation => tviol_ADB6_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB7_dly,
+        TestSignalName => "ADB7",
+        TestDelay => tisd_ADB7_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB7_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB7_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB7_CLKB_noedge_posedge,
+        HoldLow => thold_ADB7_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB7_CLKB_TimingDatash,
+        Violation => tviol_ADB7_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB8_dly,
+        TestSignalName => "ADB8",
+        TestDelay => tisd_ADB8_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB8_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB8_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB8_CLKB_noedge_posedge,
+        HoldLow => thold_ADB8_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB8_CLKB_TimingDatash,
+        Violation => tviol_ADB8_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB9_dly,
+        TestSignalName => "ADB9",
+        TestDelay => tisd_ADB9_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB9_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB9_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB9_CLKB_noedge_posedge,
+        HoldLow => thold_ADB9_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB9_CLKB_TimingDatash,
+        Violation => tviol_ADB9_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB10_dly,
+        TestSignalName => "ADB10",
+        TestDelay => tisd_ADB10_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB10_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB10_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB10_CLKB_noedge_posedge,
+        HoldLow => thold_ADB10_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB10_CLKB_TimingDatash,
+        Violation => tviol_ADB10_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB11_dly,
+        TestSignalName => "ADB11",
+        TestDelay => tisd_ADB11_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB11_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB11_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB11_CLKB_noedge_posedge,
+        HoldLow => thold_ADB11_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB11_CLKB_TimingDatash,
+        Violation => tviol_ADB11_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB12_dly,
+        TestSignalName => "ADB12",
+        TestDelay => tisd_ADB12_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB12_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB12_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB12_CLKB_noedge_posedge,
+        HoldLow => thold_ADB12_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB12_CLKB_TimingDatash,
+        Violation => tviol_ADB12_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB13_dly,
+        TestSignalName => "ADB13",
+        TestDelay => tisd_ADB13_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB13_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB13_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB13_CLKB_noedge_posedge,
+        HoldLow => thold_ADB13_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB13_CLKB_TimingDatash,
+        Violation => tviol_ADB13_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB6_dly,
+        TestSignalName => "DIB6",
+        TestDelay => tisd_DIB6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB6_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB6_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB6_CLKA_noedge_posedge,
+        HoldLow => thold_DIB6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB6_CLKA_TimingDatash,
+        Violation => tviol_DIB6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB8_dly,
+        TestSignalName => "DIB8",
+        TestDelay => tisd_DIB8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB8_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB8_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB8_CLKA_noedge_posedge,
+        HoldLow => thold_DIB8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB8_CLKA_TimingDatash,
+        Violation => tviol_DIB8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB9_dly,
+        TestSignalName => "DIB9",
+        TestDelay => tisd_DIB9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB9_CLKA_noedge_posedge,
+        HoldLow => thold_DIB9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB9_CLKA_TimingDatash,
+        Violation => tviol_DIB9_CLKA,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKA_ipd,
+        TestSignalName => "CLKA",
+        Period => tperiod_CLKA,
+        PulseWidthHigh => tpw_CLKA_posedge,
+        PulseWidthLow => tpw_CLKA_negedge,
+        PeriodData => periodcheckinfo_CLKA,
+        Violation => tviol_CLKA_CLKA,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKB_ipd,
+        TestSignalName => "CLKB",
+        Period => tperiod_CLKB,
+        PulseWidthHigh => tpw_CLKB_posedge,
+        PulseWidthLow => tpw_CLKB_negedge,
+        PeriodData => periodcheckinfo_CLKB,
+        Violation => tviol_CLKB_CLKB,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    DOA17_zd 	:= DOA17_out;
+    DOA16_zd 	:= DOA16_out;
+    DOA15_zd 	:= DOA15_out;
+    DOA14_zd 	:= DOA14_out;
+    DOA13_zd 	:= DOA13_out;
+    DOA12_zd 	:= DOA12_out;
+    DOA11_zd 	:= DOA11_out;
+    DOA10_zd 	:= DOA10_out;
+    DOA9_zd 	:= DOA9_out;
+    DOA8_zd 	:= DOA8_out;
+    DOA7_zd 	:= DOA7_out;
+    DOA6_zd 	:= DOA6_out;
+    DOA5_zd 	:= DOA5_out;
+    DOA4_zd 	:= DOA4_out;
+    DOA3_zd 	:= DOA3_out;
+    DOA2_zd 	:= DOA2_out;
+    DOA1_zd 	:= DOA1_out;
+    DOA0_zd 	:= DOA0_out;
+    DOB0_zd 	:= DOB0_out;
+    DOB1_zd 	:= DOB1_out;
+    DOB2_zd 	:= DOB2_out;
+    DOB3_zd 	:= DOB3_out;
+    DOB4_zd 	:= DOB4_out;
+    DOB5_zd 	:= DOB5_out;
+
+    VitalPathDelay01 (
+      OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA17,
+                           PathCondition => TRUE)),
+      GlitchData => DOA17_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA16,
+                           PathCondition => TRUE)),
+      GlitchData => DOA16_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA15,
+                           PathCondition => TRUE)),
+      GlitchData => DOA15_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA14,
+                           PathCondition => TRUE)),
+      GlitchData => DOA14_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA13,
+                           PathCondition => TRUE)),
+      GlitchData => DOA13_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA12,
+                           PathCondition => TRUE)),
+      GlitchData => DOA12_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA11,
+                           PathCondition => TRUE)),
+      GlitchData => DOA11_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA10,
+                           PathCondition => TRUE)),
+      GlitchData => DOA10_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA9,
+                           PathCondition => TRUE)),
+      GlitchData => DOA9_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA8,
+                           PathCondition => TRUE)),
+      GlitchData => DOA8_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA7,
+                           PathCondition => TRUE)),
+      GlitchData => DOA7_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA6,
+                           PathCondition => TRUE)),
+      GlitchData => DOA6_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA5,
+                           PathCondition => TRUE)),
+      GlitchData => DOA5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA4,
+                           PathCondition => TRUE)),
+      GlitchData => DOA4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA3,
+                           PathCondition => TRUE)),
+      GlitchData => DOA3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA2,
+                           PathCondition => TRUE)),
+      GlitchData => DOA2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA1,
+                           PathCondition => TRUE)),
+      GlitchData => DOA1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA0,
+                           PathCondition => TRUE)),
+      GlitchData => DOA0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB0,
+                           PathCondition => TRUE)),
+      GlitchData => DOB0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB1,
+                           PathCondition => TRUE)),
+      GlitchData => DOB1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB2,
+                           PathCondition => TRUE)),
+      GlitchData => DOB2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB3,
+                           PathCondition => TRUE)),
+      GlitchData => DOB3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB4,
+                           PathCondition => TRUE)),
+      GlitchData => DOB4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB5,
+                           PathCondition => TRUE)),
+      GlitchData => DOB5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity PDPW16KD0255
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity PDPW16KD0255 is
+    port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+          CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+          OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+          CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+          BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+          BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+          DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+          DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+          DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+          DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+          DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+          DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+          DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+          DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+          DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+          DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+          DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+          DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+          ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+          ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+          ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+          ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+          ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+          ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+          ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+          DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+          DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+          DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+          DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+          DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+          DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+          DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+          DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+          DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+          DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+          DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+          DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PDPW16KD0255 : ENTITY IS TRUE;
+
+  end PDPW16KD0255;
+
+  architecture Structure of PDPW16KD0255 is
+  begin
+    INST10: PDPW16KD
+      generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", 
+                   CSDECODE_W => "0b001", DATA_WIDTH_R => 36, 
+                   DATA_WIDTH_W => 36, GSR => "DISABLED", 
+                   INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , 
+                   INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+                   , INIT_DATA => "STATIC", REGMODE => "NOREG", 
+                   RESETMODE => "ASYNC")
+      port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, 
+                DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, 
+                DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, 
+                DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, 
+                DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, 
+                DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, 
+                DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, 
+                ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, 
+                ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, 
+                BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, 
+                CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, 
+                ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, 
+                ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, 
+                ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, 
+                CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, 
+                DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, 
+                DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, 
+                DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, 
+                DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, 
+                DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, 
+                DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, 
+                DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35);
+  end Structure;
+
+-- entity fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1";
+
+      tipd_DIA17  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA16  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA15  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA14  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIA0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADA5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKA  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_OCEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CEB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_ADB13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB10  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB11  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB12  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB13  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB14  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DIB15  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA17	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA16	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA15	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA14	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA13	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA12	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA11	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA10	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA9	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA8	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA7	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA6	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA5	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOA0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB4	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB5	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB6	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB7	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB8	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB9	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB10	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB11	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB12	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKB_DOB13	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLKA	: VitalDelayType := 0 ns;
+      tisd_DIA17_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA17_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA17_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA16_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA16_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA16_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA15_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA14_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA14_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA14_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA4_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA4_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA4_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA3_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA3_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA3_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA2_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA2_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA2_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA1_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA1_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA1_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIA0_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIA0_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIA0_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADA5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADA5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEA_CLKA	: VitalDelayType := 0 ns;
+      tsetup_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEA_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      ticd_CLKB	: VitalDelayType := 0 ns;
+      tisd_OCEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_OCEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CEB_CLKB	: VitalDelayType := 0 ns;
+      tsetup_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CEB_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB5_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB5_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB6_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB6_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB7_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB7_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB8_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB8_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB9_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB9_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB10_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB10_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB11_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB11_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB12_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB12_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_ADB13_CLKB	: VitalDelayType := 0 ns;
+      tsetup_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_ADB13_CLKB_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB0_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB0_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB0_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB1_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB1_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB1_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB2_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB2_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB2_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB3_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB3_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB3_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB4_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB4_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB4_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB5_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB5_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB6_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB6_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB7_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB7_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB8_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB8_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB9_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB9_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB10_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB10_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB11_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB11_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB12_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB12_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB13_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB13_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB14_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB14_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB14_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DIB15_CLKA	: VitalDelayType := 0 ns;
+      tsetup_DIB15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DIB15_CLKA_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLKA 	: VitalDelayType := 0 ns;
+      tpw_CLKA_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKA_negedge	: VitalDelayType := 0 ns;
+      tperiod_CLKB 	: VitalDelayType := 0 ns;
+      tpw_CLKB_posedge	: VitalDelayType := 0 ns;
+      tpw_CLKB_negedge	: VitalDelayType := 0 ns);
+
+    port (DIA17: in Std_logic; DIA16: in Std_logic; DIA15: in Std_logic; 
+          DIA14: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+          DIA11: in Std_logic; DIA10: in Std_logic; DIA9: in Std_logic; 
+          DIA8: in Std_logic; DIA7: in Std_logic; DIA6: in Std_logic; 
+          DIA5: in Std_logic; DIA4: in Std_logic; DIA3: in Std_logic; 
+          DIA2: in Std_logic; DIA1: in Std_logic; DIA0: in Std_logic; 
+          ADA13: in Std_logic; ADA12: in Std_logic; ADA11: in Std_logic; 
+          ADA10: in Std_logic; ADA9: in Std_logic; ADA8: in Std_logic; 
+          ADA7: in Std_logic; ADA6: in Std_logic; ADA5: in Std_logic; 
+          DOA17: out Std_logic; DOA16: out Std_logic; DOA15: out Std_logic; 
+          DOA14: out Std_logic; DOA13: out Std_logic; DOA12: out Std_logic; 
+          DOA11: out Std_logic; DOA10: out Std_logic; DOA9: out Std_logic; 
+          DOA8: out Std_logic; DOA7: out Std_logic; DOA6: out Std_logic; 
+          DOA5: out Std_logic; DOA4: out Std_logic; DOA3: out Std_logic; 
+          DOA2: out Std_logic; DOA1: out Std_logic; DOA0: out Std_logic; 
+          CEA: in Std_logic; CLKA: in Std_logic; CLKB: in Std_logic; 
+          OCEB: in Std_logic; CEB: in Std_logic; DOB0: out Std_logic; 
+          DOB1: out Std_logic; DOB2: out Std_logic; DOB3: out Std_logic; 
+          DOB4: out Std_logic; DOB5: out Std_logic; DOB6: out Std_logic; 
+          DOB7: out Std_logic; DOB8: out Std_logic; DOB9: out Std_logic; 
+          DOB10: out Std_logic; DOB11: out Std_logic; DOB12: out Std_logic; 
+          DOB13: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+          ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+          ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+          ADB13: in Std_logic; DIB0: in Std_logic; DIB1: in Std_logic; 
+          DIB2: in Std_logic; DIB3: in Std_logic; DIB4: in Std_logic; 
+          DIB5: in Std_logic; DIB6: in Std_logic; DIB7: in Std_logic; 
+          DIB8: in Std_logic; DIB9: in Std_logic; DIB10: in Std_logic; 
+          DIB11: in Std_logic; DIB12: in Std_logic; DIB13: in Std_logic; 
+          DIB14: in Std_logic; DIB15: in Std_logic);
+
+
+          ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 : ENTITY IS TRUE;
+
+  end fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1;
+
+  architecture Structure of fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal DIA17_ipd 	: std_logic := 'X';
+    signal DIA17_dly 	: std_logic := 'X';
+    signal DIA16_ipd 	: std_logic := 'X';
+    signal DIA16_dly 	: std_logic := 'X';
+    signal DIA15_ipd 	: std_logic := 'X';
+    signal DIA15_dly 	: std_logic := 'X';
+    signal DIA14_ipd 	: std_logic := 'X';
+    signal DIA14_dly 	: std_logic := 'X';
+    signal DIA13_ipd 	: std_logic := 'X';
+    signal DIA13_dly 	: std_logic := 'X';
+    signal DIA12_ipd 	: std_logic := 'X';
+    signal DIA12_dly 	: std_logic := 'X';
+    signal DIA11_ipd 	: std_logic := 'X';
+    signal DIA11_dly 	: std_logic := 'X';
+    signal DIA10_ipd 	: std_logic := 'X';
+    signal DIA10_dly 	: std_logic := 'X';
+    signal DIA9_ipd 	: std_logic := 'X';
+    signal DIA9_dly 	: std_logic := 'X';
+    signal DIA8_ipd 	: std_logic := 'X';
+    signal DIA8_dly 	: std_logic := 'X';
+    signal DIA7_ipd 	: std_logic := 'X';
+    signal DIA7_dly 	: std_logic := 'X';
+    signal DIA6_ipd 	: std_logic := 'X';
+    signal DIA6_dly 	: std_logic := 'X';
+    signal DIA5_ipd 	: std_logic := 'X';
+    signal DIA5_dly 	: std_logic := 'X';
+    signal DIA4_ipd 	: std_logic := 'X';
+    signal DIA4_dly 	: std_logic := 'X';
+    signal DIA3_ipd 	: std_logic := 'X';
+    signal DIA3_dly 	: std_logic := 'X';
+    signal DIA2_ipd 	: std_logic := 'X';
+    signal DIA2_dly 	: std_logic := 'X';
+    signal DIA1_ipd 	: std_logic := 'X';
+    signal DIA1_dly 	: std_logic := 'X';
+    signal DIA0_ipd 	: std_logic := 'X';
+    signal DIA0_dly 	: std_logic := 'X';
+    signal ADA13_ipd 	: std_logic := 'X';
+    signal ADA13_dly 	: std_logic := 'X';
+    signal ADA12_ipd 	: std_logic := 'X';
+    signal ADA12_dly 	: std_logic := 'X';
+    signal ADA11_ipd 	: std_logic := 'X';
+    signal ADA11_dly 	: std_logic := 'X';
+    signal ADA10_ipd 	: std_logic := 'X';
+    signal ADA10_dly 	: std_logic := 'X';
+    signal ADA9_ipd 	: std_logic := 'X';
+    signal ADA9_dly 	: std_logic := 'X';
+    signal ADA8_ipd 	: std_logic := 'X';
+    signal ADA8_dly 	: std_logic := 'X';
+    signal ADA7_ipd 	: std_logic := 'X';
+    signal ADA7_dly 	: std_logic := 'X';
+    signal ADA6_ipd 	: std_logic := 'X';
+    signal ADA6_dly 	: std_logic := 'X';
+    signal ADA5_ipd 	: std_logic := 'X';
+    signal ADA5_dly 	: std_logic := 'X';
+    signal DOA17_out 	: std_logic := 'X';
+    signal DOA16_out 	: std_logic := 'X';
+    signal DOA15_out 	: std_logic := 'X';
+    signal DOA14_out 	: std_logic := 'X';
+    signal DOA13_out 	: std_logic := 'X';
+    signal DOA12_out 	: std_logic := 'X';
+    signal DOA11_out 	: std_logic := 'X';
+    signal DOA10_out 	: std_logic := 'X';
+    signal DOA9_out 	: std_logic := 'X';
+    signal DOA8_out 	: std_logic := 'X';
+    signal DOA7_out 	: std_logic := 'X';
+    signal DOA6_out 	: std_logic := 'X';
+    signal DOA5_out 	: std_logic := 'X';
+    signal DOA4_out 	: std_logic := 'X';
+    signal DOA3_out 	: std_logic := 'X';
+    signal DOA2_out 	: std_logic := 'X';
+    signal DOA1_out 	: std_logic := 'X';
+    signal DOA0_out 	: std_logic := 'X';
+    signal CEA_ipd 	: std_logic := 'X';
+    signal CEA_dly 	: std_logic := 'X';
+    signal CLKA_ipd 	: std_logic := 'X';
+    signal CLKA_dly 	: std_logic := 'X';
+    signal CLKB_ipd 	: std_logic := 'X';
+    signal CLKB_dly 	: std_logic := 'X';
+    signal OCEB_ipd 	: std_logic := 'X';
+    signal OCEB_dly 	: std_logic := 'X';
+    signal CEB_ipd 	: std_logic := 'X';
+    signal CEB_dly 	: std_logic := 'X';
+    signal DOB0_out 	: std_logic := 'X';
+    signal DOB1_out 	: std_logic := 'X';
+    signal DOB2_out 	: std_logic := 'X';
+    signal DOB3_out 	: std_logic := 'X';
+    signal DOB4_out 	: std_logic := 'X';
+    signal DOB5_out 	: std_logic := 'X';
+    signal DOB6_out 	: std_logic := 'X';
+    signal DOB7_out 	: std_logic := 'X';
+    signal DOB8_out 	: std_logic := 'X';
+    signal DOB9_out 	: std_logic := 'X';
+    signal DOB10_out 	: std_logic := 'X';
+    signal DOB11_out 	: std_logic := 'X';
+    signal DOB12_out 	: std_logic := 'X';
+    signal DOB13_out 	: std_logic := 'X';
+    signal ADB5_ipd 	: std_logic := 'X';
+    signal ADB5_dly 	: std_logic := 'X';
+    signal ADB6_ipd 	: std_logic := 'X';
+    signal ADB6_dly 	: std_logic := 'X';
+    signal ADB7_ipd 	: std_logic := 'X';
+    signal ADB7_dly 	: std_logic := 'X';
+    signal ADB8_ipd 	: std_logic := 'X';
+    signal ADB8_dly 	: std_logic := 'X';
+    signal ADB9_ipd 	: std_logic := 'X';
+    signal ADB9_dly 	: std_logic := 'X';
+    signal ADB10_ipd 	: std_logic := 'X';
+    signal ADB10_dly 	: std_logic := 'X';
+    signal ADB11_ipd 	: std_logic := 'X';
+    signal ADB11_dly 	: std_logic := 'X';
+    signal ADB12_ipd 	: std_logic := 'X';
+    signal ADB12_dly 	: std_logic := 'X';
+    signal ADB13_ipd 	: std_logic := 'X';
+    signal ADB13_dly 	: std_logic := 'X';
+    signal DIB0_ipd 	: std_logic := 'X';
+    signal DIB0_dly 	: std_logic := 'X';
+    signal DIB1_ipd 	: std_logic := 'X';
+    signal DIB1_dly 	: std_logic := 'X';
+    signal DIB2_ipd 	: std_logic := 'X';
+    signal DIB2_dly 	: std_logic := 'X';
+    signal DIB3_ipd 	: std_logic := 'X';
+    signal DIB3_dly 	: std_logic := 'X';
+    signal DIB4_ipd 	: std_logic := 'X';
+    signal DIB4_dly 	: std_logic := 'X';
+    signal DIB5_ipd 	: std_logic := 'X';
+    signal DIB5_dly 	: std_logic := 'X';
+    signal DIB6_ipd 	: std_logic := 'X';
+    signal DIB6_dly 	: std_logic := 'X';
+    signal DIB7_ipd 	: std_logic := 'X';
+    signal DIB7_dly 	: std_logic := 'X';
+    signal DIB8_ipd 	: std_logic := 'X';
+    signal DIB8_dly 	: std_logic := 'X';
+    signal DIB9_ipd 	: std_logic := 'X';
+    signal DIB9_dly 	: std_logic := 'X';
+    signal DIB10_ipd 	: std_logic := 'X';
+    signal DIB10_dly 	: std_logic := 'X';
+    signal DIB11_ipd 	: std_logic := 'X';
+    signal DIB11_dly 	: std_logic := 'X';
+    signal DIB12_ipd 	: std_logic := 'X';
+    signal DIB12_dly 	: std_logic := 'X';
+    signal DIB13_ipd 	: std_logic := 'X';
+    signal DIB13_dly 	: std_logic := 'X';
+    signal DIB14_ipd 	: std_logic := 'X';
+    signal DIB14_dly 	: std_logic := 'X';
+    signal DIB15_ipd 	: std_logic := 'X';
+    signal DIB15_dly 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component PDPW16KD0255
+      port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; 
+            CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; 
+            OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; 
+            CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; 
+            BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; 
+            BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; 
+            DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; 
+            DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; 
+            DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; 
+            DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; 
+            DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; 
+            DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; 
+            DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; 
+            DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; 
+            DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; 
+            DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; 
+            DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; 
+            DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; 
+            ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; 
+            ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; 
+            ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; 
+            ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; 
+            ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; 
+            ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; 
+            ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; 
+            DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; 
+            DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; 
+            DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; 
+            DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; 
+            DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; 
+            DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; 
+            DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; 
+            DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; 
+            DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; 
+            DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; 
+            DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; 
+            DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic);
+    end component;
+  begin
+    fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1_PDPW16KD: PDPW16KD0255
+      port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, 
+                CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, 
+                CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, 
+                BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>DIA0_dly, DI1=>DIA1_dly, 
+                DI2=>DIA2_dly, DI3=>DIA3_dly, DI4=>DIA4_dly, DI5=>DIA5_dly, 
+                DI6=>DIA6_dly, DI7=>DIA7_dly, DI8=>DIA8_dly, DI9=>DIA9_dly, 
+                DI10=>DIA10_dly, DI11=>DIA11_dly, DI12=>DIA12_dly, 
+                DI13=>DIA13_dly, DI14=>DIA14_dly, DI15=>DIA15_dly, 
+                DI16=>DIA16_dly, DI17=>DIA17_dly, DI18=>DIB0_dly, 
+                DI19=>DIB1_dly, DI20=>DIB2_dly, DI21=>DIB3_dly, DI22=>DIB4_dly, 
+                DI23=>DIB5_dly, DI24=>DIB6_dly, DI25=>DIB7_dly, DI26=>DIB8_dly, 
+                DI27=>DIB9_dly, DI28=>DIB10_dly, DI29=>DIB11_dly, 
+                DI30=>DIB12_dly, DI31=>DIB13_dly, DI32=>DIB14_dly, 
+                DI33=>DIB15_dly, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, 
+                ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, 
+                ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, 
+                ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, 
+                ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, 
+                ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, 
+                ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, 
+                ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, 
+                DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>DOB6_out, 
+                DO7=>DOB7_out, DO8=>DOB8_out, DO9=>DOB9_out, DO10=>DOB10_out, 
+                DO11=>DOB11_out, DO12=>DOB12_out, DO13=>DOB13_out, DO14=>open, 
+                DO15=>open, DO16=>open, DO17=>open, DO18=>DOA0_out, 
+                DO19=>DOA1_out, DO20=>DOA2_out, DO21=>DOA3_out, DO22=>DOA4_out, 
+                DO23=>DOA5_out, DO24=>DOA6_out, DO25=>DOA7_out, DO26=>DOA8_out, 
+                DO27=>DOA9_out, DO28=>DOA10_out, DO29=>DOA11_out, 
+                DO30=>DOA12_out, DO31=>DOA13_out, DO32=>DOA14_out, 
+                DO33=>DOA15_out, DO34=>DOA16_out, DO35=>DOA17_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(DIA17_ipd, DIA17, tipd_DIA17);
+      VitalWireDelay(DIA16_ipd, DIA16, tipd_DIA16);
+      VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15);
+      VitalWireDelay(DIA14_ipd, DIA14, tipd_DIA14);
+      VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13);
+      VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12);
+      VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11);
+      VitalWireDelay(DIA10_ipd, DIA10, tipd_DIA10);
+      VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9);
+      VitalWireDelay(DIA8_ipd, DIA8, tipd_DIA8);
+      VitalWireDelay(DIA7_ipd, DIA7, tipd_DIA7);
+      VitalWireDelay(DIA6_ipd, DIA6, tipd_DIA6);
+      VitalWireDelay(DIA5_ipd, DIA5, tipd_DIA5);
+      VitalWireDelay(DIA4_ipd, DIA4, tipd_DIA4);
+      VitalWireDelay(DIA3_ipd, DIA3, tipd_DIA3);
+      VitalWireDelay(DIA2_ipd, DIA2, tipd_DIA2);
+      VitalWireDelay(DIA1_ipd, DIA1, tipd_DIA1);
+      VitalWireDelay(DIA0_ipd, DIA0, tipd_DIA0);
+      VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13);
+      VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12);
+      VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11);
+      VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10);
+      VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9);
+      VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8);
+      VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7);
+      VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6);
+      VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5);
+      VitalWireDelay(CEA_ipd, CEA, tipd_CEA);
+      VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA);
+      VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB);
+      VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB);
+      VitalWireDelay(CEB_ipd, CEB, tipd_CEB);
+      VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5);
+      VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6);
+      VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7);
+      VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8);
+      VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9);
+      VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10);
+      VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11);
+      VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12);
+      VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13);
+      VitalWireDelay(DIB0_ipd, DIB0, tipd_DIB0);
+      VitalWireDelay(DIB1_ipd, DIB1, tipd_DIB1);
+      VitalWireDelay(DIB2_ipd, DIB2, tipd_DIB2);
+      VitalWireDelay(DIB3_ipd, DIB3, tipd_DIB3);
+      VitalWireDelay(DIB4_ipd, DIB4, tipd_DIB4);
+      VitalWireDelay(DIB5_ipd, DIB5, tipd_DIB5);
+      VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6);
+      VitalWireDelay(DIB7_ipd, DIB7, tipd_DIB7);
+      VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8);
+      VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9);
+      VitalWireDelay(DIB10_ipd, DIB10, tipd_DIB10);
+      VitalWireDelay(DIB11_ipd, DIB11, tipd_DIB11);
+      VitalWireDelay(DIB12_ipd, DIB12, tipd_DIB12);
+      VitalWireDelay(DIB13_ipd, DIB13, tipd_DIB13);
+      VitalWireDelay(DIB14_ipd, DIB14, tipd_DIB14);
+      VitalWireDelay(DIB15_ipd, DIB15, tipd_DIB15);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DIA17_dly, DIA17_ipd, tisd_DIA17_CLKA);
+      VitalSignalDelay(DIA16_dly, DIA16_ipd, tisd_DIA16_CLKA);
+      VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA);
+      VitalSignalDelay(DIA14_dly, DIA14_ipd, tisd_DIA14_CLKA);
+      VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA);
+      VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA);
+      VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA);
+      VitalSignalDelay(DIA10_dly, DIA10_ipd, tisd_DIA10_CLKA);
+      VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA);
+      VitalSignalDelay(DIA8_dly, DIA8_ipd, tisd_DIA8_CLKA);
+      VitalSignalDelay(DIA7_dly, DIA7_ipd, tisd_DIA7_CLKA);
+      VitalSignalDelay(DIA6_dly, DIA6_ipd, tisd_DIA6_CLKA);
+      VitalSignalDelay(DIA5_dly, DIA5_ipd, tisd_DIA5_CLKA);
+      VitalSignalDelay(DIA4_dly, DIA4_ipd, tisd_DIA4_CLKA);
+      VitalSignalDelay(DIA3_dly, DIA3_ipd, tisd_DIA3_CLKA);
+      VitalSignalDelay(DIA2_dly, DIA2_ipd, tisd_DIA2_CLKA);
+      VitalSignalDelay(DIA1_dly, DIA1_ipd, tisd_DIA1_CLKA);
+      VitalSignalDelay(DIA0_dly, DIA0_ipd, tisd_DIA0_CLKA);
+      VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA);
+      VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA);
+      VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA);
+      VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA);
+      VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA);
+      VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA);
+      VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA);
+      VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA);
+      VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA);
+      VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA);
+      VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA);
+      VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB);
+      VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB);
+      VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB);
+      VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB);
+      VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB);
+      VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB);
+      VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB);
+      VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB);
+      VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB);
+      VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB);
+      VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB);
+      VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB);
+      VitalSignalDelay(DIB0_dly, DIB0_ipd, tisd_DIB0_CLKA);
+      VitalSignalDelay(DIB1_dly, DIB1_ipd, tisd_DIB1_CLKA);
+      VitalSignalDelay(DIB2_dly, DIB2_ipd, tisd_DIB2_CLKA);
+      VitalSignalDelay(DIB3_dly, DIB3_ipd, tisd_DIB3_CLKA);
+      VitalSignalDelay(DIB4_dly, DIB4_ipd, tisd_DIB4_CLKA);
+      VitalSignalDelay(DIB5_dly, DIB5_ipd, tisd_DIB5_CLKA);
+      VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA);
+      VitalSignalDelay(DIB7_dly, DIB7_ipd, tisd_DIB7_CLKA);
+      VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA);
+      VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA);
+      VitalSignalDelay(DIB10_dly, DIB10_ipd, tisd_DIB10_CLKA);
+      VitalSignalDelay(DIB11_dly, DIB11_ipd, tisd_DIB11_CLKA);
+      VitalSignalDelay(DIB12_dly, DIB12_ipd, tisd_DIB12_CLKA);
+      VitalSignalDelay(DIB13_dly, DIB13_ipd, tisd_DIB13_CLKA);
+      VitalSignalDelay(DIB14_dly, DIB14_ipd, tisd_DIB14_CLKA);
+      VitalSignalDelay(DIB15_dly, DIB15_ipd, tisd_DIB15_CLKA);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (DIA17_dly, DIA16_dly, DIA15_dly, DIA14_dly, 
+      DIA13_dly, DIA12_dly, DIA11_dly, DIA10_dly, DIA9_dly, DIA8_dly, DIA7_dly, 
+      DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, 
+      ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, 
+      ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, 
+      DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, 
+      DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, 
+      CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, 
+      DOB2_out, DOB3_out, DOB4_out, DOB5_out, DOB6_out, DOB7_out, DOB8_out, 
+      DOB9_out, DOB10_out, DOB11_out, DOB12_out, DOB13_out, ADB5_dly, ADB6_dly, 
+      ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, 
+      DIB0_dly, DIB1_dly, DIB2_dly, DIB3_dly, DIB4_dly, DIB5_dly, DIB6_dly, 
+      DIB7_dly, DIB8_dly, DIB9_dly, DIB10_dly, DIB11_dly, DIB12_dly, DIB13_dly, 
+      DIB14_dly, DIB15_dly)
+    VARIABLE DOA17_zd         	: std_logic := 'X';
+    VARIABLE DOA17_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA16_zd         	: std_logic := 'X';
+    VARIABLE DOA16_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA15_zd         	: std_logic := 'X';
+    VARIABLE DOA15_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA14_zd         	: std_logic := 'X';
+    VARIABLE DOA14_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA13_zd         	: std_logic := 'X';
+    VARIABLE DOA13_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA12_zd         	: std_logic := 'X';
+    VARIABLE DOA12_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA11_zd         	: std_logic := 'X';
+    VARIABLE DOA11_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA10_zd         	: std_logic := 'X';
+    VARIABLE DOA10_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA9_zd         	: std_logic := 'X';
+    VARIABLE DOA9_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA8_zd         	: std_logic := 'X';
+    VARIABLE DOA8_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA7_zd         	: std_logic := 'X';
+    VARIABLE DOA7_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA6_zd         	: std_logic := 'X';
+    VARIABLE DOA6_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA5_zd         	: std_logic := 'X';
+    VARIABLE DOA5_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA4_zd         	: std_logic := 'X';
+    VARIABLE DOA4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA3_zd         	: std_logic := 'X';
+    VARIABLE DOA3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA2_zd         	: std_logic := 'X';
+    VARIABLE DOA2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA1_zd         	: std_logic := 'X';
+    VARIABLE DOA1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOA0_zd         	: std_logic := 'X';
+    VARIABLE DOA0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB0_zd         	: std_logic := 'X';
+    VARIABLE DOB0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB1_zd         	: std_logic := 'X';
+    VARIABLE DOB1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB2_zd         	: std_logic := 'X';
+    VARIABLE DOB2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB3_zd         	: std_logic := 'X';
+    VARIABLE DOB3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB4_zd         	: std_logic := 'X';
+    VARIABLE DOB4_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB5_zd         	: std_logic := 'X';
+    VARIABLE DOB5_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB6_zd         	: std_logic := 'X';
+    VARIABLE DOB6_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB7_zd         	: std_logic := 'X';
+    VARIABLE DOB7_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB8_zd         	: std_logic := 'X';
+    VARIABLE DOB8_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB9_zd         	: std_logic := 'X';
+    VARIABLE DOB9_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB10_zd         	: std_logic := 'X';
+    VARIABLE DOB10_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB11_zd         	: std_logic := 'X';
+    VARIABLE DOB11_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB12_zd         	: std_logic := 'X';
+    VARIABLE DOB12_GlitchData 	: VitalGlitchDataType;
+    VARIABLE DOB13_zd         	: std_logic := 'X';
+    VARIABLE DOB13_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DIA17_CLKA       	: x01 := '0';
+    VARIABLE DIA17_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA16_CLKA       	: x01 := '0';
+    VARIABLE DIA16_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA15_CLKA       	: x01 := '0';
+    VARIABLE DIA15_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA14_CLKA       	: x01 := '0';
+    VARIABLE DIA14_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA13_CLKA       	: x01 := '0';
+    VARIABLE DIA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA12_CLKA       	: x01 := '0';
+    VARIABLE DIA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA11_CLKA       	: x01 := '0';
+    VARIABLE DIA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA10_CLKA       	: x01 := '0';
+    VARIABLE DIA10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA9_CLKA       	: x01 := '0';
+    VARIABLE DIA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA8_CLKA       	: x01 := '0';
+    VARIABLE DIA8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA7_CLKA       	: x01 := '0';
+    VARIABLE DIA7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA6_CLKA       	: x01 := '0';
+    VARIABLE DIA6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA5_CLKA       	: x01 := '0';
+    VARIABLE DIA5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA4_CLKA       	: x01 := '0';
+    VARIABLE DIA4_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA3_CLKA       	: x01 := '0';
+    VARIABLE DIA3_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA2_CLKA       	: x01 := '0';
+    VARIABLE DIA2_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA1_CLKA       	: x01 := '0';
+    VARIABLE DIA1_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIA0_CLKA       	: x01 := '0';
+    VARIABLE DIA0_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA13_CLKA       	: x01 := '0';
+    VARIABLE ADA13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA12_CLKA       	: x01 := '0';
+    VARIABLE ADA12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA11_CLKA       	: x01 := '0';
+    VARIABLE ADA11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA10_CLKA       	: x01 := '0';
+    VARIABLE ADA10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA9_CLKA       	: x01 := '0';
+    VARIABLE ADA9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA8_CLKA       	: x01 := '0';
+    VARIABLE ADA8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA7_CLKA       	: x01 := '0';
+    VARIABLE ADA7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA6_CLKA       	: x01 := '0';
+    VARIABLE ADA6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADA5_CLKA       	: x01 := '0';
+    VARIABLE ADA5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEA_CLKA       	: x01 := '0';
+    VARIABLE CEA_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_OCEB_CLKB       	: x01 := '0';
+    VARIABLE OCEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CEB_CLKB       	: x01 := '0';
+    VARIABLE CEB_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB5_CLKB       	: x01 := '0';
+    VARIABLE ADB5_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB6_CLKB       	: x01 := '0';
+    VARIABLE ADB6_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB7_CLKB       	: x01 := '0';
+    VARIABLE ADB7_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB8_CLKB       	: x01 := '0';
+    VARIABLE ADB8_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB9_CLKB       	: x01 := '0';
+    VARIABLE ADB9_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB10_CLKB       	: x01 := '0';
+    VARIABLE ADB10_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB11_CLKB       	: x01 := '0';
+    VARIABLE ADB11_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB12_CLKB       	: x01 := '0';
+    VARIABLE ADB12_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_ADB13_CLKB       	: x01 := '0';
+    VARIABLE ADB13_CLKB_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB0_CLKA       	: x01 := '0';
+    VARIABLE DIB0_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB1_CLKA       	: x01 := '0';
+    VARIABLE DIB1_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB2_CLKA       	: x01 := '0';
+    VARIABLE DIB2_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB3_CLKA       	: x01 := '0';
+    VARIABLE DIB3_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB4_CLKA       	: x01 := '0';
+    VARIABLE DIB4_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB5_CLKA       	: x01 := '0';
+    VARIABLE DIB5_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB6_CLKA       	: x01 := '0';
+    VARIABLE DIB6_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB7_CLKA       	: x01 := '0';
+    VARIABLE DIB7_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB8_CLKA       	: x01 := '0';
+    VARIABLE DIB8_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB9_CLKA       	: x01 := '0';
+    VARIABLE DIB9_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB10_CLKA       	: x01 := '0';
+    VARIABLE DIB10_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB11_CLKA       	: x01 := '0';
+    VARIABLE DIB11_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB12_CLKA       	: x01 := '0';
+    VARIABLE DIB12_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB13_CLKA       	: x01 := '0';
+    VARIABLE DIB13_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB14_CLKA       	: x01 := '0';
+    VARIABLE DIB14_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DIB15_CLKA       	: x01 := '0';
+    VARIABLE DIB15_CLKA_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLKA_CLKA          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKA	: VitalPeriodDataType;
+    VARIABLE tviol_CLKB_CLKB          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLKB	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DIA17_dly,
+        TestSignalName => "DIA17",
+        TestDelay => tisd_DIA17_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA17_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA17_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA17_CLKA_noedge_posedge,
+        HoldLow => thold_DIA17_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA17_CLKA_TimingDatash,
+        Violation => tviol_DIA17_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA16_dly,
+        TestSignalName => "DIA16",
+        TestDelay => tisd_DIA16_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA16_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA16_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA16_CLKA_noedge_posedge,
+        HoldLow => thold_DIA16_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA16_CLKA_TimingDatash,
+        Violation => tviol_DIA16_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA15_dly,
+        TestSignalName => "DIA15",
+        TestDelay => tisd_DIA15_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA15_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA15_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA15_CLKA_noedge_posedge,
+        HoldLow => thold_DIA15_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA15_CLKA_TimingDatash,
+        Violation => tviol_DIA15_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA14_dly,
+        TestSignalName => "DIA14",
+        TestDelay => tisd_DIA14_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA14_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA14_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA14_CLKA_noedge_posedge,
+        HoldLow => thold_DIA14_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA14_CLKA_TimingDatash,
+        Violation => tviol_DIA14_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA13_dly,
+        TestSignalName => "DIA13",
+        TestDelay => tisd_DIA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA13_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA13_CLKA_noedge_posedge,
+        HoldLow => thold_DIA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA13_CLKA_TimingDatash,
+        Violation => tviol_DIA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA12_dly,
+        TestSignalName => "DIA12",
+        TestDelay => tisd_DIA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA12_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA12_CLKA_noedge_posedge,
+        HoldLow => thold_DIA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA12_CLKA_TimingDatash,
+        Violation => tviol_DIA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA11_dly,
+        TestSignalName => "DIA11",
+        TestDelay => tisd_DIA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA11_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA11_CLKA_noedge_posedge,
+        HoldLow => thold_DIA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA11_CLKA_TimingDatash,
+        Violation => tviol_DIA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA10_dly,
+        TestSignalName => "DIA10",
+        TestDelay => tisd_DIA10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA10_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA10_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA10_CLKA_noedge_posedge,
+        HoldLow => thold_DIA10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA10_CLKA_TimingDatash,
+        Violation => tviol_DIA10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA9_dly,
+        TestSignalName => "DIA9",
+        TestDelay => tisd_DIA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA9_CLKA_noedge_posedge,
+        HoldLow => thold_DIA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA9_CLKA_TimingDatash,
+        Violation => tviol_DIA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA8_dly,
+        TestSignalName => "DIA8",
+        TestDelay => tisd_DIA8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA8_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA8_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA8_CLKA_noedge_posedge,
+        HoldLow => thold_DIA8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA8_CLKA_TimingDatash,
+        Violation => tviol_DIA8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA7_dly,
+        TestSignalName => "DIA7",
+        TestDelay => tisd_DIA7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA7_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA7_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA7_CLKA_noedge_posedge,
+        HoldLow => thold_DIA7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA7_CLKA_TimingDatash,
+        Violation => tviol_DIA7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA6_dly,
+        TestSignalName => "DIA6",
+        TestDelay => tisd_DIA6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA6_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA6_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA6_CLKA_noedge_posedge,
+        HoldLow => thold_DIA6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA6_CLKA_TimingDatash,
+        Violation => tviol_DIA6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA5_dly,
+        TestSignalName => "DIA5",
+        TestDelay => tisd_DIA5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA5_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA5_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA5_CLKA_noedge_posedge,
+        HoldLow => thold_DIA5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA5_CLKA_TimingDatash,
+        Violation => tviol_DIA5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA4_dly,
+        TestSignalName => "DIA4",
+        TestDelay => tisd_DIA4_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA4_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA4_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA4_CLKA_noedge_posedge,
+        HoldLow => thold_DIA4_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA4_CLKA_TimingDatash,
+        Violation => tviol_DIA4_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA3_dly,
+        TestSignalName => "DIA3",
+        TestDelay => tisd_DIA3_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA3_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA3_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA3_CLKA_noedge_posedge,
+        HoldLow => thold_DIA3_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA3_CLKA_TimingDatash,
+        Violation => tviol_DIA3_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA2_dly,
+        TestSignalName => "DIA2",
+        TestDelay => tisd_DIA2_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA2_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA2_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA2_CLKA_noedge_posedge,
+        HoldLow => thold_DIA2_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA2_CLKA_TimingDatash,
+        Violation => tviol_DIA2_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA1_dly,
+        TestSignalName => "DIA1",
+        TestDelay => tisd_DIA1_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA1_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA1_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA1_CLKA_noedge_posedge,
+        HoldLow => thold_DIA1_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA1_CLKA_TimingDatash,
+        Violation => tviol_DIA1_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIA0_dly,
+        TestSignalName => "DIA0",
+        TestDelay => tisd_DIA0_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIA0_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIA0_CLKA_noedge_posedge,
+        HoldHigh => thold_DIA0_CLKA_noedge_posedge,
+        HoldLow => thold_DIA0_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIA0_CLKA_TimingDatash,
+        Violation => tviol_DIA0_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA13_dly,
+        TestSignalName => "ADA13",
+        TestDelay => tisd_ADA13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA13_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA13_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA13_CLKA_noedge_posedge,
+        HoldLow => thold_ADA13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA13_CLKA_TimingDatash,
+        Violation => tviol_ADA13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA12_dly,
+        TestSignalName => "ADA12",
+        TestDelay => tisd_ADA12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA12_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA12_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA12_CLKA_noedge_posedge,
+        HoldLow => thold_ADA12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA12_CLKA_TimingDatash,
+        Violation => tviol_ADA12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA11_dly,
+        TestSignalName => "ADA11",
+        TestDelay => tisd_ADA11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA11_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA11_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA11_CLKA_noedge_posedge,
+        HoldLow => thold_ADA11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA11_CLKA_TimingDatash,
+        Violation => tviol_ADA11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA10_dly,
+        TestSignalName => "ADA10",
+        TestDelay => tisd_ADA10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA10_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA10_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA10_CLKA_noedge_posedge,
+        HoldLow => thold_ADA10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA10_CLKA_TimingDatash,
+        Violation => tviol_ADA10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA9_dly,
+        TestSignalName => "ADA9",
+        TestDelay => tisd_ADA9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA9_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA9_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA9_CLKA_noedge_posedge,
+        HoldLow => thold_ADA9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA9_CLKA_TimingDatash,
+        Violation => tviol_ADA9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA8_dly,
+        TestSignalName => "ADA8",
+        TestDelay => tisd_ADA8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA8_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA8_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA8_CLKA_noedge_posedge,
+        HoldLow => thold_ADA8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA8_CLKA_TimingDatash,
+        Violation => tviol_ADA8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA7_dly,
+        TestSignalName => "ADA7",
+        TestDelay => tisd_ADA7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA7_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA7_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA7_CLKA_noedge_posedge,
+        HoldLow => thold_ADA7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA7_CLKA_TimingDatash,
+        Violation => tviol_ADA7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA6_dly,
+        TestSignalName => "ADA6",
+        TestDelay => tisd_ADA6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA6_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA6_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA6_CLKA_noedge_posedge,
+        HoldLow => thold_ADA6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA6_CLKA_TimingDatash,
+        Violation => tviol_ADA6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADA5_dly,
+        TestSignalName => "ADA5",
+        TestDelay => tisd_ADA5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_ADA5_CLKA_noedge_posedge,
+        SetupLow => tsetup_ADA5_CLKA_noedge_posedge,
+        HoldHigh => thold_ADA5_CLKA_noedge_posedge,
+        HoldLow => thold_ADA5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADA5_CLKA_TimingDatash,
+        Violation => tviol_ADA5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEA_dly,
+        TestSignalName => "CEA",
+        TestDelay => tisd_CEA_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_CEA_CLKA_noedge_posedge,
+        SetupLow => tsetup_CEA_CLKA_noedge_posedge,
+        HoldHigh => thold_CEA_CLKA_noedge_posedge,
+        HoldLow => thold_CEA_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEA_CLKA_TimingDatash,
+        Violation => tviol_CEA_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => OCEB_dly,
+        TestSignalName => "OCEB",
+        TestDelay => tisd_OCEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_OCEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_OCEB_CLKB_noedge_posedge,
+        HoldHigh => thold_OCEB_CLKB_noedge_posedge,
+        HoldLow => thold_OCEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => OCEB_CLKB_TimingDatash,
+        Violation => tviol_OCEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CEB_dly,
+        TestSignalName => "CEB",
+        TestDelay => tisd_CEB_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_CEB_CLKB_noedge_posedge,
+        SetupLow => tsetup_CEB_CLKB_noedge_posedge,
+        HoldHigh => thold_CEB_CLKB_noedge_posedge,
+        HoldLow => thold_CEB_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CEB_CLKB_TimingDatash,
+        Violation => tviol_CEB_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB5_dly,
+        TestSignalName => "ADB5",
+        TestDelay => tisd_ADB5_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB5_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB5_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB5_CLKB_noedge_posedge,
+        HoldLow => thold_ADB5_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB5_CLKB_TimingDatash,
+        Violation => tviol_ADB5_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB6_dly,
+        TestSignalName => "ADB6",
+        TestDelay => tisd_ADB6_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB6_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB6_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB6_CLKB_noedge_posedge,
+        HoldLow => thold_ADB6_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB6_CLKB_TimingDatash,
+        Violation => tviol_ADB6_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB7_dly,
+        TestSignalName => "ADB7",
+        TestDelay => tisd_ADB7_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB7_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB7_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB7_CLKB_noedge_posedge,
+        HoldLow => thold_ADB7_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB7_CLKB_TimingDatash,
+        Violation => tviol_ADB7_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB8_dly,
+        TestSignalName => "ADB8",
+        TestDelay => tisd_ADB8_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB8_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB8_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB8_CLKB_noedge_posedge,
+        HoldLow => thold_ADB8_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB8_CLKB_TimingDatash,
+        Violation => tviol_ADB8_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB9_dly,
+        TestSignalName => "ADB9",
+        TestDelay => tisd_ADB9_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB9_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB9_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB9_CLKB_noedge_posedge,
+        HoldLow => thold_ADB9_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB9_CLKB_TimingDatash,
+        Violation => tviol_ADB9_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB10_dly,
+        TestSignalName => "ADB10",
+        TestDelay => tisd_ADB10_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB10_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB10_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB10_CLKB_noedge_posedge,
+        HoldLow => thold_ADB10_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB10_CLKB_TimingDatash,
+        Violation => tviol_ADB10_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB11_dly,
+        TestSignalName => "ADB11",
+        TestDelay => tisd_ADB11_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB11_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB11_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB11_CLKB_noedge_posedge,
+        HoldLow => thold_ADB11_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB11_CLKB_TimingDatash,
+        Violation => tviol_ADB11_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB12_dly,
+        TestSignalName => "ADB12",
+        TestDelay => tisd_ADB12_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB12_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB12_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB12_CLKB_noedge_posedge,
+        HoldLow => thold_ADB12_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB12_CLKB_TimingDatash,
+        Violation => tviol_ADB12_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => ADB13_dly,
+        TestSignalName => "ADB13",
+        TestDelay => tisd_ADB13_CLKB,
+        RefSignal => CLKB_dly,
+        RefSignalName => "CLKB",
+        RefDelay => ticd_CLKB,
+        SetupHigh => tsetup_ADB13_CLKB_noedge_posedge,
+        SetupLow => tsetup_ADB13_CLKB_noedge_posedge,
+        HoldHigh => thold_ADB13_CLKB_noedge_posedge,
+        HoldLow => thold_ADB13_CLKB_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => ADB13_CLKB_TimingDatash,
+        Violation => tviol_ADB13_CLKB,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB0_dly,
+        TestSignalName => "DIB0",
+        TestDelay => tisd_DIB0_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB0_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB0_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB0_CLKA_noedge_posedge,
+        HoldLow => thold_DIB0_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB0_CLKA_TimingDatash,
+        Violation => tviol_DIB0_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB1_dly,
+        TestSignalName => "DIB1",
+        TestDelay => tisd_DIB1_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB1_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB1_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB1_CLKA_noedge_posedge,
+        HoldLow => thold_DIB1_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB1_CLKA_TimingDatash,
+        Violation => tviol_DIB1_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB2_dly,
+        TestSignalName => "DIB2",
+        TestDelay => tisd_DIB2_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB2_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB2_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB2_CLKA_noedge_posedge,
+        HoldLow => thold_DIB2_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB2_CLKA_TimingDatash,
+        Violation => tviol_DIB2_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB3_dly,
+        TestSignalName => "DIB3",
+        TestDelay => tisd_DIB3_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB3_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB3_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB3_CLKA_noedge_posedge,
+        HoldLow => thold_DIB3_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB3_CLKA_TimingDatash,
+        Violation => tviol_DIB3_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB4_dly,
+        TestSignalName => "DIB4",
+        TestDelay => tisd_DIB4_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB4_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB4_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB4_CLKA_noedge_posedge,
+        HoldLow => thold_DIB4_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB4_CLKA_TimingDatash,
+        Violation => tviol_DIB4_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB5_dly,
+        TestSignalName => "DIB5",
+        TestDelay => tisd_DIB5_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB5_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB5_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB5_CLKA_noedge_posedge,
+        HoldLow => thold_DIB5_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB5_CLKA_TimingDatash,
+        Violation => tviol_DIB5_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB6_dly,
+        TestSignalName => "DIB6",
+        TestDelay => tisd_DIB6_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB6_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB6_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB6_CLKA_noedge_posedge,
+        HoldLow => thold_DIB6_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB6_CLKA_TimingDatash,
+        Violation => tviol_DIB6_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB7_dly,
+        TestSignalName => "DIB7",
+        TestDelay => tisd_DIB7_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB7_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB7_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB7_CLKA_noedge_posedge,
+        HoldLow => thold_DIB7_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB7_CLKA_TimingDatash,
+        Violation => tviol_DIB7_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB8_dly,
+        TestSignalName => "DIB8",
+        TestDelay => tisd_DIB8_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB8_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB8_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB8_CLKA_noedge_posedge,
+        HoldLow => thold_DIB8_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB8_CLKA_TimingDatash,
+        Violation => tviol_DIB8_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB9_dly,
+        TestSignalName => "DIB9",
+        TestDelay => tisd_DIB9_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB9_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB9_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB9_CLKA_noedge_posedge,
+        HoldLow => thold_DIB9_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB9_CLKA_TimingDatash,
+        Violation => tviol_DIB9_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB10_dly,
+        TestSignalName => "DIB10",
+        TestDelay => tisd_DIB10_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB10_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB10_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB10_CLKA_noedge_posedge,
+        HoldLow => thold_DIB10_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB10_CLKA_TimingDatash,
+        Violation => tviol_DIB10_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB11_dly,
+        TestSignalName => "DIB11",
+        TestDelay => tisd_DIB11_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB11_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB11_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB11_CLKA_noedge_posedge,
+        HoldLow => thold_DIB11_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB11_CLKA_TimingDatash,
+        Violation => tviol_DIB11_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB12_dly,
+        TestSignalName => "DIB12",
+        TestDelay => tisd_DIB12_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB12_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB12_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB12_CLKA_noedge_posedge,
+        HoldLow => thold_DIB12_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB12_CLKA_TimingDatash,
+        Violation => tviol_DIB12_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB13_dly,
+        TestSignalName => "DIB13",
+        TestDelay => tisd_DIB13_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB13_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB13_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB13_CLKA_noedge_posedge,
+        HoldLow => thold_DIB13_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB13_CLKA_TimingDatash,
+        Violation => tviol_DIB13_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB14_dly,
+        TestSignalName => "DIB14",
+        TestDelay => tisd_DIB14_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB14_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB14_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB14_CLKA_noedge_posedge,
+        HoldLow => thold_DIB14_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB14_CLKA_TimingDatash,
+        Violation => tviol_DIB14_CLKA,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DIB15_dly,
+        TestSignalName => "DIB15",
+        TestDelay => tisd_DIB15_CLKA,
+        RefSignal => CLKA_dly,
+        RefSignalName => "CLKA",
+        RefDelay => ticd_CLKA,
+        SetupHigh => tsetup_DIB15_CLKA_noedge_posedge,
+        SetupLow => tsetup_DIB15_CLKA_noedge_posedge,
+        HoldHigh => thold_DIB15_CLKA_noedge_posedge,
+        HoldLow => thold_DIB15_CLKA_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DIB15_CLKA_TimingDatash,
+        Violation => tviol_DIB15_CLKA,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKA_ipd,
+        TestSignalName => "CLKA",
+        Period => tperiod_CLKA,
+        PulseWidthHigh => tpw_CLKA_posedge,
+        PulseWidthLow => tpw_CLKA_negedge,
+        PeriodData => periodcheckinfo_CLKA,
+        Violation => tviol_CLKA_CLKA,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLKB_ipd,
+        TestSignalName => "CLKB",
+        Period => tperiod_CLKB,
+        PulseWidthHigh => tpw_CLKB_posedge,
+        PulseWidthLow => tpw_CLKB_negedge,
+        PeriodData => periodcheckinfo_CLKB,
+        Violation => tviol_CLKB_CLKB,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    DOA17_zd 	:= DOA17_out;
+    DOA16_zd 	:= DOA16_out;
+    DOA15_zd 	:= DOA15_out;
+    DOA14_zd 	:= DOA14_out;
+    DOA13_zd 	:= DOA13_out;
+    DOA12_zd 	:= DOA12_out;
+    DOA11_zd 	:= DOA11_out;
+    DOA10_zd 	:= DOA10_out;
+    DOA9_zd 	:= DOA9_out;
+    DOA8_zd 	:= DOA8_out;
+    DOA7_zd 	:= DOA7_out;
+    DOA6_zd 	:= DOA6_out;
+    DOA5_zd 	:= DOA5_out;
+    DOA4_zd 	:= DOA4_out;
+    DOA3_zd 	:= DOA3_out;
+    DOA2_zd 	:= DOA2_out;
+    DOA1_zd 	:= DOA1_out;
+    DOA0_zd 	:= DOA0_out;
+    DOB0_zd 	:= DOB0_out;
+    DOB1_zd 	:= DOB1_out;
+    DOB2_zd 	:= DOB2_out;
+    DOB3_zd 	:= DOB3_out;
+    DOB4_zd 	:= DOB4_out;
+    DOB5_zd 	:= DOB5_out;
+    DOB6_zd 	:= DOB6_out;
+    DOB7_zd 	:= DOB7_out;
+    DOB8_zd 	:= DOB8_out;
+    DOB9_zd 	:= DOB9_out;
+    DOB10_zd 	:= DOB10_out;
+    DOB11_zd 	:= DOB11_out;
+    DOB12_zd 	:= DOB12_out;
+    DOB13_zd 	:= DOB13_out;
+
+    VitalPathDelay01 (
+      OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA17,
+                           PathCondition => TRUE)),
+      GlitchData => DOA17_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA16,
+                           PathCondition => TRUE)),
+      GlitchData => DOA16_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA15,
+                           PathCondition => TRUE)),
+      GlitchData => DOA15_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA14,
+                           PathCondition => TRUE)),
+      GlitchData => DOA14_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA13,
+                           PathCondition => TRUE)),
+      GlitchData => DOA13_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA12,
+                           PathCondition => TRUE)),
+      GlitchData => DOA12_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA11,
+                           PathCondition => TRUE)),
+      GlitchData => DOA11_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA10,
+                           PathCondition => TRUE)),
+      GlitchData => DOA10_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA9,
+                           PathCondition => TRUE)),
+      GlitchData => DOA9_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA8,
+                           PathCondition => TRUE)),
+      GlitchData => DOA8_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA7,
+                           PathCondition => TRUE)),
+      GlitchData => DOA7_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA6,
+                           PathCondition => TRUE)),
+      GlitchData => DOA6_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA5,
+                           PathCondition => TRUE)),
+      GlitchData => DOA5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA4,
+                           PathCondition => TRUE)),
+      GlitchData => DOA4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA3,
+                           PathCondition => TRUE)),
+      GlitchData => DOA3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA2,
+                           PathCondition => TRUE)),
+      GlitchData => DOA2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA1,
+                           PathCondition => TRUE)),
+      GlitchData => DOA1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOA0,
+                           PathCondition => TRUE)),
+      GlitchData => DOA0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB0,
+                           PathCondition => TRUE)),
+      GlitchData => DOB0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB1,
+                           PathCondition => TRUE)),
+      GlitchData => DOB1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB2,
+                           PathCondition => TRUE)),
+      GlitchData => DOB2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB3,
+                           PathCondition => TRUE)),
+      GlitchData => DOB3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB4,
+                           PathCondition => TRUE)),
+      GlitchData => DOB4_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB5,
+                           PathCondition => TRUE)),
+      GlitchData => DOB5_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB6, OutSignalName => "DOB6", OutTemp => DOB6_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB6,
+                           PathCondition => TRUE)),
+      GlitchData => DOB6_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB7, OutSignalName => "DOB7", OutTemp => DOB7_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB7,
+                           PathCondition => TRUE)),
+      GlitchData => DOB7_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB8, OutSignalName => "DOB8", OutTemp => DOB8_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB8,
+                           PathCondition => TRUE)),
+      GlitchData => DOB8_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB9, OutSignalName => "DOB9", OutTemp => DOB9_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB9,
+                           PathCondition => TRUE)),
+      GlitchData => DOB9_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB10, OutSignalName => "DOB10", OutTemp => DOB10_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB10,
+                           PathCondition => TRUE)),
+      GlitchData => DOB10_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB11, OutSignalName => "DOB11", OutTemp => DOB11_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB11,
+                           PathCondition => TRUE)),
+      GlitchData => DOB11_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB12, OutSignalName => "DOB12", OutTemp => DOB12_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB12,
+                           PathCondition => TRUE)),
+      GlitchData => DOB12_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => DOB13, OutSignalName => "DOB13", OutTemp => DOB13_zd,
+      Paths      => (0 => (InputChangeTime => CLKB_dly'last_event,
+                           PathDelay => tpd_CLKB_DOB13,
+                           PathCondition => TRUE)),
+      GlitchData => DOB13_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity EHXPLLLB
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity EHXPLLLB is
+    port (CLKI: in Std_logic; CLKFB: in Std_logic; PHASESEL1: in Std_logic; 
+          PHASESEL0: in Std_logic; PHASEDIR: in Std_logic; 
+          PHASESTEP: in Std_logic; PHASELOADREG: in Std_logic; 
+          STDBY: in Std_logic; PLLWAKESYNC: in Std_logic; RST: in Std_logic; 
+          ENCLKOP: in Std_logic; ENCLKOS: in Std_logic; ENCLKOS2: in Std_logic; 
+          ENCLKOS3: in Std_logic; CLKOP: out Std_logic; CLKOS: out Std_logic; 
+          CLKOS2: out Std_logic; CLKOS3: out Std_logic; LOCK: out Std_logic; 
+          INTLOCK: out Std_logic; REFCLK: out Std_logic; 
+          CLKINTFB: out Std_logic);
+
+
+
+  end EHXPLLLB;
+
+  architecture Structure of EHXPLLLB is
+  begin
+    INST10: EHXPLLL
+      generic map (CLKFB_DIV => 3, CLKI_DIV => 1, CLKOP_CPHASE => 1, 
+                   CLKOP_DIV => 2, CLKOP_ENABLE => "ENABLED", 
+                   CLKOP_FPHASE => 0, CLKOP_TRIM_DELAY => 0, 
+                   CLKOP_TRIM_POL => "FALLING", CLKOS2_CPHASE => 1, 
+                   CLKOS2_DIV => 2, CLKOS2_ENABLE => "ENABLED", 
+                   CLKOS2_FPHASE => 4, CLKOS3_CPHASE => 1, CLKOS3_DIV => 2, 
+                   CLKOS3_ENABLE => "ENABLED", CLKOS3_FPHASE => 6, 
+                   CLKOS_CPHASE => 1, CLKOS_DIV => 2, 
+                   CLKOS_ENABLE => "ENABLED", CLKOS_FPHASE => 2, 
+                   CLKOS_TRIM_DELAY => 0, CLKOS_TRIM_POL => "FALLING", 
+                   DPHASE_SOURCE => "DISABLED", FEEDBK_PATH => "CLKOP", 
+                   INTFB_WAKE => "DISABLED", INT_LOCK_STICKY => "ENABLED", 
+                   OUTDIVIDER_MUXA => "DIVA", OUTDIVIDER_MUXB => "DIVB", 
+                   OUTDIVIDER_MUXC => "DIVC", OUTDIVIDER_MUXD => "DIVD", 
+                   PLLRST_ENA => "DISABLED", PLL_LOCK_DELAY => 200, 
+                   PLL_LOCK_MODE => 0, REFIN_RESET => "DISABLED", 
+                   STDBY_ENABLE => "DISABLED", SYNC_ENABLE => "DISABLED")
+      port map (CLKI=>CLKI, CLKFB=>CLKFB, PHASESEL1=>PHASESEL1, 
+                PHASESEL0=>PHASESEL0, PHASEDIR=>PHASEDIR, PHASESTEP=>PHASESTEP, 
+                PHASELOADREG=>PHASELOADREG, STDBY=>STDBY, 
+                PLLWAKESYNC=>PLLWAKESYNC, RST=>RST, ENCLKOP=>ENCLKOP, 
+                ENCLKOS=>ENCLKOS, ENCLKOS2=>ENCLKOS2, ENCLKOS3=>ENCLKOS3, 
+                CLKOP=>CLKOP, CLKOS=>CLKOS, CLKOS2=>CLKOS2, CLKOS3=>CLKOS3, 
+                LOCK=>LOCK, INTLOCK=>INTLOCK, REFCLK=>REFCLK, 
+                CLKINTFB=>CLKINTFB);
+  end Structure;
+
+-- entity pll0inst_PLLInst_0
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity pll0inst_PLLInst_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "pll0inst_PLLInst_0";
+
+      tipd_CLKI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLKFB  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_STDBY  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKI_CLKOS3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKI_CLKOS2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKI_CLKOS	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKI_CLKOP	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKFB_CLKOS3	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKFB_CLKOS2	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKFB_CLKOS	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLKFB_CLKOP	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (CLKI: in Std_logic; CLKFB: in Std_logic; STDBY: in Std_logic; 
+          CLKOS3: out Std_logic; CLKOS2: out Std_logic; CLKOS: out Std_logic; 
+          CLKOP: out Std_logic);
+
+
+
+  end pll0inst_PLLInst_0;
+
+  architecture Structure of pll0inst_PLLInst_0 is
+    signal CLKI_ipd 	: std_logic := 'X';
+    signal CLKFB_ipd 	: std_logic := 'X';
+    signal STDBY_ipd 	: std_logic := 'X';
+    signal CLKOS3_out 	: std_logic := 'X';
+    signal CLKOS2_out 	: std_logic := 'X';
+    signal CLKOS_out 	: std_logic := 'X';
+    signal CLKOP_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component EHXPLLLB
+      port (CLKI: in Std_logic; CLKFB: in Std_logic; PHASESEL1: in Std_logic; 
+            PHASESEL0: in Std_logic; PHASEDIR: in Std_logic; 
+            PHASESTEP: in Std_logic; PHASELOADREG: in Std_logic; 
+            STDBY: in Std_logic; PLLWAKESYNC: in Std_logic; RST: in Std_logic; 
+            ENCLKOP: in Std_logic; ENCLKOS: in Std_logic; 
+            ENCLKOS2: in Std_logic; ENCLKOS3: in Std_logic; 
+            CLKOP: out Std_logic; CLKOS: out Std_logic; CLKOS2: out Std_logic; 
+            CLKOS3: out Std_logic; LOCK: out Std_logic; INTLOCK: out Std_logic; 
+            REFCLK: out Std_logic; CLKINTFB: out Std_logic);
+    end component;
+  begin
+    pll0inst_PLLInst_0_EHXPLLL: EHXPLLLB
+      port map (CLKI=>CLKI_ipd, CLKFB=>CLKFB_ipd, PHASESEL1=>GNDI, 
+                PHASESEL0=>GNDI, PHASEDIR=>GNDI, PHASESTEP=>GNDI, 
+                PHASELOADREG=>GNDI, STDBY=>STDBY_ipd, PLLWAKESYNC=>GNDI, 
+                RST=>GNDI, ENCLKOP=>GNDI, ENCLKOS=>GNDI, ENCLKOS2=>GNDI, 
+                ENCLKOS3=>GNDI, CLKOP=>CLKOP_out, CLKOS=>CLKOS_out, 
+                CLKOS2=>CLKOS2_out, CLKOS3=>CLKOS3_out, LOCK=>open, 
+                INTLOCK=>open, REFCLK=>open, CLKINTFB=>open);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CLKI_ipd, CLKI, tipd_CLKI);
+      VitalWireDelay(CLKFB_ipd, CLKFB, tipd_CLKFB);
+      VitalWireDelay(STDBY_ipd, STDBY, tipd_STDBY);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (CLKI_ipd, CLKFB_ipd, STDBY_ipd, CLKOS3_out, 
+      CLKOS2_out, CLKOS_out, CLKOP_out)
+    VARIABLE CLKOS3_zd         	: std_logic := 'X';
+    VARIABLE CLKOS3_GlitchData 	: VitalGlitchDataType;
+    VARIABLE CLKOS2_zd         	: std_logic := 'X';
+    VARIABLE CLKOS2_GlitchData 	: VitalGlitchDataType;
+    VARIABLE CLKOS_zd         	: std_logic := 'X';
+    VARIABLE CLKOS_GlitchData 	: VitalGlitchDataType;
+    VARIABLE CLKOP_zd         	: std_logic := 'X';
+    VARIABLE CLKOP_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    CLKOS3_zd 	:= CLKOS3_out;
+    CLKOS2_zd 	:= CLKOS2_out;
+    CLKOS_zd 	:= CLKOS_out;
+    CLKOP_zd 	:= CLKOP_out;
+
+    VitalPathDelay01 (
+      OutSignal => CLKOS3, OutSignalName => "CLKOS3", OutTemp => CLKOS3_zd,
+      Paths      => (0 => (InputChangeTime => CLKI_ipd'last_event,
+                           PathDelay => tpd_CLKI_CLKOS3,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => CLKFB_ipd'last_event,
+                           PathDelay => tpd_CLKFB_CLKOS3,
+                           PathCondition => TRUE)),
+      GlitchData => CLKOS3_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => CLKOS2, OutSignalName => "CLKOS2", OutTemp => CLKOS2_zd,
+      Paths      => (0 => (InputChangeTime => CLKI_ipd'last_event,
+                           PathDelay => tpd_CLKI_CLKOS2,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => CLKFB_ipd'last_event,
+                           PathDelay => tpd_CLKFB_CLKOS2,
+                           PathCondition => TRUE)),
+      GlitchData => CLKOS2_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => CLKOS, OutSignalName => "CLKOS", OutTemp => CLKOS_zd,
+      Paths      => (0 => (InputChangeTime => CLKI_ipd'last_event,
+                           PathDelay => tpd_CLKI_CLKOS,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => CLKFB_ipd'last_event,
+                           PathDelay => tpd_CLKFB_CLKOS,
+                           PathCondition => TRUE)),
+      GlitchData => CLKOS_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => CLKOP, OutSignalName => "CLKOP", OutTemp => CLKOP_zd,
+      Paths      => (0 => (InputChangeTime => CLKI_ipd'last_event,
+                           PathDelay => tpd_CLKI_CLKOP,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => CLKFB_ipd'last_event,
+                           PathDelay => tpd_CLKFB_CLKOP,
+                           PathCondition => TRUE)),
+      GlitchData => CLKOP_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity top_tf
+  library IEEE, vital2000, ECP5UM;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use ECP5UM.COMPONENTS.ALL;
+
+  entity top_tf is
+    port (clk: in Std_logic; rd_clk: in Std_logic; reset_dc: in Std_logic; 
+          trig: in Std_logic_vector (2 downto 0); 
+          fifo_data_out: out Std_logic_vector (31 downto 0); 
+          fifo_rden: out Std_logic; fifo_empty1: out Std_logic; 
+          LVL1_TRG_DATA_VALID_IN: in Std_logic; 
+          LVL1_INVALID_TRG_IN: in Std_logic; 
+          FEE_DATA_OUT: out Std_logic_vector (31 downto 0); 
+          FEE_DATA_WRITE_OUT: out Std_logic; 
+          FEE_DATAFINISHED_OUT: out Std_logic; 
+          FEE_TRG_RELEASE_OUT: out Std_logic; 
+          LVL1_TRG_DATA_VALI_IN_rising: out Std_logic; burst: out Std_logic; 
+          discard: out Std_logic; last_buf_empty: out Std_logic; 
+          finished: out Std_logic; release_out: out Std_logic; 
+          hades_trig: in Std_logic; hades_raw_out_valid: out Std_logic; 
+          hades_raw_valid_vect: out Std_logic_vector (1 downto 0); 
+          hades_lvl1: in Std_logic; hades_lvl1_invalid: in Std_logic; 
+          hades_offset: out Std_logic_vector (8 downto 0); 
+          hades_offset_valid: out Std_logic; hades_window_end: out Std_logic; 
+          hades_buf_out_valid: out Std_logic; hades_buf_release: out Std_logic; 
+          hades_buf_finished: out Std_logic; 
+          hades_hit_out_i: out Std_logic_vector (3 downto 0); 
+          hades_hit_valid: out Std_logic_vector (3 downto 0); 
+          hades_discard: out Std_logic; 
+          hades_invalid_dl: out Std_logic_vector (3 downto 0); 
+          hades_buf_drop: out Std_logic_vector (3 downto 0); 
+          hades_dbg2_out: out Std_logic_vector (31 downto 0); 
+          hades_dbg2_coarse: out Std_logic_vector (8 downto 0); 
+          hades_drop_cmp_buf: out Std_logic_vector (11 downto 0); 
+          hades_drop_cmp_buf_coarse: out Std_logic_vector (11 downto 0); 
+          hades_drop_cmp_buf_valid: out Std_logic);
+
+
+
+  end top_tf;
+
+  architecture Structure of top_tf is
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic;
+    signal pll_clks_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic;
+    signal fifo_empty_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic;
+    signal fifo_empty_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic;
+    signal fifo_empty1_c: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gctr_ci: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wren_i: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_iwcount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gctr_ci: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rden_i: Std_logic;
+    signal rd_clk_c: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co0_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co1_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co2_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co3_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_ircount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_cmp_ci: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co0_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co1_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co2_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co3_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_empty_cmp_set: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_empty_cmp_clr: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wcount_r8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_empty_d_c: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_empty_d: Std_logic;
+    signal last_buf_empty_c: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_cmp_ci_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co0_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co1_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co2_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_co3_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_full_cmp_clr: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_full_cmp_set: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rcount_w8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_full_d_c: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_full_d: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_Full: Std_logic;
+    signal hades_tdc_bundle_inst_hit_valid25_0_I_27_cry: Std_logic;
+    signal hades_tdc_bundle_inst_hit_valid25: Std_logic;
+    signal hades_dbg2_coarse_c_1: Std_logic;
+    signal hades_dbg2_coarse_c_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14: Std_logic;
+    signal hades_dbg2_coarse_c_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3: Std_logic;
+    signal hades_dbg2_coarse_c_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0: Std_logic;
+    signal hades_dbg2_coarse_c_8: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4: Std_logic;
+    signal hades_dbg2_coarse_c_7: Std_logic;
+    signal hades_dbg2_coarse_c_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0: Std_logic;
+    signal hades_drop_cmp_buf_c_0: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_0: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_1: Std_logic;
+    signal hades_drop_cmp_buf_c_1: Std_logic;
+    signal hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_5: Std_logic;
+    signal hades_drop_cmp_buf_c_5: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_4: Std_logic;
+    signal hades_drop_cmp_buf_c_4: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_3: Std_logic;
+    signal hades_drop_cmp_buf_c_2: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_2: Std_logic;
+    signal hades_drop_cmp_buf_c_3: Std_logic;
+    signal hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2: Std_logic;
+    signal hades_drop_cmp_buf_c_8: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_9: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_8: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_7: Std_logic;
+    signal hades_drop_cmp_buf_coarse_c_6: Std_logic;
+    signal hades_drop_cmp_buf_c_6: Std_logic;
+    signal hades_drop_cmp_buf_c_7: Std_logic;
+    signal ANB1: Std_logic;
+    signal ANB2: Std_logic;
+    signal ANB0: Std_logic;
+    signal ANB3: Std_logic;
+    signal hades_tdc_bundle_inst_N_247_i: Std_logic;
+    signal hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0: Std_logic;
+    signal reset_dl_2: Std_logic;
+    signal hades_tdc_bundle_inst_N_50_i_i: Std_logic;
+    signal hades_tdc_bundle_inst_N_46_i: Std_logic;
+    signal hades_discard_c: Std_logic;
+    signal hades_tdc_bundle_inst_hit_out_i_6_2: Std_logic;
+    signal trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0: Std_logic;
+    signal discard_c: Std_logic;
+    signal fifo_colector_inst_iterator_0: Std_logic;
+    signal fifo_colector_inst_in_empty_pmux_i: Std_logic;
+    signal fifo_colector_inst_iterator_1: Std_logic;
+    signal fifo_colector_inst_buffer_wr_enable: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_8: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_0: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_0: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_16: Std_logic;
+    signal fifo_colector_inst_data_buffer_0: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_9: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_1: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_1: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_17: Std_logic;
+    signal fifo_colector_inst_data_buffer_1: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_2: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_10: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_2: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_18: Std_logic;
+    signal fifo_colector_inst_data_buffer_2: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_3: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_11: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_3: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_19: Std_logic;
+    signal fifo_colector_inst_data_buffer_3: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_4: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_12: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_4: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_20: Std_logic;
+    signal fifo_colector_inst_data_buffer_4: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_13: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_5: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_5: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_21: Std_logic;
+    signal fifo_colector_inst_data_buffer_5: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_14: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_6: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_6: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_22: Std_logic;
+    signal fifo_colector_inst_data_buffer_6: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_7: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_15: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_7: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_23: Std_logic;
+    signal fifo_colector_inst_data_buffer_7: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_9: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_17: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_16: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_8: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_9: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_8: Std_logic;
+    signal fifo_colector_inst_iterator_RNI7U5I_1: Std_logic;
+    signal fifo_colector_inst_data_buffer_8: Std_logic;
+    signal fifo_colector_inst_data_buffer_9: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_19: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_11: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_10: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_18: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_11: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_10: Std_logic;
+    signal fifo_colector_inst_data_buffer_10: Std_logic;
+    signal fifo_colector_inst_data_buffer_11: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_21: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_13: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_20: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_12: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_13: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_12: Std_logic;
+    signal fifo_colector_inst_data_buffer_12: Std_logic;
+    signal fifo_colector_inst_data_buffer_13: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_23: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_15: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_22: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_14: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_15: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_14: Std_logic;
+    signal fifo_colector_inst_data_buffer_14: Std_logic;
+    signal fifo_colector_inst_data_buffer_15: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_1: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_17: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_16: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_0: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_17: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_16: Std_logic;
+    signal fifo_colector_inst_data_buffer_16: Std_logic;
+    signal fifo_colector_inst_data_buffer_17: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_3: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_19: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_18: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_2: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_19: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_18: Std_logic;
+    signal fifo_colector_inst_data_buffer_18: Std_logic;
+    signal fifo_colector_inst_data_buffer_19: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_5: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_21: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_20: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_4: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_21: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_20: Std_logic;
+    signal fifo_colector_inst_data_buffer_20: Std_logic;
+    signal fifo_colector_inst_data_buffer_21: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_7: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_23: Std_logic;
+    signal genblk1_0_un1_tdc_channel_fifo_out_inst_22: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_6: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_23: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_22: Std_logic;
+    signal fifo_colector_inst_data_buffer_22: Std_logic;
+    signal fifo_colector_inst_data_buffer_23: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_9: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_1: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_8: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_0: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_25: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_24: Std_logic;
+    signal fifo_colector_inst_data_buffer_24: Std_logic;
+    signal fifo_colector_inst_data_buffer_25: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_11: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_3: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_2: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_10: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_27: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_26: Std_logic;
+    signal fifo_colector_inst_data_buffer_26: Std_logic;
+    signal fifo_colector_inst_data_buffer_27: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_13: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_5: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_4: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_12: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_29: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_28: Std_logic;
+    signal fifo_colector_inst_data_buffer_28: Std_logic;
+    signal fifo_colector_inst_data_buffer_29: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_15: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_7: Std_logic;
+    signal genblk1_1_un1_tdc_channel_fifo_out_inst_6: Std_logic;
+    signal genblk1_2_un1_tdc_channel_fifo_out_inst_14: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_31: Std_logic;
+    signal fifo_colector_inst_data_buffer_3_30: Std_logic;
+    signal fifo_colector_inst_data_buffer_30: Std_logic;
+    signal fifo_colector_inst_data_buffer_31: Std_logic;
+    signal fifo_colector_inst_data_buffer_32: Std_logic;
+    signal fifo_colector_inst_data_buffer_33: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gdata_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w20: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w21: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w22: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w23: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w24: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w25: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w26: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w27: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w28: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_gcount_w29: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_rptr_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gdata_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r9: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r20: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r21: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r22: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r23: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r24: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r25: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r26: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r27: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r28: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_gcount_r29: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_2: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_3: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_4: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_5: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_6: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_7: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_8: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_wptr_9: Std_logic;
+    signal fifo_colector_inst_un5_in_read_enable: Std_logic;
+    signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1: Std_logic;
+    signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2: Std_logic;
+    signal fifo_rden_c: Std_logic;
+    signal burst_c: Std_logic;
+    signal trb_adapter_inst_buf_rden4: Std_logic;
+    signal fifo_read_1: Std_logic;
+    signal fifo_read_0: Std_logic;
+    signal fifo_colector_inst_fb_0_1: Std_logic;
+    signal fifo_colector_inst_fb_0: Std_logic;
+    signal fifo_colector_inst_in_empty_pmux: Std_logic;
+    signal fifo_read_2: Std_logic;
+    signal fifo_colector_inst_fb_0_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_decoder_valid: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fb_0: Std_logic;
+    signal trig_c_i_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic;
+    signal pll_clks_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic;
+    signal pll_clks_1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic;
+    signal pll_clks_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_decoder_valid: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fb_0: Std_logic;
+    signal trig_c_i_1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_decoder_valid: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fb_0: Std_logic;
+    signal trig_c_i_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic;
+    signal hades_tdc_bundle_inst_buf_finished5: Std_logic;
+    signal hades_buf_finished_c: Std_logic;
+    signal hades_tdc_bundle_inst_N_80: Std_logic;
+    signal hades_buf_release_c: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0: Std_logic;
+    signal hades_dbg2_coarse_c_2: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2: Std_logic;
+    signal hades_dbg2_coarse_c_4: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_4: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_3: Std_logic;
+    signal un1_hit_i_2_0_a2: Std_logic;
+    signal hades_dbg2_out_c_4: Std_logic;
+    signal hades_dbg2_out_c_5: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_6: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_5: Std_logic;
+    signal hades_dbg2_out_c_6: Std_logic;
+    signal hades_dbg2_out_c_7: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_8: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_7: Std_logic;
+    signal hades_dbg2_out_c_8: Std_logic;
+    signal hades_dbg2_out_c_9: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_10: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_9: Std_logic;
+    signal hades_dbg2_out_c_10: Std_logic;
+    signal hades_dbg2_out_c_11: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_11: Std_logic;
+    signal hades_dbg2_out_c_12: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97: Std_logic;
+    signal hades_invalid_dl_c_3: Std_logic;
+    signal hades_invalid_dl_c_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9: Std_logic;
+    signal hades_hit_valid_c_1: Std_logic;
+    signal hades_drop_cmp_buf_valid_c: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i: Std_logic;
+    signal hades_hit_valid_c_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_valid: Std_logic;
+    signal hades_tdc_bundle_inst_hit_i_0: Std_logic;
+    signal hades_tdc_bundle_inst_N_246_i: Std_logic;
+    signal hades_tdc_bundle_inst_hit_i_1: Std_logic;
+    signal hades_tdc_bundle_inst_N_44: Std_logic;
+    signal hades_tdc_bundle_inst_N_243_i: Std_logic;
+    signal hades_hit_valid_c_2: Std_logic;
+    signal hades_tdc_bundle_inst_N_245_i: Std_logic;
+    signal hades_hit_valid_c_3: Std_logic;
+    signal hades_tdc_bundle_inst_N_244_i: Std_logic;
+    signal hades_invalid_dl_c_1: Std_logic;
+    signal hades_invalid_dl_c_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0: Std_logic;
+    signal hades_offset_valid_c: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_12: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_13: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_14: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_15: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_16: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_17: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_18: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_19: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_20: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_21: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_22: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11: Std_logic;
+    signal hades_tdc_bundle_inst_hades_raw_out_23: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal: Std_logic;
+    signal hades_lvl1_c_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0: Std_logic;
+    signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid: Std_logic;
+    signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal: Std_logic;
+    signal hades_trig_c_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7: Std_logic;
+    signal hades_trig_c: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7: Std_logic;
+    signal hades_tdc_bundle_inst_SUM1_0_0: Std_logic;
+    signal hades_tdc_bundle_inst_N_59_i: Std_logic;
+
+      signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5: Std_logic;
+    signal hades_window_end_c: Std_logic;
+    signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0: Std_logic;
+    signal trb_adapter_inst_buf_rden_prev: Std_logic;
+    signal finished_c: Std_logic;
+    signal trb_adapter_inst_finished_prev: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic;
+
+      signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic;
+
+      signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic;
+
+      signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1: Std_logic;
+    signal N_248_i: Std_logic;
+    signal hades_tdc_bundle_inst_N_45: Std_logic;
+    signal hades_tdc_bundle_inst_N_66: Std_logic;
+    signal hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0: Std_logic;
+    signal fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1: Std_logic;
+    signal fifo_colector_inst_in_empty_pmux_0: Std_logic;
+    signal hades_tdc_bundle_inst_N_90: Std_logic;
+    signal hades_tdc_bundle_inst_buf_out12: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0: Std_logic;
+    signal hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa: Std_logic;
+    signal genblk1_2_tdc_channel_fifo_out_inst_fifo_wren: Std_logic;
+    signal genblk1_1_tdc_channel_fifo_out_inst_fifo_wren: Std_logic;
+    signal genblk1_0_tdc_channel_fifo_out_inst_fifo_wren: Std_logic;
+    signal LVL1_TRG_DATA_VALI_IN_rising_c: Std_logic;
+    signal release_out_c: Std_logic;
+    signal valid_fast_RNI999V: Std_logic;
+    signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0: Std_logic;
+    signal reset_dl_1: Std_logic;
+    signal pll0inst_GND: Std_logic;
+    signal hades_lvl1_c: Std_logic;
+    signal trig_c_0: Std_logic;
+    signal trig_c_1: Std_logic;
+    signal trig_c_2: Std_logic;
+    signal FEE_DATA_OUT_c_0: Std_logic;
+    signal clk_c: Std_logic;
+    signal hades_dbg2_out_c_28: Std_logic;
+    signal hades_dbg2_out_c_27: Std_logic;
+    signal hades_dbg2_out_c_26: Std_logic;
+    signal hades_dbg2_out_c_25: Std_logic;
+    signal hades_dbg2_out_c_24: Std_logic;
+    signal hades_dbg2_out_c_23: Std_logic;
+    signal hades_dbg2_out_c_22: Std_logic;
+    signal hades_dbg2_out_c_21: Std_logic;
+    signal hades_dbg2_out_c_20: Std_logic;
+    signal hades_dbg2_out_c_18: Std_logic;
+    signal hades_dbg2_out_c_17: Std_logic;
+    signal hades_dbg2_out_c_16: Std_logic;
+    signal hades_dbg2_out_c_2: Std_logic;
+    signal hades_dbg2_out_c_1: Std_logic;
+    signal hades_dbg2_out_c_0: Std_logic;
+    signal hades_buf_drop_c_1: Std_logic;
+    signal hades_buf_out_valid_c: Std_logic;
+    signal hades_offset_c_8: Std_logic;
+    signal hades_offset_c_7: Std_logic;
+    signal hades_offset_c_6: Std_logic;
+    signal hades_offset_c_5: Std_logic;
+    signal hades_offset_c_4: Std_logic;
+    signal hades_offset_c_3: Std_logic;
+    signal hades_offset_c_2: Std_logic;
+    signal hades_offset_c_1: Std_logic;
+    signal hades_offset_c_0: Std_logic;
+    signal hades_lvl1_invalid_c: Std_logic;
+    signal hades_raw_out_valid_c: Std_logic;
+    signal FEE_TRG_RELEASE_OUT_c: Std_logic;
+    signal FEE_DATAFINISHED_OUT_c: Std_logic;
+    signal FEE_DATA_WRITE_OUT_c: Std_logic;
+    signal FEE_DATA_OUT_c_31: Std_logic;
+    signal FEE_DATA_OUT_c_30: Std_logic;
+    signal FEE_DATA_OUT_c_29: Std_logic;
+    signal FEE_DATA_OUT_c_28: Std_logic;
+    signal FEE_DATA_OUT_c_27: Std_logic;
+    signal FEE_DATA_OUT_c_26: Std_logic;
+    signal FEE_DATA_OUT_c_25: Std_logic;
+    signal FEE_DATA_OUT_c_24: Std_logic;
+    signal FEE_DATA_OUT_c_23: Std_logic;
+    signal FEE_DATA_OUT_c_22: Std_logic;
+    signal FEE_DATA_OUT_c_21: Std_logic;
+    signal FEE_DATA_OUT_c_20: Std_logic;
+    signal FEE_DATA_OUT_c_19: Std_logic;
+    signal FEE_DATA_OUT_c_18: Std_logic;
+    signal FEE_DATA_OUT_c_17: Std_logic;
+    signal FEE_DATA_OUT_c_16: Std_logic;
+    signal FEE_DATA_OUT_c_15: Std_logic;
+    signal FEE_DATA_OUT_c_14: Std_logic;
+    signal FEE_DATA_OUT_c_13: Std_logic;
+    signal FEE_DATA_OUT_c_12: Std_logic;
+    signal FEE_DATA_OUT_c_11: Std_logic;
+    signal FEE_DATA_OUT_c_10: Std_logic;
+    signal FEE_DATA_OUT_c_9: Std_logic;
+    signal FEE_DATA_OUT_c_8: Std_logic;
+    signal FEE_DATA_OUT_c_7: Std_logic;
+    signal FEE_DATA_OUT_c_6: Std_logic;
+    signal FEE_DATA_OUT_c_5: Std_logic;
+    signal FEE_DATA_OUT_c_4: Std_logic;
+    signal FEE_DATA_OUT_c_3: Std_logic;
+    signal FEE_DATA_OUT_c_2: Std_logic;
+    signal FEE_DATA_OUT_c_1: Std_logic;
+    signal LVL1_INVALID_TRG_IN_c: Std_logic;
+    signal LVL1_TRG_DATA_VALID_IN_c: Std_logic;
+    signal reset_dc_c: Std_logic;
+    signal VCCI: Std_logic;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2
+      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7
+      port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28
+      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30
+      port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57
+      port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58
+      port (FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60
+      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_78
+      port (FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_79
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_80
+      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_81
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_82
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_83
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_84
+      port (FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_85
+      port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_86
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_87
+      port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_88
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_89
+      port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_90
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_91
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_92
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_93
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_94
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_95
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_96
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_97
+      port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_98
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_99
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_100
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_101
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_102
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_103
+      port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_104
+      port (FCI: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108
+      port (FCI: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112
+      port (FCI: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117
+      port (B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_118
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_119
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_120
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_121
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_122
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_123
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_124
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_125
+      port (B1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_126
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_127
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_128
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_129
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_130
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_131
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_132
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_133
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_134
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_135
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_136
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_137
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_138
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_139
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_140
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_141
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_142
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_143
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_144
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_145
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_146
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_147
+      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_148
+      port (D1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_149
+      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_150
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_151
+      port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_152
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_153
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_154
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_155
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_156
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_157
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_158
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_159
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_160
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_161
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_162
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_163
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_164
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_165
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_166
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_167
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_168
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_169
+      port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_170
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_171
+      port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_172
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_173
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_174
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_175
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_176
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_177
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_178
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_179
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_180
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_181
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_182
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_183
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_184
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_185
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_186
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_187
+      port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_188
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_189
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_190
+      port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207
+      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208
+      port (D1: in Std_logic; B1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209
+      port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210
+      port (C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226
+      port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228
+      port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229
+      port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230
+      port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_SLICE_246
+      port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290
+      port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310
+      port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_SLICE_326
+      port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366
+      port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368
+      port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370
+      port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386
+      port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390
+      port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_SLICE_406
+      port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_432
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_433
+      port (M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_434
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_435
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_436
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_437
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_438
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_439
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_440
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_441
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_442
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_443
+      port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_445
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_446
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_447
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_448
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_449
+      port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_450
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_451
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_452
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_453
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_454
+      port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_455
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_456
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_457
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_458
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_459
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_460
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463
+      port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473
+      port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527
+      port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528
+      port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541
+      port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_628
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_631
+      port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_632
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_633
+      port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; OFX0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_648
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_649
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_653
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_654
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_673
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_674
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_675
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_676
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_677
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_678
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_679
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_680
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_681
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_683
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_691
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_692
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_693
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_698
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_701
+      port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_702
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_703
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708
+      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_710
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_SLICE_711
+      port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712
+      port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713
+      port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_SLICE_714
+      port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715
+      port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716
+      port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_SLICE_717
+      port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718
+      port (B0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719
+      port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_720
+      port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_SLICE_721
+      port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+    end component;
+    component fifo_colector_inst_SLICE_722
+      port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_723
+      port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+    end component;
+    component trb_adapter_inst_SLICE_724
+      port (B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725
+      port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726
+      port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729
+      port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730
+      port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731
+      port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+
+      component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734
+      port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737
+      port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739
+      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component SLICE_740
+      port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component hades_tdc_bundle_inst_SLICE_741
+      port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component pll0inst_SLICE_742
+      port (F0: out Std_logic);
+    end component;
+    component SLICE_743
+      port (D0: in Std_logic; F0: out Std_logic);
+    end component;
+    component SLICE_744
+      port (D0: in Std_logic; F0: out Std_logic);
+    end component;
+    component SLICE_745
+      port (D0: in Std_logic; F0: out Std_logic);
+    end component;
+    component SLICE_746
+      port (D0: in Std_logic; F0: out Std_logic);
+    end component;
+    component SLICE_747
+      port (A0: in Std_logic; F0: out Std_logic);
+    end component;
+    component hades_raw_valid_vect_0_B
+      port (hadesrawvalidvect0: out Std_logic);
+    end component;
+    component fifo_data_out_0_B
+      port (PADDO: in Std_logic; fifodataout0: out Std_logic);
+    end component;
+    component clkB
+      port (PADDI: out Std_logic; clkS: in Std_logic);
+    end component;
+    component hades_drop_cmp_buf_validB
+      port (PADDO: in Std_logic; hadesdropcmpbufvalid: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_11_B
+      port (hadesdropcmpbufcoarse11: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_10_B
+      port (hadesdropcmpbufcoarse10: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_9_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse9: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_8_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse8: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_7_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse7: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_6_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse6: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_5_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse5: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_4_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse4: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_3_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse3: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_2_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse2: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_1_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse1: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_coarse_0_B
+      port (PADDO: in Std_logic; hadesdropcmpbufcoarse0: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_11_B
+      port (hadesdropcmpbuf11: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_10_B
+      port (hadesdropcmpbuf10: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_9_B
+      port (hadesdropcmpbuf9: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_8_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf8: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_7_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf7: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_6_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf6: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_5_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf5: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_4_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf4: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_3_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf3: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_2_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf2: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_1_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf1: out Std_logic);
+    end component;
+    component hades_drop_cmp_buf_0_B
+      port (PADDO: in Std_logic; hadesdropcmpbuf0: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_8_B
+      port (PADDO: in Std_logic; hadesdbg2coarse8: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_7_B
+      port (PADDO: in Std_logic; hadesdbg2coarse7: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_6_B
+      port (PADDO: in Std_logic; hadesdbg2coarse6: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_5_B
+      port (PADDO: in Std_logic; hadesdbg2coarse5: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_4_B
+      port (PADDO: in Std_logic; hadesdbg2coarse4: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_3_B
+      port (PADDO: in Std_logic; hadesdbg2coarse3: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_2_B
+      port (PADDO: in Std_logic; hadesdbg2coarse2: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_1_B
+      port (PADDO: in Std_logic; hadesdbg2coarse1: out Std_logic);
+    end component;
+    component hades_dbg2_coarse_0_B
+      port (PADDO: in Std_logic; hadesdbg2coarse0: out Std_logic);
+    end component;
+    component hades_dbg2_out_31_B
+      port (hadesdbg2out31: out Std_logic);
+    end component;
+    component hades_dbg2_out_30_B
+      port (hadesdbg2out30: out Std_logic);
+    end component;
+    component hades_dbg2_out_29_B
+      port (hadesdbg2out29: out Std_logic);
+    end component;
+    component hades_dbg2_out_28_B
+      port (IOLDO: in Std_logic; hadesdbg2out28: out Std_logic);
+    end component;
+    component hades_dbg2_out_28_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_27_B
+      port (IOLDO: in Std_logic; hadesdbg2out27: out Std_logic);
+    end component;
+    component hades_dbg2_out_27_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_26_B
+      port (IOLDO: in Std_logic; hadesdbg2out26: out Std_logic);
+    end component;
+    component hades_dbg2_out_26_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_25_B
+      port (IOLDO: in Std_logic; hadesdbg2out25: out Std_logic);
+    end component;
+    component hades_dbg2_out_25_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_24_B
+      port (IOLDO: in Std_logic; hadesdbg2out24: out Std_logic);
+    end component;
+    component hades_dbg2_out_24_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_23_B
+      port (IOLDO: in Std_logic; hadesdbg2out23: out Std_logic);
+    end component;
+    component hades_dbg2_out_23_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_22_B
+      port (IOLDO: in Std_logic; hadesdbg2out22: out Std_logic);
+    end component;
+    component hades_dbg2_out_22_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_21_B
+      port (IOLDO: in Std_logic; hadesdbg2out21: out Std_logic);
+    end component;
+    component hades_dbg2_out_21_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_20_B
+      port (IOLDO: in Std_logic; hadesdbg2out20: out Std_logic);
+    end component;
+    component hades_dbg2_out_20_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_19_B
+      port (hadesdbg2out19: out Std_logic);
+    end component;
+    component hades_dbg2_out_18_B
+      port (IOLDO: in Std_logic; hadesdbg2out18: out Std_logic);
+    end component;
+    component hades_dbg2_out_18_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_17_B
+      port (IOLDO: in Std_logic; hadesdbg2out17: out Std_logic);
+    end component;
+    component hades_dbg2_out_17_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_16_B
+      port (IOLDO: in Std_logic; hadesdbg2out16: out Std_logic);
+    end component;
+    component hades_dbg2_out_16_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_15_B
+      port (hadesdbg2out15: out Std_logic);
+    end component;
+    component hades_dbg2_out_14_B
+      port (hadesdbg2out14: out Std_logic);
+    end component;
+    component hades_dbg2_out_13_B
+      port (hadesdbg2out13: out Std_logic);
+    end component;
+    component hades_dbg2_out_12_B
+      port (PADDO: in Std_logic; hadesdbg2out12: out Std_logic);
+    end component;
+    component hades_dbg2_out_11_B
+      port (PADDO: in Std_logic; hadesdbg2out11: out Std_logic);
+    end component;
+    component hades_dbg2_out_10_B
+      port (PADDO: in Std_logic; hadesdbg2out10: out Std_logic);
+    end component;
+    component hades_dbg2_out_9_B
+      port (PADDO: in Std_logic; hadesdbg2out9: out Std_logic);
+    end component;
+    component hades_dbg2_out_8_B
+      port (PADDO: in Std_logic; hadesdbg2out8: out Std_logic);
+    end component;
+    component hades_dbg2_out_7_B
+      port (PADDO: in Std_logic; hadesdbg2out7: out Std_logic);
+    end component;
+    component hades_dbg2_out_6_B
+      port (PADDO: in Std_logic; hadesdbg2out6: out Std_logic);
+    end component;
+    component hades_dbg2_out_5_B
+      port (PADDO: in Std_logic; hadesdbg2out5: out Std_logic);
+    end component;
+    component hades_dbg2_out_4_B
+      port (PADDO: in Std_logic; hadesdbg2out4: out Std_logic);
+    end component;
+    component hades_dbg2_out_3_B
+      port (hadesdbg2out3: out Std_logic);
+    end component;
+    component hades_dbg2_out_2_B
+      port (IOLDO: in Std_logic; hadesdbg2out2: out Std_logic);
+    end component;
+    component hades_dbg2_out_2_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_1_B
+      port (IOLDO: in Std_logic; hadesdbg2out1: out Std_logic);
+    end component;
+    component hades_dbg2_out_1_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_dbg2_out_0_B
+      port (IOLDO: in Std_logic; hadesdbg2out0: out Std_logic);
+    end component;
+    component hades_dbg2_out_0_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_buf_drop_3_B
+      port (hadesbufdrop3: out Std_logic);
+    end component;
+    component hades_buf_drop_2_B
+      port (hadesbufdrop2: out Std_logic);
+    end component;
+    component hades_buf_drop_1_B
+      port (IOLDO: in Std_logic; hadesbufdrop1: out Std_logic);
+    end component;
+    component hades_buf_drop_1_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_buf_drop_0_B
+      port (hadesbufdrop0: out Std_logic);
+    end component;
+    component hades_invalid_dl_3_B
+      port (PADDO: in Std_logic; hadesinvaliddl3: out Std_logic);
+    end component;
+    component hades_invalid_dl_2_B
+      port (PADDO: in Std_logic; hadesinvaliddl2: out Std_logic);
+    end component;
+    component hades_invalid_dl_1_B
+      port (PADDO: in Std_logic; hadesinvaliddl1: out Std_logic);
+    end component;
+    component hades_invalid_dl_0_B
+      port (PADDO: in Std_logic; hadesinvaliddl0: out Std_logic);
+    end component;
+    component hades_discardB
+      port (PADDO: in Std_logic; hadesdiscard: out Std_logic);
+    end component;
+    component hades_hit_valid_3_B
+      port (PADDO: in Std_logic; hadeshitvalid3: out Std_logic);
+    end component;
+    component hades_hit_valid_2_B
+      port (PADDO: in Std_logic; hadeshitvalid2: out Std_logic);
+    end component;
+    component hades_hit_valid_1_B
+      port (PADDO: in Std_logic; hadeshitvalid1: out Std_logic);
+    end component;
+    component hades_hit_valid_0_B
+      port (PADDO: in Std_logic; hadeshitvalid0: out Std_logic);
+    end component;
+    component hades_hit_out_i_3_B
+      port (PADDO: in Std_logic; hadeshitouti3: out Std_logic);
+    end component;
+    component hades_hit_out_i_2_B
+      port (PADDO: in Std_logic; hadeshitouti2: out Std_logic);
+    end component;
+    component hades_hit_out_i_1_B
+      port (PADDO: in Std_logic; hadeshitouti1: out Std_logic);
+    end component;
+    component hades_hit_out_i_0_B
+      port (PADDO: in Std_logic; hadeshitouti0: out Std_logic);
+    end component;
+    component hades_buf_finishedB
+      port (PADDO: in Std_logic; hadesbuffinished: out Std_logic);
+    end component;
+    component hades_buf_releaseB
+      port (PADDO: in Std_logic; hadesbufrelease: out Std_logic);
+    end component;
+    component hades_buf_out_validB
+      port (IOLDO: in Std_logic; hadesbufoutvalid: out Std_logic);
+    end component;
+    component hades_buf_out_valid_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component hades_window_endB
+      port (PADDO: in Std_logic; hadeswindowend: out Std_logic);
+    end component;
+    component hades_offset_validB
+      port (PADDO: in Std_logic; hadesoffsetvalid: out Std_logic);
+    end component;
+    component hades_offset_8_B
+      port (IOLDO: in Std_logic; hadesoffset8: out Std_logic);
+    end component;
+    component hades_offset_8_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_7_B
+      port (IOLDO: in Std_logic; hadesoffset7: out Std_logic);
+    end component;
+    component hades_offset_7_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_6_B
+      port (IOLDO: in Std_logic; hadesoffset6: out Std_logic);
+    end component;
+    component hades_offset_6_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_5_B
+      port (IOLDO: in Std_logic; hadesoffset5: out Std_logic);
+    end component;
+    component hades_offset_5_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_4_B
+      port (IOLDO: in Std_logic; hadesoffset4: out Std_logic);
+    end component;
+    component hades_offset_4_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_3_B
+      port (IOLDO: in Std_logic; hadesoffset3: out Std_logic);
+    end component;
+    component hades_offset_3_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_2_B
+      port (IOLDO: in Std_logic; hadesoffset2: out Std_logic);
+    end component;
+    component hades_offset_2_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_1_B
+      port (IOLDO: in Std_logic; hadesoffset1: out Std_logic);
+    end component;
+    component hades_offset_1_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_offset_0_B
+      port (IOLDO: in Std_logic; hadesoffset0: out Std_logic);
+    end component;
+    component hades_offset_0_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_lvl1_invalidB
+      port (PADDI: out Std_logic; hadeslvl1invalid: in Std_logic);
+    end component;
+    component hades_lvl1_invalid_MGIOL
+      port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+    end component;
+    component hades_lvl1B
+      port (PADDI: out Std_logic; hadeslvl1: in Std_logic);
+    end component;
+    component hades_lvl1_MGIOL
+      port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+    end component;
+    component hades_raw_valid_vect_1_B
+      port (hadesrawvalidvect1: out Std_logic);
+    end component;
+    component hades_raw_out_validB
+      port (IOLDO: in Std_logic; hadesrawoutvalid: out Std_logic);
+    end component;
+    component hades_raw_out_valid_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CLK: in Std_logic);
+    end component;
+    component hades_trigB
+      port (PADDI: out Std_logic; hadestrig: in Std_logic);
+    end component;
+    component release_outB
+      port (PADDO: in Std_logic; releaseout: out Std_logic);
+    end component;
+    component finishedB
+      port (PADDO: in Std_logic; finishedS: out Std_logic);
+    end component;
+    component last_buf_emptyB
+      port (PADDO: in Std_logic; lastbufempty: out Std_logic);
+    end component;
+    component discardB
+      port (PADDO: in Std_logic; discardS: out Std_logic);
+    end component;
+    component burstB
+      port (PADDO: in Std_logic; burstS: out Std_logic);
+    end component;
+    component LVL1_TRG_DATA_VALI_IN_risingB
+      port (PADDO: in Std_logic; LVL1TRGDATAVALIINrising: out Std_logic);
+    end component;
+    component FEE_TRG_RELEASE_OUTB
+      port (IOLDO: in Std_logic; FEETRGRELEASEOUT: out Std_logic);
+    end component;
+    component FEE_TRG_RELEASE_OUT_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component FEE_DATAFINISHED_OUTB
+      port (IOLDO: in Std_logic; FEEDATAFINISHEDOUT: out Std_logic);
+    end component;
+    component FEE_DATAFINISHED_OUT_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component FEE_DATA_WRITE_OUTB
+      port (IOLDO: in Std_logic; FEEDATAWRITEOUT: out Std_logic);
+    end component;
+    component FEE_DATA_WRITE_OUT_MGIOL
+      port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic);
+    end component;
+    component FEE_DATA_OUT_31_B
+      port (PADDO: in Std_logic; FEEDATAOUT31: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_30_B
+      port (PADDO: in Std_logic; FEEDATAOUT30: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_29_B
+      port (PADDO: in Std_logic; FEEDATAOUT29: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_28_B
+      port (PADDO: in Std_logic; FEEDATAOUT28: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_27_B
+      port (PADDO: in Std_logic; FEEDATAOUT27: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_26_B
+      port (PADDO: in Std_logic; FEEDATAOUT26: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_25_B
+      port (PADDO: in Std_logic; FEEDATAOUT25: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_24_B
+      port (PADDO: in Std_logic; FEEDATAOUT24: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_23_B
+      port (PADDO: in Std_logic; FEEDATAOUT23: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_22_B
+      port (PADDO: in Std_logic; FEEDATAOUT22: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_21_B
+      port (PADDO: in Std_logic; FEEDATAOUT21: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_20_B
+      port (PADDO: in Std_logic; FEEDATAOUT20: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_19_B
+      port (PADDO: in Std_logic; FEEDATAOUT19: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_18_B
+      port (PADDO: in Std_logic; FEEDATAOUT18: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_17_B
+      port (PADDO: in Std_logic; FEEDATAOUT17: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_16_B
+      port (PADDO: in Std_logic; FEEDATAOUT16: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_15_B
+      port (PADDO: in Std_logic; FEEDATAOUT15: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_14_B
+      port (PADDO: in Std_logic; FEEDATAOUT14: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_13_B
+      port (PADDO: in Std_logic; FEEDATAOUT13: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_12_B
+      port (PADDO: in Std_logic; FEEDATAOUT12: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_11_B
+      port (PADDO: in Std_logic; FEEDATAOUT11: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_10_B
+      port (PADDO: in Std_logic; FEEDATAOUT10: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_9_B
+      port (PADDO: in Std_logic; FEEDATAOUT9: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_8_B
+      port (PADDO: in Std_logic; FEEDATAOUT8: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_7_B
+      port (PADDO: in Std_logic; FEEDATAOUT7: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_6_B
+      port (PADDO: in Std_logic; FEEDATAOUT6: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_5_B
+      port (PADDO: in Std_logic; FEEDATAOUT5: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_4_B
+      port (PADDO: in Std_logic; FEEDATAOUT4: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_3_B
+      port (PADDO: in Std_logic; FEEDATAOUT3: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_2_B
+      port (PADDO: in Std_logic; FEEDATAOUT2: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_1_B
+      port (PADDO: in Std_logic; FEEDATAOUT1: out Std_logic);
+    end component;
+    component FEE_DATA_OUT_0_B
+      port (PADDO: in Std_logic; FEEDATAOUT0: out Std_logic);
+    end component;
+    component LVL1_INVALID_TRG_INB
+      port (PADDI: out Std_logic; LVL1INVALIDTRGIN: in Std_logic);
+    end component;
+    component LVL1_INVALID_TRG_IN_MGIOL
+      port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+    end component;
+    component LVL1_TRG_DATA_VALID_INB
+      port (PADDI: out Std_logic; LVL1TRGDATAVALIDIN: in Std_logic);
+    end component;
+    component LVL1_TRG_DATA_VALID_IN_MGIOL
+      port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+    end component;
+    component fifo_empty1B
+      port (PADDO: in Std_logic; fifoempty1: out Std_logic);
+    end component;
+    component fifo_rdenB
+      port (PADDO: in Std_logic; fiforden: out Std_logic);
+    end component;
+    component fifo_data_out_31_B
+      port (PADDO: in Std_logic; fifodataout31: out Std_logic);
+    end component;
+    component fifo_data_out_30_B
+      port (PADDO: in Std_logic; fifodataout30: out Std_logic);
+    end component;
+    component fifo_data_out_29_B
+      port (PADDO: in Std_logic; fifodataout29: out Std_logic);
+    end component;
+    component fifo_data_out_28_B
+      port (PADDO: in Std_logic; fifodataout28: out Std_logic);
+    end component;
+    component fifo_data_out_27_B
+      port (PADDO: in Std_logic; fifodataout27: out Std_logic);
+    end component;
+    component fifo_data_out_26_B
+      port (PADDO: in Std_logic; fifodataout26: out Std_logic);
+    end component;
+    component fifo_data_out_25_B
+      port (PADDO: in Std_logic; fifodataout25: out Std_logic);
+    end component;
+    component fifo_data_out_24_B
+      port (PADDO: in Std_logic; fifodataout24: out Std_logic);
+    end component;
+    component fifo_data_out_23_B
+      port (PADDO: in Std_logic; fifodataout23: out Std_logic);
+    end component;
+    component fifo_data_out_22_B
+      port (PADDO: in Std_logic; fifodataout22: out Std_logic);
+    end component;
+    component fifo_data_out_21_B
+      port (PADDO: in Std_logic; fifodataout21: out Std_logic);
+    end component;
+    component fifo_data_out_20_B
+      port (PADDO: in Std_logic; fifodataout20: out Std_logic);
+    end component;
+    component fifo_data_out_19_B
+      port (PADDO: in Std_logic; fifodataout19: out Std_logic);
+    end component;
+    component fifo_data_out_18_B
+      port (PADDO: in Std_logic; fifodataout18: out Std_logic);
+    end component;
+    component fifo_data_out_17_B
+      port (PADDO: in Std_logic; fifodataout17: out Std_logic);
+    end component;
+    component fifo_data_out_16_B
+      port (PADDO: in Std_logic; fifodataout16: out Std_logic);
+    end component;
+    component fifo_data_out_15_B
+      port (PADDO: in Std_logic; fifodataout15: out Std_logic);
+    end component;
+    component fifo_data_out_14_B
+      port (PADDO: in Std_logic; fifodataout14: out Std_logic);
+    end component;
+    component fifo_data_out_13_B
+      port (PADDO: in Std_logic; fifodataout13: out Std_logic);
+    end component;
+    component fifo_data_out_12_B
+      port (PADDO: in Std_logic; fifodataout12: out Std_logic);
+    end component;
+    component fifo_data_out_11_B
+      port (PADDO: in Std_logic; fifodataout11: out Std_logic);
+    end component;
+    component fifo_data_out_10_B
+      port (PADDO: in Std_logic; fifodataout10: out Std_logic);
+    end component;
+    component fifo_data_out_9_B
+      port (PADDO: in Std_logic; fifodataout9: out Std_logic);
+    end component;
+    component fifo_data_out_8_B
+      port (PADDO: in Std_logic; fifodataout8: out Std_logic);
+    end component;
+    component fifo_data_out_7_B
+      port (PADDO: in Std_logic; fifodataout7: out Std_logic);
+    end component;
+    component fifo_data_out_6_B
+      port (PADDO: in Std_logic; fifodataout6: out Std_logic);
+    end component;
+    component fifo_data_out_5_B
+      port (PADDO: in Std_logic; fifodataout5: out Std_logic);
+    end component;
+    component fifo_data_out_4_B
+      port (PADDO: in Std_logic; fifodataout4: out Std_logic);
+    end component;
+    component fifo_data_out_3_B
+      port (PADDO: in Std_logic; fifodataout3: out Std_logic);
+    end component;
+    component fifo_data_out_2_B
+      port (PADDO: in Std_logic; fifodataout2: out Std_logic);
+    end component;
+    component fifo_data_out_1_B
+      port (PADDO: in Std_logic; fifodataout1: out Std_logic);
+    end component;
+    component trig_2_B
+      port (PADDI: out Std_logic; trig2: in Std_logic);
+    end component;
+    component trig_1_B
+      port (PADDI: out Std_logic; trig1: in Std_logic);
+    end component;
+    component trig_0_B
+      port (PADDI: out Std_logic; trig0: in Std_logic);
+    end component;
+    component reset_dcB
+      port (PADDI: out Std_logic; resetdc: in Std_logic);
+    end component;
+    component reset_dc_MGIOL
+      port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic);
+    end component;
+    component rd_clkB
+      port (PADDI: out Std_logic; rdclk: in Std_logic);
+    end component;
+    component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+            DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+            ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+            ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+            ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+            DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+            DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+            DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+            DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+            DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+            DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+            CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+            CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+            DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+            DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+            ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+            ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+            ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+            DIB9: in Std_logic);
+    end component;
+    component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+            DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+            ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+            ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+            ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+            DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+            DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+            DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+            DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+            DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+            DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+            CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+            CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+            DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+            DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+            ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+            ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+            ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+            DIB9: in Std_logic);
+    end component;
+    component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+            DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; 
+            ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; 
+            ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; 
+            ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; 
+            DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; 
+            DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; 
+            DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; 
+            DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; 
+            DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; 
+            DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; 
+            CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; 
+            CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; 
+            DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; 
+            DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+            ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+            ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+            ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; 
+            DIB9: in Std_logic);
+    end component;
+    component fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1
+      port (DIA17: in Std_logic; DIA16: in Std_logic; DIA15: in Std_logic; 
+            DIA14: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; 
+            DIA11: in Std_logic; DIA10: in Std_logic; DIA9: in Std_logic; 
+            DIA8: in Std_logic; DIA7: in Std_logic; DIA6: in Std_logic; 
+            DIA5: in Std_logic; DIA4: in Std_logic; DIA3: in Std_logic; 
+            DIA2: in Std_logic; DIA1: in Std_logic; DIA0: in Std_logic; 
+            ADA13: in Std_logic; ADA12: in Std_logic; ADA11: in Std_logic; 
+            ADA10: in Std_logic; ADA9: in Std_logic; ADA8: in Std_logic; 
+            ADA7: in Std_logic; ADA6: in Std_logic; ADA5: in Std_logic; 
+            DOA17: out Std_logic; DOA16: out Std_logic; DOA15: out Std_logic; 
+            DOA14: out Std_logic; DOA13: out Std_logic; DOA12: out Std_logic; 
+            DOA11: out Std_logic; DOA10: out Std_logic; DOA9: out Std_logic; 
+            DOA8: out Std_logic; DOA7: out Std_logic; DOA6: out Std_logic; 
+            DOA5: out Std_logic; DOA4: out Std_logic; DOA3: out Std_logic; 
+            DOA2: out Std_logic; DOA1: out Std_logic; DOA0: out Std_logic; 
+            CEA: in Std_logic; CLKA: in Std_logic; CLKB: in Std_logic; 
+            OCEB: in Std_logic; CEB: in Std_logic; DOB0: out Std_logic; 
+            DOB1: out Std_logic; DOB2: out Std_logic; DOB3: out Std_logic; 
+            DOB4: out Std_logic; DOB5: out Std_logic; DOB6: out Std_logic; 
+            DOB7: out Std_logic; DOB8: out Std_logic; DOB9: out Std_logic; 
+            DOB10: out Std_logic; DOB11: out Std_logic; DOB12: out Std_logic; 
+            DOB13: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; 
+            ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; 
+            ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; 
+            ADB13: in Std_logic; DIB0: in Std_logic; DIB1: in Std_logic; 
+            DIB2: in Std_logic; DIB3: in Std_logic; DIB4: in Std_logic; 
+            DIB5: in Std_logic; DIB6: in Std_logic; DIB7: in Std_logic; 
+            DIB8: in Std_logic; DIB9: in Std_logic; DIB10: in Std_logic; 
+            DIB11: in Std_logic; DIB12: in Std_logic; DIB13: in Std_logic; 
+            DIB14: in Std_logic; DIB15: in Std_logic);
+    end component;
+    component pll0inst_PLLInst_0
+      port (CLKI: in Std_logic; CLKFB: in Std_logic; STDBY: in Std_logic; 
+            CLKOS3: out Std_logic; CLKOS2: out Std_logic; CLKOS: out Std_logic; 
+            CLKOP: out Std_logic);
+    end component;
+  begin
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0
+      port map (
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2
+      port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3
+      port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6
+      port map (
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8
+      port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9
+      port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18
+      port map (DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                Q0=>fifo_empty_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20
+      port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24
+      port map (
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, 
+                FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25
+      port map (DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26
+      port map (
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28
+      port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29
+      port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32
+      port map (
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34
+      port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35
+      port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44
+      port map (DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                Q0=>fifo_empty_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50
+      port map (
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, 
+                FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51
+      port map (DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52
+      port map (
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54
+      port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55
+      port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58
+      port map (
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60
+      port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61
+      port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70
+      port map (DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, 
+                Q0=>fifo_empty1_c);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73
+      port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76
+      port map (
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, 
+                FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77
+      port map (DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                CLK=>pll_clks_3, 
+                FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full);
+
+      fifo_colector_inst_fifo40_inst_SLICE_78I: fifo_colector_inst_fifo40_inst_SLICE_78
+      port map (FCO=>fifo_colector_inst_fifo40_inst_w_gctr_ci);
+
+      fifo_colector_inst_fifo40_inst_SLICE_79I: fifo_colector_inst_fifo40_inst_SLICE_79
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_0, 
+                DI1=>fifo_colector_inst_fifo40_inst_iwcount_1, 
+                DI0=>fifo_colector_inst_fifo40_inst_iwcount_0, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_w_gctr_ci, 
+                F0=>fifo_colector_inst_fifo40_inst_iwcount_0, 
+                Q0=>fifo_colector_inst_fifo40_inst_wcount_0, 
+                F1=>fifo_colector_inst_fifo40_inst_iwcount_1, 
+                Q1=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                FCO=>fifo_colector_inst_fifo40_inst_co0);
+
+      fifo_colector_inst_fifo40_inst_SLICE_80I: fifo_colector_inst_fifo40_inst_SLICE_80
+      port map (A1=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                DI1=>fifo_colector_inst_fifo40_inst_iwcount_3, 
+                DI0=>fifo_colector_inst_fifo40_inst_iwcount_2, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_co0, 
+                F0=>fifo_colector_inst_fifo40_inst_iwcount_2, 
+                Q0=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                F1=>fifo_colector_inst_fifo40_inst_iwcount_3, 
+                Q1=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_co1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_81I: fifo_colector_inst_fifo40_inst_SLICE_81
+      port map (A1=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                DI1=>fifo_colector_inst_fifo40_inst_iwcount_5, 
+                DI0=>fifo_colector_inst_fifo40_inst_iwcount_4, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_co1, 
+                F0=>fifo_colector_inst_fifo40_inst_iwcount_4, 
+                Q0=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                F1=>fifo_colector_inst_fifo40_inst_iwcount_5, 
+                Q1=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                FCO=>fifo_colector_inst_fifo40_inst_co2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_82I: fifo_colector_inst_fifo40_inst_SLICE_82
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                DI1=>fifo_colector_inst_fifo40_inst_iwcount_7, 
+                DI0=>fifo_colector_inst_fifo40_inst_iwcount_6, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_co2, 
+                F0=>fifo_colector_inst_fifo40_inst_iwcount_6, 
+                Q0=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                F1=>fifo_colector_inst_fifo40_inst_iwcount_7, 
+                Q1=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                FCO=>fifo_colector_inst_fifo40_inst_co3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_83I: fifo_colector_inst_fifo40_inst_SLICE_83
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                DI1=>fifo_colector_inst_fifo40_inst_iwcount_9, 
+                DI0=>fifo_colector_inst_fifo40_inst_iwcount_8, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_co3, 
+                F0=>fifo_colector_inst_fifo40_inst_iwcount_8, 
+                Q0=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                F1=>fifo_colector_inst_fifo40_inst_iwcount_9, 
+                Q1=>fifo_colector_inst_fifo40_inst_wcount_9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_84I: fifo_colector_inst_fifo40_inst_SLICE_84
+      port map (FCO=>fifo_colector_inst_fifo40_inst_r_gctr_ci);
+
+      fifo_colector_inst_fifo40_inst_SLICE_85I: fifo_colector_inst_fifo40_inst_SLICE_85
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_0, 
+                DI1=>fifo_colector_inst_fifo40_inst_ircount_1, 
+                DI0=>fifo_colector_inst_fifo40_inst_ircount_0, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_r_gctr_ci, 
+                F0=>fifo_colector_inst_fifo40_inst_ircount_0, 
+                Q0=>fifo_colector_inst_fifo40_inst_rcount_0, 
+                F1=>fifo_colector_inst_fifo40_inst_ircount_1, 
+                Q1=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                FCO=>fifo_colector_inst_fifo40_inst_co0_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_86I: fifo_colector_inst_fifo40_inst_SLICE_86
+      port map (A1=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                DI1=>fifo_colector_inst_fifo40_inst_ircount_3, 
+                DI0=>fifo_colector_inst_fifo40_inst_ircount_2, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_co0_1, 
+                F0=>fifo_colector_inst_fifo40_inst_ircount_2, 
+                Q0=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                F1=>fifo_colector_inst_fifo40_inst_ircount_3, 
+                Q1=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_co1_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_87I: fifo_colector_inst_fifo40_inst_SLICE_87
+      port map (A1=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                DI1=>fifo_colector_inst_fifo40_inst_ircount_5, 
+                DI0=>fifo_colector_inst_fifo40_inst_ircount_4, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_co1_1, 
+                F0=>fifo_colector_inst_fifo40_inst_ircount_4, 
+                Q0=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                F1=>fifo_colector_inst_fifo40_inst_ircount_5, 
+                Q1=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                FCO=>fifo_colector_inst_fifo40_inst_co2_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_88I: fifo_colector_inst_fifo40_inst_SLICE_88
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                DI1=>fifo_colector_inst_fifo40_inst_ircount_7, 
+                DI0=>fifo_colector_inst_fifo40_inst_ircount_6, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_co2_1, 
+                F0=>fifo_colector_inst_fifo40_inst_ircount_6, 
+                Q0=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                F1=>fifo_colector_inst_fifo40_inst_ircount_7, 
+                Q1=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                FCO=>fifo_colector_inst_fifo40_inst_co3_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_89I: fifo_colector_inst_fifo40_inst_SLICE_89
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                DI1=>fifo_colector_inst_fifo40_inst_ircount_9, 
+                DI0=>fifo_colector_inst_fifo40_inst_ircount_8, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_co3_1, 
+                F0=>fifo_colector_inst_fifo40_inst_ircount_8, 
+                Q0=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                F1=>fifo_colector_inst_fifo40_inst_ircount_9, 
+                Q1=>fifo_colector_inst_fifo40_inst_rcount_9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_90I: fifo_colector_inst_fifo40_inst_SLICE_90
+      port map (B1=>fifo_colector_inst_fifo40_inst_rden_i, 
+                A1=>fifo_colector_inst_fifo40_inst_rden_i, 
+                FCO=>fifo_colector_inst_fifo40_inst_cmp_ci);
+
+      fifo_colector_inst_fifo40_inst_SLICE_91I: fifo_colector_inst_fifo40_inst_SLICE_91
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                A1=>fifo_colector_inst_fifo40_inst_wcount_r1, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_0, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_r0, 
+                FCI=>fifo_colector_inst_fifo40_inst_cmp_ci, 
+                FCO=>fifo_colector_inst_fifo40_inst_co0_2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_92I: fifo_colector_inst_fifo40_inst_SLICE_92
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                A1=>fifo_colector_inst_fifo40_inst_wcount_r3, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_r2, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                FCI=>fifo_colector_inst_fifo40_inst_co0_2, 
+                FCO=>fifo_colector_inst_fifo40_inst_co1_2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_93I: fifo_colector_inst_fifo40_inst_SLICE_93
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_r5, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_r4, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                FCI=>fifo_colector_inst_fifo40_inst_co1_2, 
+                FCO=>fifo_colector_inst_fifo40_inst_co2_2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_94I: fifo_colector_inst_fifo40_inst_SLICE_94
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                A1=>fifo_colector_inst_fifo40_inst_wcount_r7, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                A0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                FCI=>fifo_colector_inst_fifo40_inst_co2_2, 
+                FCO=>fifo_colector_inst_fifo40_inst_co3_2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_95I: fifo_colector_inst_fifo40_inst_SLICE_95
+      port map (B1=>fifo_colector_inst_fifo40_inst_empty_cmp_set, 
+                A1=>fifo_colector_inst_fifo40_inst_empty_cmp_clr, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_r8, 
+                FCI=>fifo_colector_inst_fifo40_inst_co3_2, 
+                FCO=>fifo_colector_inst_fifo40_inst_empty_d_c);
+
+      fifo_colector_inst_fifo40_inst_SLICE_96I: fifo_colector_inst_fifo40_inst_SLICE_96
+      port map (DI0=>fifo_colector_inst_fifo40_inst_empty_d, CLK=>rd_clk_c, 
+                FCI=>fifo_colector_inst_fifo40_inst_empty_d_c, 
+                F0=>fifo_colector_inst_fifo40_inst_empty_d, 
+                Q0=>last_buf_empty_c);
+
+      fifo_colector_inst_fifo40_inst_SLICE_97I: fifo_colector_inst_fifo40_inst_SLICE_97
+      port map (B1=>fifo_colector_inst_fifo40_inst_wren_i, 
+                A1=>fifo_colector_inst_fifo40_inst_wren_i, 
+                FCO=>fifo_colector_inst_fifo40_inst_cmp_ci_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_98I: fifo_colector_inst_fifo40_inst_SLICE_98
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_w1, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_w0, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_0, 
+                FCI=>fifo_colector_inst_fifo40_inst_cmp_ci_1, 
+                FCO=>fifo_colector_inst_fifo40_inst_co0_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_99I: fifo_colector_inst_fifo40_inst_SLICE_99
+      port map (B1=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_w3, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_w2, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                FCI=>fifo_colector_inst_fifo40_inst_co0_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_co1_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_100I: fifo_colector_inst_fifo40_inst_SLICE_100
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_w5, 
+                A1=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_w4, 
+                FCI=>fifo_colector_inst_fifo40_inst_co1_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_co2_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_101I: fifo_colector_inst_fifo40_inst_SLICE_101
+      port map (B1=>fifo_colector_inst_fifo40_inst_rcount_w7, 
+                A1=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                A0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, 
+                FCI=>fifo_colector_inst_fifo40_inst_co2_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_co3_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_102I: fifo_colector_inst_fifo40_inst_SLICE_102
+      port map (B1=>fifo_colector_inst_fifo40_inst_full_cmp_clr, 
+                A1=>fifo_colector_inst_fifo40_inst_full_cmp_set, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_w8, 
+                FCI=>fifo_colector_inst_fifo40_inst_co3_3, 
+                FCO=>fifo_colector_inst_fifo40_inst_full_d_c);
+
+      fifo_colector_inst_fifo40_inst_SLICE_103I: fifo_colector_inst_fifo40_inst_SLICE_103
+      port map (DI0=>fifo_colector_inst_fifo40_inst_full_d, CLK=>pll_clks_3, 
+                FCI=>fifo_colector_inst_fifo40_inst_full_d_c, 
+                F0=>fifo_colector_inst_fifo40_inst_full_d, 
+                Q0=>fifo_colector_inst_fifo40_inst_Full);
+    hades_tdc_bundle_inst_SLICE_104I: hades_tdc_bundle_inst_SLICE_104
+      port map (FCI=>hades_tdc_bundle_inst_hit_valid25_0_I_27_cry, 
+                F0=>hades_tdc_bundle_inst_hit_valid25);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105
+      port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_0, 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106
+      port map (D1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5, 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14
+                , B1=>hades_dbg2_coarse_c_5, 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6
+                , B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_dbg2_coarse_c_3, 
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107
+      port map (D1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, 
+                C1=>hades_dbg2_coarse_c_8, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                D0=>hades_dbg2_coarse_c_7, C0=>hades_dbg2_coarse_c_6, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108
+      port map (
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109
+      port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_0, 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8
+                , B1=>hades_dbg2_coarse_c_5, 
+                A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5, 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6
+                , B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_dbg2_coarse_c_3, 
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111
+      port map (D1=>hades_dbg2_coarse_c_8, 
+                C1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                D0=>hades_dbg2_coarse_c_6, C0=>hades_dbg2_coarse_c_7, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112
+      port map (
+                FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113
+      port map (
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114
+      port map (
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115
+      port map (
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, 
+                FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116
+      port map (
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , 
+                FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1
+                , 
+                FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117
+      port map (
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2
+                , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, 
+                FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0
+                );
+    hades_tdc_bundle_inst_SLICE_118I: hades_tdc_bundle_inst_SLICE_118
+      port map (D1=>hades_drop_cmp_buf_c_0, C1=>hades_drop_cmp_buf_coarse_c_0, 
+                B1=>hades_drop_cmp_buf_coarse_c_1, A1=>hades_drop_cmp_buf_c_1, 
+                FCO=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0);
+    hades_tdc_bundle_inst_SLICE_119I: hades_tdc_bundle_inst_SLICE_119
+      port map (D1=>hades_drop_cmp_buf_coarse_c_5, C1=>hades_drop_cmp_buf_c_5, 
+                B1=>hades_drop_cmp_buf_coarse_c_4, A1=>hades_drop_cmp_buf_c_4, 
+                D0=>hades_drop_cmp_buf_coarse_c_3, C0=>hades_drop_cmp_buf_c_2, 
+                B0=>hades_drop_cmp_buf_coarse_c_2, A0=>hades_drop_cmp_buf_c_3, 
+                FCI=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0, 
+                FCO=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2);
+    hades_tdc_bundle_inst_SLICE_120I: hades_tdc_bundle_inst_SLICE_120
+      port map (D1=>hades_drop_cmp_buf_c_8, C1=>hades_drop_cmp_buf_coarse_c_9, 
+                B1=>hades_drop_cmp_buf_coarse_c_8, 
+                D0=>hades_drop_cmp_buf_coarse_c_7, 
+                C0=>hades_drop_cmp_buf_coarse_c_6, B0=>hades_drop_cmp_buf_c_6, 
+                A0=>hades_drop_cmp_buf_c_7, 
+                FCI=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2, 
+                FCO=>hades_tdc_bundle_inst_hit_valid25_0_I_27_cry);
+    hades_tdc_bundle_inst_SLICE_121I: hades_tdc_bundle_inst_SLICE_121
+      port map (D1=>ANB1, C1=>ANB2, B1=>ANB0, A1=>ANB3, D0=>ANB0, 
+                DI0=>hades_tdc_bundle_inst_N_247_i, 
+                M0=>hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_N_247_i, Q0=>ANB0);
+    hades_tdc_bundle_inst_SLICE_122I: hades_tdc_bundle_inst_SLICE_122
+      port map (D1=>ANB1, C1=>ANB0, B1=>ANB2, A1=>ANB3, C0=>ANB0, B0=>ANB1, 
+                DI1=>hades_tdc_bundle_inst_N_50_i_i, 
+                DI0=>hades_tdc_bundle_inst_N_46_i, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_N_46_i, Q0=>ANB1, 
+                F1=>hades_tdc_bundle_inst_N_50_i_i, Q1=>ANB3);
+    hades_tdc_bundle_inst_SLICE_123I: hades_tdc_bundle_inst_SLICE_123
+      port map (B1=>ANB2, A1=>ANB1, D0=>hades_discard_c, C0=>ANB1, B0=>ANB2, 
+                A0=>ANB3, DI0=>hades_tdc_bundle_inst_hit_out_i_6_2, M0=>ANB0, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hit_out_i_6_2, Q0=>ANB2);
+    trb_adapter_inst_SLICE_124I: trb_adapter_inst_SLICE_124
+      port map (M0=>trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0, CLK=>rd_clk_c, 
+                Q0=>discard_c);
+    fifo_colector_inst_SLICE_125I: fifo_colector_inst_SLICE_125
+      port map (B1=>fifo_empty_2, D0=>fifo_empty_1, 
+                C0=>fifo_colector_inst_iterator_0, A0=>fifo_empty1_c, 
+                DI0=>fifo_colector_inst_in_empty_pmux_i, 
+                M0=>fifo_colector_inst_iterator_1, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_in_empty_pmux_i, 
+                Q0=>fifo_colector_inst_buffer_wr_enable);
+    fifo_colector_inst_SLICE_126I: fifo_colector_inst_SLICE_126
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, 
+                B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_0, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_16, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_0, 
+                Q0=>fifo_colector_inst_data_buffer_0);
+    fifo_colector_inst_SLICE_127I: fifo_colector_inst_SLICE_127
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, 
+                B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_1, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_17, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_1, 
+                Q0=>fifo_colector_inst_data_buffer_1);
+    fifo_colector_inst_SLICE_128I: fifo_colector_inst_SLICE_128
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, 
+                B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_2, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_18, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_2, 
+                Q0=>fifo_colector_inst_data_buffer_2);
+    fifo_colector_inst_SLICE_129I: fifo_colector_inst_SLICE_129
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, 
+                B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_3, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_19, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_3, 
+                Q0=>fifo_colector_inst_data_buffer_3);
+    fifo_colector_inst_SLICE_130I: fifo_colector_inst_SLICE_130
+      port map (D1=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, 
+                C1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, 
+                C0=>fifo_colector_inst_iterator_0, 
+                B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_4, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_20, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_4, 
+                Q0=>fifo_colector_inst_data_buffer_4);
+    fifo_colector_inst_SLICE_131I: fifo_colector_inst_SLICE_131
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, 
+                B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_5, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_21, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_5, 
+                Q0=>fifo_colector_inst_data_buffer_5);
+    fifo_colector_inst_SLICE_132I: fifo_colector_inst_SLICE_132
+      port map (D1=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, 
+                C1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, 
+                C0=>fifo_colector_inst_iterator_0, 
+                B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_6, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_22, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_6, 
+                Q0=>fifo_colector_inst_data_buffer_6);
+    fifo_colector_inst_SLICE_133I: fifo_colector_inst_SLICE_133
+      port map (D1=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, 
+                B1=>fifo_colector_inst_iterator_0, 
+                A1=>fifo_colector_inst_iterator_1, 
+                D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, 
+                B0=>fifo_colector_inst_iterator_0, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_data_buffer_3_7, 
+                M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_23, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                OFX0=>fifo_colector_inst_data_buffer_3_7, 
+                Q0=>fifo_colector_inst_data_buffer_7);
+    fifo_colector_inst_SLICE_134I: fifo_colector_inst_SLICE_134
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_9, 
+                A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_17, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_16, 
+                B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_8, 
+                DI1=>fifo_colector_inst_data_buffer_3_9, 
+                DI0=>fifo_colector_inst_data_buffer_3_8, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_8, 
+                Q0=>fifo_colector_inst_data_buffer_8, 
+                F1=>fifo_colector_inst_data_buffer_3_9, 
+                Q1=>fifo_colector_inst_data_buffer_9);
+    fifo_colector_inst_SLICE_135I: fifo_colector_inst_SLICE_135
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_19, 
+                A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_11, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_10, 
+                B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_18, 
+                DI1=>fifo_colector_inst_data_buffer_3_11, 
+                DI0=>fifo_colector_inst_data_buffer_3_10, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_10, 
+                Q0=>fifo_colector_inst_data_buffer_10, 
+                F1=>fifo_colector_inst_data_buffer_3_11, 
+                Q1=>fifo_colector_inst_data_buffer_11);
+    fifo_colector_inst_SLICE_136I: fifo_colector_inst_SLICE_136
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_21, 
+                A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_13, 
+                D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_20, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_12, 
+                A0=>fifo_colector_inst_iterator_0, 
+                DI1=>fifo_colector_inst_data_buffer_3_13, 
+                DI0=>fifo_colector_inst_data_buffer_3_12, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_12, 
+                Q0=>fifo_colector_inst_data_buffer_12, 
+                F1=>fifo_colector_inst_data_buffer_3_13, 
+                Q1=>fifo_colector_inst_data_buffer_13);
+    fifo_colector_inst_SLICE_137I: fifo_colector_inst_SLICE_137
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_23, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_15, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_22, 
+                A0=>genblk1_0_un1_tdc_channel_fifo_out_inst_14, 
+                DI1=>fifo_colector_inst_data_buffer_3_15, 
+                DI0=>fifo_colector_inst_data_buffer_3_14, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_14, 
+                Q0=>fifo_colector_inst_data_buffer_14, 
+                F1=>fifo_colector_inst_data_buffer_3_15, 
+                Q1=>fifo_colector_inst_data_buffer_15);
+    fifo_colector_inst_SLICE_138I: fifo_colector_inst_SLICE_138
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_1, 
+                B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_17, 
+                D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_16, 
+                C0=>genblk1_2_un1_tdc_channel_fifo_out_inst_0, 
+                B0=>fifo_colector_inst_iterator_0, 
+                DI1=>fifo_colector_inst_data_buffer_3_17, 
+                DI0=>fifo_colector_inst_data_buffer_3_16, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_16, 
+                Q0=>fifo_colector_inst_data_buffer_16, 
+                F1=>fifo_colector_inst_data_buffer_3_17, 
+                Q1=>fifo_colector_inst_data_buffer_17);
+    fifo_colector_inst_SLICE_139I: fifo_colector_inst_SLICE_139
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_3, 
+                A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_19, 
+                D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_18, 
+                B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_2, 
+                A0=>fifo_colector_inst_iterator_0, 
+                DI1=>fifo_colector_inst_data_buffer_3_19, 
+                DI0=>fifo_colector_inst_data_buffer_3_18, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_18, 
+                Q0=>fifo_colector_inst_data_buffer_18, 
+                F1=>fifo_colector_inst_data_buffer_3_19, 
+                Q1=>fifo_colector_inst_data_buffer_19);
+    fifo_colector_inst_SLICE_140I: fifo_colector_inst_SLICE_140
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_5, 
+                A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_21, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_20, 
+                B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_4, 
+                DI1=>fifo_colector_inst_data_buffer_3_21, 
+                DI0=>fifo_colector_inst_data_buffer_3_20, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_20, 
+                Q0=>fifo_colector_inst_data_buffer_20, 
+                F1=>fifo_colector_inst_data_buffer_3_21, 
+                Q1=>fifo_colector_inst_data_buffer_21);
+    fifo_colector_inst_SLICE_141I: fifo_colector_inst_SLICE_141
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_7, 
+                A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_23, 
+                D0=>fifo_colector_inst_iterator_0, 
+                C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_22, 
+                A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_6, 
+                DI1=>fifo_colector_inst_data_buffer_3_23, 
+                DI0=>fifo_colector_inst_data_buffer_3_22, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_22, 
+                Q0=>fifo_colector_inst_data_buffer_22, 
+                F1=>fifo_colector_inst_data_buffer_3_23, 
+                Q1=>fifo_colector_inst_data_buffer_23);
+    fifo_colector_inst_SLICE_142I: fifo_colector_inst_SLICE_142
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_9, 
+                A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_1, 
+                C0=>fifo_colector_inst_iterator_0, 
+                B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_8, 
+                A0=>genblk1_1_un1_tdc_channel_fifo_out_inst_0, 
+                DI1=>fifo_colector_inst_data_buffer_3_25, 
+                DI0=>fifo_colector_inst_data_buffer_3_24, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_24, 
+                Q0=>fifo_colector_inst_data_buffer_24, 
+                F1=>fifo_colector_inst_data_buffer_3_25, 
+                Q1=>fifo_colector_inst_data_buffer_25);
+    fifo_colector_inst_SLICE_143I: fifo_colector_inst_SLICE_143
+      port map (D1=>fifo_colector_inst_iterator_0, 
+                C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_11, 
+                B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_3, 
+                D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_2, 
+                B0=>fifo_colector_inst_iterator_0, 
+                A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_10, 
+                DI1=>fifo_colector_inst_data_buffer_3_27, 
+                DI0=>fifo_colector_inst_data_buffer_3_26, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_26, 
+                Q0=>fifo_colector_inst_data_buffer_26, 
+                F1=>fifo_colector_inst_data_buffer_3_27, 
+                Q1=>fifo_colector_inst_data_buffer_27);
+    fifo_colector_inst_SLICE_144I: fifo_colector_inst_SLICE_144
+      port map (D1=>genblk1_2_un1_tdc_channel_fifo_out_inst_13, 
+                B1=>fifo_colector_inst_iterator_0, 
+                A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_5, 
+                C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_4, 
+                B0=>fifo_colector_inst_iterator_0, 
+                A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_12, 
+                DI1=>fifo_colector_inst_data_buffer_3_29, 
+                DI0=>fifo_colector_inst_data_buffer_3_28, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_28, 
+                Q0=>fifo_colector_inst_data_buffer_28, 
+                F1=>fifo_colector_inst_data_buffer_3_29, 
+                Q1=>fifo_colector_inst_data_buffer_29);
+    fifo_colector_inst_SLICE_145I: fifo_colector_inst_SLICE_145
+      port map (D1=>genblk1_2_un1_tdc_channel_fifo_out_inst_15, 
+                C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_7, 
+                B1=>fifo_colector_inst_iterator_0, 
+                D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_6, 
+                C0=>fifo_colector_inst_iterator_0, 
+                B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_14, 
+                DI1=>fifo_colector_inst_data_buffer_3_31, 
+                DI0=>fifo_colector_inst_data_buffer_3_30, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, 
+                LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_data_buffer_3_30, 
+                Q0=>fifo_colector_inst_data_buffer_30, 
+                F1=>fifo_colector_inst_data_buffer_3_31, 
+                Q1=>fifo_colector_inst_data_buffer_31);
+    fifo_colector_inst_SLICE_146I: fifo_colector_inst_SLICE_146
+      port map (M1=>fifo_colector_inst_iterator_1, 
+                M0=>fifo_colector_inst_iterator_0, 
+                CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_data_buffer_32, 
+                Q1=>fifo_colector_inst_data_buffer_33);
+
+      fifo_colector_inst_fifo40_inst_SLICE_147I: fifo_colector_inst_fifo40_inst_SLICE_147
+      port map (C1=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                D0=>fifo_colector_inst_fifo40_inst_rcount_0, 
+                C0=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                DI1=>fifo_colector_inst_fifo40_inst_r_gdata_1, 
+                DI0=>fifo_colector_inst_fifo40_inst_r_gdata_0, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                F0=>fifo_colector_inst_fifo40_inst_r_gdata_0, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_0, 
+                F1=>fifo_colector_inst_fifo40_inst_r_gdata_1, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_148I: fifo_colector_inst_fifo40_inst_SLICE_148
+      port map (D1=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                DI1=>fifo_colector_inst_fifo40_inst_r_gdata_3, 
+                DI0=>fifo_colector_inst_fifo40_inst_r_gdata_2, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                F0=>fifo_colector_inst_fifo40_inst_r_gdata_2, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_2, 
+                F1=>fifo_colector_inst_fifo40_inst_r_gdata_3, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_149I: fifo_colector_inst_fifo40_inst_SLICE_149
+      port map (C1=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                A1=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                D0=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                A0=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                DI1=>fifo_colector_inst_fifo40_inst_r_gdata_5, 
+                DI0=>fifo_colector_inst_fifo40_inst_r_gdata_4, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                F0=>fifo_colector_inst_fifo40_inst_r_gdata_4, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_4, 
+                F1=>fifo_colector_inst_fifo40_inst_r_gdata_5, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_150I: fifo_colector_inst_fifo40_inst_SLICE_150
+      port map (D1=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                C1=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                D0=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                C0=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                DI1=>fifo_colector_inst_fifo40_inst_r_gdata_7, 
+                DI0=>fifo_colector_inst_fifo40_inst_r_gdata_6, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                F0=>fifo_colector_inst_fifo40_inst_r_gdata_6, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_6, 
+                F1=>fifo_colector_inst_fifo40_inst_r_gdata_7, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_151I: fifo_colector_inst_fifo40_inst_SLICE_151
+      port map (D0=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                B0=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                DI0=>fifo_colector_inst_fifo40_inst_r_gdata_8, 
+                M1=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                F0=>fifo_colector_inst_fifo40_inst_r_gdata_8, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_8, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_152I: fifo_colector_inst_fifo40_inst_SLICE_152
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_1, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_0, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w0, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_153I: fifo_colector_inst_fifo40_inst_SLICE_153
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_3, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_2, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w2, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_154I: fifo_colector_inst_fifo40_inst_SLICE_154
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_5, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_4, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w4, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_155I: fifo_colector_inst_fifo40_inst_SLICE_155
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_7, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_6, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w6, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_156I: fifo_colector_inst_fifo40_inst_SLICE_156
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_9, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_8, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w8, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_157I: fifo_colector_inst_fifo40_inst_SLICE_157
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w1, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w0, 
+                CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w20, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w21);
+
+      fifo_colector_inst_fifo40_inst_SLICE_158I: fifo_colector_inst_fifo40_inst_SLICE_158
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w3, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w2, 
+                CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w22, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w23);
+
+      fifo_colector_inst_fifo40_inst_SLICE_159I: fifo_colector_inst_fifo40_inst_SLICE_159
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w5, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w4, 
+                CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w25);
+
+      fifo_colector_inst_fifo40_inst_SLICE_160I: fifo_colector_inst_fifo40_inst_SLICE_160
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w7, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w6, 
+                CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w27);
+
+      fifo_colector_inst_fifo40_inst_SLICE_161I: fifo_colector_inst_fifo40_inst_SLICE_161
+      port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w9, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w8, 
+                CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w29);
+
+      fifo_colector_inst_fifo40_inst_SLICE_162I: fifo_colector_inst_fifo40_inst_SLICE_162
+      port map (M1=>fifo_colector_inst_fifo40_inst_rcount_1, 
+                M0=>fifo_colector_inst_fifo40_inst_rcount_0, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_rptr_0, 
+                Q1=>fifo_colector_inst_fifo40_inst_rptr_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_163I: fifo_colector_inst_fifo40_inst_SLICE_163
+      port map (M1=>fifo_colector_inst_fifo40_inst_rcount_3, 
+                M0=>fifo_colector_inst_fifo40_inst_rcount_2, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_rptr_2, 
+                Q1=>fifo_colector_inst_fifo40_inst_rptr_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_164I: fifo_colector_inst_fifo40_inst_SLICE_164
+      port map (M1=>fifo_colector_inst_fifo40_inst_rcount_5, 
+                M0=>fifo_colector_inst_fifo40_inst_rcount_4, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_rptr_4, 
+                Q1=>fifo_colector_inst_fifo40_inst_rptr_5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_165I: fifo_colector_inst_fifo40_inst_SLICE_165
+      port map (M1=>fifo_colector_inst_fifo40_inst_rcount_7, 
+                M0=>fifo_colector_inst_fifo40_inst_rcount_6, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_rptr_6, 
+                Q1=>fifo_colector_inst_fifo40_inst_rptr_7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_166I: fifo_colector_inst_fifo40_inst_SLICE_166
+      port map (M1=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                M0=>fifo_colector_inst_fifo40_inst_rcount_8, 
+                CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_rptr_8, 
+                Q1=>fifo_colector_inst_fifo40_inst_rptr_9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_167I: fifo_colector_inst_fifo40_inst_SLICE_167
+      port map (C1=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                B1=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                D0=>fifo_colector_inst_fifo40_inst_wcount_0, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                DI1=>fifo_colector_inst_fifo40_inst_w_gdata_1, 
+                DI0=>fifo_colector_inst_fifo40_inst_w_gdata_0, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fifo40_inst_w_gdata_0, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_0, 
+                F1=>fifo_colector_inst_fifo40_inst_w_gdata_1, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_168I: fifo_colector_inst_fifo40_inst_SLICE_168
+      port map (D1=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                C1=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                D0=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                C0=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                DI1=>fifo_colector_inst_fifo40_inst_w_gdata_3, 
+                DI0=>fifo_colector_inst_fifo40_inst_w_gdata_2, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fifo40_inst_w_gdata_2, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_2, 
+                F1=>fifo_colector_inst_fifo40_inst_w_gdata_3, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_169I: fifo_colector_inst_fifo40_inst_SLICE_169
+      port map (D1=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                C1=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                C0=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                A0=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                DI1=>fifo_colector_inst_fifo40_inst_w_gdata_5, 
+                DI0=>fifo_colector_inst_fifo40_inst_w_gdata_4, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fifo40_inst_w_gdata_4, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_4, 
+                F1=>fifo_colector_inst_fifo40_inst_w_gdata_5, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_170I: fifo_colector_inst_fifo40_inst_SLICE_170
+      port map (D1=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                B1=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                D0=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                B0=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                DI1=>fifo_colector_inst_fifo40_inst_w_gdata_7, 
+                DI0=>fifo_colector_inst_fifo40_inst_w_gdata_6, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fifo40_inst_w_gdata_6, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_6, 
+                F1=>fifo_colector_inst_fifo40_inst_w_gdata_7, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_171I: fifo_colector_inst_fifo40_inst_SLICE_171
+      port map (D0=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                C0=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                DI0=>fifo_colector_inst_fifo40_inst_w_gdata_8, 
+                M1=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fifo40_inst_w_gdata_8, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_8, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_172I: fifo_colector_inst_fifo40_inst_SLICE_172
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_1, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_0, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r0, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_173I: fifo_colector_inst_fifo40_inst_SLICE_173
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_3, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_2, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r2, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_174I: fifo_colector_inst_fifo40_inst_SLICE_174
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_5, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_4, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r4, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_175I: fifo_colector_inst_fifo40_inst_SLICE_175
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_7, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_6, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r6, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_176I: fifo_colector_inst_fifo40_inst_SLICE_176
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_9, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_8, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r8, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r9);
+
+      fifo_colector_inst_fifo40_inst_SLICE_177I: fifo_colector_inst_fifo40_inst_SLICE_177
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r1, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_r0, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r20, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r21);
+
+      fifo_colector_inst_fifo40_inst_SLICE_178I: fifo_colector_inst_fifo40_inst_SLICE_178
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r3, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_r2, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r22, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r23);
+
+      fifo_colector_inst_fifo40_inst_SLICE_179I: fifo_colector_inst_fifo40_inst_SLICE_179
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r5, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_r4, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r24, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r25);
+
+      fifo_colector_inst_fifo40_inst_SLICE_180I: fifo_colector_inst_fifo40_inst_SLICE_180
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r7, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_r6, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r26, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r27);
+
+      fifo_colector_inst_fifo40_inst_SLICE_181I: fifo_colector_inst_fifo40_inst_SLICE_181
+      port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r9, 
+                M0=>fifo_colector_inst_fifo40_inst_w_gcount_r8, CLK=>rd_clk_c, 
+                Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, 
+                Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r29);
+
+      fifo_colector_inst_fifo40_inst_SLICE_182I: fifo_colector_inst_fifo40_inst_SLICE_182
+      port map (M1=>fifo_colector_inst_fifo40_inst_wcount_1, 
+                M0=>fifo_colector_inst_fifo40_inst_wcount_0, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_wptr_0, 
+                Q1=>fifo_colector_inst_fifo40_inst_wptr_1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_183I: fifo_colector_inst_fifo40_inst_SLICE_183
+      port map (M1=>fifo_colector_inst_fifo40_inst_wcount_3, 
+                M0=>fifo_colector_inst_fifo40_inst_wcount_2, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_wptr_2, 
+                Q1=>fifo_colector_inst_fifo40_inst_wptr_3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_184I: fifo_colector_inst_fifo40_inst_SLICE_184
+      port map (M1=>fifo_colector_inst_fifo40_inst_wcount_5, 
+                M0=>fifo_colector_inst_fifo40_inst_wcount_4, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_wptr_4, 
+                Q1=>fifo_colector_inst_fifo40_inst_wptr_5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_185I: fifo_colector_inst_fifo40_inst_SLICE_185
+      port map (M1=>fifo_colector_inst_fifo40_inst_wcount_7, 
+                M0=>fifo_colector_inst_fifo40_inst_wcount_6, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_wptr_6, 
+                Q1=>fifo_colector_inst_fifo40_inst_wptr_7);
+
+      fifo_colector_inst_fifo40_inst_SLICE_186I: fifo_colector_inst_fifo40_inst_SLICE_186
+      port map (M1=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                M0=>fifo_colector_inst_fifo40_inst_wcount_8, 
+                CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, 
+                Q0=>fifo_colector_inst_fifo40_inst_wptr_8, 
+                Q1=>fifo_colector_inst_fifo40_inst_wptr_9);
+    fifo_colector_inst_SLICE_187I: fifo_colector_inst_SLICE_187
+      port map (C0=>fifo_colector_inst_iterator_0, 
+                B0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_un5_in_read_enable, 
+                M1=>fifo_colector_inst_iterator_0, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_un5_in_read_enable, 
+                Q0=>fifo_colector_inst_iterator_0, 
+                Q1=>fifo_colector_inst_iterator_1);
+    trb_adapter_inst_SLICE_188I: trb_adapter_inst_SLICE_188
+      port map (C1=>discard_c, 
+                B1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, 
+                A1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2, 
+                D0=>fifo_rden_c, C0=>last_buf_empty_c, B0=>burst_c, 
+                DI0=>trb_adapter_inst_buf_rden4, CLK=>rd_clk_c, 
+                F0=>trb_adapter_inst_buf_rden4, Q0=>fifo_rden_c, F1=>burst_c);
+    fifo_colector_inst_SLICE_189I: fifo_colector_inst_SLICE_189
+      port map (C1=>fifo_colector_inst_iterator_0, B1=>fifo_read_1, 
+                D0=>fifo_read_0, C0=>fifo_colector_inst_iterator_0, 
+                A0=>fifo_colector_inst_iterator_1, 
+                DI1=>fifo_colector_inst_fb_0_1, DI0=>fifo_colector_inst_fb_0, 
+                LSR=>fifo_colector_inst_in_empty_pmux, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fb_0, Q0=>fifo_read_0, 
+                F1=>fifo_colector_inst_fb_0_1, Q1=>fifo_read_1);
+    fifo_colector_inst_SLICE_190I: fifo_colector_inst_SLICE_190
+      port map (D0=>fifo_read_2, A0=>fifo_colector_inst_iterator_1, 
+                DI0=>fifo_colector_inst_fb_0_0, 
+                LSR=>fifo_colector_inst_in_empty_pmux, CLK=>pll_clks_3, 
+                F0=>fifo_colector_inst_fb_0_0, Q0=>fifo_read_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204
+      port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                , B0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i, 
+                LSR=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208
+      port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209
+      port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210
+      port map (C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226
+      port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230
+      port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240
+      port map (
+                M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245
+      port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I: genblk1_0_tdc_channel_fifo_out_inst_SLICE_246
+      port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid, 
+                DI0=>genblk1_0_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>genblk1_0_tdc_channel_fifo_out_inst_fb_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263
+      port map (M1=>trig_c_i_0, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6);
+
+      genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271
+      port map (
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284
+      port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                , B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i, 
+                LSR=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290
+      port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308
+      port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309
+      port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310
+      port map (B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320
+      port map (
+                M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325
+      port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I: genblk1_1_tdc_channel_fifo_out_inst_SLICE_326
+      port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid, 
+                DI0=>genblk1_1_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>genblk1_1_tdc_channel_fifo_out_inst_fb_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343
+      port map (M1=>trig_c_i_1, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6);
+
+      genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351
+      port map (
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364
+      port map (
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                , C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i, 
+                LSR=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367
+      port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370
+      port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387
+      port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390
+      port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400
+      port map (
+                M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405
+      port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, 
+                CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I: genblk1_2_tdc_channel_fifo_out_inst_SLICE_406
+      port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid, 
+                DI0=>genblk1_2_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>genblk1_2_tdc_channel_fifo_out_inst_fb_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423
+      port map (M1=>trig_c_i_2, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, 
+                CLK=>pll_clks_0, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, 
+                CLK=>pll_clks_1, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, 
+                CLK=>pll_clks_2, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6);
+
+      genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431
+      port map (
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, 
+                CLK=>pll_clks_3, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7);
+    hades_tdc_bundle_inst_SLICE_432I: hades_tdc_bundle_inst_SLICE_432
+      port map (D1=>ANB1, B1=>ANB3, D0=>ANB0, C0=>ANB1, B0=>ANB3, A0=>ANB2, 
+                DI0=>hades_tdc_bundle_inst_buf_finished5, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_buf_finished5, 
+                Q0=>hades_buf_finished_c, F1=>hades_tdc_bundle_inst_N_80);
+    hades_tdc_bundle_inst_SLICE_433I: hades_tdc_bundle_inst_SLICE_433
+      port map (M0=>hades_buf_finished_c, LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_buf_release_c);
+    hades_tdc_bundle_inst_SLICE_434I: hades_tdc_bundle_inst_SLICE_434
+      port map (C1=>hades_dbg2_coarse_c_0, B1=>hades_dbg2_coarse_c_1, 
+                D0=>hades_dbg2_coarse_c_0, 
+                DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, 
+                DI0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, 
+                Q0=>hades_dbg2_coarse_c_0, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, 
+                Q1=>hades_dbg2_coarse_c_1);
+    hades_tdc_bundle_inst_SLICE_435I: hades_tdc_bundle_inst_SLICE_435
+      port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_3, 
+                B1=>hades_dbg2_coarse_c_2, A1=>hades_dbg2_coarse_c_0, 
+                D0=>hades_dbg2_coarse_c_1, C0=>hades_dbg2_coarse_c_2, 
+                A0=>hades_dbg2_coarse_c_0, 
+                DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, 
+                Q0=>hades_dbg2_coarse_c_2, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, 
+                Q1=>hades_dbg2_coarse_c_3);
+    hades_tdc_bundle_inst_SLICE_436I: hades_tdc_bundle_inst_SLICE_436
+      port map (D1=>hades_dbg2_coarse_c_5, C1=>hades_dbg2_coarse_c_4, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A1=>hades_dbg2_coarse_c_3, D0=>hades_dbg2_coarse_c_4, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_dbg2_coarse_c_3, 
+                DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, 
+                Q0=>hades_dbg2_coarse_c_4, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, 
+                Q1=>hades_dbg2_coarse_c_5);
+    hades_tdc_bundle_inst_SLICE_437I: hades_tdc_bundle_inst_SLICE_437
+      port map (D1=>hades_dbg2_coarse_c_7, C1=>hades_dbg2_coarse_c_6, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                D0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                C0=>hades_dbg2_coarse_c_6, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_dbg2_coarse_c_3, 
+                DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, 
+                Q0=>hades_dbg2_coarse_c_6, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, 
+                Q1=>hades_dbg2_coarse_c_7);
+    hades_tdc_bundle_inst_SLICE_438I: hades_tdc_bundle_inst_SLICE_438
+      port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_3, 
+                B1=>hades_dbg2_coarse_c_0, A1=>hades_dbg2_coarse_c_2, 
+                D0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, 
+                C0=>hades_dbg2_coarse_c_8, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, 
+                Q0=>hades_dbg2_coarse_c_8, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4);
+    hades_tdc_bundle_inst_SLICE_439I: hades_tdc_bundle_inst_SLICE_439
+      port map (M1=>hades_tdc_bundle_inst_hades_raw_out_4, 
+                M0=>hades_tdc_bundle_inst_hades_raw_out_3, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_4, 
+                Q1=>hades_dbg2_out_c_5);
+    hades_tdc_bundle_inst_SLICE_440I: hades_tdc_bundle_inst_SLICE_440
+      port map (M1=>hades_tdc_bundle_inst_hades_raw_out_6, 
+                M0=>hades_tdc_bundle_inst_hades_raw_out_5, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_6, 
+                Q1=>hades_dbg2_out_c_7);
+    hades_tdc_bundle_inst_SLICE_441I: hades_tdc_bundle_inst_SLICE_441
+      port map (M1=>hades_tdc_bundle_inst_hades_raw_out_8, 
+                M0=>hades_tdc_bundle_inst_hades_raw_out_7, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_8, 
+                Q1=>hades_dbg2_out_c_9);
+    hades_tdc_bundle_inst_SLICE_442I: hades_tdc_bundle_inst_SLICE_442
+      port map (M1=>hades_tdc_bundle_inst_hades_raw_out_10, 
+                M0=>hades_tdc_bundle_inst_hades_raw_out_9, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_10, 
+                Q1=>hades_dbg2_out_c_11);
+    hades_tdc_bundle_inst_SLICE_443I: hades_tdc_bundle_inst_SLICE_443
+      port map (M0=>hades_tdc_bundle_inst_hades_raw_out_11, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_12);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444
+      port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa, 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, 
+                D0=>hades_invalid_dl_c_3, C0=>hades_invalid_dl_c_2, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa
+                , CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa, 
+                Q0=>hades_discard_c, 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en);
+    hades_tdc_bundle_inst_SLICE_445I: hades_tdc_bundle_inst_SLICE_445
+      port map (M1=>hades_dbg2_out_c_5, M0=>hades_dbg2_out_c_4, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_0, 
+                Q1=>hades_drop_cmp_buf_c_1);
+    hades_tdc_bundle_inst_SLICE_446I: hades_tdc_bundle_inst_SLICE_446
+      port map (M1=>hades_dbg2_out_c_7, M0=>hades_dbg2_out_c_6, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_2, 
+                Q1=>hades_drop_cmp_buf_c_3);
+    hades_tdc_bundle_inst_SLICE_447I: hades_tdc_bundle_inst_SLICE_447
+      port map (M1=>hades_dbg2_out_c_9, M0=>hades_dbg2_out_c_8, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_4, 
+                Q1=>hades_drop_cmp_buf_c_5);
+    hades_tdc_bundle_inst_SLICE_448I: hades_tdc_bundle_inst_SLICE_448
+      port map (M1=>hades_dbg2_out_c_11, M0=>hades_dbg2_out_c_10, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_6, 
+                Q1=>hades_drop_cmp_buf_c_7);
+    hades_tdc_bundle_inst_SLICE_449I: hades_tdc_bundle_inst_SLICE_449
+      port map (M0=>hades_dbg2_out_c_12, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_8);
+    hades_tdc_bundle_inst_SLICE_450I: hades_tdc_bundle_inst_SLICE_450
+      port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, 
+                M0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_0, 
+                Q1=>hades_drop_cmp_buf_coarse_c_1);
+    hades_tdc_bundle_inst_SLICE_451I: hades_tdc_bundle_inst_SLICE_451
+      port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, 
+                M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_2, 
+                Q1=>hades_drop_cmp_buf_coarse_c_3);
+    hades_tdc_bundle_inst_SLICE_452I: hades_tdc_bundle_inst_SLICE_452
+      port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, 
+                M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_4, 
+                Q1=>hades_drop_cmp_buf_coarse_c_5);
+    hades_tdc_bundle_inst_SLICE_453I: hades_tdc_bundle_inst_SLICE_453
+      port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, 
+                M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_6, 
+                Q1=>hades_drop_cmp_buf_coarse_c_7);
+    hades_tdc_bundle_inst_SLICE_454I: hades_tdc_bundle_inst_SLICE_454
+      port map (M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_8);
+    hades_tdc_bundle_inst_SLICE_455I: hades_tdc_bundle_inst_SLICE_455
+      port map (D1=>hades_dbg2_coarse_c_4, C1=>hades_dbg2_coarse_c_8, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, 
+                A1=>hades_dbg2_coarse_c_5, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9, 
+                M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, 
+                CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9, 
+                Q0=>hades_drop_cmp_buf_coarse_c_9);
+    hades_tdc_bundle_inst_SLICE_456I: hades_tdc_bundle_inst_SLICE_456
+      port map (D0=>hades_hit_valid_c_1, C0=>hades_drop_cmp_buf_valid_c, 
+                B0=>hades_tdc_bundle_inst_hit_valid25, 
+                DI0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i, 
+                CE=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i, 
+                Q0=>hades_drop_cmp_buf_valid_c);
+    hades_tdc_bundle_inst_SLICE_457I: hades_tdc_bundle_inst_SLICE_457
+      port map (D1=>hades_hit_valid_c_0, B1=>hades_buf_release_c, 
+                D0=>hades_buf_release_c, C0=>hades_hit_valid_c_0, 
+                B0=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                A0=>hades_tdc_bundle_inst_hit_i_0, 
+                DI0=>hades_tdc_bundle_inst_N_246_i, 
+                M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, 
+                CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_246_i, 
+                Q0=>hades_hit_valid_c_0);
+    hades_tdc_bundle_inst_SLICE_458I: hades_tdc_bundle_inst_SLICE_458
+      port map (D1=>hades_buf_release_c, C1=>hades_tdc_bundle_inst_hit_valid25, 
+                B1=>hades_drop_cmp_buf_valid_c, D0=>hades_buf_release_c, 
+                C0=>hades_tdc_bundle_inst_hit_valid25, 
+                B0=>hades_drop_cmp_buf_valid_c, A0=>hades_tdc_bundle_inst_N_44, 
+                DI0=>hades_tdc_bundle_inst_N_243_i, M0=>hades_hit_valid_c_1, 
+                CE=>reset_dl_2, CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_N_243_i, Q0=>hades_hit_valid_c_1);
+    hades_tdc_bundle_inst_SLICE_459I: hades_tdc_bundle_inst_SLICE_459
+      port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                C1=>hades_buf_release_c, B1=>hades_tdc_bundle_inst_hit_i_0, 
+                A1=>hades_hit_valid_c_2, D0=>hades_hit_valid_c_2, 
+                C0=>hades_buf_release_c, DI0=>hades_tdc_bundle_inst_N_245_i, 
+                M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, 
+                CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_245_i, 
+                Q0=>hades_hit_valid_c_2);
+    hades_tdc_bundle_inst_SLICE_460I: hades_tdc_bundle_inst_SLICE_460
+      port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                C1=>hades_hit_valid_c_3, B1=>hades_buf_release_c, 
+                A1=>hades_tdc_bundle_inst_hit_i_0, D0=>hades_hit_valid_c_3, 
+                C0=>hades_buf_release_c, DI0=>hades_tdc_bundle_inst_N_244_i, 
+                M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, 
+                CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_244_i, 
+                Q0=>hades_hit_valid_c_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461
+      port map (M1=>hades_invalid_dl_c_1, M0=>hades_invalid_dl_c_0, 
+                CLK=>pll_clks_3, Q0=>hades_invalid_dl_c_1, 
+                Q1=>hades_invalid_dl_c_2);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462
+      port map (M0=>hades_invalid_dl_c_2, CLK=>pll_clks_3, 
+                Q0=>hades_invalid_dl_c_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                A0=>hades_discard_c, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i, 
+                Q0=>hades_offset_valid_c);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_0, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_1);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_2, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_12);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_13, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_14);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_15, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_16);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_17, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_18);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_19, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_20);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_21, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_22);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_23);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474
+      port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475
+      port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476
+      port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477
+      port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                , 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1
+                , 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290, 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0
+                , 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i
+                , 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506
+      port map (M1=>hades_lvl1_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515
+      port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516
+      port map (M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0, 
+                M0=>hades_discard_c, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                B1=>hades_discard_c, A1=>reset_dl_2, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                B0=>hades_discard_c, A0=>reset_dl_2, 
+                DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520
+      port map (D0=>hades_invalid_dl_c_2, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3, 
+                B0=>hades_invalid_dl_c_3, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , M0=>reset_dl_2, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2, 
+                CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0
+                , C1=>reset_dl_2, 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                A1=>hades_discard_c, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1
+                , C0=>reset_dl_2, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                A0=>hades_discard_c, 
+                DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0
+                , C1=>reset_dl_2, B1=>hades_discard_c, 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1
+                , C0=>reset_dl_2, B0=>hades_discard_c, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6, 
+                LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6, 
+                Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7, 
+                Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_3, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_4);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_5, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_6);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_7, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_8);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_9, 
+                Q1=>hades_tdc_bundle_inst_hades_raw_out_10);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_11);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, 
+                Q0=>hades_tdc_bundle_inst_hades_raw_out_valid);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530
+      port map (M1=>hades_dbg2_coarse_c_0, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531
+      port map (M1=>hades_dbg2_coarse_c_2, M0=>hades_dbg2_coarse_c_1, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532
+      port map (M1=>hades_dbg2_coarse_c_4, M0=>hades_dbg2_coarse_c_3, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533
+      port map (M1=>hades_dbg2_coarse_c_6, M0=>hades_dbg2_coarse_c_5, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534
+      port map (M1=>hades_dbg2_coarse_c_8, M0=>hades_dbg2_coarse_c_7, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4
+                , CE=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537
+      port map (M1=>hades_dbg2_coarse_c_0, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2
+                , 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538
+      port map (M1=>hades_dbg2_coarse_c_2, M0=>hades_dbg2_coarse_c_1, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539
+      port map (M1=>hades_dbg2_coarse_c_4, M0=>hades_dbg2_coarse_c_3, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540
+      port map (M1=>hades_dbg2_coarse_c_6, M0=>hades_dbg2_coarse_c_5, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541
+      port map (M1=>hades_dbg2_coarse_c_8, M0=>hades_dbg2_coarse_c_7, 
+                CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7, 
+                CE=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3
+                , 
+                DI1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5
+                , 
+                DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0
+                , 
+                LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i
+                , CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i
+                , 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576
+      port map (
+                M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1
+                , 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595
+      port map (M1=>hades_trig_c_i, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611
+      port map (M1=>hades_trig_c, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7
+                , 
+                Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4
+                , CLK=>pll_clks_0, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5
+                , CLK=>pll_clks_1, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6
+                , CLK=>pll_clks_2, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627
+      port map (
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7
+                , CLK=>pll_clks_3, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7
+                );
+    hades_tdc_bundle_inst_SLICE_628I: hades_tdc_bundle_inst_SLICE_628
+      port map (D1=>hades_tdc_bundle_inst_hit_i_0, 
+                C1=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                A1=>hades_tdc_bundle_inst_hit_i_1, 
+                C0=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                A0=>hades_tdc_bundle_inst_hit_i_0, 
+                DI1=>hades_tdc_bundle_inst_SUM1_0_0, 
+                DI0=>hades_tdc_bundle_inst_N_59_i, LSR=>reset_dl_2, 
+                CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_N_59_i, 
+                Q0=>hades_tdc_bundle_inst_hit_i_0, 
+                F1=>hades_tdc_bundle_inst_SUM1_0_0, 
+                Q1=>hades_tdc_bundle_inst_hit_i_1);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629
+      port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3
+                , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                CLK=>pll_clks_3, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5, 
+                Q0=>hades_window_end_c);
+    trb_adapter_inst_SLICE_631I: trb_adapter_inst_SLICE_631
+      port map (M1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, 
+                M0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0, 
+                CLK=>rd_clk_c, 
+                Q0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, 
+                Q1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2);
+    trb_adapter_inst_SLICE_632I: trb_adapter_inst_SLICE_632
+      port map (M0=>fifo_rden_c, CLK=>rd_clk_c, 
+                Q0=>trb_adapter_inst_buf_rden_prev);
+    trb_adapter_inst_SLICE_633I: trb_adapter_inst_SLICE_633
+      port map (M0=>finished_c, CLK=>rd_clk_c, 
+                Q0=>trb_adapter_inst_finished_prev);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634
+      port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, 
+                C1=>hades_discard_c, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                A0=>hades_discard_c, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635
+      port map (D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3
+                , M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_648I: fifo_colector_inst_fifo40_inst_SLICE_648
+      port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                C1=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                A1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                M0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, 
+                OFX0=>fifo_colector_inst_fifo40_inst_rcount_w2);
+
+      fifo_colector_inst_fifo40_inst_SLICE_649I: fifo_colector_inst_fifo40_inst_SLICE_649
+      port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                C1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                A1=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                M0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, 
+                OFX0=>fifo_colector_inst_fifo40_inst_rcount_w5);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                OFX0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651
+      port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                OFX0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652
+      port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, 
+                OFX0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0
+                );
+    hades_tdc_bundle_inst_SLICE_653I: hades_tdc_bundle_inst_SLICE_653
+      port map (D0=>ANB3, C0=>ANB0, B0=>ANB2, A0=>ANB1, M0=>reset_dl_2, 
+                OFX0=>N_248_i);
+    hades_tdc_bundle_inst_SLICE_654I: hades_tdc_bundle_inst_SLICE_654
+      port map (D1=>hades_tdc_bundle_inst_N_45, C1=>ANB1, B1=>ANB2, A1=>ANB3, 
+                D0=>hades_tdc_bundle_inst_N_66, C0=>hades_hit_valid_c_0, 
+                B0=>ANB2, A0=>hades_tdc_bundle_inst_N_80, 
+                F0=>hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0, 
+                F1=>hades_tdc_bundle_inst_N_66);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660
+      port map (
+                D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26
+                , 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4);
+
+      fifo_colector_inst_fifo40_inst_SLICE_673I: fifo_colector_inst_fifo40_inst_SLICE_673
+      port map (D1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                C1=>fifo_colector_inst_fifo40_inst_w_gcount_r20, 
+                B1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, 
+                A1=>fifo_colector_inst_fifo40_inst_w_gcount_r21, 
+                D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, 
+                C0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, 
+                B0=>fifo_colector_inst_fifo40_inst_w_gcount_r27, 
+                A0=>fifo_colector_inst_fifo40_inst_w_gcount_r26, 
+                F0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                F1=>fifo_colector_inst_fifo40_inst_wcount_r0);
+
+      fifo_colector_inst_fifo40_inst_SLICE_674I: fifo_colector_inst_fifo40_inst_SLICE_674
+      port map (D1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                C1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, 
+                B1=>fifo_colector_inst_fifo40_inst_w_gcount_r21, 
+                D0=>fifo_colector_inst_fifo40_inst_w_gcount_r22, 
+                C0=>fifo_colector_inst_fifo40_inst_w_gcount_r25, 
+                B0=>fifo_colector_inst_fifo40_inst_w_gcount_r23, 
+                A0=>fifo_colector_inst_fifo40_inst_w_gcount_r24, 
+                F0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, 
+                F1=>fifo_colector_inst_fifo40_inst_wcount_r1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_675I: fifo_colector_inst_fifo40_inst_SLICE_675
+      port map (D1=>fifo_colector_inst_fifo40_inst_wcount_r8, 
+                C1=>fifo_colector_inst_fifo40_inst_w_gcount_r27, 
+                B1=>fifo_colector_inst_fifo40_inst_w_gcount_r26, 
+                A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, 
+                D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, 
+                B0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, 
+                F0=>fifo_colector_inst_fifo40_inst_wcount_r8, 
+                F1=>fifo_colector_inst_fifo40_inst_wcount_r5);
+
+      fifo_colector_inst_fifo40_inst_SLICE_676I: fifo_colector_inst_fifo40_inst_SLICE_676
+      port map (D1=>fifo_colector_inst_fifo40_inst_wcount_r7, 
+                C1=>fifo_colector_inst_fifo40_inst_w_gcount_r26, 
+                B1=>fifo_colector_inst_fifo40_inst_w_gcount_r24, 
+                A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, 
+                D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, 
+                B0=>fifo_colector_inst_fifo40_inst_w_gcount_r27, 
+                A0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, 
+                F0=>fifo_colector_inst_fifo40_inst_wcount_r7, 
+                F1=>fifo_colector_inst_fifo40_inst_wcount_r4);
+
+      fifo_colector_inst_fifo40_inst_SLICE_677I: fifo_colector_inst_fifo40_inst_SLICE_677
+      port map (D1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, 
+                C1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w20, 
+                A1=>fifo_colector_inst_fifo40_inst_r_gcount_w21, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                F0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, 
+                F1=>fifo_colector_inst_fifo40_inst_rcount_w0);
+
+      fifo_colector_inst_fifo40_inst_SLICE_678I: fifo_colector_inst_fifo40_inst_SLICE_678
+      port map (D1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, 
+                C1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w21, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w23, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, 
+                B0=>fifo_colector_inst_fifo40_inst_r_gcount_w22, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, 
+                F0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, 
+                F1=>fifo_colector_inst_fifo40_inst_rcount_w1);
+
+      fifo_colector_inst_fifo40_inst_SLICE_679I: fifo_colector_inst_fifo40_inst_SLICE_679
+      port map (D1=>fifo_colector_inst_fifo40_inst_rcount_w7, 
+                C1=>fifo_colector_inst_fifo40_inst_r_gcount_w24, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, 
+                A1=>fifo_colector_inst_fifo40_inst_r_gcount_w25, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, 
+                B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                F0=>fifo_colector_inst_fifo40_inst_rcount_w7, 
+                F1=>fifo_colector_inst_fifo40_inst_rcount_w4);
+    fifo_colector_inst_SLICE_680I: fifo_colector_inst_SLICE_680
+      port map (D1=>fifo_colector_inst_iterator_0, C1=>fifo_empty1_c, 
+                A1=>fifo_empty_1, D0=>fifo_empty_2, 
+                B0=>fifo_colector_inst_iterator_1, 
+                A0=>fifo_colector_inst_in_empty_pmux_0, 
+                F0=>fifo_colector_inst_in_empty_pmux, 
+                F1=>fifo_colector_inst_in_empty_pmux_0);
+    hades_tdc_bundle_inst_SLICE_681I: hades_tdc_bundle_inst_SLICE_681
+      port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_2, 
+                B1=>hades_dbg2_coarse_c_0, 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7
+                , C0=>hades_dbg2_coarse_c_4, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_dbg2_coarse_c_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14
+                , F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682
+      port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3
+                , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                A0=>hades_discard_c, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c
+                , F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97);
+    hades_tdc_bundle_inst_SLICE_683I: hades_tdc_bundle_inst_SLICE_683
+      port map (D1=>ANB0, C1=>ANB1, A1=>ANB3, 
+                D0=>hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0, 
+                B0=>hades_tdc_bundle_inst_N_90, A0=>hades_hit_valid_c_3, 
+                F0=>hades_tdc_bundle_inst_buf_out12, 
+                F1=>hades_tdc_bundle_inst_N_90);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684
+      port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685
+      port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                );
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686
+      port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687
+      port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688
+      port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690
+      port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set
+                , 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr
+                );
+
+      fifo_colector_inst_fifo40_inst_SLICE_691I: fifo_colector_inst_fifo40_inst_SLICE_691
+      port map (C1=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                B1=>fifo_colector_inst_fifo40_inst_wptr_9, 
+                A1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                C0=>fifo_colector_inst_fifo40_inst_wcount_9, 
+                B0=>fifo_colector_inst_fifo40_inst_wptr_9, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                F0=>fifo_colector_inst_fifo40_inst_full_cmp_clr, 
+                F1=>fifo_colector_inst_fifo40_inst_full_cmp_set);
+
+      fifo_colector_inst_fifo40_inst_SLICE_692I: fifo_colector_inst_fifo40_inst_SLICE_692
+      port map (D1=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                C1=>fifo_colector_inst_fifo40_inst_rptr_9, 
+                A1=>fifo_colector_inst_fifo40_inst_w_gcount_r29, 
+                D0=>fifo_colector_inst_fifo40_inst_rcount_9, 
+                C0=>fifo_colector_inst_fifo40_inst_rptr_9, 
+                A0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, 
+                F0=>fifo_colector_inst_fifo40_inst_empty_cmp_set, 
+                F1=>fifo_colector_inst_fifo40_inst_empty_cmp_clr);
+    hades_tdc_bundle_inst_SLICE_693I: hades_tdc_bundle_inst_SLICE_693
+      port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                C1=>hades_tdc_bundle_inst_hit_i_1, 
+                B1=>hades_tdc_bundle_inst_hit_i_0, 
+                D0=>hades_tdc_bundle_inst_hades_raw_out_valid, 
+                C0=>hades_tdc_bundle_inst_hit_i_1, 
+                B0=>hades_tdc_bundle_inst_hit_i_0, A0=>reset_dl_2, 
+                F0=>un1_hit_i_2_0_a2, F1=>hades_tdc_bundle_inst_N_44);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0
+                , 
+                B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1
+                , 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697
+      port map (D1=>hades_dbg2_coarse_c_0, C1=>hades_dbg2_coarse_c_2, 
+                B1=>hades_dbg2_coarse_c_1, 
+                A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5
+                , D0=>hades_dbg2_coarse_c_0, 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5
+                , B0=>hades_dbg2_coarse_c_1, A0=>hades_dbg2_coarse_c_2, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19
+                , 
+                F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19
+                );
+    hades_tdc_bundle_inst_SLICE_698I: hades_tdc_bundle_inst_SLICE_698
+      port map (D1=>hades_dbg2_coarse_c_4, 
+                B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A1=>hades_dbg2_coarse_c_3, D0=>hades_dbg2_coarse_c_4, 
+                C0=>hades_dbg2_coarse_c_3, 
+                B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14
+                , F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3
+                , 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700
+      port map (
+                D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1
+                , 
+                C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0
+                , 
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2
+                , 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290, 
+                F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0
+                );
+    hades_tdc_bundle_inst_SLICE_701I: hades_tdc_bundle_inst_SLICE_701
+      port map (D1=>hades_dbg2_coarse_c_4, B1=>hades_dbg2_coarse_c_5, 
+                C0=>hades_dbg2_coarse_c_6, A0=>hades_dbg2_coarse_c_7, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0);
+
+      fifo_colector_inst_fifo40_inst_SLICE_702I: fifo_colector_inst_fifo40_inst_SLICE_702
+      port map (D1=>fifo_colector_inst_fifo40_inst_w_gcount_r24, 
+                C1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                B1=>fifo_colector_inst_fifo40_inst_w_gcount_r23, 
+                A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, 
+                D0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, 
+                C0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, 
+                F0=>fifo_colector_inst_fifo40_inst_wcount_r2, 
+                F1=>fifo_colector_inst_fifo40_inst_wcount_r3);
+
+      fifo_colector_inst_fifo40_inst_SLICE_703I: fifo_colector_inst_fifo40_inst_SLICE_703
+      port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, 
+                B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, 
+                D0=>fifo_colector_inst_fifo40_inst_r_gcount_w23, 
+                C0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, 
+                B0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, 
+                A0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, 
+                F0=>fifo_colector_inst_fifo40_inst_rcount_w3, 
+                F1=>fifo_colector_inst_fifo40_inst_rcount_w8);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704
+      port map (
+                C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705
+      port map (
+                D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707
+      port map (
+                D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708
+      port map (
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28
+                , 
+                A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709
+      port map (
+                C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28
+                , 
+                B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29
+                , 
+                D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0
+                , 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23
+                , 
+                B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25
+                , 
+                A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24
+                , 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, 
+                F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8);
+    hades_tdc_bundle_inst_SLICE_710I: hades_tdc_bundle_inst_SLICE_710
+      port map (D1=>hades_drop_cmp_buf_valid_c, 
+                C1=>hades_tdc_bundle_inst_hit_valid25, D0=>ANB0, 
+                C0=>hades_hit_valid_c_1, B0=>hades_hit_valid_c_2, 
+                F0=>hades_tdc_bundle_inst_N_45, 
+                F1=>hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa);
+
+      genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I: genblk1_2_tdc_channel_fifo_out_inst_SLICE_711
+      port map (D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_wren, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, 
+                M0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_wren);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712
+      port map (D0=>fifo_read_2, A0=>fifo_empty_2, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i);
+
+      genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713
+      port map (D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, 
+                C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                F0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                );
+
+      genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I: genblk1_1_tdc_channel_fifo_out_inst_SLICE_714
+      port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_wren, 
+                C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, 
+                M0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_wren);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715
+      port map (D0=>fifo_read_1, A0=>fifo_empty_1, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i);
+
+      genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716
+      port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, 
+                B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                F0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                );
+
+      genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I: genblk1_0_tdc_channel_fifo_out_inst_SLICE_717
+      port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_wren, 
+                C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, 
+                M0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_wren);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718
+      port map (B0=>fifo_read_0, A0=>fifo_empty1_c, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i);
+
+      genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719
+      port map (C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, 
+                A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, 
+                F0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i
+                );
+
+      fifo_colector_inst_fifo40_inst_SLICE_720I: fifo_colector_inst_fifo40_inst_SLICE_720
+      port map (D0=>last_buf_empty_c, C0=>fifo_rden_c, 
+                F0=>fifo_colector_inst_fifo40_inst_rden_i);
+
+      fifo_colector_inst_fifo40_inst_SLICE_721I: fifo_colector_inst_fifo40_inst_SLICE_721
+      port map (C0=>fifo_colector_inst_fifo40_inst_Full, 
+                B0=>fifo_colector_inst_buffer_wr_enable, 
+                F0=>fifo_colector_inst_fifo40_inst_wren_i);
+    fifo_colector_inst_SLICE_722I: fifo_colector_inst_SLICE_722
+      port map (D0=>fifo_colector_inst_iterator_1, A0=>fifo_empty_2, 
+                F0=>fifo_colector_inst_iterator_RNI7U5I_1);
+    trb_adapter_inst_SLICE_723I: trb_adapter_inst_SLICE_723
+      port map (D0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2, 
+                B0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, 
+                F0=>LVL1_TRG_DATA_VALI_IN_rising_c);
+    trb_adapter_inst_SLICE_724I: trb_adapter_inst_SLICE_724
+      port map (B0=>trb_adapter_inst_finished_prev, A0=>finished_c, 
+                M0=>trb_adapter_inst_buf_rden_prev, LSR=>fifo_rden_c, 
+                CLK=>rd_clk_c, F0=>release_out_c, Q0=>finished_c);
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready
+                , A0=>reset_dl_2, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730
+      port map (
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid
+                , C0=>reset_dl_2, 
+                M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, 
+                Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid
+                );
+
+      hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6
+                , 
+                C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3
+                , 
+                B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, 
+                B0=>reset_dl_2, A0=>hades_discard_c, F0=>valid_fast_RNI999V);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734
+      port map (
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3
+                , 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6
+                , 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5
+                , 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0, 
+                A0=>reset_dl_2, 
+                M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal
+                , CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0
+                , B0=>hades_discard_c, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1
+                , 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2
+                );
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738
+      port map (
+                D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1
+                , C0=>reset_dl_2, B0=>hades_discard_c, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2);
+
+      hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739
+      port map (D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, 
+                C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, 
+                B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, 
+                A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, 
+                F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0);
+    SLICE_740I: SLICE_740
+      port map (D0=>reset_dl_2, C0=>hades_hit_valid_c_1, M0=>reset_dl_1, 
+                CLK=>pll_clks_3, 
+                F0=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, 
+                Q0=>reset_dl_2);
+    hades_tdc_bundle_inst_SLICE_741I: hades_tdc_bundle_inst_SLICE_741
+      port map (C0=>hades_window_end_c, A0=>hades_discard_c, 
+                F0=>hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0);
+    pll0inst_SLICE_742I: pll0inst_SLICE_742
+      port map (F0=>pll0inst_GND);
+    SLICE_743I: SLICE_743
+      port map (D0=>hades_lvl1_c, F0=>hades_lvl1_c_i);
+    SLICE_744I: SLICE_744
+      port map (D0=>trig_c_0, F0=>trig_c_i_0);
+    SLICE_745I: SLICE_745
+      port map (D0=>trig_c_1, F0=>trig_c_i_1);
+    SLICE_746I: SLICE_746
+      port map (D0=>trig_c_2, F0=>trig_c_i_2);
+    SLICE_747I: SLICE_747
+      port map (A0=>hades_trig_c, F0=>hades_trig_c_i);
+    hades_raw_valid_vect_0_I: hades_raw_valid_vect_0_B
+      port map (hadesrawvalidvect0=>hades_raw_valid_vect(0));
+    fifo_data_out_0_I: fifo_data_out_0_B
+      port map (PADDO=>FEE_DATA_OUT_c_0, fifodataout0=>fifo_data_out(0));
+    clkI: clkB
+      port map (PADDI=>clk_c, clkS=>clk);
+    hades_drop_cmp_buf_validI: hades_drop_cmp_buf_validB
+      port map (PADDO=>hades_drop_cmp_buf_valid_c, 
+                hadesdropcmpbufvalid=>hades_drop_cmp_buf_valid);
+    hades_drop_cmp_buf_coarse_11_I: hades_drop_cmp_buf_coarse_11_B
+      port map (hadesdropcmpbufcoarse11=>hades_drop_cmp_buf_coarse(11));
+    hades_drop_cmp_buf_coarse_10_I: hades_drop_cmp_buf_coarse_10_B
+      port map (hadesdropcmpbufcoarse10=>hades_drop_cmp_buf_coarse(10));
+    hades_drop_cmp_buf_coarse_9_I: hades_drop_cmp_buf_coarse_9_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_9, 
+                hadesdropcmpbufcoarse9=>hades_drop_cmp_buf_coarse(9));
+    hades_drop_cmp_buf_coarse_8_I: hades_drop_cmp_buf_coarse_8_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_8, 
+                hadesdropcmpbufcoarse8=>hades_drop_cmp_buf_coarse(8));
+    hades_drop_cmp_buf_coarse_7_I: hades_drop_cmp_buf_coarse_7_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_7, 
+                hadesdropcmpbufcoarse7=>hades_drop_cmp_buf_coarse(7));
+    hades_drop_cmp_buf_coarse_6_I: hades_drop_cmp_buf_coarse_6_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_6, 
+                hadesdropcmpbufcoarse6=>hades_drop_cmp_buf_coarse(6));
+    hades_drop_cmp_buf_coarse_5_I: hades_drop_cmp_buf_coarse_5_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_5, 
+                hadesdropcmpbufcoarse5=>hades_drop_cmp_buf_coarse(5));
+    hades_drop_cmp_buf_coarse_4_I: hades_drop_cmp_buf_coarse_4_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_4, 
+                hadesdropcmpbufcoarse4=>hades_drop_cmp_buf_coarse(4));
+    hades_drop_cmp_buf_coarse_3_I: hades_drop_cmp_buf_coarse_3_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_3, 
+                hadesdropcmpbufcoarse3=>hades_drop_cmp_buf_coarse(3));
+    hades_drop_cmp_buf_coarse_2_I: hades_drop_cmp_buf_coarse_2_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_2, 
+                hadesdropcmpbufcoarse2=>hades_drop_cmp_buf_coarse(2));
+    hades_drop_cmp_buf_coarse_1_I: hades_drop_cmp_buf_coarse_1_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_1, 
+                hadesdropcmpbufcoarse1=>hades_drop_cmp_buf_coarse(1));
+    hades_drop_cmp_buf_coarse_0_I: hades_drop_cmp_buf_coarse_0_B
+      port map (PADDO=>hades_drop_cmp_buf_coarse_c_0, 
+                hadesdropcmpbufcoarse0=>hades_drop_cmp_buf_coarse(0));
+    hades_drop_cmp_buf_11_I: hades_drop_cmp_buf_11_B
+      port map (hadesdropcmpbuf11=>hades_drop_cmp_buf(11));
+    hades_drop_cmp_buf_10_I: hades_drop_cmp_buf_10_B
+      port map (hadesdropcmpbuf10=>hades_drop_cmp_buf(10));
+    hades_drop_cmp_buf_9_I: hades_drop_cmp_buf_9_B
+      port map (hadesdropcmpbuf9=>hades_drop_cmp_buf(9));
+    hades_drop_cmp_buf_8_I: hades_drop_cmp_buf_8_B
+      port map (PADDO=>hades_drop_cmp_buf_c_8, 
+                hadesdropcmpbuf8=>hades_drop_cmp_buf(8));
+    hades_drop_cmp_buf_7_I: hades_drop_cmp_buf_7_B
+      port map (PADDO=>hades_drop_cmp_buf_c_7, 
+                hadesdropcmpbuf7=>hades_drop_cmp_buf(7));
+    hades_drop_cmp_buf_6_I: hades_drop_cmp_buf_6_B
+      port map (PADDO=>hades_drop_cmp_buf_c_6, 
+                hadesdropcmpbuf6=>hades_drop_cmp_buf(6));
+    hades_drop_cmp_buf_5_I: hades_drop_cmp_buf_5_B
+      port map (PADDO=>hades_drop_cmp_buf_c_5, 
+                hadesdropcmpbuf5=>hades_drop_cmp_buf(5));
+    hades_drop_cmp_buf_4_I: hades_drop_cmp_buf_4_B
+      port map (PADDO=>hades_drop_cmp_buf_c_4, 
+                hadesdropcmpbuf4=>hades_drop_cmp_buf(4));
+    hades_drop_cmp_buf_3_I: hades_drop_cmp_buf_3_B
+      port map (PADDO=>hades_drop_cmp_buf_c_3, 
+                hadesdropcmpbuf3=>hades_drop_cmp_buf(3));
+    hades_drop_cmp_buf_2_I: hades_drop_cmp_buf_2_B
+      port map (PADDO=>hades_drop_cmp_buf_c_2, 
+                hadesdropcmpbuf2=>hades_drop_cmp_buf(2));
+    hades_drop_cmp_buf_1_I: hades_drop_cmp_buf_1_B
+      port map (PADDO=>hades_drop_cmp_buf_c_1, 
+                hadesdropcmpbuf1=>hades_drop_cmp_buf(1));
+    hades_drop_cmp_buf_0_I: hades_drop_cmp_buf_0_B
+      port map (PADDO=>hades_drop_cmp_buf_c_0, 
+                hadesdropcmpbuf0=>hades_drop_cmp_buf(0));
+    hades_dbg2_coarse_8_I: hades_dbg2_coarse_8_B
+      port map (PADDO=>hades_dbg2_coarse_c_8, 
+                hadesdbg2coarse8=>hades_dbg2_coarse(8));
+    hades_dbg2_coarse_7_I: hades_dbg2_coarse_7_B
+      port map (PADDO=>hades_dbg2_coarse_c_7, 
+                hadesdbg2coarse7=>hades_dbg2_coarse(7));
+    hades_dbg2_coarse_6_I: hades_dbg2_coarse_6_B
+      port map (PADDO=>hades_dbg2_coarse_c_6, 
+                hadesdbg2coarse6=>hades_dbg2_coarse(6));
+    hades_dbg2_coarse_5_I: hades_dbg2_coarse_5_B
+      port map (PADDO=>hades_dbg2_coarse_c_5, 
+                hadesdbg2coarse5=>hades_dbg2_coarse(5));
+    hades_dbg2_coarse_4_I: hades_dbg2_coarse_4_B
+      port map (PADDO=>hades_dbg2_coarse_c_4, 
+                hadesdbg2coarse4=>hades_dbg2_coarse(4));
+    hades_dbg2_coarse_3_I: hades_dbg2_coarse_3_B
+      port map (PADDO=>hades_dbg2_coarse_c_3, 
+                hadesdbg2coarse3=>hades_dbg2_coarse(3));
+    hades_dbg2_coarse_2_I: hades_dbg2_coarse_2_B
+      port map (PADDO=>hades_dbg2_coarse_c_2, 
+                hadesdbg2coarse2=>hades_dbg2_coarse(2));
+    hades_dbg2_coarse_1_I: hades_dbg2_coarse_1_B
+      port map (PADDO=>hades_dbg2_coarse_c_1, 
+                hadesdbg2coarse1=>hades_dbg2_coarse(1));
+    hades_dbg2_coarse_0_I: hades_dbg2_coarse_0_B
+      port map (PADDO=>hades_dbg2_coarse_c_0, 
+                hadesdbg2coarse0=>hades_dbg2_coarse(0));
+    hades_dbg2_out_31_I: hades_dbg2_out_31_B
+      port map (hadesdbg2out31=>hades_dbg2_out(31));
+    hades_dbg2_out_30_I: hades_dbg2_out_30_B
+      port map (hadesdbg2out30=>hades_dbg2_out(30));
+    hades_dbg2_out_29_I: hades_dbg2_out_29_B
+      port map (hadesdbg2out29=>hades_dbg2_out(29));
+    hades_dbg2_out_28_I: hades_dbg2_out_28_B
+      port map (IOLDO=>hades_dbg2_out_c_28, hadesdbg2out28=>hades_dbg2_out(28));
+    hades_dbg2_out_28_MGIOLI: hades_dbg2_out_28_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_28, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_23, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_27_I: hades_dbg2_out_27_B
+      port map (IOLDO=>hades_dbg2_out_c_27, hadesdbg2out27=>hades_dbg2_out(27));
+    hades_dbg2_out_27_MGIOLI: hades_dbg2_out_27_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_27, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_22, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_26_I: hades_dbg2_out_26_B
+      port map (IOLDO=>hades_dbg2_out_c_26, hadesdbg2out26=>hades_dbg2_out(26));
+    hades_dbg2_out_26_MGIOLI: hades_dbg2_out_26_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_26, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_21, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_25_I: hades_dbg2_out_25_B
+      port map (IOLDO=>hades_dbg2_out_c_25, hadesdbg2out25=>hades_dbg2_out(25));
+    hades_dbg2_out_25_MGIOLI: hades_dbg2_out_25_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_25, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_20, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_24_I: hades_dbg2_out_24_B
+      port map (IOLDO=>hades_dbg2_out_c_24, hadesdbg2out24=>hades_dbg2_out(24));
+    hades_dbg2_out_24_MGIOLI: hades_dbg2_out_24_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_24, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_19, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_23_I: hades_dbg2_out_23_B
+      port map (IOLDO=>hades_dbg2_out_c_23, hadesdbg2out23=>hades_dbg2_out(23));
+    hades_dbg2_out_23_MGIOLI: hades_dbg2_out_23_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_23, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_18, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_22_I: hades_dbg2_out_22_B
+      port map (IOLDO=>hades_dbg2_out_c_22, hadesdbg2out22=>hades_dbg2_out(22));
+    hades_dbg2_out_22_MGIOLI: hades_dbg2_out_22_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_22, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_17, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_21_I: hades_dbg2_out_21_B
+      port map (IOLDO=>hades_dbg2_out_c_21, hadesdbg2out21=>hades_dbg2_out(21));
+    hades_dbg2_out_21_MGIOLI: hades_dbg2_out_21_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_21, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_16, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_20_I: hades_dbg2_out_20_B
+      port map (IOLDO=>hades_dbg2_out_c_20, hadesdbg2out20=>hades_dbg2_out(20));
+    hades_dbg2_out_20_MGIOLI: hades_dbg2_out_20_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_20, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_15, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_19_I: hades_dbg2_out_19_B
+      port map (hadesdbg2out19=>hades_dbg2_out(19));
+    hades_dbg2_out_18_I: hades_dbg2_out_18_B
+      port map (IOLDO=>hades_dbg2_out_c_18, hadesdbg2out18=>hades_dbg2_out(18));
+    hades_dbg2_out_18_MGIOLI: hades_dbg2_out_18_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_18, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_14, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_17_I: hades_dbg2_out_17_B
+      port map (IOLDO=>hades_dbg2_out_c_17, hadesdbg2out17=>hades_dbg2_out(17));
+    hades_dbg2_out_17_MGIOLI: hades_dbg2_out_17_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_17, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_13, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_16_I: hades_dbg2_out_16_B
+      port map (IOLDO=>hades_dbg2_out_c_16, hadesdbg2out16=>hades_dbg2_out(16));
+    hades_dbg2_out_16_MGIOLI: hades_dbg2_out_16_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_16, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_12, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_15_I: hades_dbg2_out_15_B
+      port map (hadesdbg2out15=>hades_dbg2_out(15));
+    hades_dbg2_out_14_I: hades_dbg2_out_14_B
+      port map (hadesdbg2out14=>hades_dbg2_out(14));
+    hades_dbg2_out_13_I: hades_dbg2_out_13_B
+      port map (hadesdbg2out13=>hades_dbg2_out(13));
+    hades_dbg2_out_12_I: hades_dbg2_out_12_B
+      port map (PADDO=>hades_dbg2_out_c_12, hadesdbg2out12=>hades_dbg2_out(12));
+    hades_dbg2_out_11_I: hades_dbg2_out_11_B
+      port map (PADDO=>hades_dbg2_out_c_11, hadesdbg2out11=>hades_dbg2_out(11));
+    hades_dbg2_out_10_I: hades_dbg2_out_10_B
+      port map (PADDO=>hades_dbg2_out_c_10, hadesdbg2out10=>hades_dbg2_out(10));
+    hades_dbg2_out_9_I: hades_dbg2_out_9_B
+      port map (PADDO=>hades_dbg2_out_c_9, hadesdbg2out9=>hades_dbg2_out(9));
+    hades_dbg2_out_8_I: hades_dbg2_out_8_B
+      port map (PADDO=>hades_dbg2_out_c_8, hadesdbg2out8=>hades_dbg2_out(8));
+    hades_dbg2_out_7_I: hades_dbg2_out_7_B
+      port map (PADDO=>hades_dbg2_out_c_7, hadesdbg2out7=>hades_dbg2_out(7));
+    hades_dbg2_out_6_I: hades_dbg2_out_6_B
+      port map (PADDO=>hades_dbg2_out_c_6, hadesdbg2out6=>hades_dbg2_out(6));
+    hades_dbg2_out_5_I: hades_dbg2_out_5_B
+      port map (PADDO=>hades_dbg2_out_c_5, hadesdbg2out5=>hades_dbg2_out(5));
+    hades_dbg2_out_4_I: hades_dbg2_out_4_B
+      port map (PADDO=>hades_dbg2_out_c_4, hadesdbg2out4=>hades_dbg2_out(4));
+    hades_dbg2_out_3_I: hades_dbg2_out_3_B
+      port map (hadesdbg2out3=>hades_dbg2_out(3));
+    hades_dbg2_out_2_I: hades_dbg2_out_2_B
+      port map (IOLDO=>hades_dbg2_out_c_2, hadesdbg2out2=>hades_dbg2_out(2));
+    hades_dbg2_out_2_MGIOLI: hades_dbg2_out_2_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_2, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_2, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_1_I: hades_dbg2_out_1_B
+      port map (IOLDO=>hades_dbg2_out_c_1, hadesdbg2out1=>hades_dbg2_out(1));
+    hades_dbg2_out_1_MGIOLI: hades_dbg2_out_1_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_1, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_1, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_dbg2_out_0_I: hades_dbg2_out_0_B
+      port map (IOLDO=>hades_dbg2_out_c_0, hadesdbg2out0=>hades_dbg2_out(0));
+    hades_dbg2_out_0_MGIOLI: hades_dbg2_out_0_MGIOL
+      port map (IOLDO=>hades_dbg2_out_c_0, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_0, 
+                CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3);
+    hades_buf_drop_3_I: hades_buf_drop_3_B
+      port map (hadesbufdrop3=>hades_buf_drop(3));
+    hades_buf_drop_2_I: hades_buf_drop_2_B
+      port map (hadesbufdrop2=>hades_buf_drop(2));
+    hades_buf_drop_1_I: hades_buf_drop_1_B
+      port map (IOLDO=>hades_buf_drop_c_1, hadesbufdrop1=>hades_buf_drop(1));
+    hades_buf_drop_1_MGIOLI: hades_buf_drop_1_MGIOL
+      port map (IOLDO=>hades_buf_drop_c_1, 
+                TXDATA0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa, 
+                LSR=>reset_dl_2, CLK=>pll_clks_3);
+    hades_buf_drop_0_I: hades_buf_drop_0_B
+      port map (hadesbufdrop0=>hades_buf_drop(0));
+    hades_invalid_dl_3_I: hades_invalid_dl_3_B
+      port map (PADDO=>hades_invalid_dl_c_3, 
+                hadesinvaliddl3=>hades_invalid_dl(3));
+    hades_invalid_dl_2_I: hades_invalid_dl_2_B
+      port map (PADDO=>hades_invalid_dl_c_2, 
+                hadesinvaliddl2=>hades_invalid_dl(2));
+    hades_invalid_dl_1_I: hades_invalid_dl_1_B
+      port map (PADDO=>hades_invalid_dl_c_1, 
+                hadesinvaliddl1=>hades_invalid_dl(1));
+    hades_invalid_dl_0_I: hades_invalid_dl_0_B
+      port map (PADDO=>hades_invalid_dl_c_0, 
+                hadesinvaliddl0=>hades_invalid_dl(0));
+    hades_discardI: hades_discardB
+      port map (PADDO=>hades_discard_c, hadesdiscard=>hades_discard);
+    hades_hit_valid_3_I: hades_hit_valid_3_B
+      port map (PADDO=>hades_hit_valid_c_3, hadeshitvalid3=>hades_hit_valid(3));
+    hades_hit_valid_2_I: hades_hit_valid_2_B
+      port map (PADDO=>hades_hit_valid_c_2, hadeshitvalid2=>hades_hit_valid(2));
+    hades_hit_valid_1_I: hades_hit_valid_1_B
+      port map (PADDO=>hades_hit_valid_c_1, hadeshitvalid1=>hades_hit_valid(1));
+    hades_hit_valid_0_I: hades_hit_valid_0_B
+      port map (PADDO=>hades_hit_valid_c_0, hadeshitvalid0=>hades_hit_valid(0));
+    hades_hit_out_i_3_I: hades_hit_out_i_3_B
+      port map (PADDO=>ANB3, hadeshitouti3=>hades_hit_out_i(3));
+    hades_hit_out_i_2_I: hades_hit_out_i_2_B
+      port map (PADDO=>ANB2, hadeshitouti2=>hades_hit_out_i(2));
+    hades_hit_out_i_1_I: hades_hit_out_i_1_B
+      port map (PADDO=>ANB1, hadeshitouti1=>hades_hit_out_i(1));
+    hades_hit_out_i_0_I: hades_hit_out_i_0_B
+      port map (PADDO=>ANB0, hadeshitouti0=>hades_hit_out_i(0));
+    hades_buf_finishedI: hades_buf_finishedB
+      port map (PADDO=>hades_buf_finished_c, 
+                hadesbuffinished=>hades_buf_finished);
+    hades_buf_releaseI: hades_buf_releaseB
+      port map (PADDO=>hades_buf_release_c, hadesbufrelease=>hades_buf_release);
+    hades_buf_out_validI: hades_buf_out_validB
+      port map (IOLDO=>hades_buf_out_valid_c, 
+                hadesbufoutvalid=>hades_buf_out_valid);
+    hades_buf_out_valid_MGIOLI: hades_buf_out_valid_MGIOL
+      port map (IOLDO=>hades_buf_out_valid_c, 
+                TXDATA0=>hades_tdc_bundle_inst_buf_out12, CE=>N_248_i, 
+                CLK=>pll_clks_3);
+    hades_window_endI: hades_window_endB
+      port map (PADDO=>hades_window_end_c, hadeswindowend=>hades_window_end);
+    hades_offset_validI: hades_offset_validB
+      port map (PADDO=>hades_offset_valid_c, 
+                hadesoffsetvalid=>hades_offset_valid);
+    hades_offset_8_I: hades_offset_8_B
+      port map (IOLDO=>hades_offset_c_8, hadesoffset8=>hades_offset(8));
+    hades_offset_8_MGIOLI: hades_offset_8_MGIOL
+      port map (IOLDO=>hades_offset_c_8, TXDATA0=>hades_dbg2_coarse_c_5, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_7_I: hades_offset_7_B
+      port map (IOLDO=>hades_offset_c_7, hadesoffset7=>hades_offset(7));
+    hades_offset_7_MGIOLI: hades_offset_7_MGIOL
+      port map (IOLDO=>hades_offset_c_7, TXDATA0=>hades_dbg2_coarse_c_4, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_6_I: hades_offset_6_B
+      port map (IOLDO=>hades_offset_c_6, hadesoffset6=>hades_offset(6));
+    hades_offset_6_MGIOLI: hades_offset_6_MGIOL
+      port map (IOLDO=>hades_offset_c_6, TXDATA0=>hades_dbg2_coarse_c_3, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_5_I: hades_offset_5_B
+      port map (IOLDO=>hades_offset_c_5, hadesoffset5=>hades_offset(5));
+    hades_offset_5_MGIOLI: hades_offset_5_MGIOL
+      port map (IOLDO=>hades_offset_c_5, TXDATA0=>hades_dbg2_coarse_c_2, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_4_I: hades_offset_4_B
+      port map (IOLDO=>hades_offset_c_4, hadesoffset4=>hades_offset(4));
+    hades_offset_4_MGIOLI: hades_offset_4_MGIOL
+      port map (IOLDO=>hades_offset_c_4, TXDATA0=>hades_dbg2_coarse_c_1, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_3_I: hades_offset_3_B
+      port map (IOLDO=>hades_offset_c_3, hadesoffset3=>hades_offset(3));
+    hades_offset_3_MGIOLI: hades_offset_3_MGIOL
+      port map (IOLDO=>hades_offset_c_3, TXDATA0=>hades_dbg2_coarse_c_0, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_2_I: hades_offset_2_B
+      port map (IOLDO=>hades_offset_c_2, hadesoffset2=>hades_offset(2));
+    hades_offset_2_MGIOLI: hades_offset_2_MGIOL
+      port map (IOLDO=>hades_offset_c_2, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_1_I: hades_offset_1_B
+      port map (IOLDO=>hades_offset_c_1, hadesoffset1=>hades_offset(1));
+    hades_offset_1_MGIOLI: hades_offset_1_MGIOL
+      port map (IOLDO=>hades_offset_c_1, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_offset_0_I: hades_offset_0_B
+      port map (IOLDO=>hades_offset_c_0, hadesoffset0=>hades_offset(0));
+    hades_offset_0_MGIOLI: hades_offset_0_MGIOL
+      port map (IOLDO=>hades_offset_c_0, 
+                TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0, 
+                CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0
+                , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3);
+    hades_lvl1_invalidI: hades_lvl1_invalidB
+      port map (PADDI=>hades_lvl1_invalid_c, 
+                hadeslvl1invalid=>hades_lvl1_invalid);
+    hades_lvl1_invalid_MGIOLI: hades_lvl1_invalid_MGIOL
+      port map (DI=>hades_lvl1_invalid_c, CLK=>pll_clks_3, 
+                INFF=>hades_invalid_dl_c_0);
+    hades_lvl1I: hades_lvl1B
+      port map (PADDI=>hades_lvl1_c, hadeslvl1=>hades_lvl1);
+    hades_lvl1_MGIOLI: hades_lvl1_MGIOL
+      port map (DI=>hades_lvl1_c, CLK=>pll_clks_3, 
+                INFF=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0);
+    hades_raw_valid_vect_1_I: hades_raw_valid_vect_1_B
+      port map (hadesrawvalidvect1=>hades_raw_valid_vect(1));
+    hades_raw_out_validI: hades_raw_out_validB
+      port map (IOLDO=>hades_raw_out_valid_c, 
+                hadesrawoutvalid=>hades_raw_out_valid);
+    hades_raw_out_valid_MGIOLI: hades_raw_out_valid_MGIOL
+      port map (IOLDO=>hades_raw_out_valid_c, TXDATA0=>hades_offset_valid_c, 
+                CLK=>pll_clks_3);
+    hades_trigI: hades_trigB
+      port map (PADDI=>hades_trig_c, hadestrig=>hades_trig);
+    release_outI: release_outB
+      port map (PADDO=>release_out_c, releaseout=>release_out);
+    finishedI: finishedB
+      port map (PADDO=>finished_c, finishedS=>finished);
+    last_buf_emptyI: last_buf_emptyB
+      port map (PADDO=>last_buf_empty_c, lastbufempty=>last_buf_empty);
+    discardI: discardB
+      port map (PADDO=>discard_c, discardS=>discard);
+    burstI: burstB
+      port map (PADDO=>burst_c, burstS=>burst);
+    LVL1_TRG_DATA_VALI_IN_risingI: LVL1_TRG_DATA_VALI_IN_risingB
+      port map (PADDO=>LVL1_TRG_DATA_VALI_IN_rising_c, 
+                LVL1TRGDATAVALIINrising=>LVL1_TRG_DATA_VALI_IN_rising);
+    FEE_TRG_RELEASE_OUTI: FEE_TRG_RELEASE_OUTB
+      port map (IOLDO=>FEE_TRG_RELEASE_OUT_c, 
+                FEETRGRELEASEOUT=>FEE_TRG_RELEASE_OUT);
+    FEE_TRG_RELEASE_OUT_MGIOLI: FEE_TRG_RELEASE_OUT_MGIOL
+      port map (IOLDO=>FEE_TRG_RELEASE_OUT_c, TXDATA0=>release_out_c, 
+                LSR=>reset_dl_2, CLK=>rd_clk_c);
+    FEE_DATAFINISHED_OUTI: FEE_DATAFINISHED_OUTB
+      port map (IOLDO=>FEE_DATAFINISHED_OUT_c, 
+                FEEDATAFINISHEDOUT=>FEE_DATAFINISHED_OUT);
+    FEE_DATAFINISHED_OUT_MGIOLI: FEE_DATAFINISHED_OUT_MGIOL
+      port map (IOLDO=>FEE_DATAFINISHED_OUT_c, TXDATA0=>finished_c, 
+                LSR=>reset_dl_2, CLK=>rd_clk_c);
+    FEE_DATA_WRITE_OUTI: FEE_DATA_WRITE_OUTB
+      port map (IOLDO=>FEE_DATA_WRITE_OUT_c, 
+                FEEDATAWRITEOUT=>FEE_DATA_WRITE_OUT);
+    FEE_DATA_WRITE_OUT_MGIOLI: FEE_DATA_WRITE_OUT_MGIOL
+      port map (IOLDO=>FEE_DATA_WRITE_OUT_c, TXDATA0=>fifo_rden_c, 
+                LSR=>reset_dl_2, CLK=>rd_clk_c);
+    FEE_DATA_OUT_31_I: FEE_DATA_OUT_31_B
+      port map (PADDO=>FEE_DATA_OUT_c_31, FEEDATAOUT31=>FEE_DATA_OUT(31));
+    FEE_DATA_OUT_30_I: FEE_DATA_OUT_30_B
+      port map (PADDO=>FEE_DATA_OUT_c_30, FEEDATAOUT30=>FEE_DATA_OUT(30));
+    FEE_DATA_OUT_29_I: FEE_DATA_OUT_29_B
+      port map (PADDO=>FEE_DATA_OUT_c_29, FEEDATAOUT29=>FEE_DATA_OUT(29));
+    FEE_DATA_OUT_28_I: FEE_DATA_OUT_28_B
+      port map (PADDO=>FEE_DATA_OUT_c_28, FEEDATAOUT28=>FEE_DATA_OUT(28));
+    FEE_DATA_OUT_27_I: FEE_DATA_OUT_27_B
+      port map (PADDO=>FEE_DATA_OUT_c_27, FEEDATAOUT27=>FEE_DATA_OUT(27));
+    FEE_DATA_OUT_26_I: FEE_DATA_OUT_26_B
+      port map (PADDO=>FEE_DATA_OUT_c_26, FEEDATAOUT26=>FEE_DATA_OUT(26));
+    FEE_DATA_OUT_25_I: FEE_DATA_OUT_25_B
+      port map (PADDO=>FEE_DATA_OUT_c_25, FEEDATAOUT25=>FEE_DATA_OUT(25));
+    FEE_DATA_OUT_24_I: FEE_DATA_OUT_24_B
+      port map (PADDO=>FEE_DATA_OUT_c_24, FEEDATAOUT24=>FEE_DATA_OUT(24));
+    FEE_DATA_OUT_23_I: FEE_DATA_OUT_23_B
+      port map (PADDO=>FEE_DATA_OUT_c_23, FEEDATAOUT23=>FEE_DATA_OUT(23));
+    FEE_DATA_OUT_22_I: FEE_DATA_OUT_22_B
+      port map (PADDO=>FEE_DATA_OUT_c_22, FEEDATAOUT22=>FEE_DATA_OUT(22));
+    FEE_DATA_OUT_21_I: FEE_DATA_OUT_21_B
+      port map (PADDO=>FEE_DATA_OUT_c_21, FEEDATAOUT21=>FEE_DATA_OUT(21));
+    FEE_DATA_OUT_20_I: FEE_DATA_OUT_20_B
+      port map (PADDO=>FEE_DATA_OUT_c_20, FEEDATAOUT20=>FEE_DATA_OUT(20));
+    FEE_DATA_OUT_19_I: FEE_DATA_OUT_19_B
+      port map (PADDO=>FEE_DATA_OUT_c_19, FEEDATAOUT19=>FEE_DATA_OUT(19));
+    FEE_DATA_OUT_18_I: FEE_DATA_OUT_18_B
+      port map (PADDO=>FEE_DATA_OUT_c_18, FEEDATAOUT18=>FEE_DATA_OUT(18));
+    FEE_DATA_OUT_17_I: FEE_DATA_OUT_17_B
+      port map (PADDO=>FEE_DATA_OUT_c_17, FEEDATAOUT17=>FEE_DATA_OUT(17));
+    FEE_DATA_OUT_16_I: FEE_DATA_OUT_16_B
+      port map (PADDO=>FEE_DATA_OUT_c_16, FEEDATAOUT16=>FEE_DATA_OUT(16));
+    FEE_DATA_OUT_15_I: FEE_DATA_OUT_15_B
+      port map (PADDO=>FEE_DATA_OUT_c_15, FEEDATAOUT15=>FEE_DATA_OUT(15));
+    FEE_DATA_OUT_14_I: FEE_DATA_OUT_14_B
+      port map (PADDO=>FEE_DATA_OUT_c_14, FEEDATAOUT14=>FEE_DATA_OUT(14));
+    FEE_DATA_OUT_13_I: FEE_DATA_OUT_13_B
+      port map (PADDO=>FEE_DATA_OUT_c_13, FEEDATAOUT13=>FEE_DATA_OUT(13));
+    FEE_DATA_OUT_12_I: FEE_DATA_OUT_12_B
+      port map (PADDO=>FEE_DATA_OUT_c_12, FEEDATAOUT12=>FEE_DATA_OUT(12));
+    FEE_DATA_OUT_11_I: FEE_DATA_OUT_11_B
+      port map (PADDO=>FEE_DATA_OUT_c_11, FEEDATAOUT11=>FEE_DATA_OUT(11));
+    FEE_DATA_OUT_10_I: FEE_DATA_OUT_10_B
+      port map (PADDO=>FEE_DATA_OUT_c_10, FEEDATAOUT10=>FEE_DATA_OUT(10));
+    FEE_DATA_OUT_9_I: FEE_DATA_OUT_9_B
+      port map (PADDO=>FEE_DATA_OUT_c_9, FEEDATAOUT9=>FEE_DATA_OUT(9));
+    FEE_DATA_OUT_8_I: FEE_DATA_OUT_8_B
+      port map (PADDO=>FEE_DATA_OUT_c_8, FEEDATAOUT8=>FEE_DATA_OUT(8));
+    FEE_DATA_OUT_7_I: FEE_DATA_OUT_7_B
+      port map (PADDO=>FEE_DATA_OUT_c_7, FEEDATAOUT7=>FEE_DATA_OUT(7));
+    FEE_DATA_OUT_6_I: FEE_DATA_OUT_6_B
+      port map (PADDO=>FEE_DATA_OUT_c_6, FEEDATAOUT6=>FEE_DATA_OUT(6));
+    FEE_DATA_OUT_5_I: FEE_DATA_OUT_5_B
+      port map (PADDO=>FEE_DATA_OUT_c_5, FEEDATAOUT5=>FEE_DATA_OUT(5));
+    FEE_DATA_OUT_4_I: FEE_DATA_OUT_4_B
+      port map (PADDO=>FEE_DATA_OUT_c_4, FEEDATAOUT4=>FEE_DATA_OUT(4));
+    FEE_DATA_OUT_3_I: FEE_DATA_OUT_3_B
+      port map (PADDO=>FEE_DATA_OUT_c_3, FEEDATAOUT3=>FEE_DATA_OUT(3));
+    FEE_DATA_OUT_2_I: FEE_DATA_OUT_2_B
+      port map (PADDO=>FEE_DATA_OUT_c_2, FEEDATAOUT2=>FEE_DATA_OUT(2));
+    FEE_DATA_OUT_1_I: FEE_DATA_OUT_1_B
+      port map (PADDO=>FEE_DATA_OUT_c_1, FEEDATAOUT1=>FEE_DATA_OUT(1));
+    FEE_DATA_OUT_0_I: FEE_DATA_OUT_0_B
+      port map (PADDO=>FEE_DATA_OUT_c_0, FEEDATAOUT0=>FEE_DATA_OUT(0));
+    LVL1_INVALID_TRG_INI: LVL1_INVALID_TRG_INB
+      port map (PADDI=>LVL1_INVALID_TRG_IN_c, 
+                LVL1INVALIDTRGIN=>LVL1_INVALID_TRG_IN);
+    LVL1_INVALID_TRG_IN_MGIOLI: LVL1_INVALID_TRG_IN_MGIOL
+      port map (DI=>LVL1_INVALID_TRG_IN_c, CLK=>rd_clk_c, 
+                INFF=>trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0);
+    LVL1_TRG_DATA_VALID_INI: LVL1_TRG_DATA_VALID_INB
+      port map (PADDI=>LVL1_TRG_DATA_VALID_IN_c, 
+                LVL1TRGDATAVALIDIN=>LVL1_TRG_DATA_VALID_IN);
+    LVL1_TRG_DATA_VALID_IN_MGIOLI: LVL1_TRG_DATA_VALID_IN_MGIOL
+      port map (DI=>LVL1_TRG_DATA_VALID_IN_c, CLK=>rd_clk_c, 
+                INFF=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0);
+    fifo_empty1I: fifo_empty1B
+      port map (PADDO=>fifo_empty1_c, fifoempty1=>fifo_empty1);
+    fifo_rdenI: fifo_rdenB
+      port map (PADDO=>fifo_rden_c, fiforden=>fifo_rden);
+    fifo_data_out_31_I: fifo_data_out_31_B
+      port map (PADDO=>FEE_DATA_OUT_c_31, fifodataout31=>fifo_data_out(31));
+    fifo_data_out_30_I: fifo_data_out_30_B
+      port map (PADDO=>FEE_DATA_OUT_c_30, fifodataout30=>fifo_data_out(30));
+    fifo_data_out_29_I: fifo_data_out_29_B
+      port map (PADDO=>FEE_DATA_OUT_c_29, fifodataout29=>fifo_data_out(29));
+    fifo_data_out_28_I: fifo_data_out_28_B
+      port map (PADDO=>FEE_DATA_OUT_c_28, fifodataout28=>fifo_data_out(28));
+    fifo_data_out_27_I: fifo_data_out_27_B
+      port map (PADDO=>FEE_DATA_OUT_c_27, fifodataout27=>fifo_data_out(27));
+    fifo_data_out_26_I: fifo_data_out_26_B
+      port map (PADDO=>FEE_DATA_OUT_c_26, fifodataout26=>fifo_data_out(26));
+    fifo_data_out_25_I: fifo_data_out_25_B
+      port map (PADDO=>FEE_DATA_OUT_c_25, fifodataout25=>fifo_data_out(25));
+    fifo_data_out_24_I: fifo_data_out_24_B
+      port map (PADDO=>FEE_DATA_OUT_c_24, fifodataout24=>fifo_data_out(24));
+    fifo_data_out_23_I: fifo_data_out_23_B
+      port map (PADDO=>FEE_DATA_OUT_c_23, fifodataout23=>fifo_data_out(23));
+    fifo_data_out_22_I: fifo_data_out_22_B
+      port map (PADDO=>FEE_DATA_OUT_c_22, fifodataout22=>fifo_data_out(22));
+    fifo_data_out_21_I: fifo_data_out_21_B
+      port map (PADDO=>FEE_DATA_OUT_c_21, fifodataout21=>fifo_data_out(21));
+    fifo_data_out_20_I: fifo_data_out_20_B
+      port map (PADDO=>FEE_DATA_OUT_c_20, fifodataout20=>fifo_data_out(20));
+    fifo_data_out_19_I: fifo_data_out_19_B
+      port map (PADDO=>FEE_DATA_OUT_c_19, fifodataout19=>fifo_data_out(19));
+    fifo_data_out_18_I: fifo_data_out_18_B
+      port map (PADDO=>FEE_DATA_OUT_c_18, fifodataout18=>fifo_data_out(18));
+    fifo_data_out_17_I: fifo_data_out_17_B
+      port map (PADDO=>FEE_DATA_OUT_c_17, fifodataout17=>fifo_data_out(17));
+    fifo_data_out_16_I: fifo_data_out_16_B
+      port map (PADDO=>FEE_DATA_OUT_c_16, fifodataout16=>fifo_data_out(16));
+    fifo_data_out_15_I: fifo_data_out_15_B
+      port map (PADDO=>FEE_DATA_OUT_c_15, fifodataout15=>fifo_data_out(15));
+    fifo_data_out_14_I: fifo_data_out_14_B
+      port map (PADDO=>FEE_DATA_OUT_c_14, fifodataout14=>fifo_data_out(14));
+    fifo_data_out_13_I: fifo_data_out_13_B
+      port map (PADDO=>FEE_DATA_OUT_c_13, fifodataout13=>fifo_data_out(13));
+    fifo_data_out_12_I: fifo_data_out_12_B
+      port map (PADDO=>FEE_DATA_OUT_c_12, fifodataout12=>fifo_data_out(12));
+    fifo_data_out_11_I: fifo_data_out_11_B
+      port map (PADDO=>FEE_DATA_OUT_c_11, fifodataout11=>fifo_data_out(11));
+    fifo_data_out_10_I: fifo_data_out_10_B
+      port map (PADDO=>FEE_DATA_OUT_c_10, fifodataout10=>fifo_data_out(10));
+    fifo_data_out_9_I: fifo_data_out_9_B
+      port map (PADDO=>FEE_DATA_OUT_c_9, fifodataout9=>fifo_data_out(9));
+    fifo_data_out_8_I: fifo_data_out_8_B
+      port map (PADDO=>FEE_DATA_OUT_c_8, fifodataout8=>fifo_data_out(8));
+    fifo_data_out_7_I: fifo_data_out_7_B
+      port map (PADDO=>FEE_DATA_OUT_c_7, fifodataout7=>fifo_data_out(7));
+    fifo_data_out_6_I: fifo_data_out_6_B
+      port map (PADDO=>FEE_DATA_OUT_c_6, fifodataout6=>fifo_data_out(6));
+    fifo_data_out_5_I: fifo_data_out_5_B
+      port map (PADDO=>FEE_DATA_OUT_c_5, fifodataout5=>fifo_data_out(5));
+    fifo_data_out_4_I: fifo_data_out_4_B
+      port map (PADDO=>FEE_DATA_OUT_c_4, fifodataout4=>fifo_data_out(4));
+    fifo_data_out_3_I: fifo_data_out_3_B
+      port map (PADDO=>FEE_DATA_OUT_c_3, fifodataout3=>fifo_data_out(3));
+    fifo_data_out_2_I: fifo_data_out_2_B
+      port map (PADDO=>FEE_DATA_OUT_c_2, fifodataout2=>fifo_data_out(2));
+    fifo_data_out_1_I: fifo_data_out_1_B
+      port map (PADDO=>FEE_DATA_OUT_c_1, fifodataout1=>fifo_data_out(1));
+    trig_2_I: trig_2_B
+      port map (PADDI=>trig_c_2, trig2=>trig(2));
+    trig_1_I: trig_1_B
+      port map (PADDI=>trig_c_1, trig1=>trig(1));
+    trig_0_I: trig_0_B
+      port map (PADDI=>trig_c_0, trig0=>trig(0));
+    reset_dcI: reset_dcB
+      port map (PADDI=>reset_dc_c, resetdc=>reset_dc);
+    reset_dc_MGIOLI: reset_dc_MGIOL
+      port map (DI=>reset_dc_c, CLK=>pll_clks_3, INFF=>reset_dl_1);
+    rd_clkI: rd_clkB
+      port map (PADDI=>rd_clk_c, rdclk=>rd_clk);
+
+      genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port map (DIA15=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA13=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA12=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA11=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA9=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                ADA13=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                ADA12=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, 
+                ADA11=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                ADA10=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, 
+                ADA9=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                ADA8=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, 
+                ADA7=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                ADA6=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, 
+                ADA5=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                DOA17=>genblk1_2_un1_tdc_channel_fifo_out_inst_17, 
+                DOA16=>genblk1_2_un1_tdc_channel_fifo_out_inst_16, 
+                DOA15=>genblk1_2_un1_tdc_channel_fifo_out_inst_15, 
+                DOA14=>genblk1_2_un1_tdc_channel_fifo_out_inst_14, 
+                DOA13=>genblk1_2_un1_tdc_channel_fifo_out_inst_13, 
+                DOA12=>genblk1_2_un1_tdc_channel_fifo_out_inst_12, 
+                DOA11=>genblk1_2_un1_tdc_channel_fifo_out_inst_11, 
+                DOA10=>genblk1_2_un1_tdc_channel_fifo_out_inst_10, 
+                DOA9=>genblk1_2_un1_tdc_channel_fifo_out_inst_9, 
+                DOA8=>genblk1_2_un1_tdc_channel_fifo_out_inst_8, 
+                DOA7=>genblk1_2_un1_tdc_channel_fifo_out_inst_7, 
+                DOA6=>genblk1_2_un1_tdc_channel_fifo_out_inst_6, 
+                DOA5=>genblk1_2_un1_tdc_channel_fifo_out_inst_5, 
+                DOA4=>genblk1_2_un1_tdc_channel_fifo_out_inst_4, 
+                DOA3=>genblk1_2_un1_tdc_channel_fifo_out_inst_3, 
+                DOA2=>genblk1_2_un1_tdc_channel_fifo_out_inst_2, 
+                DOA1=>genblk1_2_un1_tdc_channel_fifo_out_inst_1, 
+                DOA0=>genblk1_2_un1_tdc_channel_fifo_out_inst_0, 
+                CEA=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLKA=>pll_clks_3, CLKB=>pll_clks_3, 
+                OCEB=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CEB=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                DOB0=>genblk1_2_un1_tdc_channel_fifo_out_inst_18, 
+                DOB1=>genblk1_2_un1_tdc_channel_fifo_out_inst_19, 
+                DOB2=>genblk1_2_un1_tdc_channel_fifo_out_inst_20, 
+                DOB3=>genblk1_2_un1_tdc_channel_fifo_out_inst_21, 
+                DOB4=>genblk1_2_un1_tdc_channel_fifo_out_inst_22, 
+                DOB5=>genblk1_2_un1_tdc_channel_fifo_out_inst_23, 
+                ADB5=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                ADB6=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, 
+                ADB7=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                ADB8=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, 
+                ADB9=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                ADB10=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, 
+                ADB11=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                ADB12=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, 
+                ADB13=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                DIB6=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB8=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB9=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port map (DIA15=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA13=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA12=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA11=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA9=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                ADA13=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                ADA12=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, 
+                ADA11=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                ADA10=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, 
+                ADA9=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                ADA8=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, 
+                ADA7=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                ADA6=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, 
+                ADA5=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                DOA17=>genblk1_1_un1_tdc_channel_fifo_out_inst_17, 
+                DOA16=>genblk1_1_un1_tdc_channel_fifo_out_inst_16, 
+                DOA15=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, 
+                DOA14=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, 
+                DOA13=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, 
+                DOA12=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, 
+                DOA11=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, 
+                DOA10=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, 
+                DOA9=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, 
+                DOA8=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, 
+                DOA7=>genblk1_1_un1_tdc_channel_fifo_out_inst_7, 
+                DOA6=>genblk1_1_un1_tdc_channel_fifo_out_inst_6, 
+                DOA5=>genblk1_1_un1_tdc_channel_fifo_out_inst_5, 
+                DOA4=>genblk1_1_un1_tdc_channel_fifo_out_inst_4, 
+                DOA3=>genblk1_1_un1_tdc_channel_fifo_out_inst_3, 
+                DOA2=>genblk1_1_un1_tdc_channel_fifo_out_inst_2, 
+                DOA1=>genblk1_1_un1_tdc_channel_fifo_out_inst_1, 
+                DOA0=>genblk1_1_un1_tdc_channel_fifo_out_inst_0, 
+                CEA=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLKA=>pll_clks_3, CLKB=>pll_clks_3, 
+                OCEB=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CEB=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                DOB0=>genblk1_1_un1_tdc_channel_fifo_out_inst_18, 
+                DOB1=>genblk1_1_un1_tdc_channel_fifo_out_inst_19, 
+                DOB2=>genblk1_1_un1_tdc_channel_fifo_out_inst_20, 
+                DOB3=>genblk1_1_un1_tdc_channel_fifo_out_inst_21, 
+                DOB4=>genblk1_1_un1_tdc_channel_fifo_out_inst_22, 
+                DOB5=>genblk1_1_un1_tdc_channel_fifo_out_inst_23, 
+                ADB5=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                ADB6=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, 
+                ADB7=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                ADB8=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, 
+                ADB9=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                ADB10=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, 
+                ADB11=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                ADB12=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, 
+                ADB13=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                DIB6=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB8=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB9=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0
+      port map (DIA15=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA13=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA12=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA11=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIA9=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                ADA13=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, 
+                ADA12=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, 
+                ADA11=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, 
+                ADA10=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, 
+                ADA9=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, 
+                ADA8=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, 
+                ADA7=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, 
+                ADA6=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, 
+                ADA5=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, 
+                DOA17=>genblk1_0_un1_tdc_channel_fifo_out_inst_17, 
+                DOA16=>genblk1_0_un1_tdc_channel_fifo_out_inst_16, 
+                DOA15=>genblk1_0_un1_tdc_channel_fifo_out_inst_15, 
+                DOA14=>genblk1_0_un1_tdc_channel_fifo_out_inst_14, 
+                DOA13=>genblk1_0_un1_tdc_channel_fifo_out_inst_13, 
+                DOA12=>genblk1_0_un1_tdc_channel_fifo_out_inst_12, 
+                DOA11=>genblk1_0_un1_tdc_channel_fifo_out_inst_11, 
+                DOA10=>genblk1_0_un1_tdc_channel_fifo_out_inst_10, 
+                DOA9=>genblk1_0_un1_tdc_channel_fifo_out_inst_9, 
+                DOA8=>genblk1_0_un1_tdc_channel_fifo_out_inst_8, 
+                DOA7=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, 
+                DOA6=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, 
+                DOA5=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, 
+                DOA4=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, 
+                DOA3=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, 
+                DOA2=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, 
+                DOA1=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, 
+                DOA0=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, 
+                CEA=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, 
+                CLKA=>pll_clks_3, CLKB=>pll_clks_3, 
+                OCEB=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                CEB=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, 
+                DOB0=>genblk1_0_un1_tdc_channel_fifo_out_inst_18, 
+                DOB1=>genblk1_0_un1_tdc_channel_fifo_out_inst_19, 
+                DOB2=>genblk1_0_un1_tdc_channel_fifo_out_inst_20, 
+                DOB3=>genblk1_0_un1_tdc_channel_fifo_out_inst_21, 
+                DOB4=>genblk1_0_un1_tdc_channel_fifo_out_inst_22, 
+                DOB5=>genblk1_0_un1_tdc_channel_fifo_out_inst_23, 
+                ADB5=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, 
+                ADB6=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, 
+                ADB7=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, 
+                ADB8=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, 
+                ADB9=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, 
+                ADB10=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, 
+                ADB11=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, 
+                ADB12=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, 
+                ADB13=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, 
+                DIB6=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB8=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, 
+                DIB9=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9);
+
+      fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I: fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1
+      port map (DIA17=>fifo_colector_inst_data_buffer_17, 
+                DIA16=>fifo_colector_inst_data_buffer_16, 
+                DIA15=>fifo_colector_inst_data_buffer_15, 
+                DIA14=>fifo_colector_inst_data_buffer_14, 
+                DIA13=>fifo_colector_inst_data_buffer_13, 
+                DIA12=>fifo_colector_inst_data_buffer_12, 
+                DIA11=>fifo_colector_inst_data_buffer_11, 
+                DIA10=>fifo_colector_inst_data_buffer_10, 
+                DIA9=>fifo_colector_inst_data_buffer_9, 
+                DIA8=>fifo_colector_inst_data_buffer_8, 
+                DIA7=>fifo_colector_inst_data_buffer_7, 
+                DIA6=>fifo_colector_inst_data_buffer_6, 
+                DIA5=>fifo_colector_inst_data_buffer_5, 
+                DIA4=>fifo_colector_inst_data_buffer_4, 
+                DIA3=>fifo_colector_inst_data_buffer_3, 
+                DIA2=>fifo_colector_inst_data_buffer_2, 
+                DIA1=>fifo_colector_inst_data_buffer_1, 
+                DIA0=>fifo_colector_inst_data_buffer_0, 
+                ADA13=>fifo_colector_inst_fifo40_inst_wptr_8, 
+                ADA12=>fifo_colector_inst_fifo40_inst_wptr_7, 
+                ADA11=>fifo_colector_inst_fifo40_inst_wptr_6, 
+                ADA10=>fifo_colector_inst_fifo40_inst_wptr_5, 
+                ADA9=>fifo_colector_inst_fifo40_inst_wptr_4, 
+                ADA8=>fifo_colector_inst_fifo40_inst_wptr_3, 
+                ADA7=>fifo_colector_inst_fifo40_inst_wptr_2, 
+                ADA6=>fifo_colector_inst_fifo40_inst_wptr_1, 
+                ADA5=>fifo_colector_inst_fifo40_inst_wptr_0, 
+                DOA17=>FEE_DATA_OUT_c_17, DOA16=>FEE_DATA_OUT_c_16, 
+                DOA15=>FEE_DATA_OUT_c_15, DOA14=>FEE_DATA_OUT_c_14, 
+                DOA13=>FEE_DATA_OUT_c_13, DOA12=>FEE_DATA_OUT_c_12, 
+                DOA11=>FEE_DATA_OUT_c_11, DOA10=>FEE_DATA_OUT_c_10, 
+                DOA9=>FEE_DATA_OUT_c_9, DOA8=>FEE_DATA_OUT_c_8, 
+                DOA7=>FEE_DATA_OUT_c_7, DOA6=>FEE_DATA_OUT_c_6, 
+                DOA5=>FEE_DATA_OUT_c_5, DOA4=>FEE_DATA_OUT_c_4, 
+                DOA3=>FEE_DATA_OUT_c_3, DOA2=>FEE_DATA_OUT_c_2, 
+                DOA1=>FEE_DATA_OUT_c_1, DOA0=>FEE_DATA_OUT_c_0, 
+                CEA=>fifo_colector_inst_fifo40_inst_wren_i, CLKA=>pll_clks_3, 
+                CLKB=>rd_clk_c, OCEB=>fifo_colector_inst_fifo40_inst_rden_i, 
+                CEB=>fifo_colector_inst_fifo40_inst_rden_i, 
+                DOB0=>FEE_DATA_OUT_c_18, DOB1=>FEE_DATA_OUT_c_19, 
+                DOB2=>FEE_DATA_OUT_c_20, DOB3=>FEE_DATA_OUT_c_21, 
+                DOB4=>FEE_DATA_OUT_c_22, DOB5=>FEE_DATA_OUT_c_23, 
+                DOB6=>FEE_DATA_OUT_c_24, DOB7=>FEE_DATA_OUT_c_25, 
+                DOB8=>FEE_DATA_OUT_c_26, DOB9=>FEE_DATA_OUT_c_27, 
+                DOB10=>FEE_DATA_OUT_c_28, DOB11=>FEE_DATA_OUT_c_29, 
+                DOB12=>FEE_DATA_OUT_c_30, DOB13=>FEE_DATA_OUT_c_31, 
+                ADB5=>fifo_colector_inst_fifo40_inst_rptr_0, 
+                ADB6=>fifo_colector_inst_fifo40_inst_rptr_1, 
+                ADB7=>fifo_colector_inst_fifo40_inst_rptr_2, 
+                ADB8=>fifo_colector_inst_fifo40_inst_rptr_3, 
+                ADB9=>fifo_colector_inst_fifo40_inst_rptr_4, 
+                ADB10=>fifo_colector_inst_fifo40_inst_rptr_5, 
+                ADB11=>fifo_colector_inst_fifo40_inst_rptr_6, 
+                ADB12=>fifo_colector_inst_fifo40_inst_rptr_7, 
+                ADB13=>fifo_colector_inst_fifo40_inst_rptr_8, 
+                DIB0=>fifo_colector_inst_data_buffer_18, 
+                DIB1=>fifo_colector_inst_data_buffer_19, 
+                DIB2=>fifo_colector_inst_data_buffer_20, 
+                DIB3=>fifo_colector_inst_data_buffer_21, 
+                DIB4=>fifo_colector_inst_data_buffer_22, 
+                DIB5=>fifo_colector_inst_data_buffer_23, 
+                DIB6=>fifo_colector_inst_data_buffer_24, 
+                DIB7=>fifo_colector_inst_data_buffer_25, 
+                DIB8=>fifo_colector_inst_data_buffer_26, 
+                DIB9=>fifo_colector_inst_data_buffer_27, 
+                DIB10=>fifo_colector_inst_data_buffer_28, 
+                DIB11=>fifo_colector_inst_data_buffer_29, 
+                DIB12=>fifo_colector_inst_data_buffer_30, 
+                DIB13=>fifo_colector_inst_data_buffer_31, 
+                DIB14=>fifo_colector_inst_data_buffer_32, 
+                DIB15=>fifo_colector_inst_data_buffer_33);
+    pll0inst_PLLInst_0I: pll0inst_PLLInst_0
+      port map (CLKI=>clk_c, CLKFB=>pll_clks_0, STDBY=>pll0inst_GND, 
+                CLKOS3=>pll_clks_3, CLKOS2=>pll_clks_2, CLKOS=>pll_clks_1, 
+                CLKOP=>pll_clks_0);
+    VHI_INST: VHI
+      port map (Z=>VCCI);
+    PUR_INST: PUR
+      port map (PUR=>VCCI);
+    GSR_INST: GSR
+      port map (GSR=>VCCI);
+  end Structure;
+
+
+
+  library IEEE, vital2000, ECP5UM;
+  configuration Structure_CON of top_tf is
+    for Structure
+    end for;
+  end Structure_CON;
+
+
diff --git a/impl1/s1_impl1_vo.sdf b/impl1/s1_impl1_vo.sdf
new file mode 100644
index 0000000..4989c4b
--- /dev/null
+++ b/impl1/s1_impl1_vo.sdf
@@ -0,0 +1,678 @@
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "top")
+  (DATE "Fri Jul 17 09:09:56 2020")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.11.2.446")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_2)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_3)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_4)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_5)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_6)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_7)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_8)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH A0 F0 (119:130:141)(119:130:141))
+        (IOPATH A0 F1 (352:372:392)(352:372:392))
+        (IOPATH A0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_9)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_10)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_11)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_12)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_13)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_14)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 F1 (119:130:141)(119:130:141))
+        (IOPATH A1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_15)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH B0 F0 (119:130:141)(119:130:141))
+        (IOPATH B0 F1 (352:372:392)(352:372:392))
+        (IOPATH B0 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q0 (257:283:309)(257:283:309))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+        (IOPATH FCI F0 (140:198:257)(140:198:257))
+        (IOPATH FCI F1 (201:237:273)(201:237:273))
+        (IOPATH FCI FCO (39:41:43)(39:41:43))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "SCCU2C")
+    (INSTANCE SLICE_16)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (119:130:141)(119:130:141))
+        (IOPATH B1 FCO (112:195:278)(112:195:278))
+        (IOPATH CLK Q1 (257:282:308)(257:282:308))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181))
+      (SETUPHOLD LSR (posedge CLK) (146:185:224)(-146:-132:-119))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (444:444:444))
+      (WIDTH (negedge LSR) (444:444:444))
+      (WIDTH (posedge CLK) (889:889:889))
+      (WIDTH (negedge CLK) (889:889:889))
+    )
+  )
+  (CELL
+    (CELLTYPE "pwm")
+    (INSTANCE pwm_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO pwm (1736:1751:1766)(1736:1751:1766))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "clk")
+    (INSTANCE clk_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH clk PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge clk) (2500:2500:2500))
+      (WIDTH (negedge clk) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "reset")
+    (INSTANCE reset_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH reset PADDI (826:851:876)(826:851:876))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge reset) (2500:2500:2500))
+      (WIDTH (negedge reset) (2500:2500:2500))
+    )
+  )
+  (CELL
+    (CELLTYPE "top")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0/Q0 SLICE_0/B0 (378:438:499)(378:438:499))
+        (INTERCONNECT SLICE_0/Q0 pwm_I/PADDO (440:497:555)(440:497:555))
+        (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT reset_I/PADDI SLICE_0/LSR (605:671:737)(605:671:737))
+        (INTERCONNECT reset_I/PADDI SLICE_1/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_1/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_2/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_2/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_3/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_3/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_4/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_4/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_5/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_5/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_6/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_6/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_7/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_7/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_8/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_8/LSR (745:828:911)(745:828:911))
+        (INTERCONNECT reset_I/PADDI SLICE_9/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_9/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_10/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_10/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_11/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_11/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_12/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_12/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_13/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_13/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_14/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_14/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_15/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_15/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT reset_I/PADDI SLICE_16/LSR (880:977:1075)(880:977:1075))
+        (INTERCONNECT clk_I/PADDI SLICE_0/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_1/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_1/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_2/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_2/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_3/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_3/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_4/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_4/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_5/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_5/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_6/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_6/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_7/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_7/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_8/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_8/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_9/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_9/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_10/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_10/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_11/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_11/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_12/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_12/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_13/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_13/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_14/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_14/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_15/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_15/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT clk_I/PADDI SLICE_16/CLK (1588:1665:1742)(1588:1665:1742))
+        (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (380:457:535)(380:457:535))
+        (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_5/Q0 SLICE_5/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_8/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (380:457:535)(380:457:535))
+        (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_9/Q0 SLICE_9/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_10/FCO SLICE_9/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_10/Q1 SLICE_10/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_10/Q0 SLICE_10/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_10/F1 SLICE_10/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_11/FCO SLICE_10/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_11/Q1 SLICE_11/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_11/F1 SLICE_11/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_12/FCO SLICE_11/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_12/Q1 SLICE_12/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_12/Q0 SLICE_12/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_13/FCO SLICE_12/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_13/Q1 SLICE_13/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_13/Q0 SLICE_13/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_13/F1 SLICE_13/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/FCO SLICE_13/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/Q1 SLICE_14/A1 (258:314:370)(258:314:370))
+        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_15/FCO SLICE_14/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_15/Q1 SLICE_15/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_15/Q0 SLICE_15/B0 (374:431:489)(374:431:489))
+        (INTERCONNECT SLICE_15/F1 SLICE_15/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_16/FCO SLICE_15/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_16/Q1 SLICE_16/B1 (272:320:369)(272:320:369))
+        (INTERCONNECT SLICE_16/F1 SLICE_16/DI1 (0:0:0)(0:0:0))
+      )
+    )
+  )
+)
diff --git a/impl1/s1_impl1_vo.vo b/impl1/s1_impl1_vo.vo
new file mode 100644
index 0000000..1501258
--- /dev/null
+++ b/impl1/s1_impl1_vo.vo
@@ -0,0 +1,207 @@
+
+// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.11.2.446
+// ldbanno -n Verilog -o s1_impl1_vo.vo -w -neg -gui s1_impl1.ncd 
+// Netlist created on Fri Jul 17 09:08:55 2020
+// Netlist written on Fri Jul 17 09:09:56 2020
+// Design is for device LFE5UM5G-45F
+// Design is for package CABGA381
+// Design is for performance grade 8
+
+`timescale 1 ns / 1 ps
+
+module top ( clk, reset, pwm );
+  input  clk, reset;
+  output pwm;
+  wire   pwm_c_31, n134, reset_c, clk_c, n216, n2, n3, n135, n136, n215, n4, 
+         n5, n137, n138, n214, n6, n7, n139, n140, n213, n8, n9, n141, n142, 
+         n212, n10, n11, n143, n144, n211, n12, n13, n145, n146, n210, n14, 
+         n15, n147, n148, n209, n16, n17, n149, n150, n208, n18, n19, n151, 
+         n152, n207, n20, n21, n153, n154, n206, n22, n23, n155, n156, n205, 
+         n24, n25, n157, n158, n204, n26, n27, n159, n160, n203, n28, n29, 
+         n161, n162, n202, n30, n31, n163, n164, n201, n32, n165, VCCI;
+
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'h0000), .REG0_SD("VHI"), 
+    .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) SLICE_0( .M1(1'bX), .A1(1'bX), 
+    .B1(1'bX), .C1(1'bX), .D1(1'bX), .DI1(1'bX), .DI0(n134), .A0(1'bX), 
+    .B0(pwm_c_31), .C0(1'bX), .D0(1'b1), .FCI(n216), .M0(1'bX), .CE(1'bX), 
+    .CLK(clk_c), .LSR(reset_c), .FCO(), .F1(), .Q1(), .F0(n134), .Q0(pwm_c_31));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_1( .M1(1'bX), .A1(n2), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n135), 
+    .DI0(n136), .A0(1'bX), .B0(n3), .C0(1'bX), .D0(1'b1), .FCI(n215), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n216), .F1(n135), 
+    .Q1(n2), .F0(n136), .Q0(n3));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_2( .M1(1'bX), .A1(n4), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n137), 
+    .DI0(n138), .A0(1'bX), .B0(n5), .C0(1'bX), .D0(1'b1), .FCI(n214), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n215), .F1(n137), 
+    .Q1(n4), .F0(n138), .Q0(n5));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_3( .M1(1'bX), .A1(1'bX), .B1(n6), .C1(1'bX), .D1(1'b1), .DI1(n139), 
+    .DI0(n140), .A0(1'bX), .B0(n7), .C0(1'bX), .D0(1'b1), .FCI(n213), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n214), .F1(n139), 
+    .Q1(n6), .F0(n140), .Q0(n7));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hAA00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_4( .M1(1'bX), .A1(1'bX), .B1(n8), .C1(1'bX), .D1(1'b1), .DI1(n141), 
+    .DI0(n142), .A0(n9), .B0(1'bX), .C0(1'bX), .D0(1'b1), .FCI(n212), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n213), .F1(n141), 
+    .Q1(n8), .F0(n142), .Q0(n9));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_5( .M1(1'bX), .A1(n10), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n143), 
+    .DI0(n144), .A0(1'bX), .B0(n11), .C0(1'bX), .D0(1'b1), .FCI(n211), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n212), .F1(n143), 
+    .Q1(n10), .F0(n144), .Q0(n11));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_6( .M1(1'bX), .A1(n12), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n145), 
+    .DI0(n146), .A0(1'bX), .B0(n13), .C0(1'bX), .D0(1'b1), .FCI(n210), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n211), .F1(n145), 
+    .Q1(n12), .F0(n146), .Q0(n13));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_7( .M1(1'bX), .A1(1'bX), .B1(n14), .C1(1'bX), .D1(1'b1), .DI1(n147), 
+    .DI0(n148), .A0(1'bX), .B0(n15), .C0(1'bX), .D0(1'b1), .FCI(n209), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n210), .F1(n147), 
+    .Q1(n14), .F0(n148), .Q0(n15));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hAA00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_8( .M1(1'bX), .A1(1'bX), .B1(n16), .C1(1'bX), .D1(1'b1), .DI1(n149), 
+    .DI0(n150), .A0(n17), .B0(1'bX), .C0(1'bX), .D0(1'b1), .FCI(n208), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n209), .F1(n149), 
+    .Q1(n16), .F0(n150), .Q0(n17));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_9( .M1(1'bX), .A1(n18), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n151), 
+    .DI0(n152), .A0(1'bX), .B0(n19), .C0(1'bX), .D0(1'b1), .FCI(n207), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n208), .F1(n151), 
+    .Q1(n18), .F0(n152), .Q0(n19));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_10( .M1(1'bX), .A1(n20), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n153), 
+    .DI0(n154), .A0(1'bX), .B0(n21), .C0(1'bX), .D0(1'b1), .FCI(n206), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n207), .F1(n153), 
+    .Q1(n20), .F0(n154), .Q0(n21));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_11( .M1(1'bX), .A1(1'bX), .B1(n22), .C1(1'bX), .D1(1'b1), .DI1(n155), 
+    .DI0(n156), .A0(1'bX), .B0(n23), .C0(1'bX), .D0(1'b1), .FCI(n205), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n206), .F1(n155), 
+    .Q1(n22), .F0(n156), .Q0(n23));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_12( .M1(1'bX), .A1(1'bX), .B1(n24), .C1(1'bX), .D1(1'b1), .DI1(n157), 
+    .DI0(n158), .A0(1'bX), .B0(n25), .C0(1'bX), .D0(1'b1), .FCI(n204), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n205), .F1(n157), 
+    .Q1(n24), .F0(n158), .Q0(n25));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_13( .M1(1'bX), .A1(n26), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n159), 
+    .DI0(n160), .A0(1'bX), .B0(n27), .C0(1'bX), .D0(1'b1), .FCI(n203), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n204), .F1(n159), 
+    .Q1(n26), .F0(n160), .Q0(n27));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_14( .M1(1'bX), .A1(n28), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n161), 
+    .DI0(n162), .A0(1'bX), .B0(n29), .C0(1'bX), .D0(1'b1), .FCI(n202), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n203), .F1(n161), 
+    .Q1(n28), .F0(n162), .Q0(n29));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), 
+    .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) 
+    SLICE_15( .M1(1'bX), .A1(1'bX), .B1(n30), .C1(1'bX), .D1(1'b1), .DI1(n163), 
+    .DI0(n164), .A0(1'bX), .B0(n31), .C0(1'bX), .D0(1'b1), .FCI(n201), 
+    .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n202), .F1(n163), 
+    .Q1(n30), .F0(n164), .Q0(n31));
+  SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), 
+    .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), 
+    .INIT0_INITVAL(16'h0000), .INIT1_INITVAL(16'h33FF), .REG1_SD("VHI"), 
+    .CHECK_DI1(1'b1), .CHECK_LSR(1'b1)) SLICE_16( .M1(1'bX), .A1(1'bX), 
+    .B1(n32), .C1(1'bX), .D1(1'b1), .DI1(n165), .DI0(1'bX), .A0(1'bX), 
+    .B0(1'bX), .C0(1'bX), .D0(1'bX), .FCI(1'bX), .M0(1'bX), .CE(1'bX), 
+    .CLK(clk_c), .LSR(reset_c), .FCO(n201), .F1(n165), .Q1(n32), .F0(), .Q0());
+  pwm pwm_I( .PADDO(pwm_c_31), .pwm(pwm));
+  clk clk_I( .PADDI(clk_c), .clk(clk));
+  reset reset_I( .PADDI(reset_c), .reset(reset));
+  VHI VHI_INST( .Z(VCCI));
+  PUR PUR_INST( .PUR(VCCI));
+  GSR GSR_INST( .GSR(VCCI));
+endmodule
+
+module pwm ( input PADDO, output pwm );
+
+  sapiobuf pwm_pad( .I(PADDO), .PAD(pwm));
+
+  specify
+    (PADDO => pwm) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module sapiobuf ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module clk ( output PADDI, input clk );
+
+  sapiobuf0001 clk_pad( .Z(PADDI), .PAD(clk));
+
+  specify
+    (clk => PADDI) = (0:0:0,0:0:0);
+    $width (posedge clk, 0:0:0);
+    $width (negedge clk, 0:0:0);
+  endspecify
+
+endmodule
+
+module sapiobuf0001 ( output Z, input PAD );
+
+  IBPD INST1( .I(PAD), .O(Z));
+endmodule
+
+module reset ( output PADDI, input reset );
+
+  sapiobuf0001 reset_pad( .Z(PADDI), .PAD(reset));
+
+  specify
+    (reset => PADDI) = (0:0:0,0:0:0);
+    $width (posedge reset, 0:0:0);
+    $width (negedge reset, 0:0:0);
+  endspecify
+
+endmodule
diff --git a/impl1/scratchproject.prs b/impl1/scratchproject.prs
new file mode 100644
index 0000000..b6e5d18
--- /dev/null
+++ b/impl1/scratchproject.prs
@@ -0,0 +1,99 @@
+#--  Synopsys, Inc.
+#--  Version O-2018.09-SP1
+#--  Project file /home/hadaq/mmichalek/lattice/simplified/impl1/scratchproject.prs
+
+#project files
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules2.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top2.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"
+add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd"
+add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd"
+
+
+
+#implementation: "impl1"
+impl -add /home/hadaq/mmichalek/lattice/simplified/impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -hdl_define -set SBP_SYNTHESIS
+set_option -include_path {/home/hadaq/mmichalek/lattice/simplified/impl1/}
+set_option -include_path {/home/hadaq/mmichalek/lattice/simplified}
+
+#device options
+set_option -technology ECP5UM5G
+set_option -part LFE5UM5G_45F
+set_option -package BG381C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "top_tf"
+
+# hdl_compiler_options
+set_option -distributed_compile 1
+
+# mapper_without_write_options
+set_option -frequency 200
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 0
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi"
+
+#set log file 
+set_option log_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf" 
+
+#design plan options
+impl -active "impl1"
diff --git a/impl1/stdout.log b/impl1/stdout.log
new file mode 100644
index 0000000..9ecd1a8
--- /dev/null
+++ b/impl1/stdout.log
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Wed Jun 16 09:19:12 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Wed Jun 16 09:19:12 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Wed Jun 16 09:19:13 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Wed Jun 16 09:19:17 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Wed Jun 16 09:19:17 2021
+
+multi_srs_gen completed
+# Wed Jun 16 09:19:17 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Wed Jun 16 09:19:17 2021
+
+premap completed with warnings
+# Wed Jun 16 09:19:18 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Wed Jun 16 09:19:18 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Wed Jun 16 09:19:18 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Wed Jun 16 09:19:25 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak b/impl1/stdout.log.bak
new file mode 100644
index 0000000..b7798bc
--- /dev/null
+++ b/impl1/stdout.log.bak
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Wed Jun 16 07:57:05 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Wed Jun 16 07:57:05 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Wed Jun 16 07:57:06 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Wed Jun 16 07:57:06 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Wed Jun 16 07:57:06 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Wed Jun 16 07:57:10 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Wed Jun 16 07:57:10 2021
+
+multi_srs_gen completed
+# Wed Jun 16 07:57:10 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Wed Jun 16 07:57:10 2021
+
+premap completed with warnings
+# Wed Jun 16 07:57:11 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Wed Jun 16 07:57:11 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Wed Jun 16 07:57:11 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Wed Jun 16 07:57:18 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak.1 b/impl1/stdout.log.bak.1
new file mode 100644
index 0000000..df11321
--- /dev/null
+++ b/impl1/stdout.log.bak.1
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Wed Jun 16 07:45:06 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Wed Jun 16 07:45:06 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Wed Jun 16 07:45:07 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Wed Jun 16 07:45:07 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Wed Jun 16 07:45:07 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Wed Jun 16 07:45:11 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Wed Jun 16 07:45:11 2021
+
+multi_srs_gen completed
+# Wed Jun 16 07:45:11 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Wed Jun 16 07:45:11 2021
+
+premap completed with warnings
+# Wed Jun 16 07:45:12 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Wed Jun 16 07:45:12 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Wed Jun 16 07:45:12 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Wed Jun 16 07:45:19 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak.2 b/impl1/stdout.log.bak.2
new file mode 100644
index 0000000..9ea0606
--- /dev/null
+++ b/impl1/stdout.log.bak.2
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Tue Jun 15 17:59:30 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Tue Jun 15 17:59:31 2021
+
+Return Code: 0
+Run Time:00h:00m:01s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Tue Jun 15 17:59:31 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Tue Jun 15 17:59:31 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Tue Jun 15 17:59:31 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Tue Jun 15 17:59:35 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Tue Jun 15 17:59:35 2021
+
+multi_srs_gen completed
+# Tue Jun 15 17:59:35 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Tue Jun 15 17:59:35 2021
+
+premap completed with warnings
+# Tue Jun 15 17:59:36 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Tue Jun 15 17:59:36 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Tue Jun 15 17:59:36 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Tue Jun 15 17:59:43 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak.3 b/impl1/stdout.log.bak.3
new file mode 100644
index 0000000..5827931
--- /dev/null
+++ b/impl1/stdout.log.bak.3
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Tue Jun 15 17:47:11 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Tue Jun 15 17:47:11 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Tue Jun 15 17:47:11 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Tue Jun 15 17:47:11 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Tue Jun 15 17:47:11 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Tue Jun 15 17:47:15 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Tue Jun 15 17:47:15 2021
+
+multi_srs_gen completed
+# Tue Jun 15 17:47:15 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Tue Jun 15 17:47:15 2021
+
+premap completed with warnings
+# Tue Jun 15 17:47:17 2021
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Tue Jun 15 17:47:17 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Tue Jun 15 17:47:17 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Tue Jun 15 17:47:23 2021
+
+Return Code: 1
+Run Time:00h:00m:06s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak.4 b/impl1/stdout.log.bak.4
new file mode 100644
index 0000000..57cc079
--- /dev/null
+++ b/impl1/stdout.log.bak.4
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Tue Jun 15 11:40:10 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Tue Jun 15 11:40:10 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Tue Jun 15 11:40:10 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Tue Jun 15 11:40:10 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Tue Jun 15 11:40:10 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Tue Jun 15 11:40:14 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Tue Jun 15 11:40:14 2021
+
+multi_srs_gen completed
+# Tue Jun 15 11:40:14 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Tue Jun 15 11:40:14 2021
+
+premap completed with warnings
+# Tue Jun 15 11:40:15 2021
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Tue Jun 15 11:40:15 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Tue Jun 15 11:40:15 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Tue Jun 15 11:40:24 2021
+
+Return Code: 1
+Run Time:00h:00m:09s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/stdout.log.bak.5 b/impl1/stdout.log.bak.5
new file mode 100644
index 0000000..90ffa6b
--- /dev/null
+++ b/impl1/stdout.log.bak.5
@@ -0,0 +1,105 @@
+
+                             Synplify (R) Premier 
+
+                Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 
+
+                    Copyright (c) 1988 - 2018 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    synbatch_orig
+Install:     /opt/synplicity/O-2018.09-SP1
+Hostname:    lxhadeb07
+Date:        Tue Jun 15 11:16:34 2021
+Version:     O-2018.09-SP1
+
+Arguments:   -product synplify_premier -batch s1_impl1_synplify.tcl
+ProductType: synplify_premier
+
+License checkout: synplifypremier
+License: synplifypremier from server lxcad03.gsi.de 
+Licensed Vendor: All FPGA
+License Option: ident
+
+
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: hdl_info_gen in foreground
+
+License granted for 4 parallel jobs
+Generating HDL info...
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+
+hdl_info_gen completed
+# Tue Jun 15 11:16:34 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Tue Jun 15 11:16:34 2021
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Tue Jun 15 11:16:34 2021
+License granted for 4 parallel jobs
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Tue Jun 15 11:16:34 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+
+compiler completed
+# Tue Jun 15 11:16:38 2021
+
+Return Code: 0
+Run Time:00h:00m:04s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Tue Jun 15 11:16:38 2021
+
+multi_srs_gen completed
+# Tue Jun 15 11:16:38 2021
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Tue Jun 15 11:16:38 2021
+
+premap completed with warnings
+# Tue Jun 15 11:16:40 2021
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Tue Jun 15 11:16:40 2021
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Tue Jun 15 11:16:40 2021
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm
+
+fpga_mapper completed with warnings
+# Tue Jun 15 11:16:47 2021
+
+Return Code: 1
+Run Time:00h:00m:07s
+Complete: Map on proj_1|impl1
+Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "s1_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj
+batch mode default:no
+License checkin: synplifypremier
diff --git a/impl1/synlog.tcl b/impl1/synlog.tcl
new file mode 100644
index 0000000..6874eb2
--- /dev/null
+++ b/impl1/synlog.tcl
@@ -0,0 +1 @@
+run_tcl -fg s1_impl1_synplify.tcl
diff --git a/impl1/synlog/distcomp0.tlg.rptmap b/impl1/synlog/distcomp0.tlg.rptmap
new file mode 100644
index 0000000..ba28008
--- /dev/null
+++ b/impl1/synlog/distcomp0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork//distcomp/distcomp0/distcomp0.tlg,distcomp0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
diff --git a/impl1/synlog/distcomp1.tlg.rptmap b/impl1/synlog/distcomp1.tlg.rptmap
new file mode 100644
index 0000000..ae29ab6
--- /dev/null
+++ b/impl1/synlog/distcomp1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork//distcomp/distcomp1/distcomp1.tlg,distcomp1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
diff --git a/impl1/synlog/incr_compile.rpt.rptmap b/impl1/synlog/incr_compile.rpt.rptmap
new file mode 100644
index 0000000..dbb7528
--- /dev/null
+++ b/impl1/synlog/incr_compile.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
diff --git a/impl1/synlog/linker.rpt.rptmap b/impl1/synlog/linker.rpt.rptmap
new file mode 100644
index 0000000..74ed6b7
--- /dev/null
+++ b/impl1/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/s1_impl1_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
diff --git a/impl1/synlog/report/metrics.db b/impl1/synlog/report/metrics.db
new file mode 100644
index 0000000..1701ec6
Binary files /dev/null and b/impl1/synlog/report/metrics.db differ
diff --git a/impl1/synlog/report/s1_impl1_compiler_errors.txt b/impl1/synlog/report/s1_impl1_compiler_errors.txt
new file mode 100644
index 0000000..9b24368
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_compiler_errors.txt
@@ -0,0 +1,2 @@
+@E: CH103 :	| One or more distribution nodes failed to compile.
+
diff --git a/impl1/synlog/report/s1_impl1_compiler_notes.txt b/impl1/synlog/report/s1_impl1_compiler_notes.txt
new file mode 100644
index 0000000..c162548
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_compiler_notes.txt
@@ -0,0 +1,34 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+@N|Running in 64-bit mode
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+
diff --git a/impl1/synlog/report/s1_impl1_compiler_runstatus.xml b/impl1/synlog/report/s1_impl1_compiler_runstatus.xml
new file mode 100644
index 0000000..6a28a3b
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+			<info name="Notes">
+  <data>33</data>
+  <report_link name="more"><data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_notes.txt</data></report_link>
+  </info>
+			<info name="Warnings">
+  <data>8</data>
+  <report_link name="more"><data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_warnings.txt</data></report_link>
+  </info>
+			<info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_errors.txt</data></report_link>
+  </info>
+			<info name="CPU Time">
+  <data>-</data>
+  </info>
+			<info name="Real Time">
+  <data>00h:00m:03s</data>
+  </info>
+			<info name="Peak Memory">
+  <data>-</data>
+  </info>
+			<info name="Date &amp;Time">
+  <data type="timestamp">1623827956</data>
+  </info>
+			</job_info>
+</job_run_status>
\ No newline at end of file
diff --git a/impl1/synlog/report/s1_impl1_compiler_warnings.txt b/impl1/synlog/report/s1_impl1_compiler_warnings.txt
new file mode 100644
index 0000000..187dc16
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_compiler_warnings.txt
@@ -0,0 +1,9 @@
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml
new file mode 100644
index 0000000..b466386
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>934</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>186</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>4</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>180</data>
+</parameter>
+</report_table>
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt
new file mode 100644
index 0000000..085063d
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt
@@ -0,0 +1,21 @@
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml
new file mode 100644
index 0000000..a357e2a
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary"></report_table>
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt b/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt
new file mode 100644
index 0000000..d7cf118
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt
@@ -0,0 +1,36 @@
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml
new file mode 100644
index 0000000..edd26c1
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_fpga_mapper.srr</data>
+<title></title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>21</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>13</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:07s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:07s</data>
+</info>
+<info name="Peak Memory">
+<data>153MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1623827965</data>
+</info>
+</job_info>
+</job_run_status>
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml
new file mode 100644
index 0000000..41bed49
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>pll0|CLKOP_inferred_clock</data>
+<data>200.0 MHz</data>
+<data>1037.3 MHz</data>
+<data>4.036</data>
+</row>
+<row>
+<data>pll0|CLKOS2_inferred_clock</data>
+<data>200.0 MHz</data>
+<data>1037.3 MHz</data>
+<data>4.036</data>
+</row>
+<row>
+<data>pll0|CLKOS3_inferred_clock</data>
+<data>200.0 MHz</data>
+<data>158.6 MHz</data>
+<data>-0.652</data>
+</row>
+<row>
+<data>pll0|CLKOS_inferred_clock</data>
+<data>200.0 MHz</data>
+<data>1037.3 MHz</data>
+<data>4.036</data>
+</row>
+<row>
+<data>top_tf|rd_clk</data>
+<data>200.0 MHz</data>
+<data>256.6 MHz</data>
+<data>1.103</data>
+</row>
+<row>
+<data>System</data>
+<data>200.0 MHz</data>
+<data>527.3 MHz</data>
+<data>3.103</data>
+</row>
+</report_table>
diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt
new file mode 100644
index 0000000..81a1838
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt
@@ -0,0 +1,13 @@
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
diff --git a/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml b/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml
new file mode 100644
index 0000000..18b0dca
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION 
+ The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************--> 
+
+<job_run_status name="hdl_info_gen"> 
+																<job_status> <data>Running</data> 
+			</job_status>
+<job_info> 
+</job_info> 
+ </job_run_status>
+		 <job_info> 
+			<info name="Notes"> 
+  <data>0</data>
+  </info>			<info name="Warnings"><data>0</data> 
+ </info> 
+ 			<info name="Errors"><data>0</data>
+ </info> 
+			<info name="CPU Time"><data>-</data></info> 
+ 			<info name="Real Time"><data>-</data></info> 
+ 			<info name="Peak Memory"><data>-</data></info> 
+ 			<info name="Date &amp;Time"><data>-</data></info> 
+ 			</job_info> 
+             </job_run_status>
\ No newline at end of file
diff --git a/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt b/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt
new file mode 100644
index 0000000..0af1174
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt
@@ -0,0 +1,29 @@
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
diff --git a/impl1/synlog/report/s1_impl1_premap_errors.txt b/impl1/synlog/report/s1_impl1_premap_errors.txt
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synlog/report/s1_impl1_premap_notes.txt b/impl1/synlog/report/s1_impl1_premap_notes.txt
new file mode 100644
index 0000000..26ac484
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_premap_notes.txt
@@ -0,0 +1,25 @@
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
diff --git a/impl1/synlog/report/s1_impl1_premap_opt_report.xml b/impl1/synlog/report/s1_impl1_premap_opt_report.xml
new file mode 100644
index 0000000..35403c5
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_premap_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>1 / 4</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>
diff --git a/impl1/synlog/report/s1_impl1_premap_runstatus.xml b/impl1/synlog/report/s1_impl1_premap_runstatus.xml
new file mode 100644
index 0000000..e28a1f7
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_premap.srr</data>
+<title></title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>25</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>8</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:01s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>145MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1623827958</data>
+</info>
+</job_info>
+</job_run_status>
diff --git a/impl1/synlog/report/s1_impl1_premap_warnings.txt b/impl1/synlog/report/s1_impl1_premap_warnings.txt
new file mode 100644
index 0000000..e5084c9
--- /dev/null
+++ b/impl1/synlog/report/s1_impl1_premap_warnings.txt
@@ -0,0 +1,8 @@
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
diff --git a/impl1/synlog/s1_impl1_compiler.srr b/impl1/synlog/s1_impl1_compiler.srr
new file mode 100644
index 0000000..f964ee1
--- /dev/null
+++ b/impl1/synlog/s1_impl1_compiler.srr
@@ -0,0 +1,279 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
diff --git a/impl1/synlog/s1_impl1_compiler.srr.db b/impl1/synlog/s1_impl1_compiler.srr.db
new file mode 100644
index 0000000..f9b8e77
Binary files /dev/null and b/impl1/synlog/s1_impl1_compiler.srr.db differ
diff --git a/impl1/synlog/s1_impl1_compiler.srr.rptmap b/impl1/synlog/s1_impl1_compiler.srr.rptmap
new file mode 100644
index 0000000..6d8e7e9
--- /dev/null
+++ b/impl1/synlog/s1_impl1_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/s1_impl1_compiler.srr,s1_impl1_compiler.srr,Compile Log
diff --git a/impl1/synlog/s1_impl1_fpga_mapper.srr b/impl1/synlog/s1_impl1_fpga_mapper.srr
new file mode 100644
index 0000000..ca796af
--- /dev/null
+++ b/impl1/synlog/s1_impl1_fpga_mapper.srr
@@ -0,0 +1,1241 @@
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
+@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
+@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
+@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
+@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
+@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Jun 16 09:19:25 2021
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS2_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS3_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll0|CLKOS_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: top_tf|rd_clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
diff --git a/impl1/synlog/s1_impl1_fpga_mapper.srr.db b/impl1/synlog/s1_impl1_fpga_mapper.srr.db
new file mode 100644
index 0000000..3d740d3
Binary files /dev/null and b/impl1/synlog/s1_impl1_fpga_mapper.srr.db differ
diff --git a/impl1/synlog/s1_impl1_fpga_mapper.szr b/impl1/synlog/s1_impl1_fpga_mapper.szr
new file mode 100644
index 0000000..440b6c9
Binary files /dev/null and b/impl1/synlog/s1_impl1_fpga_mapper.szr differ
diff --git a/impl1/synlog/s1_impl1_multi_srs_gen.srr b/impl1/synlog/s1_impl1_multi_srs_gen.srr
new file mode 100644
index 0000000..2dbe59d
--- /dev/null
+++ b/impl1/synlog/s1_impl1_multi_srs_gen.srr
@@ -0,0 +1,31 @@
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
diff --git a/impl1/synlog/s1_impl1_multi_srs_gen.srr.db b/impl1/synlog/s1_impl1_multi_srs_gen.srr.db
new file mode 100644
index 0000000..33612a2
Binary files /dev/null and b/impl1/synlog/s1_impl1_multi_srs_gen.srr.db differ
diff --git a/impl1/synlog/s1_impl1_premap.srr b/impl1/synlog/s1_impl1_premap.srr
new file mode 100644
index 0000000..60ab429
--- /dev/null
+++ b/impl1/synlog/s1_impl1_premap.srr
@@ -0,0 +1,183 @@
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
diff --git a/impl1/synlog/s1_impl1_premap.srr.db b/impl1/synlog/s1_impl1_premap.srr.db
new file mode 100644
index 0000000..ab7def4
Binary files /dev/null and b/impl1/synlog/s1_impl1_premap.srr.db differ
diff --git a/impl1/synlog/s1_impl1_premap.szr b/impl1/synlog/s1_impl1_premap.szr
new file mode 100644
index 0000000..4f6c1ed
Binary files /dev/null and b/impl1/synlog/s1_impl1_premap.szr differ
diff --git a/impl1/synlog/s1_impl1_premap.xck b/impl1/synlog/s1_impl1_premap.xck
new file mode 100644
index 0000000..6d0350e
--- /dev/null
+++ b/impl1/synlog/s1_impl1_premap.xck
@@ -0,0 +1,5 @@
+ckid0_1:@|S:pll0inst.PLLInst_0.CLKOS3@|E:reset_dl[2:1]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
+ckid0_3:@|S:pll0inst.PLLInst_0.CLKOS2@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
+ckid0_5:@|S:pll0inst.PLLInst_0.CLKOS@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5
+ckid0_7:@|S:pll0inst.PLLInst_0.CLKOP@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7
+ckid0_8:@|S:rd_clk@|E:trb_adapter_inst.FEE_DATA_WRITE_OUT@|F:@syn_dgcc_clockid0_8==1@|M:ClockId_0_8
diff --git a/impl1/synlog/syntax.log.rptmap b/impl1/synlog/syntax.log.rptmap
new file mode 100644
index 0000000..ec1cbda
--- /dev/null
+++ b/impl1/synlog/syntax.log.rptmap
@@ -0,0 +1 @@
+./syntax.log,syntax.log,Compile Log
diff --git a/impl1/synlog/syntax_constraint_check.rpt.rptmap b/impl1/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644
index 0000000..638a804
--- /dev/null
+++ b/impl1/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./s1_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
diff --git a/impl1/syntax.log b/impl1/syntax.log
new file mode 100644
index 0000000..8dfd131
--- /dev/null
+++ b/impl1/syntax.log
@@ -0,0 +1,30 @@
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+@N|Running in 64-bit mode
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:12 2021
+
+###########################################################]
diff --git a/impl1/syntax.log.db b/impl1/syntax.log.db
new file mode 100644
index 0000000..33612a2
Binary files /dev/null and b/impl1/syntax.log.db differ
diff --git a/impl1/synthesis.log b/impl1/synthesis.log
new file mode 100644
index 0000000..f5c31f3
--- /dev/null
+++ b/impl1/synthesis.log
@@ -0,0 +1,154 @@
+synthesis:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Fri Jul 24 14:34:04 2020
+
+
+Command Line:  synthesis -f s1_impl1_lattice.synproj -gui 
+
+Synthesis options:
+The -a option is ECP5UM5G.
+The -s option is 8.
+The -t option is CABGA381.
+The -d option is LFE5UM5G-45F.
+Using package CABGA381.
+Using performance grade 8.
+                                                          
+
+##########################################################
+
+### Lattice Family : ECP5UM5G
+
+### Device  : LFE5UM5G-45F
+
+### Package : CABGA381
+
+### Speed   : 8
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Timing
+Top-level module name = top.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = FALSE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
+-p /home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data (searchpath added)
+-p /home/hadaq/mmichalek/lattice/simplified/impl1 (searchpath added)
+-p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
+Verilog design file = /home/hadaq/mmichalek/lattice/simplified/top.v
+NGD file = s1_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+--------- Intermediate File Dump will be done -----------
+
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top.v. VERI-1482
+Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
+Top module name (Verilog): top
+INFO - synthesis: /home/hadaq/mmichalek/lattice/simplified/top.v(1): compiling module top. VERI-1018
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Top-level module name = top.
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in top_drc.log.
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+WARNING - synthesis: logical net 'GND_net' has no load.
+WARNING - synthesis: DRC complete with 1 warnings.
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file s1_impl1.ngd.
+
+################### Begin Area Report (top)######################
+Number of register bits => 2 of 44457 (0 % )
+FD1S3IX => 2
+GSR => 1
+IB => 2
+LUT4 => 2
+OB => 2
+################### End Area Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 1
+  Net : clk_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 0
+Top 0 highest fanout Clock Enables:
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : cnt_c_0, loads : 3
+  Net : reset_c, loads : 2
+  Net : cnt_c_1, loads : 2
+  Net : n14, loads : 1
+  Net : n15, loads : 1
+  Net : cnt[1], loads : 0
+  Net : cnt[0], loads : 0
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets clk_c]                   |  200.000 MHz|  388.500 MHz|     2  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Peak Memory Usage: 245.766  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.976  secs
+--------------------------------------------------------------
diff --git a/impl1/synthesis_lse.html b/impl1/synthesis_lse.html
new file mode 100644
index 0000000..767f468
--- /dev/null
+++ b/impl1/synthesis_lse.html
@@ -0,0 +1,219 @@
+<HTML>
+<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
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+</STYLE>
+</HEAD>
+<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild  Report</big></U></B>
+synthesis:  version Diamond (64-bit) 3.11.2.446
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Fri Jul 24 14:34:04 2020
+
+
+Command Line:  synthesis -f s1_impl1_lattice.synproj -gui 
+
+Synthesis options:
+The -a option is ECP5UM5G.
+The -s option is 8.
+The -t option is CABGA381.
+The -d option is LFE5UM5G-45F.
+Using package CABGA381.
+Using performance grade 8.
+                                                          
+
+##########################################################
+
+### Lattice Family : ECP5UM5G
+
+### Device  : LFE5UM5G-45F
+
+### Package : CABGA381
+
+### Speed   : 8
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Timing
+Top-level module name = top.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = FALSE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
+-p /home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data (searchpath added)
+-p /home/hadaq/mmichalek/lattice/simplified/impl1 (searchpath added)
+-p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
+Verilog design file = /home/hadaq/mmichalek/lattice/simplified/top.v
+NGD file = s1_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+--------- Intermediate File Dump will be done -----------
+
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top.v. VERI-1482
+Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
+Top module name (Verilog): top
+INFO - synthesis: /home/hadaq/mmichalek/lattice/simplified/top.v(1): compiling module top. VERI-1018
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.38.
+Top-level module name = top.
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in top_drc.log.
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+WARNING - synthesis: logical net 'GND_net' has no load.
+WARNING - synthesis: DRC complete with 1 warnings.
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file s1_impl1.ngd.
+
+################### Begin Area Report (top)######################
+Number of register bits => 2 of 44457 (0 % )
+FD1S3IX => 2
+GSR => 1
+IB => 2
+LUT4 => 2
+OB => 2
+################### End Area Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 1
+  Net : clk_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 0
+Top 0 highest fanout Clock Enables:
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : cnt_c_0, loads : 3
+  Net : reset_c, loads : 2
+  Net : cnt_c_1, loads : 2
+  Net : n14, loads : 1
+  Net : n15, loads : 1
+  Net : cnt[1], loads : 0
+  Net : cnt[0], loads : 0
+################### End Clock Report ##################
+
+<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets clk_c]                   |  200.000 MHz|  388.500 MHz|     2  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Peak Memory Usage: 245.766  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.976  secs
+--------------------------------------------------------------
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
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+<BR>
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+<BR>
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+<BR>
+<BR>
+<BR>
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+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/syntmp/closed.png b/impl1/syntmp/closed.png
new file mode 100644
index 0000000..0d78634
Binary files /dev/null and b/impl1/syntmp/closed.png differ
diff --git a/impl1/syntmp/cmdrec_compiler.log b/impl1/syntmp/cmdrec_compiler.log
new file mode 100644
index 0000000..5eb4ef5
--- /dev/null
+++ b/impl1/syntmp/cmdrec_compiler.log
@@ -0,0 +1,29 @@
+/opt/synplicity/O-2018.09-SP1/bin/c_hdl  -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs  -top  top_tf  -hdllog  /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_compiler.srr  -encrypt  -mp  4  -prodtype  synplify_premier  -distcompmode 1 -verification_mode 0  -vhdl  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd  -verilog  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/hadaq/mmichalek/lattice/simplified  -I /home/hadaq/mmichalek/lattice/simplified/impl1/  -I /opt/synplicity/O-2018.09-SP1/lib   -v2001  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v  -encrypt  -pro    -DSBP_SYNTHESIS    -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -jobname  "compiler" 
+relcom:/opt/synplicity/O-2018.09-SP1/bin/c_hdl -osyn ../synwork/s1_impl1_comp.srs -top top_tf -hdllog ../synlog/s1_impl1_compiler.srr -encrypt -mp 4 -prodtype synplify_premier -distcompmode 1 -verification_mode 0 -vhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen ../dm -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -lib work ../../../multipll/uart/source/intface.vhd -lib work ../../../multipll/uart/source/modem.vhd -lib work ../../../multipll/uart/source/rxcver.vhd -lib work ../../../multipll/uart/source/txmitt.vhd -lib work ../../endp_dummy.vhd -lib work ../../endp_handler.vhd -lib work ../../../multipll/uart/source/uart_top.vhd -lib work ../../trb5_tb.vhd -verilog -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ../../../simplified -I ../ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -dmgen ../dm -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work ../../pll0/pll0.v -lib work ../../pll1/pll1.v -lib work ../../fifo32dc/fifo32dc.v -lib work ../../../multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work ../../pll8/pll8.v -lib work ../../pll_random/pll_random.v -lib work ../../modules2.v -lib work ../../fifo_colector.v -lib work ../../fifo40_dc/fifo40_dc.v -lib work ../../top2.v -lib work ../../hades_modules.v -lib work ../../hades_modules2.v -jobname "compiler"
+rc:0 success:1 runtime:4
+file:../synwork/s1_impl1_comp.srs|io:o|time:1623827956|size:53444|exec:0|csum:
+file:../synlog/s1_impl1_compiler.srr|io:o|time:1623827956|size:16163|exec:0|csum:
+file:../../../multipll/uart/source/intface.vhd|io:i|time:1592814713|size:30051|exec:0|csum:D854FC2C3D95524B00DCCAC08FAF5A18
+file:../../../multipll/uart/source/modem.vhd|io:i|time:1591120075|size:4404|exec:0|csum:F335C4420DFC40C4363DB3951A785F87
+file:../../../multipll/uart/source/rxcver.vhd|io:i|time:1591120075|size:16473|exec:0|csum:F4321EC8CFE7E32BE35EB328020CC76E
+file:../../../multipll/uart/source/txmitt.vhd|io:i|time:1591120075|size:12706|exec:0|csum:A35E3A0C179588788B2581CBCE8006D2
+file:../../endp_dummy.vhd|io:i|time:1614208577|size:2063|exec:0|csum:9006F992ED92E1AFD763F7542917903F
+file:../../endp_handler.vhd|io:i|time:1614208577|size:1573|exec:0|csum:A164DE39CB446FDDD4439A37589EACE2
+file:../../../multipll/uart/source/uart_top.vhd|io:i|time:1591120075|size:11998|exec:0|csum:A1341B5E671CAFFDA707C183974A0AE5
+file:../../trb5_tb.vhd|io:i|time:1614208538|size:3169|exec:0|csum:39D3A8013FEB8D9D61AE50C023F8946C
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|io:i|time:1543381843|size:87866|exec:0|csum:860F88D9F12F192B101D34E522DBD633
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|io:i|time:1543381843|size:39414|exec:0|csum:530CC5906D70AB3C6A4AA0861AC94BDF
+file:../../pll0/pll0.v|io:i|time:1603268894|size:3944|exec:0|csum:E34244DD864C34A7BBC769C32E2DDA19
+file:../../pll1/pll1.v|io:i|time:1603268905|size:3170|exec:0|csum:207089EE34402023668BE04664C126CB
+file:../../fifo32dc/fifo32dc.v|io:i|time:1600007909|size:41091|exec:0|csum:A4AC3932E5EA82E2F0544EAF8E51FD99
+file:../../../multipll/uart/source/UART_VerilogWrapper_TOP.v|io:i|time:1591120075|size:6017|exec:0|csum:E2C0828639780017B920EBAC02603DF1
+file:../../pll8/pll8.v|io:i|time:1603268916|size:3413|exec:0|csum:594D89D2672E246D4879133695CCB39C
+file:../../pll_random/pll_random.v|io:i|time:1603268926|size:3705|exec:0|csum:0641107DF287A320BFE4F05DD1B35292
+file:../../modules2.v|io:i|time:1623422897|size:9354|exec:0|csum:024E1B8C15106724E9C3A0D318B7DC35
+file:../../fifo_colector.v|io:i|time:1623231962|size:2679|exec:0|csum:E53F6AE06C3116749F16615804A03CE5
+file:../../fifo40_dc/fifo40_dc.v|io:i|time:1612873166|size:43620|exec:0|csum:130DD4717374BC3F5AF8439126E0ECBF
+file:../../top2.v|io:i|time:1623749991|size:9192|exec:0|csum:BDB1B93A479842BB4E024EE22456B46C
+file:../../hades_modules.v|io:i|time:1623772752|size:5537|exec:0|csum:E0449E435EC13BF4F50B1E34A6925CC7
+file:../../hades_modules2.v|io:i|time:1623827946|size:4936|exec:0|csum:2FEAF5628831294381058DD4D9FCED0F
+file:/opt/synplicity/O-2018.09-SP1/linux_a_64/c_hdl|io:i|time:1543382462|size:8760008|exec:1|csum:CF968C540087EF9F5288FFCDBF191EA5
+file:/opt/synplicity/O-2018.09-SP1/bin/c_hdl|io:i|time:1543382354|size:367|exec:1|csum:E52A0D56112AD6C22F02B648B6F508CE
diff --git a/impl1/syntmp/cmdrec_fpga_mapper.log b/impl1/syntmp/cmdrec_fpga_mapper.log
new file mode 100644
index 0000000..2edc76b
--- /dev/null
+++ b/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -0,0 +1,12 @@
+/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice  -prodtype  synplify_premier  -encrypt  -pro  -rundir  /home/hadaq/mmichalek/lattice/simplified/impl1   -part LFE5UM5G_45F  -package BG381C  -grade -8    -maxfan 1000 -pipe -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -summaryfile /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  top_tf  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi   -freq 200.000   /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srd  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v  -ologparam  /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1.plg  -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm  -prjdir  /home/hadaq/mmichalek/lattice/simplified/impl1/  -prjname  proj_1  -log  /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_fpga_mapper.srr  -sn  2018.09  -jobname  "fpga_mapper" 
+relcom:/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice -prodtype synplify_premier -encrypt -pro -rundir ../../impl1 -part LFE5UM5G_45F -package BG381C -grade -8 -maxfan 1000 -pipe -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -summaryfile ../synlog/report/s1_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top_tf -flow mapping -multisrs -ta_num_paths 3 -oedif ../s1_impl1.edi -freq 200.000 ../synwork/s1_impl1_prem.srd -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -ologparam s1_impl1.plg -osyn ../s1_impl1.srm -prjdir ../ -prjname proj_1 -log ../synlog/s1_impl1_fpga_mapper.srr -sn 2018.09 -jobname "fpga_mapper"
+rc:1 success:1 runtime:7
+file:../s1_impl1.edi|io:o|time:1623827965|size:982212|exec:0|csum:
+file:../synwork/s1_impl1_prem.srd|io:i|time:1623827958|size:79120|exec:0|csum:BEBDEB80DF8C0EBE914176CBB1DA42DC
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|io:i|time:1543381843|size:87866|exec:0|csum:860F88D9F12F192B101D34E522DBD633
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|io:i|time:1543381843|size:39414|exec:0|csum:530CC5906D70AB3C6A4AA0861AC94BDF
+file:s1_impl1.plg|io:o|time:1623827965|size:2266|exec:0|csum:
+file:../s1_impl1.srm|io:o|time:1623827965|size:22210|exec:0|csum:
+file:../synlog/s1_impl1_fpga_mapper.srr|io:o|time:1623827965|size:109779|exec:0|csum:
+file:/opt/synplicity/O-2018.09-SP1/linux_a_64/m_gen_lattice|io:i|time:1543382453|size:37442576|exec:1|csum:909C57B48639E574B9988525DAE21826
+file:/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice|io:i|time:1543381999|size:347|exec:1|csum:04851DFC0CBB288ED81DA3E420127D0D
diff --git a/impl1/syntmp/cmdrec_hdl_info_gen.log b/impl1/syntmp/cmdrec_hdl_info_gen.log
new file mode 100644
index 0000000..ee00692
--- /dev/null
+++ b/impl1/syntmp/cmdrec_hdl_info_gen.log
@@ -0,0 +1,15 @@
+/opt/synplicity/O-2018.09-SP1/bin/c_vhdl  -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_hdl_.srs  -top  top_tf  -prodtype  synplify_premier  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/hadaq/mmichalek/lattice/simplified/impl1/dm  -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd  -log  /home/hadaq/mmichalek/lattice/simplified/impl1/syntax.log  -fileorder  /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/hdlorder.tcl  -jobname  "hdl_info_gen" 
+relcom:/opt/synplicity/O-2018.09-SP1/bin/c_vhdl -osyn ../synwork/s1_impl1_hdl_.srs -top top_tf -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen ../dm -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -lib work ../../../multipll/uart/source/intface.vhd -lib work ../../../multipll/uart/source/modem.vhd -lib work ../../../multipll/uart/source/rxcver.vhd -lib work ../../../multipll/uart/source/txmitt.vhd -lib work ../../../multipll/uart/source/uart_top.vhd -lib work ../../trb5_tb.vhd -lib work ../../endp_dummy.vhd -lib work ../../endp_handler.vhd -log ../syntax.log -fileorder hdlorder.tcl -jobname "hdl_info_gen"
+rc:0 success:1 runtime:0
+file:../synwork/s1_impl1_hdl_.srs|io:o|time:0|size:-1|exec:0|csum:
+file:../../../multipll/uart/source/intface.vhd|io:i|time:1592814713|size:30051|exec:0|csum:D854FC2C3D95524B00DCCAC08FAF5A18
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+file:../../endp_dummy.vhd|io:i|time:1614208577|size:2063|exec:0|csum:9006F992ED92E1AFD763F7542917903F
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+file:../syntax.log|io:o|time:1623827952|size:1105|exec:0|csum:
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+file:/opt/synplicity/O-2018.09-SP1/bin/c_vhdl|io:i|time:1543382354|size:367|exec:1|csum:E52A0D56112AD6C22F02B648B6F508CE
diff --git a/impl1/syntmp/cmdrec_multi_srs_gen.log b/impl1/syntmp/cmdrec_multi_srs_gen.log
new file mode 100644
index 0000000..2ce0b60
--- /dev/null
+++ b/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -0,0 +1,8 @@
+/opt/synplicity/O-2018.09-SP1/bin/syn_nfilter  -link  -top  top_tf  -multisrs  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs  -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs  -log  /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_multi_srs_gen.srr 
+relcom:/opt/synplicity/O-2018.09-SP1/bin/syn_nfilter -link -top top_tf -multisrs ../synwork/s1_impl1_comp.srs -osyn ../synwork/s1_impl1_mult.srs -log ../synlog/s1_impl1_multi_srs_gen.srr
+rc:0 success:1 runtime:0
+file:../synwork/s1_impl1_comp.srs|io:i|time:1623827956|size:53444|exec:0|csum:7C7EE07F75660AF32A372CD3E4D8C85B
+file:../synwork/s1_impl1_mult.srs|io:o|time:1623827957|size:7441|exec:0|csum:
+file:../synlog/s1_impl1_multi_srs_gen.srr|io:o|time:1623827957|size:1220|exec:0|csum:
+file:/opt/synplicity/O-2018.09-SP1/linux_a_64/syn_nfilter|io:i|time:1543382463|size:12202632|exec:1|csum:2CF5CA82A12C53A85C3E36D57C2461DC
+file:/opt/synplicity/O-2018.09-SP1/bin/syn_nfilter|io:i|time:1543382354|size:368|exec:1|csum:004E4455B64BA10AD6A92FB2301610E0
diff --git a/impl1/syntmp/cmdrec_premap.log b/impl1/syntmp/cmdrec_premap.log
new file mode 100644
index 0000000..fb79300
--- /dev/null
+++ b/impl1/syntmp/cmdrec_premap.log
@@ -0,0 +1,14 @@
+/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice  -prodtype  synplify_premier  -encrypt  -pro  -rundir  /home/hadaq/mmichalek/lattice/simplified/impl1   -part LFE5UM5G_45F  -package BG381C  -grade -8    -maxfan 1000 -pipe -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -summaryfile /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  top_tf  -ta_num_paths  3  -oedif  /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi  -conchk_prepass  /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_cck.rpt   -freq 200.000   /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srd  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v  -devicelib  /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v  -ologparam  /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1.plg  -osyn  /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srd  -prjdir  /home/hadaq/mmichalek/lattice/simplified/impl1/  -prjname  proj_1  -log  /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_premap.srr  -sn  2018.09  -jobname  "premap" 
+relcom:/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice -prodtype synplify_premier -encrypt -pro -rundir ../../impl1 -part LFE5UM5G_45F -package BG381C -grade -8 -maxfan 1000 -pipe -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -summaryfile ../synlog/report/s1_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module top_tf -ta_num_paths 3 -oedif ../s1_impl1.edi -conchk_prepass ../s1_impl1_cck.rpt -freq 200.000 ../synwork/s1_impl1_mult.srs -flow prepass -gcc_prepass -osrd ../synwork/s1_impl1_prem.srd -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -ologparam s1_impl1.plg -osyn ../synwork/s1_impl1_prem.srd -prjdir ../ -prjname proj_1 -log ../synlog/s1_impl1_premap.srr -sn 2018.09 -jobname "premap"
+rc:1 success:1 runtime:1
+file:../s1_impl1.edi|io:o|time:1623823038|size:981867|exec:0|csum:
+file:../s1_impl1_cck.rpt|io:o|time:1623827958|size:8358|exec:0|csum:
+file:../synwork/s1_impl1_mult.srs|io:i|time:1623827957|size:7441|exec:0|csum:E0B18287D09678D81EED6A7D3C346336
+file:../synwork/s1_impl1_prem.srd|io:o|time:1623827958|size:79120|exec:0|csum:
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|io:i|time:1543381843|size:87866|exec:0|csum:860F88D9F12F192B101D34E522DBD633
+file:/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|io:i|time:1543381843|size:39414|exec:0|csum:530CC5906D70AB3C6A4AA0861AC94BDF
+file:s1_impl1.plg|io:o|time:1623827957|size:0|exec:0|csum:
+file:../synwork/s1_impl1_prem.srd|io:o|time:1623827958|size:79120|exec:0|csum:
+file:../synlog/s1_impl1_premap.srr|io:o|time:1623827958|size:18788|exec:0|csum:
+file:/opt/synplicity/O-2018.09-SP1/linux_a_64/m_gen_lattice|io:i|time:1543382453|size:37442576|exec:1|csum:909C57B48639E574B9988525DAE21826
+file:/opt/synplicity/O-2018.09-SP1/bin/m_gen_lattice|io:i|time:1543381999|size:347|exec:1|csum:04851DFC0CBB288ED81DA3E420127D0D
diff --git a/impl1/syntmp/hdlorder.tcl b/impl1/syntmp/hdlorder.tcl
new file mode 100644
index 0000000..ae0c210
--- /dev/null
+++ b/impl1/syntmp/hdlorder.tcl
@@ -0,0 +1 @@
+project -fileorder "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd" "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd" "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd" 
\ No newline at end of file
diff --git a/impl1/syntmp/open.png b/impl1/syntmp/open.png
new file mode 100644
index 0000000..a227005
Binary files /dev/null and b/impl1/syntmp/open.png differ
diff --git a/impl1/syntmp/run_option.xml b/impl1/syntmp/run_option.xml
new file mode 100644
index 0000000..321be06
--- /dev/null
+++ b/impl1/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version O-2018.09-SP1
+  Project file /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/run_option.xml
+  Written on Wed Jun 16 09:19:13 2021
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">proj_1</option>
+     <option name="device_name" display_name="Device Name">impl1: Lattice ECP5UM5G : LFE5UM5G_45F</option>
+     <option name="impl_name" display_name="Implementation Name">impl1</option>
+     <option name="top_module" display_name="Top Module">top_tf</option>
+     <option name="pipe" display_name="Pipelining">1</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">0</option>
+     <option name="maxfan" display_name="Fanout Guide">1000</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+
diff --git a/impl1/syntmp/s1_impl1.plg b/impl1/syntmp/s1_impl1.plg
new file mode 100644
index 0000000..aa50bf5
--- /dev/null
+++ b/impl1/syntmp/s1_impl1.plg
@@ -0,0 +1,59 @@
+@P:  Worst Slack : -0.652
+@P:  pll0|CLKOP_inferred_clock - Estimated Frequency : 1037.3 MHz
+@P:  pll0|CLKOP_inferred_clock - Requested Frequency : 200.0 MHz
+@P:  pll0|CLKOP_inferred_clock - Estimated Period : 0.964
+@P:  pll0|CLKOP_inferred_clock - Requested Period : 5.000
+@P:  pll0|CLKOP_inferred_clock - Slack : 4.036
+@P:  pll0|CLKOS2_inferred_clock - Estimated Frequency : 1037.3 MHz
+@P:  pll0|CLKOS2_inferred_clock - Requested Frequency : 200.0 MHz
+@P:  pll0|CLKOS2_inferred_clock - Estimated Period : 0.964
+@P:  pll0|CLKOS2_inferred_clock - Requested Period : 5.000
+@P:  pll0|CLKOS2_inferred_clock - Slack : 4.036
+@P:  pll0|CLKOS3_inferred_clock - Estimated Frequency : 158.6 MHz
+@P:  pll0|CLKOS3_inferred_clock - Requested Frequency : 200.0 MHz
+@P:  pll0|CLKOS3_inferred_clock - Estimated Period : 6.305
+@P:  pll0|CLKOS3_inferred_clock - Requested Period : 5.000
+@P:  pll0|CLKOS3_inferred_clock - Slack : -0.652
+@P:  pll0|CLKOS_inferred_clock - Estimated Frequency : 1037.3 MHz
+@P:  pll0|CLKOS_inferred_clock - Requested Frequency : 200.0 MHz
+@P:  pll0|CLKOS_inferred_clock - Estimated Period : 0.964
+@P:  pll0|CLKOS_inferred_clock - Requested Period : 5.000
+@P:  pll0|CLKOS_inferred_clock - Slack : 4.036
+@P:  top_tf|rd_clk - Estimated Frequency : 256.6 MHz
+@P:  top_tf|rd_clk - Requested Frequency : 200.0 MHz
+@P:  top_tf|rd_clk - Estimated Period : 3.897
+@P:  top_tf|rd_clk - Requested Period : 5.000
+@P:  top_tf|rd_clk - Slack : 1.103
+@P:  System - Estimated Frequency : 527.3 MHz
+@P:  System - Requested Frequency : 200.0 MHz
+@P:  System - Estimated Period : 1.897
+@P:  System - Requested Period : 5.000
+@P:  System - Slack : 3.103
+@P:  Total Area : 200.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:06s
diff --git a/impl1/syntmp/s1_impl1_srr.htm b/impl1/syntmp/s1_impl1_srr.htm
new file mode 100644
index 0000000..3352fe1
--- /dev/null
+++ b/impl1/syntmp/s1_impl1_srr.htm
@@ -0,0 +1,1777 @@
+<html><body><samp><pre>
+<!@TC:1623827953>
+#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
+#install: /opt/synplicity/O-2018.09-SP1
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Jun 16 09:19:13 2021
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827956> | Running in 64-bit mode 
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport2></a>Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827956> | Running in 64-bit mode 
+@N: : <a href="/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd:8:7:8:14:@N::@XP_MSG">trb5_tb.vhd(8)</a><!@TM:1623827956> | Top entity is set to trb5_tb.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport3></a>Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827956> | Running in 64-bit mode 
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+<font color=#A52A2A>@W:<a href="@W:CG921:@XP_HELP">CG921</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:181:21:181:34:@W:CG921:@XP_MSG">top2.v(181)</a><!@TM:1623827956> | fifo_data_out is already declared in this scope.</font>
+<font color=#A52A2A>@W:<a href="@W:CG1337:@XP_HELP">CG1337</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:270:9:270:25:@W:CG1337:@XP_MSG">top2.v(270)</a><!@TM:1623827956> | Net buf_rden_falling is not declared.</font>
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+<font color=#A52A2A>@W:<a href="@W:CG1249:@XP_HELP">CG1249</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:170:12:170:23:@W:CG1249:@XP_MSG">hades_modules2.v(170)</a><!@TM:1623827956> | Redeclaration of implicit signal decoder_out</font>
+<font color=#A52A2A>@W:<a href="@W:CG1249:@XP_HELP">CG1249</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:171:12:171:27:@W:CG1249:@XP_MSG">hades_modules2.v(171)</a><!@TM:1623827956> | Redeclaration of implicit signal decoder_out_neg</font>
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+<font color=#A52A2A>@W:<a href="@W:CG921:@XP_HELP">CG921</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:181:21:181:34:@W:CG921:@XP_MSG">top2.v(181)</a><!@TM:1623827956> | fifo_data_out is already declared in this scope.</font>
+<font color=#A52A2A>@W:<a href="@W:CG1337:@XP_HELP">CG1337</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:270:9:270:25:@W:CG1337:@XP_MSG">top2.v(270)</a><!@TM:1623827956> | Net buf_rden_falling is not declared.</font>
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+<font color=#A52A2A>@W:<a href="@W:CG1249:@XP_HELP">CG1249</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:170:12:170:23:@W:CG1249:@XP_MSG">hades_modules2.v(170)</a><!@TM:1623827956> | Redeclaration of implicit signal decoder_out</font>
+<font color=#A52A2A>@W:<a href="@W:CG1249:@XP_HELP">CG1249</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:171:12:171:27:@W:CG1249:@XP_MSG">hades_modules2.v(171)</a><!@TM:1623827956> | Redeclaration of implicit signal decoder_out_neg</font>
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:757:7:757:10:@N:CG364:@XP_MSG">ecp5um5g.v(757)</a><!@TM:1623827956> | Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:761:7:761:10:@N:CG364:@XP_MSG">ecp5um5g.v(761)</a><!@TM:1623827956> | Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:1696:7:1696:14:@N:CG364:@XP_MSG">ecp5um5g.v(1696)</a><!@TM:1623827956> | Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v:8:7:8:11:@N:CG364:@XP_MSG">pll0.v(8)</a><!@TM:1623827956> | Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:160:7:160:20:@N:CG364:@XP_MSG">modules2.v(160)</a><!@TM:1623827956> | Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:236:7:236:22:@N:CG364:@XP_MSG">modules2.v(236)</a><!@TM:1623827956> | Synthesizing module output_decoder8 in library work.
+Running optimization stage 1 on output_decoder8 .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:2:7:2:25:@N:CG364:@XP_MSG">hades_modules2.v(2)</a><!@TM:1623827956> | Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:341:7:341:15:@N:CG364:@XP_MSG">modules2.v(341)</a><!@TM:1623827956> | Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:110:7:110:32:@N:CG364:@XP_MSG">hades_modules2.v(110)</a><!@TM:1623827956> | Synthesizing module hades_tdc_channel_raw_out in library work.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules.v:2:7:2:23:@N:CG364:@XP_MSG">hades_modules.v(2)</a><!@TM:1623827956> | Synthesizing module hades_tdc_bundle in library work.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:230:7:230:18:@N:CG364:@XP_MSG">top2.v(230)</a><!@TM:1623827956> | Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:25:7:25:11:@N:CG364:@XP_MSG">ecp5um5g.v(25)</a><!@TM:1623827956> | Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:367:7:367:10:@N:CG364:@XP_MSG">ecp5um5g.v(367)</a><!@TM:1623827956> | Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:656:7:656:10:@N:CG364:@XP_MSG">ecp5um5g.v(656)</a><!@TM:1623827956> | Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:810:7:810:11:@N:CG364:@XP_MSG">ecp5um5g.v(810)</a><!@TM:1623827956> | Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:710:7:710:15:@N:CG364:@XP_MSG">ecp5um5g.v(710)</a><!@TM:1623827956> | Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:959:7:959:15:@N:CG364:@XP_MSG">ecp5um5g.v(959)</a><!@TM:1623827956> | Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:110:7:110:14:@N:CG364:@XP_MSG">ecp5um5g.v(110)</a><!@TM:1623827956> | Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:119:7:119:14:@N:CG364:@XP_MSG">ecp5um5g.v(119)</a><!@TM:1623827956> | Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:168:7:168:14:@N:CG364:@XP_MSG">ecp5um5g.v(168)</a><!@TM:1623827956> | Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:160:7:160:14:@N:CG364:@XP_MSG">ecp5um5g.v(160)</a><!@TM:1623827956> | Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v:76:7:76:12:@N:CG364:@XP_MSG">ecp5um5g.v(76)</a><!@TM:1623827956> | Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v:8:7:8:16:@N:CG364:@XP_MSG">fifo40_dc.v(8)</a><!@TM:1623827956> | Synthesizing module fifo40_dc in library work.
+Running optimization stage 1 on fifo40_dc .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v:3:7:3:20:@N:CG364:@XP_MSG">fifo_colector.v(3)</a><!@TM:1623827956> | Synthesizing module fifo_colector in library work.
+Running optimization stage 1 on fifo_colector .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:1:7:1:13:@N:CG364:@XP_MSG">top2.v(1)</a><!@TM:1623827956> | Synthesizing module top_tf in library work.
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v:8:7:8:15:@N:CG364:@XP_MSG">fifo32dc.v(8)</a><!@TM:1623827956> | Synthesizing module fifo32dc in library work.
+Running optimization stage 1 on fifo32dc .......
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:3:7:3:27:@N:CG364:@XP_MSG">modules2.v(3)</a><!@TM:1623827956> | Synthesizing module tdc_channel_fifo_out in library work.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+Running optimization stage 1 on top_tf .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827956> | Running in 64-bit mode 
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:13 2021
+
+###########################################################]
+
+Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Divided design in to 1 groups
+Log file for distribution node work.top_tf.verilog  <a href="/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log:@XP_FILE">distcomp0.log</a>
+Compiling work_top_tf_verilog as a separate process
+Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
+
+Distributed Compiler Report
+***************************
+
+DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
+==============================================================================================================================================================================
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport5></a>Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827956> | Running in 64-bit mode 
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:16 2021
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1623827953>
+###########################################################[
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=compilerReport6></a>Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49</a>
+
+@N: : <!@TM:1623827957> | Running in 64-bit mode 
+File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Jun 16 09:19:17 2021
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1623827953>
+Premap Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1623827953>
+# Wed Jun 16 09:19:17 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=mapperReport7></a>Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52</a>
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1623827958> | No constraint file specified. 
+@N:<a href="@N:MF284:@XP_HELP">MF284</a> : <!@TM:1623827958> | Setting synthesis effort to medium for the design 
+Linked File:  <a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt:@XP_FILE">s1_impl1_scck.rpt</a>
+Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
+@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1623827958> | Option synthesis_strategy=base is enabled.  
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1623827958> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1623827958> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+@N:<a href="@N:MF284:@XP_HELP">MF284</a> : <!@TM:1623827958> | Setting synthesis effort to medium for the design 
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:90:17:90:29:@N:BN115:@XP_MSG">modules2.v(90)</a><!@TM:1623827958> | Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:69:15:69:27:@N:BN115:@XP_MSG">modules2.v(69)</a><!@TM:1623827958> | Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:43:10:43:24:@N:BN115:@XP_MSG">modules2.v(43)</a><!@TM:1623827958> | Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:37:10:37:24:@N:BN115:@XP_MSG">modules2.v(37)</a><!@TM:1623827958> | Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:31:10:31:24:@N:BN115:@XP_MSG">modules2.v(31)</a><!@TM:1623827958> | Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827958> | Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827958> | Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1623827958> | UMR3 is only supported for HAPS-80. 
+@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1623827958> | UMR3 is only supported for HAPS-80. 
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827958> | Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827958> | Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:262:0:262:6:@N:BN362:@XP_MSG">modules2.v(262)</a><!@TM:1623827958> | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:262:0:262:6:@N:BN362:@XP_MSG">modules2.v(262)</a><!@TM:1623827958> | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:262:0:262:6:@N:BN362:@XP_MSG">modules2.v(262)</a><!@TM:1623827958> | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules.v:153:2:153:8:@N:BN362:@XP_MSG">hades_modules.v(153)</a><!@TM:1623827958> | Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules.v:96:1:96:7:@N:BN362:@XP_MSG">hades_modules.v(96)</a><!@TM:1623827958> | Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:272:1:272:7:@N:BN362:@XP_MSG">modules2.v(272)</a><!@TM:1623827958> | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:272:1:272:7:@N:BN362:@XP_MSG">modules2.v(272)</a><!@TM:1623827958> | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:272:1:272:7:@N:BN362:@XP_MSG">modules2.v(272)</a><!@TM:1623827958> | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
+<font color=#A52A2A>@W:<a href="@W:BN114:@XP_HELP">BN114</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v:407:13:407:26:@W:BN114:@XP_MSG">fifo40_dc.v(407)</a><!@TM:1623827958> | Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.</font>
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules.v:122:1:122:7:@N:BN362:@XP_MSG">hades_modules.v(122)</a><!@TM:1623827958> | Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:220:0:220:6:@N:BN362:@XP_MSG">top2.v(220)</a><!@TM:1623827958> | Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+syn_allowed_resources : blockrams=108  set on top level netlist top_tf
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+
+<a name=mapperReport8></a>Clock Summary</a>
+******************
+
+          Start                          Requested     Requested     Clock        Clock                   Clock
+Level     Clock                          Frequency     Period        Type         Group                   Load 
+---------------------------------------------------------------------------------------------------------------
+0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
+                                                                                                               
+0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
+                                                                                                               
+0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
+                                                                                                               
+0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
+                                                                                                               
+0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
+                                                                                                               
+0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
+===============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
+Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                         0         -                                      -                                                                                     -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
+                                                                                                                                                                                                                                                             
+top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
+                                                                                                                                                                                                                                                             
+pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
+                                                                                                                                                                                                                                                             
+pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
+                                                                                                                                                                                                                                                             
+pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
+=============================================================================================================================================================================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:181:3:181:9:@W:MT529:@XP_MSG">modules2.v(181)</a><!@TM:1623827958> | Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:181:3:181:9:@W:MT529:@XP_MSG">modules2.v(181)</a><!@TM:1623827958> | Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:181:3:181:9:@W:MT529:@XP_MSG">modules2.v(181)</a><!@TM:1623827958> | Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:181:3:181:9:@W:MT529:@XP_MSG">modules2.v(181)</a><!@TM:1623827958> | Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:305:2:305:8:@W:MT529:@XP_MSG">top2.v(305)</a><!@TM:1623827958> | Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+<a name=clockReport9></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>
+
+1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
+4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
+0 instances converted, 895 sequential instances remain driven by gated/generated clocks
+
+===================================== Non-Gated/Non-Generated Clocks ======================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
+-----------------------------------------------------------------------------------------------------------
+<a href="@|L:/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srm@|S:rd_clk@|E:trb_adapter_inst.FEE_DATA_WRITE_OUT@|F:@syn_dgcc_clockid0_8==1@|M:ClockId_0_8 @XP_NAMES_BY_PROP">ClockId_0_8</a>       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
+===========================================================================================================
+======================================================================================== Gated/Generated Clocks ========================================================================================
+Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+<a href="@|L:/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srm@|S:pll0inst.PLLInst_0.CLKOS3@|E:reset_dl[2:1]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
+<a href="@|L:/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srm@|S:pll0inst.PLLInst_0.CLKOS2@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
+<a href="@|L:/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srm@|S:pll0inst.PLLInst_0.CLKOS@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
+<a href="@|L:/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_prem.srm@|S:pll0inst.PLLInst_0.CLKOP@|E:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7 @XP_NAMES_BY_PROP">ClockId_0_7</a>       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
+========================================================================================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1623827958> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Jun 16 09:19:18 2021
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1623827953>
+Map & Optimize Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1623827953>
+# Wed Jun 16 09:19:18 2021
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+<a name=mapperReport10></a>Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52</a>
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+@N:<a href="@N:MF284:@XP_HELP">MF284</a> : <!@TM:1623827965> | Setting synthesis effort to medium for the design 
+@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1623827965> | Option synthesis_strategy=base is enabled.  
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1623827965> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1623827965> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N:<a href="@N:MF284:@XP_HELP">MF284</a> : <!@TM:1623827965> | Setting synthesis effort to medium for the design 
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827965> | Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827965> | Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules.v:140:8:140:44:@N:MF179:@XP_MSG">hades_modules.v(140)</a><!@TM:1623827965> | Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@N:BN362:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@N:BN362:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@N:BN362:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1623827965> | Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) 
+@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1623827965> | Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) 
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:138:1:138:7:@W:BN132:@XP_MSG">modules2.v(138)</a><!@TM:1623827965> | Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    -0.86ns		 187 /       525
+   2		0h:00m:02s		    -0.86ns		 184 /       525
+@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/modules2.v:262:0:262:6:@N:FX271:@XP_MSG">modules2.v(262)</a><!@TM:1623827965> | Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   3		0h:00m:04s		    -0.74ns		 186 /       526
+
+
+   4		0h:00m:04s		    -0.74ns		 186 /       526
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1623827965> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827965> | Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/top2.v:28:10:28:30:@N:MO111:@XP_MSG">top2.v(28)</a><!@TM:1623827965> | Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v:74:1:74:7:@A:BN291:@XP_MSG">hades_modules2.v(74)</a><!@TM:1623827965> | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1623827965> | Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi 
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1623827965> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v:60:12:60:21:@W:MT246:@XP_MSG">pll0.v(60)</a><!@TM:1623827965> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)</font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1623827965> | Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1623827965> | Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1623827965> | Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1623827965> | Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1623827965> | Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.</font> 
+
+
+<a name=timingReport11></a>##### START OF TIMING REPORT #####[</a>
+<a name=12></a># Timing Report written on Wed Jun 16 09:19:25 2021</a>
+#
+
+
+Top view:               top_tf
+Requested Frequency:    200.0 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1623827965> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1623827965> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary13></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: -0.652
+
+                               Requested     Estimated      Requested     Estimated                Clock        Clock              
+Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
+-----------------------------------------------------------------------------------------------------------------------------------
+pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
+pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
+pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
+pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
+top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
+System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
+===================================================================================================================================
+
+
+
+
+
+<a name=clockRelationships14></a>Clock Relationships</a>
+*******************
+
+Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
+-----------------------------------------------------------------------------------------------------------------------------------------------
+Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
+-----------------------------------------------------------------------------------------------------------------------------------------------
+System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
+pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
+pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
+pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
+top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
+top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
+===============================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo15></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport16></a>Detailed Report for Clock: pll0|CLKOP_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack17></a>Starting Points with Worst Slack</a>
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+<a name=endingSlack18></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+<a name=worstPaths19></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:63278:63716:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
+    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[0]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport20></a>Detailed Report for Clock: pll0|CLKOS2_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack21></a>Starting Points with Worst Slack</a>
+********************************
+
+                                                                                                     Starting                                                                Arrival          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
+==============================================================================================================================================================================================
+
+
+<a name=endingSlack22></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                                                                     Starting                                                                Required          
+Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
+===============================================================================================================================================================================================
+
+
+
+<a name=worstPaths23></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:75108:75546:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
+    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[2]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport24></a>Detailed Report for Clock: pll0|CLKOS3_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack25></a>Starting Points with Worst Slack</a>
+********************************
+
+                                                                      Starting                                                               Arrival           
+Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
+                                                                      Clock                                                                                    
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
+===============================================================================================================================================================
+
+
+<a name=endingSlack26></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                              Starting                                                                   Required           
+Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
+                                                              Clock                                                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
+============================================================================================================================================================
+
+
+
+<a name=worstPaths27></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:85904:89312:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.942
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -0.652
+
+    Number of logic level(s):                7
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_0                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
+=============================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      2.500
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         2.289
+
+    - Propagation time:                      2.882
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.593
+
+    Number of logic level(s):                6
+    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
+    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
+    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                              Pin      Pin               Arrival     No. of    
+Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
+valid_fast                                                                     Net          -        -       -         -           4         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
+un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
+un1_window_8_cry_2                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
+un1_window_8_cry_4                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
+un1_window_8_cry_6                                                             Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
+un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
+window_6[7]                                                                    Net          -        -       -         -           1         
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
+=============================================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport28></a>Detailed Report for Clock: pll0|CLKOS_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack29></a>Starting Points with Worst Slack</a>
+********************************
+
+                                                                                                     Starting                                                               Arrival          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
+                                                                                                     Clock                                                                                   
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
+=============================================================================================================================================================================================
+
+
+<a name=endingSlack30></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                                                                     Starting                                                               Required          
+Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
+                                                                                                     Clock                                                                                    
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
+==============================================================================================================================================================================================
+
+
+
+<a name=worstPaths31></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:105655:106093:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      0.753
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.036
+
+    Number of logic level(s):                0
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
+    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
+Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
+in_clk_synced[1]                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
+=================================================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport32></a>Detailed Report for Clock: top_tf|rd_clk</a>
+====================================
+
+
+
+<a name=startingSlack33></a>Starting Points with Worst Slack</a>
+********************************
+
+                                         Starting                                               Arrival          
+Instance                                 Reference         Type        Pin     Net              Time        Slack
+                                         Clock                                                                   
+-----------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
+fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
+fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
+fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
+fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
+fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
+fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
+fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
+=================================================================================================================
+
+
+<a name=endingSlack34></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                 Starting                                              Required          
+Instance                                         Reference         Type         Pin      Net           Time         Slack
+                                                 Clock                                                                   
+-------------------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
+fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
+fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
+fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
+fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
+fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
+=========================================================================================================================
+
+
+
+<a name=worstPaths35></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:115046:118016:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.686
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.103
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
+w_gcount_r29                                   Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
+fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
+wcount_r1                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
+=============================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      3.640
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.148
+
+    Number of logic level(s):                8
+    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
+    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
+    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
+    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
+
+Instance / Net                                              Pin      Pin               Arrival     No. of    
+Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------------
+fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
+w_gcount_r28                                   Net          -        -       -         -           3         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
+fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
+w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
+fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
+wcount_r0                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
+co0_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
+co1_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
+co2_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
+co3_2                                          Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
+fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
+empty_d_c                                      Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
+fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
+empty_d                                        Net          -        -       -         -           1         
+fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
+=============================================================================================================
+
+
+
+
+====================================
+<a name=clockReport36></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack37></a>Starting Points with Worst Slack</a>
+********************************
+
+                                                                   Starting                                     Arrival          
+Instance                                                           Reference     Type     Pin     Net           Time        Slack
+                                                                   Clock                                                         
+---------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
+fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
+=================================================================================================================================
+
+
+<a name=endingSlack38></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                                        Starting                                       Required          
+Instance                                                                Reference     Type         Pin     Net         Time         Slack
+                                                                        Clock                                                            
+-----------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
+fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
+=========================================================================================================================================
+
+
+
+<a name=worstPaths39></a>Worst Path Information</a>
+<a href="/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr:srsf/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs:fp:132132:135372:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      5.000
+    - Setup time:                            0.211
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.789
+
+    - Propagation time:                      1.685
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 3.103
+
+    Number of logic level(s):                7
+    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
+    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
+
+Instance / Net                                                                       Pin      Pin               Arrival     No. of    
+Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------------------
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
+rden_i                                                                   Net         -        -       -         -           34        
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
+cmp_ci                                                                   Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
+co0_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
+co1_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
+co2_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
+co3_2                                                                    Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
+empty_d_c                                                                Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
+empty_d                                                                  Net         -        -       -         -           1         
+genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
+======================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+<a name=resourceUsage40></a>Resource Usage Report</a>
+Part: lfe5um5g_45f-8
+
+Register bits: 934 of 43848 (2%)
+PIC Latch:       0
+I/O cells:       186
+Block Rams : 4 of 108 (3%)
+
+
+Details:
+AND2:           8
+CCU2C:          121
+EHXPLLL:        1
+FD1P3AX:        69
+FD1P3BX:        8
+FD1P3DX:        232
+FD1P3IX:        50
+FD1S3AX:        321
+FD1S3BX:        4
+FD1S3DX:        164
+FD1S3IX:        41
+FD1S3JX:        10
+GSR:            1
+IB:             11
+IFS1P3DX:       5
+INV:            20
+OB:             173
+OBZ:            2
+OFS1P3DX:       17
+OFS1P3IX:       13
+OR2:            4
+ORCALUT4:       180
+PDPW16KD:       4
+PUR:            1
+ROM16X1A:       96
+VHI:            25
+VLO:            6
+XOR2:           72
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
+
+Process took 0h:00m:07s realtime, 0h:00m:07s cputime
+# Wed Jun 16 09:19:25 2021
+
+###########################################################]
+
+</pre></samp></body></html>
diff --git a/impl1/syntmp/s1_impl1_toc.htm b/impl1/syntmp/s1_impl1_toc.htm
new file mode 100644
index 0000000..6b60a7d
--- /dev/null
+++ b/impl1/syntmp/s1_impl1_toc.htm
@@ -0,0 +1,73 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///opt/synplicity/O-2018.09-SP1/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///opt/synplicity/O-2018.09-SP1/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="impl1-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">proj_1 (impl1)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#mapperReport7" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#mapperReport8" target="srrFrame" title="">Clock Summary</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#mapperReport10" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#timingReport11" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#performanceSummary13" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockRelationships14" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#interfaceInfo15" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport16" target="srrFrame" title="">Clock: pll0|CLKOP_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack17" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack18" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths19" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport20" target="srrFrame" title="">Clock: pll0|CLKOS2_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack21" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack22" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths23" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport24" target="srrFrame" title="">Clock: pll0|CLKOS3_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack25" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack26" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths27" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport28" target="srrFrame" title="">Clock: pll0|CLKOS_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack29" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack30" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths31" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport32" target="srrFrame" title="">Clock: top_tf|rd_clk</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack33" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack34" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths35" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#clockReport36" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#startingSlack37" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#endingSlack38" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#worstPaths39" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm#resourceUsage40" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (09:19 16-Jun)</a>  </li></ul></li>
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Place and Route -  </b> 
+<ul rel="open">
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/s1_impl1_srr.htm" target="srrFrame" title="">Timing Report</a>  </li></ul></li>
+<li><a href="file:///home/hadaq/mmichalek/lattice/simplified/impl1/stdout.log" target="srrFrame" title="">Session Log (09:19 16-Jun)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("impl1-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file
diff --git a/impl1/syntmp/statusReport.html b/impl1/syntmp/statusReport.html
new file mode 100644
index 0000000..c31e077
--- /dev/null
+++ b/impl1/syntmp/statusReport.html
@@ -0,0 +1,117 @@
+<html> 
+ 			<head> 			<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+			<title>Project Status Summary Page</title>
+			<link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+			<script type = "text/javascript" src="projectstatuspage.js"></script>
+			</head>
+
+ 			<body style="background-color:#f0f0ff;">
+ 			
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0"> 	     <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> proj_1</td> <td class="optionTitle" align="left"> Device Name</td> <td> impl1: Lattice ECP5UM5G : LFE5UM5G_45F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> impl1</td> <td class="optionTitle" align="left"> Top Module</td> <td> top_tf</td> </tr>
+ 		 </thead> 
+		 <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 1</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 0</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 1000</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>	 <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+ 				   <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+ 		<tr>
+ 			<th align="left" width="17%">Job Name</th>
+			<th align="left">Status</th>
+ 			<td class="lnote" align="center" title="Notes"></td>
+ 			<td class="lwarn" align="center" title="Warnings"></td>
+ 			<td class="lerror" align="center" title="Errors"></td>
+ 			<th align="left">CPU Time</th>
+ 			<th align="left">Real Time</th>
+ 			<th align="left">Memory</th>
+ 			<th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>33</td>
+ <td>8</td>
+<td>0</td>
+<td>-</td>
+<td>00m:03s</td>
+<td>-</td>
+<td><font size="-1">6/16/21</font><br/><font size="-2">9:19 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>25</td>
+ <td>8</td>
+<td>0</td>
+<td>0m:01s</td>
+<td>0m:00s</td>
+<td>145MB</td>
+<td><font size="-1">6/16/21</font><br/><font size="-2">9:19 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>21</td>
+ <td>13</td>
+<td>0</td>
+<td>0m:07s</td>
+<td>0m:07s</td>
+<td>153MB</td>
+<td><font size="-1">6/16/21</font><br/><font size="-2">9:19 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">6/16/21</font><br/><font size="-2">9:19 AM</font></td> 		</tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+ 				   <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>934</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>186</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>4</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>180</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+ 				   <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">pll0|CLKOP_inferred_clock</td><td  align="left">200.0 MHz</td><td  align="left">1037.3 MHz</td><td  align="left">4.036</td></tr> 
+<tr> <td  align="left">pll0|CLKOS2_inferred_clock</td><td  align="left">200.0 MHz</td><td  align="left">1037.3 MHz</td><td  align="left">4.036</td></tr> 
+<tr> <td  align="left">pll0|CLKOS3_inferred_clock</td><td  align="left">200.0 MHz</td><td  align="left">158.6 MHz</td><td  align="left">-0.652</td></tr> 
+<tr> <td  align="left">pll0|CLKOS_inferred_clock</td><td  align="left">200.0 MHz</td><td  align="left">1037.3 MHz</td><td  align="left">4.036</td></tr> 
+<tr> <td  align="left">top_tf|rd_clk</td><td  align="left">200.0 MHz</td><td  align="left">256.6 MHz</td><td  align="left">1.103</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">200.0 MHz</td><td  align="left">527.3 MHz</td><td  align="left">3.103</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+ 				   <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>1 / 4</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file
diff --git a/impl1/syntmp/traplog.tlg b/impl1/syntmp/traplog.tlg
new file mode 100644
index 0000000..49bcb5d
--- /dev/null
+++ b/impl1/syntmp/traplog.tlg
@@ -0,0 +1,23 @@
+@N: CD630 :"/home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/gentmp1842Qm2Ltg":4:7:4:9|Synthesizing work.top.gen.
+@N: CD630 :"syng0rf3Y85":71:7:71:12|Synthesizing work.cmp_eq.cell_level.
+@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 5 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
+@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 6 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
+@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 7 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
+@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 8 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
+@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 9 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
+@W: CD638 :"syng0rf3Y85":105:8:105:9|Signal t1 is undriven. Either assign the signal a value or remove the signal declaration.
+@N: CD630 :"syng0rf3Y85":8:7:8:16|Synthesizing work.eq_element.eqn.
+@W: CD280 :"syng0rf3Y85":17:11:17:17|Unbound component MUXCY_L mapped to black box
+@N: CD630 :"syng0rf3Y85":17:11:17:17|Synthesizing work.muxcy_l.syn_black_box.
+Post processing for work.muxcy_l.syn_black_box
+Running optimization stage 1 on MUXCY_L .......
+Post processing for work.eq_element.eqn
+Running optimization stage 1 on eq_element .......
+Post processing for work.cmp_eq.cell_level
+Running optimization stage 1 on CMP_EQ .......
+Post processing for work.top.gen
+Running optimization stage 1 on top .......
+Running optimization stage 2 on MUXCY_L .......
+Running optimization stage 2 on eq_element .......
+Running optimization stage 2 on CMP_EQ .......
+Running optimization stage 2 on top .......
diff --git a/impl1/syntmp/traplog.tlg.db b/impl1/syntmp/traplog.tlg.db
new file mode 100644
index 0000000..83dfd3c
Binary files /dev/null and b/impl1/syntmp/traplog.tlg.db differ
diff --git a/impl1/synwork/.cckTransfer b/impl1/synwork/.cckTransfer
new file mode 100644
index 0000000..32050b5
Binary files /dev/null and b/impl1/synwork/.cckTransfer differ
diff --git a/impl1/synwork/_mh_info b/impl1/synwork/_mh_info
new file mode 100644
index 0000000..37bc105
--- /dev/null
+++ b/impl1/synwork/_mh_info
@@ -0,0 +1 @@
+|1|
diff --git a/impl1/synwork/_slc_mhdlc b/impl1/synwork/_slc_mhdlc
new file mode 100644
index 0000000..e07b673
--- /dev/null
+++ b/impl1/synwork/_slc_mhdlc
@@ -0,0 +1,8 @@
+fifo32dc
+output_decoder8
+tdc4ddr_short
+trig_inv
+tdc_channel_fifo_out
+fifo40_dc
+trb_adapter
+pll0
diff --git a/impl1/synwork/_verilog_hintfile b/impl1/synwork/_verilog_hintfile
new file mode 100644
index 0000000..67e15e1
--- /dev/null
+++ b/impl1/synwork/_verilog_hintfile
@@ -0,0 +1,161 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-distcompmode|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd":1614208577
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/math_real.vhd":1543382461
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd":1614208577
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":1614208538
+@E8lFkRDC06sL_
+0LDsHLNRs$I	Fs
+8CMlkF8DlC
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+0FkbRk0p4ep_ta)_a7qqq_ep_Q7mRza4k
+F00bkRppe4h_QeQqp7)_atz_ma
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+M0bkR w _a7qq)_WQ_a Q4hR
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+R4Fbk0kw0R a _))t_ qp 1m _z4aR
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+bHMk70RNA0NHR0#.M
+HbRk01b0FA#H0RH.
+M0bkRsuNH 0$MDNLC
+R4HkMb0NRus$H0 MPCRH4
+M0bkRsuNH10$0	HORH4
+M0bkRAaGs	CNRF4
+kk0b0]Ra)4 R
+0FkbRk0aa vRC4
+MF8l8CkD
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+HNLssI$RF
+s	HkMb0CR)#RC04M
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+HbRk01RQh4M
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+M0bkR))ARFU
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+RUHkMb01Rv)
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+0FkbRk0))Ls7sM_C
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+M0FkRsp#)_7Ms4CR
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+kk0b0NR70HNL0.#R
+0FkbRk01b0FL#H0RF.
+kk0b0NRus$H0 LMND4CR
+0FkbRk0uHNs0P$ C4MR
+0FkbRk0uHNs00$1HRO	4k
+F00bkRAaGs	CNRH4
+M0bkR))G74YR
+bHMkm0RPsCsksM s
+R4HkMb0NRus$H0 Rss4M
+HbRk0wlsNCs sRH4
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+R4HkMb0]Ra)4 R
+bHMka0R Rva4M
+C88lFk
+DC
+
+@ 
diff --git a/impl1/synwork/containment.fdep b/impl1/synwork/containment.fdep
new file mode 100644
index 0000000..401df9d
--- /dev/null
+++ b/impl1/synwork/containment.fdep
@@ -0,0 +1,79 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946
+0			"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" verilog
+1			"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" verilog
+2			"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" verilog
+3			"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" verilog
+4			"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" verilog
+5			"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" verilog
+6			"/home/hadaq/mmichalek/lattice/simplified/modules2.v" verilog
+7			"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" verilog
+8			"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" verilog
+9			"/home/hadaq/mmichalek/lattice/simplified/top2.v" verilog
+10			"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" verilog
+11			"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+1 -1
+2 -1
+3 -1
+4 -1
+5 -1
+6 2
+7 8
+8 -1
+9 6 0 10 7
+10 11
+11 6
+#Dependency Lists(Users Of)
+0 9
+1 -1
+2 6
+3 -1
+4 -1
+5 -1
+6 11 9
+7 9
+8 7
+9 -1
+10 9
+11 10
+#Design Unit to File Association
+module work hades_tdc_channel_raw_out 11
+module work hades_LVL1_raw_out 11
+module work top_tf 9
+module work trb_adapter 9
+module work hades_tdc_bundle 10
+module work fifo_colector 7
+module work fifo40_dc 8
+module work tdc4ddr 6
+module work tdc_channel_fifo_out 6
+module work output_decoder8 6
+module work tdc4ddr_short 6
+module work trig_inv 6
+module work pll_random 5
+module work pll8 4
+module work UART_VerilogWrapper_TOP 3
+module work fifo32dc 2
+module work pll1 1
+module work pll0 0
diff --git a/impl1/synwork/containment.linkerlog b/impl1/synwork/containment.linkerlog
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/containment.srs b/impl1/synwork/containment.srs
new file mode 100644
index 0000000..7e81269
Binary files /dev/null and b/impl1/synwork/containment.srs differ
diff --git a/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl b/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl
new file mode 100644
index 0000000..0352194
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl
@@ -0,0 +1,3 @@
+work.trig_inv
+work.trig_inv
+work.trig_inv
diff --git a/impl1/synwork/distcomp/distcomp0/_slc_mhdlc b/impl1/synwork/distcomp/distcomp0/_slc_mhdlc
new file mode 100644
index 0000000..8ee23fe
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/_slc_mhdlc
@@ -0,0 +1,8 @@
+pll0
+tdc4ddr_short
+output_decoder8
+trig_inv
+trb_adapter
+fifo40_dc
+fifo32dc
+tdc_channel_fifo_out
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo b/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo1 b/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo1
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.cdc b/impl1/synwork/distcomp/distcomp0/distcomp0.cdc
new file mode 100644
index 0000000..bf7c90d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.cdc
@@ -0,0 +1,27 @@
+define_directive {v:work.top_tf} {.noprune} {1}
+define_directive {v:work.top_tf} {.distcompnoprune} {1}
+define_directive {v:work.fifo_colector} {.noprune} {1}
+define_directive {v:work.fifo_colector} {.distcompnoprune} {1}
+define_directive {v:work.fifo40_dc} {.noprune} {1}
+define_directive {v:work.fifo40_dc} {.distcompnoprune} {1}
+define_directive {v:work.trb_adapter} {.noprune} {1}
+define_directive {v:work.trb_adapter} {.distcompnoprune} {1}
+define_directive {v:work.hades_tdc_bundle} {.noprune} {1}
+define_directive {v:work.hades_tdc_bundle} {.distcompnoprune} {1}
+define_directive {v:work.hades_tdc_channel_raw_out} {.noprune} {1}
+define_directive {v:work.hades_tdc_channel_raw_out} {.distcompnoprune} {1}
+define_directive {v:work.output_decoder8} {.noprune} {1}
+define_directive {v:work.output_decoder8} {.distcompnoprune} {1}
+define_directive {v:work.hades_LVL1_raw_out} {.noprune} {1}
+define_directive {v:work.hades_LVL1_raw_out} {.distcompnoprune} {1}
+define_directive {v:work.tdc4ddr_short} {.noprune} {1}
+define_directive {v:work.tdc4ddr_short} {.distcompnoprune} {1}
+define_directive {v:work.pll0} {.noprune} {1}
+define_directive {v:work.pll0} {.distcompnoprune} {1}
+define_directive {v:work.tdc_channel_fifo_out} {.noprune} {1}
+define_directive {v:work.tdc_channel_fifo_out} {.distcompnoprune} {1}
+define_directive {v:work.trig_inv} {.noprune} {1}
+define_directive {v:work.trig_inv} {.distcompnoprune} {1}
+define_directive {v:work.fifo32dc} {.noprune} {1}
+define_directive {v:work.fifo32dc} {.distcompnoprune} {1}
+define_directive {v:work.top_tf} {.distcompmodetop} {1}
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.fdep b/impl1/synwork/distcomp/distcomp0/distcomp0.fdep
new file mode 100644
index 0000000..3dd41e2
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.fdep
@@ -0,0 +1,54 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-distcompsynthmode|-cdc|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc|-mixedhdl|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-top|work.Uart_top.uart_top_a|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc":1600097169
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl
+1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl
+2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl
+3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl
+4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 0 1 2 3 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work intface intface_a 0
+module work intface 0
+arch work modem modem_a 1
+module work modem 1
+arch work rxcver rxcver_a 2
+module work rxcver 2
+arch work txmitt txmitt_a 3
+module work txmitt 3
+arch work uart_top uart_top_a 4
+module work uart_top 4
+
+# Unbound Instances to File Association
+
+
+# Configuration files used
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig b/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig
new file mode 100644
index 0000000..93040c2
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig
@@ -0,0 +1,51 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-distcompsynthmode|-cdc|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc|-mixedhdl|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-top|work.Uart_top.uart_top_a|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc":1600097169
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl
+1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl
+2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl
+3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl
+4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 0 1 2 3 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work intface intface_a 0
+module work intface 0
+arch work modem modem_a 1
+module work modem 1
+arch work rxcver rxcver_a 2
+module work rxcver 2
+arch work txmitt txmitt_a 3
+module work txmitt 3
+arch work uart_top uart_top_a 4
+module work uart_top 4
+
+# Unbound Instances to File Association
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.log b/impl1/synwork/distcomp/distcomp0/distcomp0.log
new file mode 100644
index 0000000..86ee22a
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.log
@@ -0,0 +1,273 @@
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":28:40:28:51|Ignoring property syn_preserve
+@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":34:16:34:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name.
+@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":40:16:40:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name.
+@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":46:16:46:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name.
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":177:44:177:55|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":178:53:178:64|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":179:52:179:63|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":182:46:182:57|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":183:57:183:68|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":184:56:184:67|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":220:44:220:55|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":221:53:221:64|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":222:52:222:63|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":227:46:227:57|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":228:57:228:68|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":229:56:229:67|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":345:31:345:38|Ignoring property syn_keep
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
+@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
+@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":141:16:141:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name.
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
+@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
+Verilog syntax check successful!
+File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
+@N:: Applying property .distcompmodetop with value 1 on module top_tf in library work
+@N:: Applying property .distcompnoprune with value 1 on module top_tf in library work
+@N:: Applying property .noprune with value 1 on module top_tf in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo_colector in library work
+@N:: Applying property .noprune with value 1 on module fifo_colector in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo40_dc in library work
+@N:: Applying property .noprune with value 1 on module fifo40_dc in library work
+@N:: Applying property .distcompnoprune with value 1 on module trb_adapter in library work
+@N:: Applying property .noprune with value 1 on module trb_adapter in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_bundle in library work
+@N:: Applying property .noprune with value 1 on module hades_tdc_bundle in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_channel_raw_out in library work
+@N:: Applying property .noprune with value 1 on module hades_tdc_channel_raw_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .noprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_LVL1_raw_out in library work
+@N:: Applying property .noprune with value 1 on module hades_LVL1_raw_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr_short in library work
+@N:: Applying property .noprune with value 1 on module tdc4ddr_short in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work
+@N:: Applying property .noprune with value 1 on module pll0 in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc_channel_fifo_out in library work
+@N:: Applying property .noprune with value 1 on module tdc_channel_fifo_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module trig_inv in library work
+@N:: Applying property .noprune with value 1 on module trig_inv in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work
+@N:: Applying property .noprune with value 1 on module fifo32dc in library work
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":168:12:168:23|Object fifo_in_data is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":169:7:169:19|Removing wire fifo_in_valid, as there is no assignment to it.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+@W: CG1340 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":108:51:108:62|Index into variable hit_valid could be out of range ; a simulation mismatch is possible.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":187:37:187:56|Port-width mismatch for port raw_valid_vect. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CL134 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Found RAM hitbuffer, depth=4, width=24
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_0_[23:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_2_[23:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_3_[23:0]. Make sure that there are no unused intermediate registers.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[9] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[11] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[2] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[3] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 3 to 2 of buf_drop[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bit 0 of buf_drop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 9 of drop_cmp_buf[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@W: CL265 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":273:2:273:7|Removing unused bit 2 of LVL1_INVALID_TRG_IN_dl[2:0]. Either assign all bits or reduce the width of the signal.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":795:12:795:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":843:12:843:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":891:12:891:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":947:12:947:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":47:14:47:14|Port-width mismatch for port Reset. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Input RPReset on instance fifo40_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 34 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 35 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 36 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 37 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 38 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 39 of data_buffer
+Running optimization stage 1 on fifo_colector .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":54:1:54:6|Pruning unused register test_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 34 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 35 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 36 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 37 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 38 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 39 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":51:7:51:19|Removing wire fifo_in_valid, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":52:13:52:25|Removing wire fifo_out_data, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":54:7:54:19|Removing wire fifo_out_rden, as there is no assignment to it.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":59:12:59:23|Object buf_positive is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":60:12:60:23|Object buf_negative is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":61:6:61:23|Object buf_positive_ready is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":62:6:62:23|Object buf_negative_ready is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":137:23:137:34|Port-width mismatch for port LVL1_offset. The port definition is 12 bits, but the actual port connection bit width is 9. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":199:19:199:19|Input raw_enable on instance fifo_colector_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":194:18:194:30|Port-width mismatch for port out_data. The port definition is 40 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Removing wire hades_raw_valid_vect, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":66:22:66:29|Removing wire tdc_out1, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":67:11:67:18|Removing wire tdc_out2, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":178:13:178:26|Removing wire fifo_data_out1, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":179:13:179:26|Removing wire fifo_data_out2, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":182:21:182:28|Removing wire in_empty, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":183:21:183:27|Removing wire in_data, as there is no assignment to it.
+Running optimization stage 1 on top_tf .......
+@W: CL318 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|*Output hades_raw_valid_vect has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
+Running optimization stage 2 on tdc_channel_fifo_out .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[1] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[2] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[3] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[4] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[5] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[6] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[7] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[8] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[14] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 31 to 28 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 25 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 23 to 16 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 14 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 10 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 8 to 0 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":6:10:6:15|Input coarse is unused.
+Running optimization stage 2 on fifo32dc .......
+Running optimization stage 2 on top_tf .......
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":185:48:185:56|*Input fifo_data[95:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on fifo_colector .......
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":5:8:5:12|Input reset is unused.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":12:8:12:14|Input discard is unused.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":14:8:14:17|Input raw_enable is unused.
+Running optimization stage 2 on fifo40_dc .......
+Running optimization stage 2 on CCU2C .......
+Running optimization stage 2 on FD1S3BX .......
+Running optimization stage 2 on FD1S3DX .......
+Running optimization stage 2 on FD1P3DX .......
+Running optimization stage 2 on FD1P3BX .......
+Running optimization stage 2 on PDPW16KD .......
+Running optimization stage 2 on ROM16X1A .......
+Running optimization stage 2 on XOR2 .......
+Running optimization stage 2 on OR2 .......
+Running optimization stage 2 on INV .......
+Running optimization stage 2 on AND2 .......
+Running optimization stage 2 on trb_adapter .......
+@W: CL138 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Removing register 'FEE_DATA_OUT' because it is only assigned 0 or its original value.
+Running optimization stage 2 on hades_tdc_bundle .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[11] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 10 of drop_cmp_buf_coarse[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on hades_tdc_channel_raw_out .......
+Running optimization stage 2 on trig_inv .......
+Running optimization stage 2 on hades_LVL1_raw_out .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Register bit window[8] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Pruning register bit 8 of window[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+Running optimization stage 2 on output_decoder8 .......
+@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible.
+Running optimization stage 2 on tdc4ddr_short .......
+Running optimization stage 2 on pll0 .......
+Running optimization stage 2 on EHXPLLL .......
+Running optimization stage 2 on VLO .......
+Running optimization stage 2 on VHI .......
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 88MB)
+
+
+Process completed successfully.
+# Wed Jun 16 09:19:14 2021
+
+###########################################################]
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.log.db b/impl1/synwork/distcomp/distcomp0/distcomp0.log.db
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diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv b/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv
new file mode 100644
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+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv
@@ -0,0 +1 @@
+Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.srs b/impl1/synwork/distcomp/distcomp0/distcomp0.srs
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diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.tlg b/impl1/synwork/distcomp/distcomp0/distcomp0.tlg
new file mode 100644
index 0000000..af7a7d1
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/distcomp0.tlg
@@ -0,0 +1,221 @@
+@N:: Applying property .distcompmodetop with value 1 on module top_tf in library work
+@N:: Applying property .distcompnoprune with value 1 on module top_tf in library work
+@N:: Applying property .noprune with value 1 on module top_tf in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo_colector in library work
+@N:: Applying property .noprune with value 1 on module fifo_colector in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo40_dc in library work
+@N:: Applying property .noprune with value 1 on module fifo40_dc in library work
+@N:: Applying property .distcompnoprune with value 1 on module trb_adapter in library work
+@N:: Applying property .noprune with value 1 on module trb_adapter in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_bundle in library work
+@N:: Applying property .noprune with value 1 on module hades_tdc_bundle in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_channel_raw_out in library work
+@N:: Applying property .noprune with value 1 on module hades_tdc_channel_raw_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .noprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module hades_LVL1_raw_out in library work
+@N:: Applying property .noprune with value 1 on module hades_LVL1_raw_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr_short in library work
+@N:: Applying property .noprune with value 1 on module tdc4ddr_short in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work
+@N:: Applying property .noprune with value 1 on module pll0 in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc_channel_fifo_out in library work
+@N:: Applying property .noprune with value 1 on module tdc_channel_fifo_out in library work
+@N:: Applying property .distcompnoprune with value 1 on module trig_inv in library work
+@N:: Applying property .noprune with value 1 on module trig_inv in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work
+@N:: Applying property .noprune with value 1 on module fifo32dc in library work
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
+Running optimization stage 1 on tdc4ddr_short .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
+Running optimization stage 1 on hades_LVL1_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
+Running optimization stage 1 on trig_inv .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":168:12:168:23|Object fifo_in_data is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":169:7:169:19|Removing wire fifo_in_valid, as there is no assignment to it.
+Running optimization stage 1 on hades_tdc_channel_raw_out .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
+@W: CG1340 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":108:51:108:62|Index into variable hit_valid could be out of range ; a simulation mismatch is possible.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":187:37:187:56|Port-width mismatch for port raw_valid_vect. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
+Running optimization stage 1 on hades_tdc_bundle .......
+@N: CL134 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Found RAM hitbuffer, depth=4, width=24
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_0_[23:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_2_[23:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_3_[23:0]. Make sure that there are no unused intermediate registers.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[9] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[11] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[2] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[3] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 3 to 2 of buf_drop[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bit 0 of buf_drop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 9 of drop_cmp_buf[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
+Running optimization stage 1 on trb_adapter .......
+@W: CL265 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":273:2:273:7|Removing unused bit 2 of LVL1_INVALID_TRG_IN_dl[2:0]. Either assign all bits or reduce the width of the signal.
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":795:12:795:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":843:12:843:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":891:12:891:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":947:12:947:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo40_dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":47:14:47:14|Port-width mismatch for port Reset. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Input RPReset on instance fifo40_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 34 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 35 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 36 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 37 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 38 of data_buffer
+@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 39 of data_buffer
+Running optimization stage 1 on fifo_colector .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":54:1:54:6|Pruning unused register test_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 34 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 35 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 36 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 37 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 38 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 39 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo32dc .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":51:7:51:19|Removing wire fifo_in_valid, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":52:13:52:25|Removing wire fifo_out_data, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":54:7:54:19|Removing wire fifo_out_rden, as there is no assignment to it.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":59:12:59:23|Object buf_positive is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":60:12:60:23|Object buf_negative is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":61:6:61:23|Object buf_positive_ready is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":62:6:62:23|Object buf_negative_ready is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on tdc_channel_fifo_out .......
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":137:23:137:34|Port-width mismatch for port LVL1_offset. The port definition is 12 bits, but the actual port connection bit width is 9. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":199:19:199:19|Input raw_enable on instance fifo_colector_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":194:18:194:30|Port-width mismatch for port out_data. The port definition is 40 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Removing wire hades_raw_valid_vect, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":66:22:66:29|Removing wire tdc_out1, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":67:11:67:18|Removing wire tdc_out2, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":178:13:178:26|Removing wire fifo_data_out1, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":179:13:179:26|Removing wire fifo_data_out2, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":182:21:182:28|Removing wire in_empty, as there is no assignment to it.
+@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":183:21:183:27|Removing wire in_data, as there is no assignment to it.
+Running optimization stage 1 on top_tf .......
+@W: CL318 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|*Output hades_raw_valid_vect has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
+Running optimization stage 2 on tdc_channel_fifo_out .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[1] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[2] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[3] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[4] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[5] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[6] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[7] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[8] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[14] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 31 to 28 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 25 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 23 to 16 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 14 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 10 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 8 to 0 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":6:10:6:15|Input coarse is unused.
+Running optimization stage 2 on fifo32dc .......
+Running optimization stage 2 on top_tf .......
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":185:48:185:56|*Input fifo_data[95:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on fifo_colector .......
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":5:8:5:12|Input reset is unused.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":12:8:12:14|Input discard is unused.
+@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":14:8:14:17|Input raw_enable is unused.
+Running optimization stage 2 on fifo40_dc .......
+Running optimization stage 2 on CCU2C .......
+Running optimization stage 2 on FD1S3BX .......
+Running optimization stage 2 on FD1S3DX .......
+Running optimization stage 2 on FD1P3DX .......
+Running optimization stage 2 on FD1P3BX .......
+Running optimization stage 2 on PDPW16KD .......
+Running optimization stage 2 on ROM16X1A .......
+Running optimization stage 2 on XOR2 .......
+Running optimization stage 2 on OR2 .......
+Running optimization stage 2 on INV .......
+Running optimization stage 2 on AND2 .......
+Running optimization stage 2 on trb_adapter .......
+@W: CL138 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Removing register 'FEE_DATA_OUT' because it is only assigned 0 or its original value.
+Running optimization stage 2 on hades_tdc_bundle .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[10] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[11] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 10 of drop_cmp_buf_coarse[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on hades_tdc_channel_raw_out .......
+Running optimization stage 2 on trig_inv .......
+Running optimization stage 2 on hades_LVL1_raw_out .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Register bit window[8] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Pruning register bit 8 of window[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+Running optimization stage 2 on output_decoder8 .......
+@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible.
+Running optimization stage 2 on tdc4ddr_short .......
+Running optimization stage 2 on pll0 .......
+Running optimization stage 2 on EHXPLLL .......
+Running optimization stage 2 on VLO .......
+Running optimization stage 2 on VHI .......
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.rt.csv
+
diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.tlg.db b/impl1/synwork/distcomp/distcomp0/distcomp0.tlg.db
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index 0000000..8cb5d78
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diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.xmr b/impl1/synwork/distcomp/distcomp0/distcomp0.xmr
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp0/modulechange.db b/impl1/synwork/distcomp/distcomp0/modulechange.db
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diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML
new file mode 100644
index 0000000..a473cbf
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc4ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc4ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML
new file mode 100644
index 0000000..6525883
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML
new file mode 100644
index 0000000..a473cbf
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc4ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc4ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML
new file mode 100644
index 0000000..6525883
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML
new file mode 100644
index 0000000..6525883
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML
new file mode 100644
index 0000000..6525883
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML
new file mode 100644
index 0000000..f9f1187
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML
new file mode 100644
index 0000000..077d6c7
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML
new file mode 100644
index 0000000..395cead
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc8ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc8ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML
new file mode 100644
index 0000000..b862748
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML
new file mode 100644
index 0000000..6525883
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML
new file mode 100644
index 0000000..4211801
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML
new file mode 100644
index 0000000..15565b0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML
new file mode 100644
index 0000000..1c89075
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML
new file mode 100644
index 0000000..0a30307
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML
new file mode 100644
index 0000000..4226b0d
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML
new file mode 100644
index 0000000..69dbbb0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML
new file mode 100644
index 0000000..367ca10
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML
new file mode 100644
index 0000000..c070e80
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs  -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro   -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd   -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl b/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl
new file mode 100644
index 0000000..a4b3e47
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl
@@ -0,0 +1,154 @@
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
+Uart_top
diff --git a/impl1/synwork/distcomp/distcomp1/_slc_mhdlc b/impl1/synwork/distcomp/distcomp1/_slc_mhdlc
new file mode 100644
index 0000000..3c82fa4
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/_slc_mhdlc
@@ -0,0 +1,12 @@
+pll0
+pll1
+pll8
+pll_random
+async_testgen
+tdc4ddr
+output_decoder8
+fifo32dc
+UART_VerilogWrapper_TOP
+tdc_channel
+two_ch_diff
+top
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo b/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo1 b/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo1
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.cdc b/impl1/synwork/distcomp/distcomp1/distcomp1.cdc
new file mode 100644
index 0000000..f465fa8
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/distcomp1.cdc
@@ -0,0 +1,29 @@
+define_directive {v:work.Uart_top.uart_top_a} {syn_black_box} {1}
+define_directive {v:work.Uart_top.uart_top_a} {.distcomp_black_box} {1}
+define_directive {v:work.Uart_top.uart_top_a} {.noprune} {1}
+define_directive {v:work.Uart_top.uart_top_a} {.distcompnoprune} {1}
+define_directive {v:work.top} {.noprune} {1}
+define_directive {v:work.top} {.distcompnoprune} {1}
+define_directive {v:work.two_ch_diff} {.noprune} {1}
+define_directive {v:work.two_ch_diff} {.distcompnoprune} {1}
+define_directive {v:work.UART_VerilogWrapper_TOP} {.noprune} {1}
+define_directive {v:work.UART_VerilogWrapper_TOP} {.distcompnoprune} {1}
+define_directive {v:work.tdc_channel} {.noprune} {1}
+define_directive {v:work.tdc_channel} {.distcompnoprune} {1}
+define_directive {v:work.fifo32dc} {.noprune} {1}
+define_directive {v:work.fifo32dc} {.distcompnoprune} {1}
+define_directive {v:work.output_decoder8} {.noprune} {1}
+define_directive {v:work.output_decoder8} {.distcompnoprune} {1}
+define_directive {v:work.tdc4ddr} {.noprune} {1}
+define_directive {v:work.tdc4ddr} {.distcompnoprune} {1}
+define_directive {v:work.async_testgen} {.noprune} {1}
+define_directive {v:work.async_testgen} {.distcompnoprune} {1}
+define_directive {v:work.pll_random} {.noprune} {1}
+define_directive {v:work.pll_random} {.distcompnoprune} {1}
+define_directive {v:work.pll8} {.noprune} {1}
+define_directive {v:work.pll8} {.distcompnoprune} {1}
+define_directive {v:work.pll1} {.noprune} {1}
+define_directive {v:work.pll1} {.distcompnoprune} {1}
+define_directive {v:work.pll0} {.noprune} {1}
+define_directive {v:work.pll0} {.distcompnoprune} {1}
+define_directive {v:work.top} {.distcompmodetop} {1}
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.log b/impl1/synwork/distcomp/distcomp1/distcomp1.log
new file mode 100644
index 0000000..693a568
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/distcomp1.log
@@ -0,0 +1,262 @@
+###########################################################[
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/hadaq/mmichalek/lattice/simplified/top.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules.v" (library work)
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":247:44:247:55|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":248:53:248:64|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":249:52:249:63|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":254:46:254:57|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":255:57:255:68|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":256:56:256:67|Ignoring property syn_preserve
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":424:7:424:9|Net wrn is not declared.
+@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":425:7:425:10|Net adsn is not declared.
+@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":85:44:85:55|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":86:53:86:64|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":87:52:87:63|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:46:90:57|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":91:57:91:68|Ignoring property syn_preserve
+@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":92:56:92:67|Ignoring property syn_preserve
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+@W::Specified module not found for constraint application: work.Uart_top.uart_top_a
+@N:: Applying property .distcompmodetop with value 1 on module top in library work
+@N:: Applying property .distcompnoprune with value 1 on module top in library work
+@N:: Applying property .noprune with value 1 on module top in library work
+@N:: Applying property .distcompnoprune with value 1 on module two_ch_diff in library work
+@N:: Applying property .noprune with value 1 on module two_ch_diff in library work
+@N:: Applying property .distcompnoprune with value 1 on module UART_VerilogWrapper_TOP in library work
+@N:: Applying property .noprune with value 1 on module UART_VerilogWrapper_TOP in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc_channel in library work
+@N:: Applying property .noprune with value 1 on module tdc_channel in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work
+@N:: Applying property .noprune with value 1 on module fifo32dc in library work
+@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .noprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr in library work
+@N:: Applying property .noprune with value 1 on module tdc4ddr in library work
+@N:: Applying property .distcompnoprune with value 1 on module async_testgen in library work
+@N:: Applying property .noprune with value 1 on module async_testgen in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll_random in library work
+@N:: Applying property .noprune with value 1 on module pll_random in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll8 in library work
+@N:: Applying property .noprune with value 1 on module pll8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll1 in library work
+@N:: Applying property .noprune with value 1 on module pll1 in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work
+@N:: Applying property .noprune with value 1 on module pll0 in library work
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":8:7:8:10|Synthesizing module pll1 in library work.
+Running optimization stage 1 on pll1 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":8:7:8:10|Synthesizing module pll8 in library work.
+Running optimization stage 1 on pll8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":8:7:8:16|Synthesizing module pll_random in library work.
+Running optimization stage 1 on pll_random .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":194:7:194:19|Synthesizing module async_testgen in library work.
+Running optimization stage 1 on async_testgen .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":218:7:218:13|Synthesizing module tdc4ddr in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":228:10:228:27|Object in_clk_down_synced is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on tdc4ddr .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":263:7:263:21|Synthesizing module output_decoder8 in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo32dc .......
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Found module with name Uart_top, attempting to match ...
+
+@N: CG364 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Synthesizing module UART_VerilogWrapper_TOP in library work.
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+Running optimization stage 1 on UART_VerilogWrapper_TOP .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":4:7:4:17|Synthesizing module tdc_channel in library work.
+@W: CG296 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":50:10:50:21|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
+@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":51:5:51:9|Referenced variable reset is not in sensitivity list.
+@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":54:23:54:28|Referenced variable s_data is not in sensitivity list.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":88:13:88:18|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 3. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":111:5:111:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input SIN on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DCDn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input CTSn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DSRn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input RIn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on tdc_channel .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":366:7:366:17|Synthesizing module two_ch_diff in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":475:13:475:19|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":496:5:496:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input SIN on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DCDn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input CTSn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DSRn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input RIn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on two_ch_diff .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in0_dl1[3:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in1_dl1[3:0]. Make sure that there are no unused intermediate registers.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top.v":1:7:1:9|Synthesizing module top in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":89:20:89:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":101:20:101:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
+Running optimization stage 1 on top .......
+Running optimization stage 2 on top .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[24] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[26] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[27] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Pruning register bits 31 to 16 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on two_ch_diff .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[2] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 3 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 1 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL257 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Register bit 0 always 0, optimizing ...
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning unused register lost[0]. Make sure that there are no unused intermediate registers.
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":500:13:500:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on tdc_channel .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[2] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":115:13:115:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on UART_VerilogWrapper_TOP .......
+Running optimization stage 2 on fifo32dc .......
+Running optimization stage 2 on CCU2C .......
+Running optimization stage 2 on FD1S3BX .......
+Running optimization stage 2 on FD1S3DX .......
+Running optimization stage 2 on FD1P3DX .......
+Running optimization stage 2 on FD1P3BX .......
+Running optimization stage 2 on PDPW16KD .......
+Running optimization stage 2 on ROM16X1A .......
+Running optimization stage 2 on XOR2 .......
+Running optimization stage 2 on OR2 .......
+Running optimization stage 2 on INV .......
+Running optimization stage 2 on AND2 .......
+Running optimization stage 2 on output_decoder8 .......
+@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible.
+Running optimization stage 2 on tdc4ddr .......
+Running optimization stage 2 on async_testgen .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[14] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[15] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[24] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[26] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[27] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Pruning register bits 31 to 14 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on pll_random .......
+Running optimization stage 2 on pll8 .......
+Running optimization stage 2 on pll1 .......
+Running optimization stage 2 on pll0 .......
+Running optimization stage 2 on EHXPLLL .......
+Running optimization stage 2 on VLO .......
+Running optimization stage 2 on VHI .......
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 73MB)
+
+
+Process completed successfully.
+# Tue Jan 26 20:17:05 2021
+
+###########################################################]
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.log.db b/impl1/synwork/distcomp/distcomp1/distcomp1.log.db
new file mode 100644
index 0000000..73deeb3
Binary files /dev/null and b/impl1/synwork/distcomp/distcomp1/distcomp1.log.db differ
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.rt.csv b/impl1/synwork/distcomp/distcomp1/distcomp1.rt.csv
new file mode 100644
index 0000000..3f23062
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/distcomp1.rt.csv
@@ -0,0 +1 @@
+Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.srs b/impl1/synwork/distcomp/distcomp1/distcomp1.srs
new file mode 100644
index 0000000..cd76cf0
Binary files /dev/null and b/impl1/synwork/distcomp/distcomp1/distcomp1.srs differ
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.tlg b/impl1/synwork/distcomp/distcomp1/distcomp1.tlg
new file mode 100644
index 0000000..94dc948
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/distcomp1.tlg
@@ -0,0 +1,219 @@
+@W::Specified module not found for constraint application: work.Uart_top.uart_top_a
+@N:: Applying property .distcompmodetop with value 1 on module top in library work
+@N:: Applying property .distcompnoprune with value 1 on module top in library work
+@N:: Applying property .noprune with value 1 on module top in library work
+@N:: Applying property .distcompnoprune with value 1 on module two_ch_diff in library work
+@N:: Applying property .noprune with value 1 on module two_ch_diff in library work
+@N:: Applying property .distcompnoprune with value 1 on module UART_VerilogWrapper_TOP in library work
+@N:: Applying property .noprune with value 1 on module UART_VerilogWrapper_TOP in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc_channel in library work
+@N:: Applying property .noprune with value 1 on module tdc_channel in library work
+@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work
+@N:: Applying property .noprune with value 1 on module fifo32dc in library work
+@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .noprune with value 1 on module output_decoder8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr in library work
+@N:: Applying property .noprune with value 1 on module tdc4ddr in library work
+@N:: Applying property .distcompnoprune with value 1 on module async_testgen in library work
+@N:: Applying property .noprune with value 1 on module async_testgen in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll_random in library work
+@N:: Applying property .noprune with value 1 on module pll_random in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll8 in library work
+@N:: Applying property .noprune with value 1 on module pll8 in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll1 in library work
+@N:: Applying property .noprune with value 1 on module pll1 in library work
+@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work
+@N:: Applying property .noprune with value 1 on module pll0 in library work
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
+Running optimization stage 1 on EHXPLLL .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
+Running optimization stage 1 on pll0 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":8:7:8:10|Synthesizing module pll1 in library work.
+Running optimization stage 1 on pll1 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":8:7:8:10|Synthesizing module pll8 in library work.
+Running optimization stage 1 on pll8 .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":8:7:8:16|Synthesizing module pll_random in library work.
+Running optimization stage 1 on pll_random .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":194:7:194:19|Synthesizing module async_testgen in library work.
+Running optimization stage 1 on async_testgen .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":218:7:218:13|Synthesizing module tdc4ddr in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":228:10:228:27|Object in_clk_down_synced is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on tdc4ddr .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":263:7:263:21|Synthesizing module output_decoder8 in library work.
+@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration.
+Running optimization stage 1 on output_decoder8 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
+Running optimization stage 1 on AND2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
+Running optimization stage 1 on INV .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
+Running optimization stage 1 on OR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
+Running optimization stage 1 on XOR2 .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
+Running optimization stage 1 on ROM16X1A .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
+Running optimization stage 1 on PDPW16KD .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
+Running optimization stage 1 on FD1P3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
+Running optimization stage 1 on FD1P3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
+Running optimization stage 1 on FD1S3DX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
+Running optimization stage 1 on FD1S3BX .......
+@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
+Running optimization stage 1 on CCU2C .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on fifo32dc .......
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Found module with name Uart_top, attempting to match ...
+
+@N: CG364 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Synthesizing module UART_VerilogWrapper_TOP in library work.
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ...
+
+@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ...
+
+Running optimization stage 1 on UART_VerilogWrapper_TOP .......
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":4:7:4:17|Synthesizing module tdc_channel in library work.
+@W: CG296 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":50:10:50:21|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
+@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":51:5:51:9|Referenced variable reset is not in sensitivity list.
+@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":54:23:54:28|Referenced variable s_data is not in sensitivity list.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":88:13:88:18|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 3. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":111:5:111:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input SIN on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DCDn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input CTSn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DSRn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input RIn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on tdc_channel .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":366:7:366:17|Synthesizing module two_ch_diff in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":475:13:475:19|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":496:5:496:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input SIN on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DCDn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input CTSn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DSRn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input RIn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on two_ch_diff .......
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in0_dl1[3:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in1_dl1[3:0]. Make sure that there are no unused intermediate registers.
+@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top.v":1:7:1:9|Synthesizing module top in library work.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":89:20:89:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":101:20:101:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
+Running optimization stage 1 on top .......
+Running optimization stage 2 on top .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[24] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[26] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[27] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Pruning register bits 31 to 16 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on two_ch_diff .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[2] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 3 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 1 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL257 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Register bit 0 always 0, optimizing ...
+@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning unused register lost[0]. Make sure that there are no unused intermediate registers.
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":500:13:500:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on tdc_channel .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[0] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[2] is always 0.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":115:13:115:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
+Running optimization stage 2 on UART_VerilogWrapper_TOP .......
+Running optimization stage 2 on fifo32dc .......
+Running optimization stage 2 on CCU2C .......
+Running optimization stage 2 on FD1S3BX .......
+Running optimization stage 2 on FD1S3DX .......
+Running optimization stage 2 on FD1P3DX .......
+Running optimization stage 2 on FD1P3BX .......
+Running optimization stage 2 on PDPW16KD .......
+Running optimization stage 2 on ROM16X1A .......
+Running optimization stage 2 on XOR2 .......
+Running optimization stage 2 on OR2 .......
+Running optimization stage 2 on INV .......
+Running optimization stage 2 on AND2 .......
+Running optimization stage 2 on output_decoder8 .......
+@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible.
+Running optimization stage 2 on tdc4ddr .......
+Running optimization stage 2 on async_testgen .......
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[14] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[15] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[16] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[17] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[18] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[19] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[20] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[21] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[22] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[23] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[24] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[25] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[26] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[27] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[28] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[29] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[30] is always 0.
+@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[31] is always 0.
+@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Pruning register bits 31 to 14 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+Running optimization stage 2 on pll_random .......
+Running optimization stage 2 on pll8 .......
+Running optimization stage 2 on pll1 .......
+Running optimization stage 2 on pll0 .......
+Running optimization stage 2 on EHXPLLL .......
+Running optimization stage 2 on VLO .......
+Running optimization stage 2 on VHI .......
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.rt.csv
+
diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.tlg.db b/impl1/synwork/distcomp/distcomp1/distcomp1.tlg.db
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new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/distcomp/distcomp1/modulechange.db b/impl1/synwork/distcomp/distcomp1/modulechange.db
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diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML
new file mode 100644
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--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML
new file mode 100644
index 0000000..695f551
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML
new file mode 100644
index 0000000..8f01e54
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML
new file mode 100644
index 0000000..1764a2a
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML
new file mode 100644
index 0000000..695f551
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML
new file mode 100644
index 0000000..695f551
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML
new file mode 100644
index 0000000..8f01e54
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML
new file mode 100644
index 0000000..695f551
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML
new file mode 100644
index 0000000..07ca1bb
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML
new file mode 100644
index 0000000..2cd43a0
--- /dev/null
+++ b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML
@@ -0,0 +1 @@
+-orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs   -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile  -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v  -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log
\ No newline at end of file
diff --git a/impl1/synwork/incr_compile.rpt b/impl1/synwork/incr_compile.rpt
new file mode 100644
index 0000000..fc9bb81
--- /dev/null
+++ b/impl1/synwork/incr_compile.rpt
@@ -0,0 +1,79 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify (R) Premier
+Build: O-2018.09-SP1
+Install: /opt/synplicity/O-2018.09-SP1
+OS: Debian GNU/Linux 9 (stretch)
+Hostname: lxhadeb07
+max virtual memory: unlimited (bytes)
+max user processes: 1031428
+max stack size: 8388608 (bytes)
+
+
+Implementation : impl1
+Synopsys HDL compiler and linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
+
+Modified Files: 1
+FID:  path (prevtimestamp, timestamp)
+36       /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06)
+
+*******************************************************************
+Modules that may have changed as a result of file changes: 8
+MID:  lib.cell.view
+6        work.fifo32dc.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+34       work.hades_LVL1_raw_out.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (module definition)
+32       work.hades_tdc_channel_raw_out.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (module definition)
+3        work.output_decoder8.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+4        work.tdc4ddr.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+24       work.tdc4ddr_short.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+25       work.tdc_channel_fifo_out.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+30       work.trig_inv.verilog may have changed because the following files changed:
+                        /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module)
+
+*******************************************************************
+Unmodified files: 19
+FID:  path (timestamp)
+12       /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v (2020-06-02 19:47:55)
+11       /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v (2020-09-13 16:38:29)
+32       /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v (2021-02-09 13:19:26)
+33       /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v (2021-06-09 11:46:02)
+35       /home/hadaq/mmichalek/lattice/simplified/hades_modules.v (2021-06-15 17:59:12)
+0        /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.xmr (2020-07-27 07:12:33)
+31       /home/hadaq/mmichalek/lattice/simplified/modules2.v (2021-06-11 16:48:17)
+9        /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v (2020-10-21 10:28:14)
+10       /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v (2020-10-21 10:28:25)
+28       /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v (2020-10-21 10:28:36)
+29       /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v (2020-10-21 10:28:46)
+34       /home/hadaq/mmichalek/lattice/simplified/top2.v (2021-06-15 11:39:51)
+2        /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v (2018-11-28 06:10:43)
+3        /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v (2018-11-28 06:10:43)
+4        /opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v (2018-11-28 06:12:11)
+5        /opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v (2018-11-28 06:17:48)
+6        /opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v (2018-11-28 06:17:48)
+7        /opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh (2018-11-28 06:17:48)
+8        /opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v (2018-08-08 09:43:25)
+
+*******************************************************************
+Unchanged modules: 10
+MID:  lib.cell.view
+7        work.UART_VerilogWrapper_TOP.verilog
+27       work.fifo40_dc.verilog
+28       work.fifo_colector.verilog
+33       work.hades_tdc_bundle.verilog
+1        work.pll0.verilog
+5        work.pll1.verilog
+18       work.pll8.verilog
+19       work.pll_random.verilog
+26       work.top_tf.verilog
+29       work.trb_adapter.verilog
diff --git a/impl1/synwork/layer0.fdep b/impl1/synwork/layer0.fdep
new file mode 100644
index 0000000..b564550
--- /dev/null
+++ b/impl1/synwork/layer0.fdep
@@ -0,0 +1,84 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946
+#numinternalfiles:7
+#defaultlanguage:verilog
+0			"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" verilog
+1			"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" verilog
+2			"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" verilog
+3			"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" verilog
+4			"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" verilog
+5			"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" verilog
+6			"/home/hadaq/mmichalek/lattice/simplified/modules2.v" verilog
+7			"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" verilog
+8			"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" verilog
+9			"/home/hadaq/mmichalek/lattice/simplified/top2.v" verilog
+10			"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" verilog
+11			"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+1 -1
+2 -1
+3 -1
+4 -1
+5 -1
+6 2
+7 8
+8 -1
+9 7 10 0 6
+10 11
+11 6
+#Dependency Lists(Users Of)
+0 9
+1 -1
+2 6
+3 -1
+4 -1
+5 -1
+6 9 11
+7 9
+8 7
+9 -1
+10 9
+11 10
+#Design Unit to File Association
+module work pll0 0
+module work pll1 1
+module work fifo32dc 2
+module work UART_VerilogWrapper_TOP 3
+module work pll8 4
+module work pll_random 5
+module work trig_inv 6
+module work tdc4ddr_short 6
+module work output_decoder8 6
+module work tdc_channel_fifo_out 6
+module work tdc4ddr 6
+module work fifo40_dc 8
+module work fifo_colector 7
+module work hades_tdc_bundle 10
+module work trb_adapter 9
+module work top_tf 9
+module work hades_LVL1_raw_out 11
+module work hades_tdc_channel_raw_out 11
+#Unbound instances to file Association.
+inst work UART_VerilogWrapper_TOP uart_top 3
+inst work UART_VerilogWrapper_TOP uart_top 3
diff --git a/impl1/synwork/layer0.fdepxmr b/impl1/synwork/layer0.fdepxmr
new file mode 100644
index 0000000..37d628b
--- /dev/null
+++ b/impl1/synwork/layer0.fdepxmr
@@ -0,0 +1 @@
+#XMR Information
diff --git a/impl1/synwork/layer0.srs b/impl1/synwork/layer0.srs
new file mode 100644
index 0000000..4b7af3d
--- /dev/null
+++ b/impl1/synwork/layer0.srs
@@ -0,0 +1,5557 @@
+%%% protect protected_file
+# Created by Synplify Verilog HDL Compiler version comp2018q4p1, Build 004R from Synplicity, Inc.
+# Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+# Synthesis Netlist written on Wed Jun 16 09:19:13 2021
+#
+#
+#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946
+f "/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v"; # file 0
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v"; # file 1
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v"; # file 2
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v"; # file 3
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v"; # file 4
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v"; # file 5
+af .standard "01";
+af .is_verilog 1;
+f "/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh"; # file 6
+af .standard "sv";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v"; # file 7
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v"; # file 8
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v"; # file 9
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"; # file 10
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v"; # file 11
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v"; # file 12
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/modules2.v"; # file 13
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v"; # file 14
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v"; # file 15
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/top2.v"; # file 16
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"; # file 17
+af .standard "01";
+af .is_verilog 1;
+f "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"; # file 18
+af .standard "01";
+af .is_verilog 1;
+@E
+@ 
+ftell;
+@E@MR@(j:n::((4n:4FRIsB	RBBz.RsPCHoDF;P
+NRG3C0MCsN4DR;P
+NRF3VsDlN_DOCDlMNCBR"BBz."N;
+PHR3#sPCHoDFR
+4;N3PRHP#_CDsHF4oR;P
+NRs3FHNohl"CRB.BzB
+";NFPRs_HoH0M#_RFV"zBB.;B"
+RNP3MDNosuNNRl#"QQhaQjRh4QaRKQh 4Ba_QjRhBK a44_"N;
+PhRQQRaj"'4nLjjjjjjjjjjjjjjjj
+";NQPRh4QaRn"4'jLjjjjjjjjjjjjjj;j"
+RNPQ hKB_a4jYR" ;1"
+RNPQ hKB_a44YR" ;1"
+RNP3M#$_0N0VlFsNH0#x"CRQahQjn=4RQQha44=n;R"
+RNP3M#$_0N0VlFsN"0RQahQjR=XQahQ4R=X"N;
+PFR3sDHoHNLMl"CRI	Fs"N;
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+NR$3#M#_kCLsLR
+4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3oI_O_0sO"HN;P
+NR$3#MH_DLC_OD4DR;P
+NR$3#Ms_0C_N0NL#_D	NOLRFG4N;
+P$R#MM_kOMFMCCO08M_Hb#k0RQ"Bh
+";N#PR$DM_HOL_CRDD4
+;
+
+@HR@Uj:d::gU4d:4QRBhQRBh
+;
+
+@HR@Uj:c::gU4c:jjRqR;qj
+@HR@Uj:cd:4::Uc4AcRjjRA;
+
+
+
+@HR@Uj:c(:4::Uc4BURjjRB;
+
+
+
+@HR@Uj:c4:.::Uc.7.RjjR7;
+
+
+
+@HR@Uj:6::gU46:j4RqR;q4
+@HR@Uj:6d:4::U64AcR44RA;
+
+
+
+@HR@Uj:6(:4::U64BUR44RB;
+
+
+
+@HR@Uj:64:.::U6.7.R44R7;
+
+
+
+@FR@Uj:nj:4::Un414Rj
+R;
+@FR@Uj:nc:4::Un416R4
+R;
+@FR@Uj:nU:4::Un.B4RmRza;-
+y--------------------------------- 
+@
+ftell;
+@E@MR@(j:n(4::4(n:IgRFRs	eRpmPHCsD;Fo
+RNP30CGCNsMD;R4
+RNP3sVFl_NDODCDMCNlRp"em
+";N3PRHC#PsFHDo;R4
+RNP3_H#PHCsDRFo4N;
+PFR3shHoNRlC"mep"N;
+PsRFHHo_M_#0F"VRe"pm;P
+NRs3FHHoDLlMNCIR"F"s	;P
+NRN3D$HCs8;Rj
+RNP3M#$_Ck#sRLL4N;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03DbDj#HM0O3#k_LNP_DFH0M#"N;
+P#R3$DM_HOL_CRDD4N;
+P#R3$0M_s0CN__N#LODN	GLFR
+4;N#PR$DM_HOL_CRDD4
+;
+
+@FR@(j:n4.:jn:(.j:4R;ZR
+-y---------------------------------
+
+@ 
+ftell;
+@E@MR@(j:6((::((6:IgRFRs	eR]QPHCsD;Fo
+RNP30CGCNsMD;R4
+RNP3sVFl_NDODCDMCNlR]"eQ
+";N3PRHC#PsFHDo;R4
+RNP3_H#PHCsDRFo4N;
+PFR3shHoNRlC"Qe]"N;
+PsRFHHo_M_#0F"VRe"]Q;P
+NRs3FHHoDLlMNCIR"F"s	;P
+NRN3D$HCs8;Rj
+RNP3M#$_Ck#sRLL4N;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03DbDj#HM0O3#k_LNP_EHH0M#"N;
+P#R3$DM_HOL_CRDD4N;
+P#R3$0M_s0CN__N#LODN	GLFR
+4;N#PR$DM_HOL_CRDD4
+;
+
+@FR@(j:64U:j6:(Uj:4R;ZR
+-y---------------------------------
+
+@ 
+ftell;
+@E@MR@4j:n(U::U4n:R4dI	FsR4w71Xd7RsPCHoDF;P
+NRG3C0MCsN4DR;P
+NRF3VsDlN_DOCDlMNCwR"7d417;X"
+RNP3PH#CDsHF4oR;P
+NR#3H_sPCHoDFR
+4;N3PRFosHhCNlR7"w471dX
+";NFPRs_HoH0M#_RFV"4w71Xd7"N;
+PDR3NuMoNlsN#tR"1;)"
+RNPtR1)"q hA7p "N;
+PFR3sDHoHNLMl"CRI	Fs"N;
+PDR3Ns$CHj8R;P
+NR$3#M#_kCLsLR
+4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_wwc;4"
+RNP3M#$_LDH_DOCD;R4
+RNP3M#$_C0sNN0_#D_LNLO	F4GR;P
+NRM#$_LDH_DOCD;R4
+@HR@4j:(4j:j(:4jj:4R77R;
+
+
+
+@HR@4j:(44:j(:444:4RRBiB
+i;
+@HR@4j:(4.:j(:4.4:4RRB7B
+7;
+@FR@4j:(4d:j(:4dj:4R;TR
+-y---------------------------------
+
+@ 
+ftell;
+@E@MR@4j:n(j::j4n:R4dI	FsR4w71XdARsPCHoDF;P
+NRG3C0MCsN4DR;P
+NRF3VsDlN_DOCDlMNCwR"7d41A;X"
+RNP3PH#CDsHF4oR;P
+NR#3H_sPCHoDFR
+4;N3PRFosHhCNlR7"w4A1dX
+";NFPRs_HoH0M#_RFV"4w71XdA"N;
+PDR3NuMoNlsN#tR"1;)"
+RNPtR1)"q hA7p "N;
+PFR3sDHoHNLMl"CRI	Fs"N;
+PDR3Ns$CHj8R;P
+NR$3#M#_kCLsLR
+4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4
+";N3PR#_$MD_HLODCDR
+4;N3PR#_$M0NsC0#_N_NLDOF	LG;R4
+RNP#_$MD_HLODCDR
+4;
+@HR@4j:n4.:jn:4.j:4R77R;
+
+
+
+@HR@4j:n4d:jn:4d4:4RRBiB
+i;
+@HR@4j:n4c:jn:4c4:4RRu7u
+7;
+@FR@4j:n46:jn:46j:4R;TR
+-y---------------------------------
+
+@ 
+ftell;
+@E@MR@4j:4(g::g44:R4dI	FsR4w7uXd7RsPCHoDF;P
+NRG3C0MCsN4DR;P
+NRF3VsDlN_DOCDlMNCwR"7d4u7;X"
+RNP3PH#CDsHF4oR;P
+NR#3H_sPCHoDFR
+4;N3PRFosHhCNlR7"w47udX
+";NFPRs_HoH0M#_RFV"4w7uXd7"N;
+PDR3NuMoNlsN#tR"1;)"
+RNPtR1)"q hA7p "N;
+PFR3sDHoHNLMl"CRI	Fs"N;
+PDR3Ns$CHj8R;P
+NR$3#M#_kCLsLR
+4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4"jj;P
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+
+
+
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+7;
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+;
+
+@HR@4j:.gd::d4.:R4jBBiRi
+;
+
+@HR@4j:.gc::c4.:R4jBB7R7
+;
+
+@FR@4j:.46:j.:46j:4R;TR
+-y---------------------------------
+
+@ 
+ftell;
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+";NFPRs_HoH0M#_RFV"4w7uXdA"N;
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+PFR3sDHoHNLMl"CRI	Fs"N;
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+4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4"j4;P
+NR$3#MH_DLC_OD4DR;P
+NR$3#Ms_0C_N0NL#_D	NOLRFG4N;
+P$R#MH_DLC_OD4DR;
+
+
+
+@HR@4j:4g.::.44:7gRR
+7;
+@HR@4j:4gd::d44:R4j11uRu
+;
+
+@HR@4j:4gc::c44:R4jBBiRi
+;
+
+@HR@4j:4g6::644:R4juu7R7
+;
+
+@FR@4j:44n:j4:4nj:4R;TR
+-y---------------------------------
+
+@ 
+ftell;
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+RNP7qqa_7WQa)]_R;dn
+RNPtR1)"q hA7p "N;
+P R)t7vm hR"mt) "N;
+P R)1v amR7 "h1YB
+";NqPR1BYh_1)  )a_ qp 1" R1BYh"N;
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+RNPQahQe_qpj"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
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+RNPQahQe_qpj"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpj"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
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+RNPQahQe_qp4"6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp4"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp.".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp." RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qp."wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
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+RNPQahQe_qpd"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
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+RNPQahQe_qpd"qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
+RNPQahQe_qpd"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j"
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+NRs3FHHoDLlMNCIR"F"s	;P
+NRN3D$HCs8;Rj
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+";N3PR#_$MD_HLODCDR
+4;N3PR#_$M0NsC0#_N_NLDOF	LG;R4
+RNP#_$MD_HLODCDR
+4;
+@HR@gj:ngj::jgn:R4.76QdRd7Q6
+;
+
+@HR@gj:n4j:6n:gjU:4Rd7QcQR7d
+c;
+@HR@gj:n.j:4n:gjc:.Rd7QdQR7d
+d;
+@HR@gj:n.j:(n:gjj:dRd7Q.QR7d
+.;
+@HR@gj:ndj:dn:gjn:dRd7Q4QR7d
+4;
+@HR@gj:ndj:gn:gj.:cRd7QjQR7d
+j;
+@HR@gj:ncj:6n:gjU:cR.7QgQR7.
+g;
+@HR@gj:n6j:4n:gjc:6R.7QUQR7.
+U;
+@HR@gj:n6j:(n:gjj:nR.7Q(QR7.
+(;
+@HR@gj:ng4::4gn:R4.7nQ.R.7Qn
+;
+
+@HR@gj:n44:6n:g4U:4R.7Q6QR7.
+6;
+@HR@gj:n.4:4n:g4c:.R.7QcQR7.
+c;
+@HR@gj:n.4:(n:g4j:dR.7QdQR7.
+d;
+@HR@gj:nd4:dn:g4n:dR.7Q.QR7.
+.;
+@HR@gj:nd4:gn:g4.:cR.7Q4QR7.
+4;
+@HR@gj:nc4:6n:g4U:cR.7QjQR7.
+j;
+@HR@gj:n64:4n:g4c:6R47QgQR74
+g;
+@HR@gj:n64:(n:g4j:nR47QUQR74
+U;
+@HR@gj:ng.::.gn:R4.7(Q4R47Q(
+;
+
+@HR@gj:n4.:6n:g.U:4R47QnQR74
+n;
+@HR@gj:n..:4n:g.c:.R47Q6QR74
+6;
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+c;
+@HR@gj:nd.:dn:g.n:dR47QdQR74
+d;
+@HR@gj:nd.:gn:g..:cR47Q.QR74
+.;
+@HR@gj:nc.:6n:g.U:cR47Q4QR74
+4;
+@HR@gj:n6.:4n:g.c:6R47QjQR74
+j;
+@HR@gj:n6.:(n:g.g:6Rg7QRg7Q;
+
+
+
+@HR@gj:ngd::dgn:R447RQU7;QU
+@HR@gj:n4d:cn:gdn:4R(7QR(7Q;
+
+
+
+@HR@gj:n4d:gn:gd4:.Rn7QRn7Q;
+
+
+
+@HR@gj:n.d:cn:gdn:.R67QR67Q;
+
+
+
+@HR@gj:n.d:gn:gd4:dRc7QRc7Q;
+
+
+
+@HR@gj:ndd:cn:gdn:dRd7QRd7Q;
+
+
+
+@HR@gj:ndd:gn:gd4:cR.7QR.7Q;
+
+
+
+@HR@gj:ncd:cn:gdn:cR47QR47Q;
+
+
+
+@HR@gj:ncd:gn:gd4:6Rj7QRj7Q;
+
+
+
+@HR@gj:ngc::cgn:R4.qU7WRWq7U
+;
+
+@HR@gj:n4c:6n:gcU:4RWq7(7RqW
+(;
+@HR@gj:n.c:4n:gcc:.RWq7n7RqW
+n;
+@HR@gj:n.c:(n:gcj:dRWq767RqW
+6;
+@HR@gj:ndc:dn:gcn:dRWq7c7RqW
+c;
+@HR@gj:ndc:gn:gc.:cRWq7d7RqW
+d;
+@HR@gj:ncc:6n:gcU:cRWq7.7RqW
+.;
+@HR@gj:n6c:4n:gcc:6RWq747RqW
+4;
+@HR@gj:n6c:(n:gcj:nRWq7j7RqW
+j;
+@HR@gj:ng6::6gn:R44AR dA; d
+@HR@gj:n46:6n:g6(:4R.A R.A ;
+
+
+
+@HR@gj:n.6:4n:g6d:.R4A R4A ;
+
+
+
+@HR@gj:n.6:nn:g6U:.RjA RjA ;
+
+
+
+@HR@gj:ngn::ngn:R44BR WB; W
+@HR@gj:n4n:cn:gn(:4RiBpWpRBi
+W;
+@HR@gj:n.n:jn:gnd:.RWB1.1RBW
+.;
+@HR@gj:n.n:nn:gng:.RWB141RBW
+4;
+@HR@gj:ndn:.n:gn6:dRWB1j1RBW
+j;
+@HR@gj:ng(::(gn:R4dq47)d7Rq);4d
+@HR@gj:n4(:nn:g(j:.R)q74q.R7.)4;
+
+
+
+@HR@gj:n.(:dn:g((:.R)q74q4R74)4;
+
+
+
+@HR@gj:nd(:jn:g(c:dR)q74qjR7j)4;
+
+
+
+@HR@gj:nd(:(n:g(j:cR)q7g7Rq)
+g;
+@HR@gj:nc(:dn:g(n:cR)q7U7Rq)
+U;
+@HR@gj:nc(:gn:g(.:6R)q7(7Rq)
+(;
+@HR@gj:n6(:6n:g(U:6R)q7n7Rq)
+n;
+@HR@gj:nn(:4n:g(c:nR)q767Rq)
+6;
+@HR@gj:ngU::Ugn:R4.qc7)R)q7c
+;
+
+@HR@gj:n4U:nn:gUg:4R)q7d7Rq)
+d;
+@HR@gj:n.U:dn:gUn:.R)q7.7Rq)
+.;
+@HR@gj:n.U:gn:gU.:dR)q747Rq)
+4;
+@HR@gj:ndU:6n:gUU:dR)q7j7Rq)
+j;
+@HR@gj:ngg::ggn:R44BR )B; )
+@HR@gj:n4g:cn:gg(:4R mB)BRm 
+);
+@HR@gj:n.g:jn:ggd:.RiBp)pRBi
+);
+@HR@gj:n.g:nn:ggg:.R)B1.1RB)
+.;
+@HR@gj:ndg:.n:gg6:dR)B141RB)
+4;
+@HR@gj:ndg:Un:gg4:cR)B1j1RB)
+j;
+@HR@gj:ncg:cn:ggn:cRa)1Ra)1;
+
+
+
+@FR@gj:(gj::jg(:R4.76mdR
+;
+
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+Sii=B__ww4S6
+BB7=7w_w_
+46STT=__ww4
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gj:(..:4:.(j:R4nI	FsR4w71Xd7RsPCHoDFR_ww4Sn
+7_=7w4w_nB
+Sii=B__ww4Sn
+BB7=7w_w_
+4nSTT=__ww4
+n;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gg:ng.:4:gng:R4nI	FsR4w71Xd7RsPCHoDFR_ww4S(
+7_=7w4w_(B
+Sii=B__ww4S(
+BB7=7w_w_
+4(STT=__ww4
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gg:nn.:4:nng:R4nI	FsR4w71Xd7RsPCHoDFR_ww4SU
+7_=7w4w_UB
+Sii=B__ww4SU
+BB7=7w_w_
+4USTT=__ww4
+U;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gg:nd.:4:dng:R4nI	FsR4w71Xd7RsPCHoDFR_ww4Sg
+7_=7w4w_gB
+Sii=B__ww4Sg
+BB7=7w_w_
+4gSTT=__ww4
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gg:nj.:4:jng:R4nI	FsR4w71Xd7RsPCHoDFR_ww.Sj
+7_=7w.w_jB
+Sii=B__ww.Sj
+BB7=7w_w_
+.jSTT=__ww.
+j;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gU:n(.:4:(nU:R4nI	FsR4w71Xd7RsPCHoDFR_ww.S4
+7_=7w.w_4B
+Sii=B__ww.S4
+BB7=7w_w_
+.4STT=__ww.
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gU:nc.:4:cnU:R4nI	FsR4w71Xd7RsPCHoDFR_ww.S.
+7_=7w.w_.B
+Sii=B__ww.S.
+BB7=7w_w_
+..STT=__ww.
+.;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gU:n4.:4:4nU:R4nI	FsR4w71Xd7RsPCHoDFR_ww.Sd
+7_=7w.w_dB
+Sii=B__ww.Sd
+BB7=7w_w_
+.dSTT=__ww.
+d;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:nU.:4:Un(:R4nI	FsR4w71Xd7RsPCHoDFR_ww.Sc
+7_=7w.w_cB
+Sii=B__ww.Sc
+BB7=7w_w_
+.cSTT=__ww.
+c;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:n6.:4:6n(:R4nI	FsR4w71Xd7RsPCHoDFR_ww.S6
+7_=7w.w_6B
+Sii=B__ww.S6
+BB7=7w_w_
+.6STT=__ww.
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:n..:4:.n(:R4nI	FsR4w71Xd7RsPCHoDFR_ww.Sn
+7_=7w.w_nB
+Sii=B__ww.Sn
+BB7=7w_w_
+.nSTT=__ww.
+n;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gn:ng.:4:gnn:R4nI	FsR4w71Xd7RsPCHoDFR_ww.S(
+7_=7w.w_(B
+Sii=B__ww.S(
+BB7=7w_w_
+.(STT=__ww.
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gn:nn.:4:nnn:R4nI	FsR4w71Xd7RsPCHoDFR_ww.SU
+7_=7w.w_UB
+Sii=B__ww.SU
+BB7=7w_w_
+.USTT=__ww.
+U;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gn:nd.:4:dnn:R4nI	FsR4w71Xd7RsPCHoDFR_ww.Sg
+7_=7w.w_gB
+Sii=B__ww.Sg
+BB7=7w_w_
+.gSTT=__ww.
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gn:nj.:4:jnn:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSj
+7_=7wdw_jB
+Sii=B__wwdSj
+BB7=7w_w_
+djSTT=__wwd
+j;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g6:n(.:4:(n6:R4nI	FsR4w71Xd7RsPCHoDFR_wwdS4
+7_=7wdw_4B
+Sii=B__wwdS4
+BB7=7w_w_
+d4STT=__wwd
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g6:nc.:4:cn6:R4nI	FsR4w71Xd7RsPCHoDFR_wwdS.
+7_=7wdw_.B
+Sii=B__wwdS.
+BB7=7w_w_
+d.STT=__wwd
+.;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g6:n4.:4:4n6:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSd
+7_=7wdw_dB
+Sii=B__wwdSd
+BB7=7w_w_
+ddSTT=__wwd
+d;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gc:nU.:4:Unc:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSc
+7_=7wdw_cB
+Sii=B__wwdSc
+BB7=7w_w_
+dcSTT=__wwd
+c;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gc:n6.:4:6nc:R4nI	FsR4w71Xd7RsPCHoDFR_wwdS6
+7_=7wdw_6B
+Sii=B__wwdS6
+BB7=7w_w_
+d6STT=__wwd
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gc:n..:4:.nc:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSn
+7_=7wdw_nB
+Sii=B__wwdSn
+BB7=7w_w_
+dnSTT=__wwd
+n;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gd:ng.:4:gnd:R4nI	FsR4w71Xd7RsPCHoDFR_wwdS(
+7_=7wdw_(B
+Sii=B__wwdS(
+BB7=7w_w_
+d(STT=__wwd
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gd:nn.:4:nnd:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSU
+7_=7wdw_UB
+Sii=B__wwdSU
+BB7=7w_w_
+dUSTT=__wwd
+U;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gd:nd.:4:dnd:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSg
+7_=7wdw_gB
+Sii=B__wwdSg
+BB7=7w_w_
+dgSTT=__wwd
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gd:nj.:4:jnd:R4nI	FsR4w71Xd7RsPCHoDFR_wwcSj
+7_=7wcw_jB
+Sii=B__wwcSj
+BB7=7w_w_
+cjSTT=__wwc
+j;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g.:n(.:4:(n.:R4nI	FsR4w71Xd7RsPCHoDFR_wwcS4
+7_=7wcw_4B
+Sii=B__wwcS4
+BB7=7w_w_
+c4STT=__wwc
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g.:nc.:4:cn.:R4nI	FsR4w7uXd7RsPCHoDFR_wwcS.
+7_=7wcw_.1
+Suu=1__wwcS.
+BBi=iw_w_
+c.S=B7Bw7_w._c
+=STTw_w_;c.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@ng:.44:..:n4n:4RsIF	7Rw47udXCRPsFHDowRw_
+cdS77=__wwcSd
+11u=uw_w_
+cdS=BiBwi_wd_c
+7SB=_B7wcw_dT
+S=wT_wd_c;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gn:4U4n.:44U:nFRIsw	R7d4u7PXRCDsHFwoRwc_c
+=S77w_w_
+ccS=1u1wu_wc_c
+iSB=_Biwcw_cB
+S77=B__wwcSc
+T_=Twcw_cN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:6n4::4.n:464InRFRs	wu74dR7XPHCsDRFowcw_67
+S=w7_w6_c
+uS1=_1uwcw_6B
+Sii=B__wwcS6
+BB7=7w_w_
+c6STT=__wwc
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g4:n..:4:.n4:R4nI	FsR4w7uXd7RsPCHoDFR_wwcSn
+7_=7wcw_n1
+Suu=1__wwcSn
+BBi=iw_w_
+cnS=B7Bw7_wn_c
+=STTw_w_;cn
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@ng:j4g:.j:ngn:4RsIF	7Rw47udXCRPsFHDowRw_
+c(S77=__wwcS(
+11u=uw_w_
+c(S=BiBwi_w(_c
+7SB=_B7wcw_(T
+S=wT_w(_c;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gn:jn4n.:j4n:nFRIsw	R7d4u7PXRCDsHFwoRwU_c
+=S77w_w_
+cUS=1u1wu_wU_c
+iSB=_Biwcw_UB
+S77=B__wwcSU
+T_=Twcw_UN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:dnj::4.n:jd4InRFRs	wu74dR7XPHCsDRFowcw_g7
+S=w7_wg_c
+uS1=_1uwcw_gB
+Sii=B__wwcSg
+BB7=7w_w_
+cgSTT=__wwc
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gj:nj.:4:jnj:R4nI	FsR4w7uXd7RsPCHoDFR_ww6Sj
+7_=7w6w_j1
+Suu=1__ww6Sj
+BBi=iw_w_
+6jS=B7Bw7_wj_6
+=STTw_w_;6j
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:g4(:.g:6(n:4RsIF	7Rw47udXCRPsFHDowRw_
+64S77=__ww6S4
+11u=uw_w_
+64S=BiBwi_w4_6
+7SB=_B7w6w_4T
+S=wT_w4_6;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:gc46.:g4c:nFRIsw	R7d4u7PXRCDsHFwoRw._6
+=S77w_w_
+6.S=1u1wu_w._6
+iSB=_Biw6w_.B
+S77=B__ww6S.
+T_=Tw6w_.N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:j6g::4.6:gj4InRFRs	wu74dR7XPHCsDRFow6w_d7
+S=w7_wd_6
+uS1=_1uw6w_dB
+Sii=B__ww6Sd
+BB7=7w_w_
+6dSTT=__ww6
+d;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gU:6n.:4:n6U:R4nI	FsR4w7uXd7RsPCHoDFR_ww6Sc
+7_=7w6w_c1
+Suu=1__ww6Sc
+BBi=iw_w_
+6cS=B7Bw7_wc_6
+=STTw_w_;6c
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:U4.:.U:6.n:4RsIF	7Rw47udXCRPsFHDowRw_
+66S77=__ww6S6
+11u=uw_w_
+66S=BiBwi_w6_6
+7SB=_B7w6w_6T
+S=wT_w6_6;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:(U46.:(4U:nFRIsw	R7d4u7PXRCDsHFwoRwn_6
+=S77w_w_
+6nS=1u1wu_wn_6
+iSB=_Biw6w_nB
+S77=B__ww6Sn
+T_=Tw6w_nN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:c6(::4.6:(c4InRFRs	wu74dR7XPHCsDRFow6w_(7
+S=w7_w(_6
+uS1=_1uw6w_(B
+Sii=B__ww6S(
+BB7=7w_w_
+6(STT=__ww6
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:6j.:4:j6(:R4nI	FsR4w7uXd7RsPCHoDFR_ww6SU
+7_=7w6w_U1
+Suu=1__ww6SU
+BBi=iw_w_
+6US=B7Bw7_wU_6
+=STTw_w_;6U
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:n4n:.n:6nn:4RsIF	7Rw47udXCRPsFHDowRw_
+6gS77=__ww6Sg
+11u=uw_w_
+6gS=BiBwi_wg_6
+7SB=_B7w6w_gT
+S=wT_wg_6;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:n.46.:n4.:nFRIsw	R7d4u7PXRCDsHFwoRwj_n
+=S77w_w_
+njS=1u1wu_wj_n
+iSB=_Biwnw_jB
+S77=B__wwnSj
+T_=Twnw_jN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:U66::4.6:6U4InRFRs	wu74dR7XPHCsDRFownw_47
+S=w7_w4_n
+uS1=_1uwnw_4B
+Sii=B__wwnS4
+BB7=7w_w_
+n4STT=__wwn
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g6:6c.:4:c66:R4nI	FsR4w7uXd7RsPCHoDFR_wwnS.
+7_=7wnw_.1
+Suu=1__wwnS.
+BBi=iw_w_
+n.S=B7Bw7_w._n
+=STTw_w_;n.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:64j:.6:6jn:4RsIF	7Rw47udXCRPsFHDowRw_
+ndS77=__wwnSd
+11u=uw_w_
+ndS=BiBwi_wd_n
+7SB=_B7wnw_dT
+S=wT_wd_n;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:cn46.:c4n:nFRIsw	R7d4u7PXRCDsHFwoRwc_n
+=S77w_w_
+ncS=1u1wu_wc_n
+iSB=_Biwnw_cB
+S77=B__wwnSc
+T_=Twnw_cN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:.6c::4.6:c.4InRFRs	wu74dR7XPHCsDRFownw_67
+S=w7_w6_n
+uS1=_1uwnw_6B
+Sii=B__wwnS6
+BB7=7w_w_
+n6STT=__wwn
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gd:6U.:4:U6d:R4nI	FsR4w7uXd7RsPCHoDFR_wwnSn
+7_=7wnw_n1
+Suu=1__wwnSn
+BBi=iw_w_
+nnS=B7Bw7_wn_n
+=STTw_w_;nn
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:d4c:.d:6cn:4RsIF	7Rw47udXCRPsFHDowRw_
+n(S77=__wwnS(
+11u=uw_w_
+n(S=BiBwi_w(_n
+7SB=_B7wnw_(T
+S=wT_w(_n;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:dj46.:d4j:nFRIsw	R7d4u7PXRCDsHFwoRwU_n
+=S77w_w_
+nUS=1u1wu_wU_n
+iSB=_Biwnw_UB
+S77=B__wwnSU
+T_=Twnw_UN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:n6.::4.6:.n4InRFRs	wu74dR7XPHCsDRFownw_g7
+S=w7_wg_n
+uS1=_1uwnw_gB
+Sii=B__wwnSg
+BB7=7w_w_
+ngSTT=__wwn
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g.:6..:4:.6.:R4nI	FsR4w7uXd7RsPCHoDFR_ww(Sj
+7_=7w(w_j1
+Suu=1__ww(Sj
+BBi=iw_w_
+(jS=B7Bw7_wj_(
+=STTw_w_;(j
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:44U:.4:6Un:4RsIF	7Rw4AudXCRPsFHDowRw_
+(4S77=__ww(S4
+11u=uw_w_
+(4S=BiBwi_w4_(
+7Su=_u7w(w_4T
+S=wT_w4_(;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@g6:4c46.:44c:nFRIsw	R7d4u7PXRCDsHFwoRw._(
+=S77w_w_
+(.S=1u1wu_w._(
+iSB=_Biw(w_.B
+S77=B__ww(S.
+T_=Tw(w_.N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:j64::4.6:4j4InRFRs	wu74dR7XPHCsDRFow(w_d7
+S=w7_wd_(
+uS1=_1uw(w_dB
+Sii=B__ww(Sd
+BB7=7w_w_
+(dSTT=__ww(
+d;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gj:6n.:4:n6j:R4nI	FsR4w7uXd7RsPCHoDFR_ww(Sc
+7_=7w(w_c1
+Suu=1__ww(Sc
+BBi=iw_w_
+(cS=B7Bw7_wc_(
+=STTw_w_;(c
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@6g:j4.:.j:6.n:4RsIF	7Rw47udXCRPsFHDowRw_
+(6S77=__ww(S6
+11u=uw_w_
+(6S=BiBwi_w6_(
+7SB=_B7w(w_6T
+S=wT_w6_(;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:gU4c.:g4U:nFRIsw	R7d4u7PXRCDsHFwoRwn_(
+=S77w_w_
+(nS=1u1wu_wn_(
+iSB=_Biw(w_nB
+S77=B__ww(Sn
+T_=Tw(w_nN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:ccg::4.c:gc4InRFRs	wu74dR7XPHCsDRFow(w_(7
+S=w7_w(_(
+uS1=_1uw(w_(B
+Sii=B__ww(S(
+BB7=7w_w_
+((STT=__ww(
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gg:cj.:4:jcg:R4nI	FsR4w7uXd7RsPCHoDFR_ww(SU
+7_=7w(w_U1
+Suu=1__ww(SU
+BBi=iw_w_
+(US=B7Bw7_wU_(
+=STTw_w_;(U
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:U4n:.U:cnn:4RsIF	7Rw47udXCRPsFHDowRw_
+(gS77=__ww(Sg
+11u=uw_w_
+(gS=BiBwi_wg_(
+7SB=_B7w(w_gT
+S=wT_wg_(;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:U.4c.:U4.:nFRIsw	R7d4u7PXRCDsHFwoRwj_U
+=S77w_w_
+UjS=1u1wu_wj_U
+iSB=_BiwUw_jB
+S77=B__wwUSj
+T_=TwUw_jN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:Uc(::4.c:(U4InRFRs	wu74dR7XPHCsDRFowUw_47
+S=w7_w4_U
+uS1=_1uwUw_4B
+Sii=B__wwUS4
+BB7=7w_w_
+U4STT=__wwU
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:cc.:4:cc(:R4nI	FsR4w7uXd7RsPCHoDFR_wwUS.
+7_=7wUw_.1
+Suu=1__wwUS.
+BBi=iw_w_
+U.S=B7Bw7_w._U
+=STTw_w_;U.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:(4j:.(:cjn:4RsIF	7Rw47udXCRPsFHDowRw_
+UdS77=__wwUSd
+11u=uw_w_
+UdS=BiBwi_wd_U
+7SB=_B7wUw_dT
+S=wT_wd_U;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:nn4c.:n4n:nFRIsw	R7d4u7PXRCDsHFwoRwc_U
+=S77w_w_
+UcS=1u1wu_wc_U
+iSB=_BiwUw_cB
+S77=B__wwUSc
+T_=TwUw_cN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:.cn::4.c:n.4InRFRs	wu74dR7XPHCsDRFowUw_67
+S=w7_w6_U
+uS1=_1uwUw_6B
+Sii=B__wwUS6
+BB7=7w_w_
+U6STT=__wwU
+6;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g6:cU.:4:Uc6:R4nI	FsR4w7uXd7RsPCHoDFR_wwUSn
+7_=7wUw_n1
+Suu=1__wwUSn
+BBi=iw_w_
+UnS=B7Bw7_wn_U
+=STTw_w_;Un
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:64c:.6:ccn:4RsIF	7Rw47udXCRPsFHDowRw_
+U(S77=__wwUS(
+11u=uw_w_
+U(S=BiBwi_w(_U
+7SB=_B7wUw_(T
+S=wT_w(_U;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:6j4c.:64j:nFRIsw	R7d4u7PXRCDsHFwoRwU_U
+=S77w_w_
+UUS=1u1wu_wU_U
+iSB=_BiwUw_UB
+S77=B__wwUSU
+T_=TwUw_UN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:ncc::4.c:cn4InRFRs	wu74dR7XPHCsDRFowUw_g7
+S=w7_wg_U
+uS1=_1uwUw_gB
+Sii=B__wwUSg
+BB7=7w_w_
+UgSTT=__wwU
+g;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@gc:c..:4:.cc:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSj
+7_=7wgw_j1
+Suu=1__wwgSj
+BBi=iw_w_
+gjS=B7Bw7_wj_g
+=STTw_w_;gj
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:d4U:.d:cUn:4RsIF	7Rw47udXCRPsFHDowRw_
+g4S77=__wwgS4
+11u=uw_w_
+g4S=BiBwi_w4_g
+7SB=_B7wgw_4T
+S=wT_w4_g;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:dc4c.:d4c:nFRIsw	R7d4u7PXRCDsHFwoRw._g
+=S77w_w_
+g.S=1u1wu_w._g
+iSB=_Biwgw_.B
+S77=B__wwgS.
+T_=Twgw_.N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:jcd::4.c:dj4InRFRs	wu74dR7XPHCsDRFowgw_d7
+S=w7_wd_g
+uS1=_1uwgw_dB
+Sii=B__wwgSd
+BB7=7w_w_
+gdSTT=__wwg
+d;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g.:cn.:4:nc.:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSc
+7_=7wgw_c1
+Suu=1__wwgSc
+BBi=iw_w_
+gcS=B7Bw7_wc_g
+=STTw_w_;gc
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:.4.:..:c.n:4RsIF	7Rw47udXCRPsFHDowRw_
+g6S77=__wwgS6
+11u=uw_w_
+g6S=BiBwi_w6_g
+7SB=_B7wgw_6T
+S=wT_w6_g;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:4U4c.:44U:nFRIsw	R7d4u7PXRCDsHFwoRwn_g
+=S77w_w_
+gnS=1u1wu_wn_g
+iSB=_Biwgw_nB
+S77=B__wwgSn
+T_=Twgw_nN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+Rg@@:cc4::4.c:4c4InRFRs	wu74dR7XPHCsDRFowgw_(7
+S=w7_w(_g
+uS1=_1uwgw_(B
+Sii=B__wwgS(
+BB7=7w_w_
+g(STT=__wwg
+(;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g4:cj.:4:jc4:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSU
+7_=7wgw_U1
+Suu=1__wwgSU
+BBi=iw_w_
+gUS=B7Bw7_wU_g
+=STTw_w_;gU
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@cg:j4n:.j:cnn:4RsIF	7Rw47udXCRPsFHDowRw_
+ggS77=__wwgSg
+11u=uw_w_
+ggS=BiBwi_wg_g
+7SB=_B7wgw_gT
+S=wT_wg_g;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@:@gc:j.4c.:j4.:(FRIsw	R7d4u7PXRCDsHFwoRwj_4j7
+S=w7_wj_4j1
+Suu=1__ww4
+jjS=BiBwi_wj_4jB
+S77=B__ww4
+jjSTT=__ww4;jj
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@dg:g4U:.g:dU(:4RsIF	7Rw4AudXCRPsFHDowRw_44j
+=S77w_w_44j
+uS1=_1uw4w_jS4
+BBi=iw_w_44j
+7Su=_u7w4w_jS4
+T_=Tw4w_j
+4;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@g(:djd:4:jd(:R.6I	FsRuu7Wi4n7CRPsFHDo8RbbN_sl__jj
+_jSd7Q6Q=7db6_8sb_Njl__jj_
+QS7d7c=Q_dcb_8bs_Nlj__jj7
+SQ=dd7dQd_bb8_lsN_jj__Sj
+7.Qd=d7Q.8_bbN_sl__jj
+_jSd7Q4Q=7db4_8sb_Njl__jj_
+QS7d7j=Q_djb_8bs_Nlj__jj7
+SQ=.g7gQ._bb8_lsN_jj__Sj
+7UQ.=.7QU8_bbN_sl__jj
+_jS.7Q(Q=7.b(_8sb_Njl__jj_
+QS7.7n=Q_.nb_8bs_Nlj__jj7
+SQ=.676Q._bb8_lsN_jj__Sj
+7cQ.=.7Qc8_bbN_sl__jj
+_jS.7QdQ=7.bd_8sb_Njl__jj_
+QS7.7.=Q_..b_8bs_Nlj__jj7
+SQ=.474Q._bb8_lsN_jj__Sj
+7jQ.=.7Qj8_bbN_sl__jj
+_jS47QgQ=74bg_8sb_Njl__jj_
+QS747U=Q_4Ub_8bs_Nlj__jj7
+SQ=4(7(Q4_bb8_lsN_jj__Sj
+7nQ4=47Qn8_bbN_sl__jj
+_jS47Q6Q=74b6_8sb_Njl__jj_
+QS747c=Q_4cb_8bs_Nlj__jj7
+SQ=4d7dQ4_bb8_lsN_jj__Sj
+7.Q4=47Q.8_bbN_sl__jj
+_jS47Q4Q=74b4_8sb_Njl__jj_
+QS747j=Q_4jb_8bs_Nlj__jj7
+SQ7g=Qbg_8sb_Njl__jj_
+QS7UQ=7U8_bbN_sl__jj
+_jS(7Q=(7Q_bb8_lsN_jj__Sj
+7=Qn7_Qnb_8bs_Nlj__jj7
+SQ76=Qb6_8sb_Njl__jj_
+QS7cQ=7c8_bbN_sl__jj
+_jSd7Q=d7Q_bb8_lsN_jj__Sj
+7=Q.7_Q.b_8bs_Nlj__jj7
+SQ74=Qb4_8sb_Njl__jj_
+QS7jQ=7j8_bbN_sl__jj
+_jSWq7U7=qWbU_8sb_Njl__jj_
+7SqWq(=7_W(b_8bs_Nlj__jjq
+S7=Wnqn7W_bb8_lsN_jj__Sj
+q67W=Wq768_bbN_sl__jj
+_jSWq7c7=qWbc_8sb_Njl__jj_
+7SqWqd=7_Wdb_8bs_Nlj__jjq
+S7=W.q.7W_bb8_lsN_jj__Sj
+q47W=Wq748_bbN_sl__jj
+_jSWq7j7=qWbj_8sb_Njl__jj_
+ SAd =Ad8_bbN_sl__jj
+_jS.A =.A _bb8_lsN_jj__Sj
+A= 4A_ 4b_8bs_Nlj__jjA
+S Aj= bj_8sb_Njl__jj_
+ SBW =BW8_bbN_sl__jj
+_jSiBpWp=BibW_8sb_Njl__jj_
+1SBWB.=1_W.b_8bs_Nlj__jjB
+S1=W4B41W_bb8_lsN_jj__Sj
+Bj1W=WB1j8_bbN_sl__jj
+_jS)q74qd=7d)4_bb8_lsN_jj__Sj
+q47).7=q)_4.b_8bs_Nlj__jjq
+S74)4=)q74b4_8sb_Njl__jj_
+7Sq)=4jq47)j8_bbN_sl__jj
+_jS)q7g7=q)bg_8sb_Njl__jj_
+7Sq)qU=7_)Ub_8bs_Nlj__jjq
+S7=)(q(7)_bb8_lsN_jj__Sj
+qn7)=)q7n8_bbN_sl__jj
+_jS)q767=q)b6_8sb_Njl__jj_
+7Sq)qc=7_)cb_8bs_Nlj__jjq
+S7=)dqd7)_bb8_lsN_jj__Sj
+q.7)=)q7.8_bbN_sl__jj
+_jS)q747=q)b4_8sb_Njl__jj_
+7Sq)qj=7_)jb_8bs_Nlj__jjB
+S B)= b)_8sb_Njl__jj_
+BSm m)=B_ )b_8bs_Nlj__jjB
+Sp=i)B)pi_bb8_lsN_jj__Sj
+B.1)=)B1.8_bbN_sl__jj
+_jS)B141=B)b4_8sb_Njl__jj_
+1SB)Bj=1_)jb_8bs_Nlj__jj)
+S1)a=1ba_8sb_Njl__jj_
+mS7d76=m_d6b_8bs_Nlj__jj7
+Sm=dc7cmd_bb8_lsN_jj__Sj
+7dmd=d7md8_bbN_sl__jj
+_jSd7m.m=7db._8sb_Njl__jj_
+mS7d74=m_d4b_8bs_Nlj__jj7
+Sm=dj7jmd_bb8_lsN_jj__Sj
+7gm.=.7mg8_bbN_sl__jj
+_jS.7mUm=7.bU_8sb_Njl__jj_
+mS7.7(=m_.(b_8bs_Nlj__jj7
+Sm=.n7nm._bb8_lsN_jj__Sj
+76m.=.7m68_bbN_sl__jj
+_jS.7mcm=7.bc_8sb_Njl__jj_
+mS7.7d=m_.db_8bs_Nlj__jj7
+Sm=..7.m._bb8_lsN_jj__Sj
+74m.=.7m48_bbN_sl__jj
+_jS.7mjm=7.bj_8sb_Njl__jj_
+mS747g=m_4gb_8bs_Nlj__jj7
+Sm=4U7Um4_bb8_lsN_jj__Sj
+7(m4=47m(8_bbN_sl__jj
+_jS47mnm=74bn_8sb_Njl__jj_
+mS7476=m_46b_8bs_Nlj__jj7
+Sm=4c7cm4_bb8_lsN_jj__Sj
+7dm4=47md8_bbN_sl__jj
+_jS47m.m=74b._8sb_Njl__jj_
+mS7474=m_44b_8bs_Nlj__jj7
+Sm=4j7jm4_bb8_lsN_jj__Sj
+7=mg7_mgb_8bs_Nlj__jj7
+Sm7U=mbU_8sb_Njl__jj_
+mS7(m=7(8_bbN_sl__jj
+_jSn7m=n7m_bb8_lsN_jj__Sj
+7=m67_m6b_8bs_Nlj__jj7
+Sm7c=mbc_8sb_Njl__jj_
+mS7dm=7d8_bbN_sl__jj
+_jS.7m=.7m_bb8_lsN_jj__Sj
+7=m47_m4b_8bs_Nlj__jj7
+Sm7j=mbj_8sb_Njl__jj_;H
+NRM#$_bMFsCkMR
+4;NQHRh_Qa7qqaRa"1qBaQ"N;
+H1RqY_hB)  1a _)p1 q 1R"Y"hB;H
+NR7B1 7Bm R_)"jjLj;j"
+RNHB 17B m7_"WRjjLj4
+";NtHR1")R Ahqp" 7;H
+NR1)  mav7" R1BYh"N;
+H R)t7vm hR"mt) "N;
+HqR7aWq_Q]7a_d)RnN;
+HqR7aWq_Q]7a_dWRnN;
+H#R3$NM_0F0Vs0lN#CHxRq"7aWq_Q]7a_d)=.qR7aWq_Q]7a_dW=.
+";N3HR#_$MNV00FNsl07R"q_aqWaQ7]=_)7qR7aWq_Q]7a_7W="N;
+H Rvvh_QQwa_QRp "
+";NvHR pv_uwB_QRp "VVHF8d.Ob3DO
+";s@R@g6:dUd:4:Ud6:R4UI	FsRv)m44nXqCRPsFHDozRpajc_
+7Sqd7=qdz_pajc_
+7Sq.7=q.z_pajc_
+7Sq47=q4z_pajc_
+7Sqj7=qjz_pajc_
+mS7jm=7jz_pajc_;H
+NRM#$_bMFsCkMR
+4;NHHRMPH0N"DR4Ln'jj4jjjjjjjjjj4jj"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@:@gd:6c4dd:64c:UFRIs)	Rmnv4XR4qPHCsDRFopcza_S4
+q=7dq_7dpcza_S4
+q=7.q_7.pcza_S4
+q=74q_74pcza_S4
+q=7jq_7jpcza_S4
+7=mj7_mjpcza_
+4;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'jLjjjjjj44jjjjjj;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g6:djd:4:jd6:R4UI	FsRv)m44nXqCRPsFHDozRpa.c_
+7Sqd7=qdz_pa.c_
+7Sq.7=q.z_pa.c_
+7Sq47=q4z_pa.c_
+7Sqj7=qjz_pa.c_
+mS7jm=7jz_pa.c_;H
+NRM#$_bMFsCkMR
+4;NHHRMPH0N"DR4Ln'j4jjjjjjjjjjjj4j"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@:@gd:cn4dd:c4n:UFRIs)	Rmnv4XR4qPHCsDRFopcza_Sd
+q=7dq_7dpcza_Sd
+q=7.q_7.pcza_Sd
+q=74q_74pcza_Sd
+q=7jq_7jpcza_Sd
+7=mj7_mjpcza_
+d;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'jLjj4jjjjjjjj4jj;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gc:d.d:4:.dc:R4UI	FsRv)m44nXqCRPsFHDozRpacc_
+7Sqd7=qdz_pacc_
+7Sq.7=q.z_pacc_
+7Sq47=q4z_pacc_
+7Sqj7=qjz_pacc_
+mS7jm=7jz_pacc_;H
+NRM#$_bMFsCkMR
+4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@:@gd:dU4dd:d4U:UFRIs)	Rmnv4XR4qPHCsDRFopcza_S6
+q=7dq_7dpcza_S6
+q=7.q_7.pcza_S6
+q=74q_74pcza_S6
+q=7jq_7jpcza_S6
+7=mj7_mjpcza_
+6;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gd:dcd:4:cdd:R4UI	FsRv)m44nXqCRPsFHDozRpanc_
+7Sqd7=qdz_panc_
+7Sq.7=q.z_panc_
+7Sq47=q4z_panc_
+7Sqj7=qjz_panc_
+mS7jm=7jz_panc_;H
+NRM#$_bMFsCkMR
+4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@:@gd:dj4dd:d4j:UFRIs)	Rmnv4XR4qPHCsDRFopcza_S(
+q=7dq_7dpcza_S(
+q=7.q_7.pcza_S(
+q=74q_74pcza_S(
+q=7jq_7jpcza_S(
+7=mj7_mjpcza_
+(;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g.:dnd:4:nd.:R4UI	FsRv)m44nXqCRPsFHDozRpaUc_
+7Sqd7=qdz_paUc_
+7Sq.7=q.z_paUc_
+7Sq47=q4z_paUc_
+7Sqj7=qjz_paUc_
+mS7jm=7jz_paUc_;H
+NRM#$_bMFsCkMR
+4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@:@gd:..4dd:.4.:UFRIs)	Rmnv4XR4qPHCsDRFopcza_Sg
+q=7dq_7dpcza_Sg
+q=7.q_7.pcza_Sg
+q=74q_74pcza_Sg
+q=7jq_7jpcza_Sg
+7=mj7_mjpcza_
+g;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g4:dUd:4:Ud4:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_jq
+S7qd=7pd_z_ac4Sj
+q=7.q_7.pcza_
+4jS4q7=4q7_apzcj_4
+7Sqj7=qjz_pa4c_j7
+Sm7j=mpj_z_ac4
+j;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g4:dcd:4:cd4:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_4q
+S7qd=7pd_z_ac4S4
+q=7.q_7.pcza_
+44S4q7=4q7_apzc4_4
+7Sqj7=qjz_pa4c_47
+Sm7j=mpj_z_ac4
+4;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g4:djd:4:jd4:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_.q
+S7qd=7pd_z_ac4S.
+q=7.q_7.pcza_
+4.S4q7=4q7_apzc._4
+7Sqj7=qjz_pa4c_.7
+Sm7j=mpj_z_ac4
+.;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gj:dnd:4:ndj:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_dq
+S7qd=7pd_z_ac4Sd
+q=7.q_7.pcza_
+4dS4q7=4q7_apzcd_4
+7Sqj7=qjz_pa4c_d7
+Sm7j=mpj_z_ac4
+d;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gj:d.d:4:.dj:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_cq
+S7qd=7pd_z_ac4Sc
+q=7.q_7.pcza_
+4cS4q7=4q7_apzcc_4
+7Sqj7=qjz_pa4c_c7
+Sm7j=mpj_z_ac4
+c;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gg:.Ud:4:U.g:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_6q
+S7qd=7pd_z_ac4S6
+q=7.q_7.pcza_
+46S4q7=4q7_apzc6_4
+7Sqj7=qjz_pa4c_67
+Sm7j=mpj_z_ac4
+6;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gg:.cd:4:c.g:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_nq
+S7qd=7pd_z_ac4Sn
+q=7.q_7.pcza_
+4nS4q7=4q7_apzcn_4
+7Sqj7=qjz_pa4c_n7
+Sm7j=mpj_z_ac4
+n;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gg:.jd:4:j.g:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_(q
+S7qd=7pd_z_ac4S(
+q=7.q_7.pcza_
+4(S4q7=4q7_apzc(_4
+7Sqj7=qjz_pa4c_(7
+Sm7j=mpj_z_ac4
+(;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gU:.nd:4:n.U:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_Uq
+S7qd=7pd_z_ac4SU
+q=7.q_7.pcza_
+4US4q7=4q7_apzcU_4
+7Sqj7=qjz_pa4c_U7
+Sm7j=mpj_z_ac4
+U;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gU:..d:4:..U:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_gq
+S7qd=7pd_z_ac4Sg
+q=7.q_7.pcza_
+4gS4q7=4q7_apzcg_4
+7Sqj7=qjz_pa4c_g7
+Sm7j=mpj_z_ac4
+g;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g(:.Ud:4:U.(:R4gI	FsRv)m44nXqCRPsFHDozRpa.c_jq
+S7qd=7pd_z_ac.Sj
+q=7.q_7.pcza_
+.jS4q7=4q7_apzcj_.
+7Sqj7=qjz_pa.c_j7
+Sm7j=mpj_z_ac.
+j;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g(:.cd:4:c.(:R4gI	FsRv)m44nXqCRPsFHDozRpa.c_4q
+S7qd=7pd_z_ac.S4
+q=7.q_7.pcza_
+.4S4q7=4q7_apzc4_.
+7Sqj7=qjz_pa.c_47
+Sm7j=mpj_z_ac.
+4;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@g(:.jd:4:j.(:R4gI	FsRv)m44nXqCRPsFHDozRpa.c_.q
+S7qd=7pd_z_ac.S.
+q=7.q_7.pcza_
+..S4q7=4q7_apzc._.
+7Sqj7=qjz_pa.c_.7
+Sm7j=mpj_z_ac.
+.;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gn:.nd:4:n.n:R4gI	FsRv)m44nXqCRPsFHDozRpa.c_dq
+S7qd=7pd_z_ac.Sd
+q=7.q_7.pcza_
+.dS4q7=4q7_apzcd_.
+7Sqj7=qjz_pa.c_d7
+Sm7j=mpj_z_ac.
+d;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@gn:.d::g.:nd4I6RFRs	X.m)RsPCHoDFR)Xm.j_0
+=Sqqm_X)0._jA
+S=XA_m_).0Sj
+Z_=ZX.m)_;0j
+RNH#_$MMsFbkRMC4s;
+Rg@@:4.n:.g:n44:6FRIsX	RmR).PHCsDRFoX.m)_
+04Sqq=_)Xm.4_0
+=SAAm_X)0._4Z
+S=XZ_m_).0
+4;N#HR$MM_FkbsM4CR;R
+s@:@g.:6gg6:.g6:4RsIF	mRX)P.RCDsHFXoRm_).0S.
+q_=qX.m)_
+0.SAA=_)Xm.._0
+=SZZm_X)0._.N;
+H$R#MF_MbMskC;R4
+@sR@.g:6g(::(.6:R46I	FsR)Xm.CRPsFHDomRX)0._dq
+S=Xq_m_).0Sd
+A_=AX.m)_
+0dSZZ=_)Xm.d_0;H
+NRM#$_bMFsCkMR
+4;s@R@g6:.6::g.:664I6RFRs	X.m)RsPCHoDFR)Xm.c_0
+=Sqqm_X)0._cA
+S=XA_m_).0Sc
+Z_=ZX.m)_;0c
+RNH#_$MMsFbkRMC4s;
+Rg@@:d.6:.g:64d:6FRIsX	RmR).PHCsDRFoX.m)_
+06Sqq=_)Xm.6_0
+=SAAm_X)0._6Z
+S=XZ_m_).0
+6;N#HR$MM_FkbsM4CR;R
+s@:@g.:64g6:.46:4RsIF	mRX)P.RCDsHFXoRm_).0Sn
+q_=qX.m)_
+0nSAA=_)Xm.n_0
+=SZZm_X)0._nN;
+H$R#MF_MbMskC;R4
+@sR@.g:cgg::g.c:R46I	FsR)Xm.CRPsFHDomRX)0._(q
+S=Xq_m_).0S(
+A_=AX.m)_
+0(SZZ=_)Xm.(_0;H
+NRM#$_bMFsCkMR
+4;s@R@gc:.(::g.:c(4I6RFRs	X.m)RsPCHoDFR)Xm.U_0
+=Sqqm_X)0._UA
+S=XA_m_).0SU
+Z_=ZX.m)_;0U
+RNH#_$MMsFbkRMC4s;
+Rg@@:6.c:.g:c46:6FRIsX	RmR).PHCsDRFoX.m)_
+0gSqq=_)Xm.g_0
+=SAAm_X)0._gZ
+S=XZ_m_).0
+g;N#HR$MM_FkbsM4CR;R
+s@:@g.:cdgc:.dn:4RsIF	mRX)P.RCDsHFXoRm_).0
+4jSqq=_)Xm.4_0jA
+S=XA_m_).0
+4jSZZ=_)Xm.4_0jN;
+H$R#MF_MbMskC;R4
+@sR@.g:cg4::4.c:R4nI	FsR)Xm.CRPsFHDomRX)0._4S4
+q_=qX.m)_404
+=SAAm_X)0._4S4
+Z_=ZX.m)_404;H
+NRM#$_bMFsCkMR
+4;s@R@gd:.g::g.:dg4InRFRs	X.m)RsPCHoDFR)Xm.4_0.q
+S=Xq_m_).0
+4.SAA=_)Xm.4_0.Z
+S=XZ_m_).0;4.
+RNH#_$MMsFbkRMC4s;
+Rg@@:(.d:.g:d4(:nFRIsX	RmR).PHCsDRFoX.m)_d04
+=Sqqm_X)0._4Sd
+A_=AX.m)_d04
+=SZZm_X)0._4
+d;N#HR$MM_FkbsM4CR;R
+s@:@g.:d6gd:.6n:4RsIF	mRX)P.RCDsHFXoRm_).0
+4cSqq=_)Xm.4_0cA
+S=XA_m_).0
+4cSZZ=_)Xm.4_0cN;
+H$R#MF_MbMskC;R4
+@sR@.g:dgd::d.d:R4nI	FsR)Xm.CRPsFHDomRX)0._4S6
+q_=qX.m)_604
+=SAAm_X)0._4S6
+Z_=ZX.m)_604;H
+NRM#$_bMFsCkMR
+4;s@R@gd:.4::g.:d44InRFRs	X.m)RsPCHoDFR)Xm.4_0nq
+S=Xq_m_).0
+4nSAA=_)Xm.4_0nZ
+S=XZ_m_).0;4n
+RNH#_$MMsFbkRMC4s;
+Rg@@:g..:.g:.4g:nFRIsX	RmR).PHCsDRFoX.m)_(04
+=Sqqm_X)0._4S(
+A_=AX.m)_(04
+=SZZm_X)0._4
+(;N#HR$MM_FkbsM4CR;R
+s@:@g.:.(U.:.(c:4RsIF	)Rm.CRPsFHDo)Rm.4_0Uq
+S=mq_)0._4SU
+A_=Am_).0
+4USZZ=_.m)_U04;H
+NRM#$_bMFsCkMR
+4;s@R@g.:.6::U.:.64I.RFRs	QRhePHCsDRFoQ_hejq
+S=Qq_hje_
+=SZZh_Qe;_j
+RNH#_$MMsFbkRMC4s;
+Rg@@:d..:.g:.4d:nFRIsq	RhR7.PHCsDRFoq.h7_g04
+=Sqqh_q70._4Sg
+A_=Aq.h7_g04
+=SZZh_q70._4
+g;N#HR$MM_FkbsM4CR;R
+s@:@g.:.4U.:.4.:4RsIF	hRQeCRPsFHDohRQe
+_4Sqq=_eQh_S4
+Z_=ZQ_he4N;
+H$R#MF_MbMskC;R4
+@sR@.g:4gg::g.4:R4nI	FsR7qh.CRPsFHDohRq70._.Sj
+q_=qq.h7_j0.
+=SAAh_q70._.Sj
+Z_=Zq.h7_j0.;H
+NRM#$_bMFsCkMR
+4;y--------------------------------
+--@
+ 
+
+ftell;
+@E@MR@:4d.:dn(d:.n4:.RsIF	kRF00bk_O8CFs8CUCRPsFHDoN;
+PVR3FNslDC_ODNDMl"CRFbk0k80_C8OFC"sU;P
+NR#3HPHCsDRFo4N;
+PHR3#C_PsFHDo;R4
+RNP3HFsolhNCFR"kk0b0C_8OCF8s;U"
+RNPFosH_#HM0V_FRk"F00bk_O8CFs8CU
+";N3PRFosHDMHLNRlC"sIF	
+";N3PRDCN$sRH8jN;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_ppe4N_sIk_F0M_H#803CHO_M"#0;P
+NRM#$_Cbs#PCsC;R4
+RNP3l#00#DH0llCko#NC3Rjjjjjj
+j;N3PR#00lD0H#0CHlRjj3jjjjj
+;
+
+@HR@:4d.:d(gd:.(4:4R	ODR	OD;
+
+
+
+@HR@:4d.:dUgd:.Uj:4RrHM(9:jRrHM(9:j;
+
+
+
+@FR@:4d.:c(4.n:c4(:UkRF0:r.j;9R
+RNH#_$Mb#sCCCsPR
+4;
+@FR@:4d.:cg4.4:c4g:6NRPDRH8;H
+NRM#$_Cbs#PCsC;R4
+@FR@:4d.:c4gc:.4j:.R_HM#O$MCD8_L:r(j;9R
+@FR@:4d.:6.4.n:6..:nNRsIN_D0COE8:r(j;9R
+RNHb#sCCCsPR
+4;y--------------------------------
+--@
+ 
+
+ftell;
+@E@MR@:4d4:nj(n:4jg:4RsIF	8R0O8c8sE_#FRs0PHCsD;Fo
+RNP3sVFl_NDODCDMCNlR8"0O8c8sE_#F"s0;P
+NR#3HPHCsDRFo4N;
+PHR3#C_PsFHDo;R4
+RNP3HFsolhNC0R"88Oc8#s_E0Fs"N;
+PsRFHHo_M_#0F"VR0c8O8_8s#sEF0
+";N3PRFosHDMHLNRlC"sIF	
+";N3PRDCN$sRH8jN;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_ppe4N_sIk_F0M_H#0038HO_M"#0;P
+NRM#$_Cbs#PCsC;R4
+RNP3l#00#DH0llCko#NC3Rjjjjjj
+j;N3PR#00lD0H#0CHlRjj3jjjjj
+;
+
+@HR@:4d4:nj.44:n.j:(sR0HCoossR0HCoos
+;
+
+@HR@:4d4:njd4j:ndj:dDRO	d#r:Rj9O#D	rjd:9
+;
+
+@FR@:4d4:njd4n:ndj:UkRF0:r(j;9R
+RNH#_$Mb#sCCCsPR
+4;y--------------------------------
+--@
+ 
+
+ftell;
+@E@MR@:4dd:c4(c:d4c:4RsIF	sR0HHo_MPPRCDsHF
+o;N3PRVlFsNOD_CMDDNRlC"H0soM_HP
+";N3PRHC#PsFHDo;R4
+RNP3_H#PHCsDRFo4N;
+PFR3shHoNRlC"H0soM_HP
+";NFPRs_HoH0M#_RFV"H0soM_HP
+";N3PRFosHDMHLNRlC"sIF	
+";N3PRDCN$sRH8jN;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_O08_NOEMDMC_IsN_0Fk_#HM0s30HHo_MHP_M4#0"N;
+P$R#Ms_bCs#CP4CR;P
+NR03#lH0D#C0llNk#ojCR3jjjj;jj
+RNP3l#00#DH0l0HC3Rjjjjjj
+j;
+@HR@:4dd:c44dn:c44:(MRHR;HM
+RNH#_$M	bCCR
+4;
+@FR@:4dd:c44dg:c.4:4kRF0
+R;N#HR$	M_CRCb4y;
+---------------------------------@-
+ 
+
+
+
+ftell;
+@E@MR@:4dd::(dn:.RsIF	8R0OE_ONCMMDH_VVFF_kP0RCDsHF
+o;N3PRVlFsNOD_CMDDNRlC"O08_NOEMDMC_VVHFk_F0
+";N3PRHC#PsFHDo;R4
+RNP3_H#PHCsDRFo4N;
+PFR3shHoNRlC"O08_NOEMDMC_VVHFk_F0
+";NFPRs_HoH0M#_RFV"O08_NOEMDMC_VVHFk_F0
+";N3PRFosHDMHLNRlC"sIF	
+";N3PRDCN$sRH8jN;
+PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03O08_NOEMDMC_VVHFk_F0M_H#;0"
+RNP3l#00#DH0llCko#NC3Rjjjjjj
+j;N3PR#00lD0H#0CHlRjj3jjjjj
+;
+
+@HR@:4dcj:4:4c:cCRs#RC0sCC#0
+;
+
+@HR@:4d6j:4:46:(DRbDD_O	d#r:Rj9b_DDO#D	rjd:9
+;
+
+@HR@:4dnj:4:4n:6FRONCs#r:.(jO9RF#NsC(r.:;j9
+@HR@:4d(j:4:4(:dsR0H0oRs;Ho
+@FR@:4dUj:4:.U:.HRVV8F_N_0NFrk0dj4:9
+R;
+@HR@:4dgj:4:4g:UHRVVsF_8RCMVFHV_Cs8M
+;
+
+@FR@:4d44j:jj:4:R4gVFHV_bCl0;$R
+@FR@:4d444:j4:4:R4n0_8OFrk0(9:jRs;
+R4@@d(:g::4jg.(:.FRIsV	RHdVF.R8OPHCsDRFoVFHVdO.8_#HM07
+SNr0Ndj4:9N=70VN_HdVF._8OH0M#r:d4jS9
+WDsBF=O	WDsBF_O	VFHVdO.8_#HM0)
+S8FBDO)	=8FBDOV	_HdVF._8OH0M#
+sSW WM=s_ MVFHVdO.8_#HM0)
+S8= M)M8 _VVHF8d.OM_H#S0
+)CC#0C=)#_C0VFHVdO.8_#HM0)
+Su#)CC)0=u#)CCV0_HdVF._8OH0M#
+rSTdj4:9_=TVFHVdO.8_#HM04rd:
+j9Sb l0 $=l$b0_VVHF8d.OM_H#S0
+wDkD=DwkDH_VV.Fd8HO_M;#0
+RNH#_$MMsFbkRMC4s;
+R4@@dj:g::4(g.j:UFRIsF	Rkk0b0C_8OCF8sPURCDsHF8oRCMO_CHo_M
+#0S	OD=	OD_O8C_oMC_#HM0H
+SM:r(jH9=MC_8OC_MoM_H#(0r:
+j9S0Fkrj.:9k=F0C_8OC_MoM_H#.0r:
+j9SDPNHP8=N8DH_O8C_oMC_#HM0H
+SM$_#M8OC_rDL(9:j=_HM#O$MCD8_LC_8OC_MoM_H#(0r:
+j9SIsN_0DNO8ECrj(:9N=sIN_D0COE8C_8OC_MoM_H#(0r:;j9
+RNH#_$MMsFbkRMC4N;
+H$R#Ms_bCs#CP4CR;R
+s@d@4::Ud4U(:dc:.RsIF	kRF00bk_O8CFs8CUCRPsFHDoCR8OM_H#S0
+O=D	O_D	8_COH0M#
+MSHrj(:9M=H_O8C_#HM0:r(jS9
+Frk0.9:j=0Fk_O8C_#HM0:r.jS9
+PHND8N=PD_H88_COH0M#
+MSH_M#$O_C8D(Lr:=j9H#M_$CMO8L_D_O8C_#HM0:r(jS9
+s_NIDON0ErC8(9:j=IsN_0DNO8EC_O8C_#HM0:r(j
+9;N#HR$MM_FkbsM4CR;R
+s@d@4::ng4n6:gn:.RsIF	8R0O8c8sE_#FRs0PHCsDRFo0_8OM_CoH0M#
+sS0HCooss=0HCoos8_0OC_MoM_H#S0
+O#D	rjd:9D=O	0#_8MO_CHo_Mr#0d9:j
+kSF0:r(jF9=k00_8MO_CHo_Mr#0(9:j;H
+NRM#$_bMFsCkMR
+4;N#HR$bM_sCC#sRPC4s;
+R4@@dc:n::46n.c:.FRIs0	R88Oc8#s_E0FsRsPCHoDFRO08_#HM00
+SsoHoC0s=soHoC0s_8HO_M
+#0S	OD#:rdjO9=D_	#0_8OH0M#rjd:9F
+Sk(0r:=j9F_k00_8OH0M#rj(:9N;
+H$R#MF_MbMskC;R4
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+=STTw_w_;44
+RNH#_$MMsFbkRMC4N;
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+=S77w_w_
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+=STTw_w_;46
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+=S77w_w_
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+=STTw_w_;4g
+RNH#_$MMsFbkRMC4N;
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+=S77w_w_
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+=STTw_w_;.d
+RNH#_$MMsFbkRMC4N;
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+@sR@:46(:4c4(.:44c:nFRIsw	R7d417PXRCDsHFwoRwc_.
+=S77w_w_
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+.(S77=__ww.S(
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+.(S=B7Bw7_w(_.
+=STTw_w_;.(
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46(:j.4(.:j4.:nFRIsw	R7d417PXRCDsHFwoRwU_.
+=S77w_w_
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+d4S77=__wwdS4
+BBi=iw_w_
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+=STTw_w_;d4
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:gj4n.:g4j:nFRIsw	R7d417PXRCDsHFwoRw._d
+=S77w_w_
+d.S=BiBwi_w._d
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+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
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+RNHtR1)"q hA7p "s;
+R4@@6U:nc.:4:cnU:R4nI	FsR4w71Xd7RsPCHoDFR_wwdSc
+7_=7wdw_cB
+Sii=B__wwdSc
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+c;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@4n6:U44:.U:n4n:4RsIF	7Rw471dXCRPsFHDowRw_
+d6S77=__wwdS6
+BBi=iw_w_
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+=STTw_w_;d6
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:(U4n.:(4U:nFRIsw	R7d417PXRCDsHFwoRwn_d
+=S77w_w_
+dnS=BiBwi_wn_d
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+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
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+RNHtR1)"q hA7p "s;
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+7_=7wdw_UB
+Sii=B__wwdSU
+BB7=7w_w_
+dUSTT=__wwd
+U;N#HR$MM_FkbsM4CR;H
+NR)t1Rh" q Ap7
+";s@R@4n6:n4g:.n:ngn:4RsIF	7Rw471dXCRPsFHDowRw_
+dgS77=__wwdSg
+BBi=iw_w_
+dgS=B7Bw7_wg_d
+=STTw_w_;dg
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:nn4n.:n4n:nFRIsw	R7d417PXRCDsHFwoRwj_c
+=S77w_w_
+cjS=BiBwi_wj_c
+7SB=_B7wcw_jT
+S=wT_wj_c;H
+NRM#$_bMFsCkMR
+4;NtHR1")R Ahqp" 7;R
+s@6@4:dnn::4.n:nd4InRFRs	w174dR7XPHCsDRFowcw_47
+S=w7_w4_c
+iSB=_Biwcw_4B
+S77=B__wwcS4
+T_=Twcw_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6n:nj.:4:jnn:R4nI	FsR4w7uXd7RsPCHoDFR_wwcS.
+7_=7wcw_.1
+Suu=1__wwcS.
+BBi=iw_w_
+c.S=B7Bw7_w._c
+=STTw_w_;c.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:6(4n.:64(:nFRIsw	R7d4u7PXRCDsHFwoRwd_c
+=S77w_w_
+cdS=1u1wu_wd_c
+iSB=_Biwcw_dB
+S77=B__wwcSd
+T_=Twcw_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@66:nc.:4:cn6:R4nI	FsR4w7uXd7RsPCHoDFR_wwcSc
+7_=7wcw_c1
+Suu=1__wwcSc
+BBi=iw_w_
+ccS=B7Bw7_wc_c
+=STTw_w_;cc
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:644n.:644:nFRIsw	R7d4u7PXRCDsHFwoRw6_c
+=S77w_w_
+c6S=1u1wu_w6_c
+iSB=_Biwcw_6B
+S77=B__wwcS6
+T_=Twcw_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6c:nU.:4:Unc:R4nI	FsR4w7uXd7RsPCHoDFR_wwcSn
+7_=7wcw_n1
+Suu=1__wwcSn
+BBi=iw_w_
+cnS=B7Bw7_wn_c
+=STTw_w_;cn
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:c64n.:c46:nFRIsw	R7d4u7PXRCDsHFwoRw(_c
+=S77w_w_
+c(S=1u1wu_w(_c
+iSB=_Biwcw_(B
+S77=B__wwcS(
+T_=Twcw_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6c:n..:4:.nc:R4nI	FsR4w7uXd7RsPCHoDFR_wwcSU
+7_=7wcw_U1
+Suu=1__wwcSU
+BBi=iw_w_
+cUS=B7Bw7_wU_c
+=STTw_w_;cU
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:dg4n.:d4g:nFRIsw	R7d4u7PXRCDsHFwoRwg_c
+=S77w_w_
+cgS=1u1wu_wg_c
+iSB=_Biwcw_gB
+S77=B__wwcSg
+T_=Twcw_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6d:nn.:4:nnd:R4nI	FsR4w7uXd7RsPCHoDFR_ww6Sj
+7_=7w6w_j1
+Suu=1__ww6Sj
+BBi=iw_w_
+6jS=B7Bw7_wj_6
+=STTw_w_;6j
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:dd4n.:d4d:nFRIsw	R7d4u7PXRCDsHFwoRw4_6
+=S77w_w_
+64S=1u1wu_w4_6
+iSB=_Biw6w_4B
+S77=B__ww6S4
+T_=Tw6w_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6d:nj.:4:jnd:R4nI	FsR4w7uXd7RsPCHoDFR_ww6S.
+7_=7w6w_.1
+Suu=1__ww6S.
+BBi=iw_w_
+6.S=B7Bw7_w._6
+=STTw_w_;6.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:.n4n.:.4n:nFRIsw	R7d4u7PXRCDsHFwoRwd_6
+=S77w_w_
+6dS=1u1wu_wd_6
+iSB=_Biw6w_dB
+S77=B__ww6Sd
+T_=Tw6w_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6.:n..:4:.n.:R4nI	FsR4w7uXd7RsPCHoDFR_ww6Sc
+7_=7w6w_c1
+Suu=1__ww6Sc
+BBi=iw_w_
+6cS=B7Bw7_wc_6
+=STTw_w_;6c
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:4U4n.:44U:nFRIsw	R7d4u7PXRCDsHFwoRw6_6
+=S77w_w_
+66S=1u1wu_w6_6
+iSB=_Biw6w_6B
+S77=B__ww6S6
+T_=Tw6w_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@64:nc.:4:cn4:R4nI	FsR4w7uXd7RsPCHoDFR_ww6Sn
+7_=7w6w_n1
+Suu=1__ww6Sn
+BBi=iw_w_
+6nS=B7Bw7_wn_6
+=STTw_w_;6n
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:4j4n.:44j:nFRIsw	R7d4u7PXRCDsHFwoRw(_6
+=S77w_w_
+6(S=1u1wu_w(_6
+iSB=_Biw6w_(B
+S77=B__ww6S(
+T_=Tw6w_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6j:nn.:4:nnj:R4nI	FsR4w7uXd7RsPCHoDFR_ww6SU
+7_=7w6w_U1
+Suu=1__ww6SU
+BBi=iw_w_
+6US=B7Bw7_wU_6
+=STTw_w_;6U
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46n:j.4n.:j4.:nFRIsw	R7d4u7PXRCDsHFwoRwg_6
+=S77w_w_
+6gS=1u1wu_wg_6
+iSB=_Biw6w_gB
+S77=B__ww6Sg
+T_=Tw6w_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6g:6U.:4:U6g:R4nI	FsR4w7uXd7RsPCHoDFR_wwnSj
+7_=7wnw_j1
+Suu=1__wwnSj
+BBi=iw_w_
+njS=B7Bw7_wj_n
+=STTw_w_;nj
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:gc46.:g4c:nFRIsw	R7d4u7PXRCDsHFwoRw4_n
+=S77w_w_
+n4S=1u1wu_w4_n
+iSB=_Biwnw_4B
+S77=B__wwnS4
+T_=Twnw_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6g:6j.:4:j6g:R4nI	FsR4w7uXd7RsPCHoDFR_wwnS.
+7_=7wnw_.1
+Suu=1__wwnS.
+BBi=iw_w_
+n.S=B7Bw7_w._n
+=STTw_w_;n.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:Un46.:U4n:nFRIsw	R7d4u7PXRCDsHFwoRwd_n
+=S77w_w_
+ndS=1u1wu_wd_n
+iSB=_Biwnw_dB
+S77=B__wwnSd
+T_=Twnw_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6U:6..:4:.6U:R4nI	FsR4w7uXd7RsPCHoDFR_wwnSc
+7_=7wnw_c1
+Suu=1__wwnSc
+BBi=iw_w_
+ncS=B7Bw7_wc_n
+=STTw_w_;nc
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:(U46.:(4U:nFRIsw	R7d4u7PXRCDsHFwoRw6_n
+=S77w_w_
+n6S=1u1wu_w6_n
+iSB=_Biwnw_6B
+S77=B__wwnS6
+T_=Twnw_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6(:6c.:4:c6(:R4nI	FsR4w7uXd7RsPCHoDFR_wwnSn
+7_=7wnw_n1
+Suu=1__wwnSn
+BBi=iw_w_
+nnS=B7Bw7_wn_n
+=STTw_w_;nn
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:(j46.:(4j:nFRIsw	R7d4u7PXRCDsHFwoRw(_n
+=S77w_w_
+n(S=1u1wu_w(_n
+iSB=_Biwnw_(B
+S77=B__wwnS(
+T_=Twnw_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6n:6n.:4:n6n:R4nI	FsR4w7uXd7RsPCHoDFR_wwnSU
+7_=7wnw_U1
+Suu=1__wwnSU
+BBi=iw_w_
+nUS=B7Bw7_wU_n
+=STTw_w_;nU
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:n.46.:n4.:nFRIsw	R7d4u7PXRCDsHFwoRwg_n
+=S77w_w_
+ngS=1u1wu_wg_n
+iSB=_Biwnw_gB
+S77=B__wwnSg
+T_=Twnw_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@66:6U.:4:U66:R4nI	FsR4w7uXd7RsPCHoDFR_ww(Sj
+7_=7w(w_j1
+Suu=1__ww(Sj
+BBi=iw_w_
+(jS=B7Bw7_wj_(
+=STTw_w_;(j
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:6c46.:64c:nFRIsw	R7d4uAPXRCDsHFwoRw4_(
+=S77w_w_
+(4S=1u1wu_w4_(
+iSB=_Biw(w_4u
+S77=u__ww(S4
+T_=Tw(w_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@66:6j.:4:j66:R4nI	FsR4w7uXd7RsPCHoDFR_ww(S.
+7_=7w(w_.1
+Suu=1__ww(S.
+BBi=iw_w_
+(.S=B7Bw7_w._(
+=STTw_w_;(.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:cn46.:c4n:nFRIsw	R7d4u7PXRCDsHFwoRwd_(
+=S77w_w_
+(dS=1u1wu_wd_(
+iSB=_Biw(w_dB
+S77=B__ww(Sd
+T_=Tw(w_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6c:6..:4:.6c:R4nI	FsR4w7uXd7RsPCHoDFR_ww(Sc
+7_=7w(w_c1
+Suu=1__ww(Sc
+BBi=iw_w_
+(cS=B7Bw7_wc_(
+=STTw_w_;(c
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:dU46.:d4U:nFRIsw	R7d4u7PXRCDsHFwoRw6_(
+=S77w_w_
+(6S=1u1wu_w6_(
+iSB=_Biw(w_6B
+S77=B__ww(S6
+T_=Tw(w_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6d:6c.:4:c6d:R4nI	FsR4w7uXd7RsPCHoDFR_ww(Sn
+7_=7w(w_n1
+Suu=1__ww(Sn
+BBi=iw_w_
+(nS=B7Bw7_wn_(
+=STTw_w_;(n
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:dj46.:d4j:nFRIsw	R7d4u7PXRCDsHFwoRw(_(
+=S77w_w_
+((S=1u1wu_w(_(
+iSB=_Biw(w_(B
+S77=B__ww(S(
+T_=Tw(w_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6.:6n.:4:n6.:R4nI	FsR4w7uXd7RsPCHoDFR_ww(SU
+7_=7w(w_U1
+Suu=1__ww(SU
+BBi=iw_w_
+(US=B7Bw7_wU_(
+=STTw_w_;(U
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:..46.:.4.:nFRIsw	R7d4u7PXRCDsHFwoRwg_(
+=S77w_w_
+(gS=1u1wu_wg_(
+iSB=_Biw(w_gB
+S77=B__ww(Sg
+T_=Tw(w_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@64:6U.:4:U64:R4nI	FsR4w7uXd7RsPCHoDFR_wwUSj
+7_=7wUw_j1
+Suu=1__wwUSj
+BBi=iw_w_
+UjS=B7Bw7_wj_U
+=STTw_w_;Uj
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:4c46.:44c:nFRIsw	R7d4u7PXRCDsHFwoRw4_U
+=S77w_w_
+U4S=1u1wu_w4_U
+iSB=_BiwUw_4B
+S77=B__wwUS4
+T_=TwUw_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@64:6j.:4:j64:R4nI	FsR4w7uXd7RsPCHoDFR_wwUS.
+7_=7wUw_.1
+Suu=1__wwUS.
+BBi=iw_w_
+U.S=B7Bw7_w._U
+=STTw_w_;U.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:466:jn46.:j4n:nFRIsw	R7d4u7PXRCDsHFwoRwd_U
+=S77w_w_
+UdS=1u1wu_wd_U
+iSB=_BiwUw_dB
+S77=B__wwUSd
+T_=TwUw_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6j:6..:4:.6j:R4nI	FsR4w7uXd7RsPCHoDFR_wwUSc
+7_=7wUw_c1
+Suu=1__wwUSc
+BBi=iw_w_
+UcS=B7Bw7_wc_U
+=STTw_w_;Uc
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:gU4c.:g4U:nFRIsw	R7d4u7PXRCDsHFwoRw6_U
+=S77w_w_
+U6S=1u1wu_w6_U
+iSB=_BiwUw_6B
+S77=B__wwUS6
+T_=TwUw_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6g:cc.:4:ccg:R4nI	FsR4w7uXd7RsPCHoDFR_wwUSn
+7_=7wUw_n1
+Suu=1__wwUSn
+BBi=iw_w_
+UnS=B7Bw7_wn_U
+=STTw_w_;Un
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:gj4c.:g4j:nFRIsw	R7d4u7PXRCDsHFwoRw(_U
+=S77w_w_
+U(S=1u1wu_w(_U
+iSB=_BiwUw_(B
+S77=B__wwUS(
+T_=TwUw_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6U:cn.:4:ncU:R4nI	FsR4w7uXd7RsPCHoDFR_wwUSU
+7_=7wUw_U1
+Suu=1__wwUSU
+BBi=iw_w_
+UUS=B7Bw7_wU_U
+=STTw_w_;UU
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:U.4c.:U4.:nFRIsw	R7d4u7PXRCDsHFwoRwg_U
+=S77w_w_
+UgS=1u1wu_wg_U
+iSB=_BiwUw_gB
+S77=B__wwUSg
+T_=TwUw_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6(:cU.:4:Uc(:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSj
+7_=7wgw_j1
+Suu=1__wwgSj
+BBi=iw_w_
+gjS=B7Bw7_wj_g
+=STTw_w_;gj
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:(c4c.:(4c:nFRIsw	R7d4u7PXRCDsHFwoRw4_g
+=S77w_w_
+g4S=1u1wu_w4_g
+iSB=_Biwgw_4B
+S77=B__wwgS4
+T_=Twgw_4N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6(:cj.:4:jc(:R4nI	FsR4w7uXd7RsPCHoDFR_wwgS.
+7_=7wgw_.1
+Suu=1__wwgS.
+BBi=iw_w_
+g.S=B7Bw7_w._g
+=STTw_w_;g.
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:nn4c.:n4n:nFRIsw	R7d4u7PXRCDsHFwoRwd_g
+=S77w_w_
+gdS=1u1wu_wd_g
+iSB=_Biwgw_dB
+S77=B__wwgSd
+T_=Twgw_dN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6n:c..:4:.cn:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSc
+7_=7wgw_c1
+Suu=1__wwgSc
+BBi=iw_w_
+gcS=B7Bw7_wc_g
+=STTw_w_;gc
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:6U4c.:64U:nFRIsw	R7d4u7PXRCDsHFwoRw6_g
+=S77w_w_
+g6S=1u1wu_w6_g
+iSB=_Biwgw_6B
+S77=B__wwgS6
+T_=Twgw_6N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@66:cc.:4:cc6:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSn
+7_=7wgw_n1
+Suu=1__wwgSn
+BBi=iw_w_
+gnS=B7Bw7_wn_g
+=STTw_w_;gn
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:6j4c.:64j:nFRIsw	R7d4u7PXRCDsHFwoRw(_g
+=S77w_w_
+g(S=1u1wu_w(_g
+iSB=_Biwgw_(B
+S77=B__wwgS(
+T_=Twgw_(N;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6c:cn.:4:ncc:R4nI	FsR4w7uXd7RsPCHoDFR_wwgSU
+7_=7wgw_U1
+Suu=1__wwgSU
+BBi=iw_w_
+gUS=B7Bw7_wU_g
+=STTw_w_;gU
+RNH#_$MMsFbkRMC4N;
+H1Rt) R"hpqA ;7"
+@sR@:46c:c.4c.:c4.:nFRIsw	R7d4u7PXRCDsHFwoRwg_g
+=S77w_w_
+ggS=1u1wu_wg_g
+iSB=_Biwgw_gB
+S77=B__wwgSg
+T_=Twgw_gN;
+H$R#MF_MbMskC;R4
+RNHtR1)"q hA7p "s;
+R4@@6d:cU.:4:Ucd:R4(I	FsR4w7uXd7RsPCHoDFR_ww4
+jjS77=__ww4
+jjS=1u1wu_wj_4jB
+Sii=B__ww4
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+RNH#_$MMsFbkRMC4N;
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+s@6@4:ndj::4dd:jn4IgRFRs	)4mvnqX4RsPCHoDFRapzcd_4
+7Sqd7=qdz_pa4c_dq
+S7q.=7p._z_ac4Sd
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+H$R#MF_MbMskC;R4
+RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j
+";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n
+";N3HR#_$MNV00FNsl0HR"MPH0NXD="s;
+R4@@6j:d.d:4:.dj:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_cq
+S7qd=7pd_z_ac4Sc
+q=7.q_7.pcza_
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+Sm7j=mpj_z_ac4
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+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@4.6:g4U:dg:.Ug:4RsIF	mR)vX4n4PqRCDsHFpoRz_ac4S6
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+46S.q7=.q7_apzc6_4
+7Sq47=q4z_pa4c_6q
+S7qj=7pj_z_ac4S6
+7=mj7_mjpcza_;46
+RNH#_$MMsFbkRMC4N;
+HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H
+NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H
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+@sR@:46.:gc4.d:g4c:gFRIs)	Rmnv4XR4qPHCsDRFopcza_
+4nSdq7=dq7_apzcn_4
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+S7q4=7p4_z_ac4Sn
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+4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@6@4:j.g::4d.:gj4IgRFRs	)4mvnqX4RsPCHoDFRapzc(_4
+7Sqd7=qdz_pa4c_(q
+S7q.=7p._z_ac4S(
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+mS7jm=7jz_pa4c_(N;
+H$R#MF_MbMskC;R4
+RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j
+";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n
+";N3HR#_$MNV00FNsl0HR"MPH0NXD="s;
+R4@@6U:.nd:4:n.U:R4gI	FsRv)m44nXqCRPsFHDozRpa4c_Uq
+S7qd=7pd_z_ac4SU
+q=7.q_7.pcza_
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+U;N#HR$MM_FkbsM4CR;H
+NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j"
+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@4.6:U4.:dU:..g:4RsIF	mR)vX4n4PqRCDsHFpoRz_ac4Sg
+q=7dq_7dpcza_
+4gS.q7=.q7_apzcg_4
+7Sq47=q4z_pa4c_gq
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+7=mj7_mjpcza_;4g
+RNH#_$MMsFbkRMC4N;
+HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H
+NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H
+NR$3#M0_N0sVFlRN0"HHM0DPN=;X"
+@sR@:46.:(U4.d:(4U:gFRIs)	Rmnv4XR4qPHCsDRFopcza_
+.jSdq7=dq7_apzcj_.
+7Sq.7=q.z_pa.c_jq
+S7q4=7p4_z_ac.Sj
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+.jSj7m=j7m_apzcj_.;H
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+4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N;
+H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N;
+H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R
+s@6@4:c.(::4d.:(c4IgRFRs	)4mvnqX4RsPCHoDFRapzc4_.
+7Sqd7=qdz_pa.c_4q
+S7q.=7p._z_ac.S4
+q=74q_74pcza_
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+RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j
+";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n
+";N3HR#_$MNV00FNsl0HR"MPH0NXD="s;
+R4@@6(:.jd:4:j.(:R4gI	FsRv)m44nXqCRPsFHDozRpa.c_.q
+S7qd=7pd_z_ac.S.
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+Sm7j=mpj_z_ac.
+.;N#HR$MM_FkbsM4CR;H
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+RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n"
+RNH3M#$_0N0VlFsN"0RH0MHP=NDX
+";s@R@4.6:n4n:dn:.ng:4RsIF	mR)vX4n4PqRCDsHFpoRz_ac.Sd
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+RNH#_$MMsFbkRMC4N;
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+@sR@:46.:ndgn:.d6:4RsIF	mRX)P.RCDsHFXoRm_).0Sj
+q_=qX.m)_
+0jSAA=_)Xm.j_0
+=SZZm_X)0._jN;
+H$R#MF_MbMskC;R4
+@sR@:46.:n4gn:.46:4RsIF	mRX)P.RCDsHFXoRm_).0S4
+q_=qX.m)_
+04SAA=_)Xm.4_0
+=SZZm_X)0._4N;
+H$R#MF_MbMskC;R4
+@sR@:46.:6gg6:.g6:4RsIF	mRX)P.RCDsHFXoRm_).0S.
+q_=qX.m)_
+0.SAA=_)Xm.._0
+=SZZm_X)0._.N;
+H$R#MF_MbMskC;R4
+@sR@:46.:6(g6:.(6:4RsIF	mRX)P.RCDsHFXoRm_).0Sd
+q_=qX.m)_
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+=SZZm_X)0._dN;
+H$R#MF_MbMskC;R4
+@sR@:46.:66g6:.66:4RsIF	mRX)P.RCDsHFXoRm_).0Sc
+q_=qX.m)_
+0cSAA=_)Xm.c_0
+=SZZm_X)0._cN;
+H$R#MF_MbMskC;R4
+@sR@:46.:6dg6:.d6:4RsIF	mRX)P.RCDsHFXoRm_).0S6
+q_=qX.m)_
+06SAA=_)Xm.6_0
+=SZZm_X)0._6N;
+H$R#MF_MbMskC;R4
+@sR@:46.:64g6:.46:4RsIF	mRX)P.RCDsHFXoRm_).0Sn
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+=SZZm_X)0._nN;
+H$R#MF_MbMskC;R4
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+=SZZm_X)0._(N;
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+@sR@:46.:c(gc:.(6:4RsIF	mRX)P.RCDsHFXoRm_).0SU
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+=SZZm_X)0._UN;
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+=SZZm_X)0._gN;
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+4;s@R@4.6:.gd::d..:R4nI	FsR7qh.CRPsFHDohRq70._4Sg
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+4;s@R@4.6:.U4::4..:R4.I	FsReQhRsPCHoDFReQh_S4
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+4;s@R@4.6:4gg::g.4:R4nI	FsR7qh.CRPsFHDohRq70._.Sj
+q_=qq.h7_j0.
+=SAAh_q70._.Sj
+Z_=Zq.h7_j0.;H
+NRM#$_bMFsCkMR
+4;y--------------------------------
+--@
+ 
+
+ftell;
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+
+
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+
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+-y---------------------------------
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+@ 
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+
+
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+@FR@:4n.:6.4.d:6d.:j Rw q_7aWq_) Qa_amzR
+;
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+
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+@FR@:4n.:c6gc:.6g:4RDsCCCN#_0FkRy;
+---------------------------------@-
+ 
+
+
+
+ftell;
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+
+
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+
+
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diff --git a/impl1/synwork/layer1.fdep b/impl1/synwork/layer1.fdep
new file mode 100644
index 0000000..29f3a90
--- /dev/null
+++ b/impl1/synwork/layer1.fdep
@@ -0,0 +1,53 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|work.Uart_top|-mpparams|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_mh_params|-layerid|1|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-distcompmode|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl
+1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl
+2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl
+3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl
+4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 0 1 2 3 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work intface intface_a 0
+module work intface 0
+arch work modem modem_a 1
+module work modem 1
+arch work rxcver rxcver_a 2
+module work rxcver 2
+arch work txmitt txmitt_a 3
+module work txmitt 3
+arch work uart_top uart_top_a 4
+module work uart_top 4
+
+# Unbound Instances to File Association
+
+
+# Configuration files used
diff --git a/impl1/synwork/layer1.fdeporig b/impl1/synwork/layer1.fdeporig
new file mode 100644
index 0000000..8082cb6
--- /dev/null
+++ b/impl1/synwork/layer1.fdeporig
@@ -0,0 +1,50 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|work.Uart_top|-mpparams|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_mh_params|-layerid|1|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-distcompmode|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl
+1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl
+2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl
+3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl
+4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 0 1 2 3 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work intface intface_a 0
+module work intface 0
+arch work modem modem_a 1
+module work modem 1
+arch work rxcver rxcver_a 2
+module work rxcver 2
+arch work txmitt txmitt_a 3
+module work txmitt 3
+arch work uart_top uart_top_a 4
+module work uart_top 4
+
+# Unbound Instances to File Association
diff --git a/impl1/synwork/libfileorder.txt b/impl1/synwork/libfileorder.txt
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/modulechange.db b/impl1/synwork/modulechange.db
new file mode 100644
index 0000000..b76d9ac
Binary files /dev/null and b/impl1/synwork/modulechange.db differ
diff --git a/impl1/synwork/s1_impl1_comp.fdep b/impl1/synwork/s1_impl1_comp.fdep
new file mode 100644
index 0000000..401df9d
--- /dev/null
+++ b/impl1/synwork/s1_impl1_comp.fdep
@@ -0,0 +1,79 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946
+0			"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" verilog
+1			"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" verilog
+2			"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" verilog
+3			"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" verilog
+4			"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" verilog
+5			"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" verilog
+6			"/home/hadaq/mmichalek/lattice/simplified/modules2.v" verilog
+7			"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" verilog
+8			"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" verilog
+9			"/home/hadaq/mmichalek/lattice/simplified/top2.v" verilog
+10			"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" verilog
+11			"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+1 -1
+2 -1
+3 -1
+4 -1
+5 -1
+6 2
+7 8
+8 -1
+9 6 0 10 7
+10 11
+11 6
+#Dependency Lists(Users Of)
+0 9
+1 -1
+2 6
+3 -1
+4 -1
+5 -1
+6 11 9
+7 9
+8 7
+9 -1
+10 9
+11 10
+#Design Unit to File Association
+module work hades_tdc_channel_raw_out 11
+module work hades_LVL1_raw_out 11
+module work top_tf 9
+module work trb_adapter 9
+module work hades_tdc_bundle 10
+module work fifo_colector 7
+module work fifo40_dc 8
+module work tdc4ddr 6
+module work tdc_channel_fifo_out 6
+module work output_decoder8 6
+module work tdc4ddr_short 6
+module work trig_inv 6
+module work pll_random 5
+module work pll8 4
+module work UART_VerilogWrapper_TOP 3
+module work fifo32dc 2
+module work pll1 1
+module work pll0 0
diff --git a/impl1/synwork/s1_impl1_comp.linkerlog b/impl1/synwork/s1_impl1_comp.linkerlog
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/s1_impl1_comp.srs b/impl1/synwork/s1_impl1_comp.srs
new file mode 100644
index 0000000..6cc1a97
Binary files /dev/null and b/impl1/synwork/s1_impl1_comp.srs differ
diff --git a/impl1/synwork/s1_impl1_hdl_.fdeporig b/impl1/synwork/s1_impl1_hdl_.fdeporig
new file mode 100644
index 0000000..e3d15b8
--- /dev/null
+++ b/impl1/synwork/s1_impl1_hdl_.fdeporig
@@ -0,0 +1,66 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-top|top_tf|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-fileorder|/home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/hdlorder.tcl"
+#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268
+#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":1614208538
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd":1614208577
+#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd":1614208577
+0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl
+1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl
+2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl
+3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl
+4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl
+5 "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd" vhdl
+6 "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd" vhdl
+7 "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 0 1 2 3 
+5 7 6 
+6 -1
+7 -1
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+5 -1
+6 5 
+7 5 
+
+# Design Unit to File Association
+arch work intface intface_a 0
+module work intface 0
+arch work modem modem_a 1
+module work modem 1
+arch work rxcver rxcver_a 2
+module work rxcver 2
+arch work txmitt txmitt_a 3
+module work txmitt 3
+arch work uart_top uart_top_a 4
+module work uart_top 4
+arch work trb5_tb behavioral 5
+module work trb5_tb 5
+arch work endp_dummy behavioral 6
+module work endp_dummy 6
+arch work endp_handler behavioral 7
+module work endp_handler 7
diff --git a/impl1/synwork/s1_impl1_m.srm b/impl1/synwork/s1_impl1_m.srm
new file mode 100644
index 0000000..febdd83
Binary files /dev/null and b/impl1/synwork/s1_impl1_m.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/1.srm b/impl1/synwork/s1_impl1_m_srm/1.srm
new file mode 100644
index 0000000..21e8439
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/1.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/2.srm b/impl1/synwork/s1_impl1_m_srm/2.srm
new file mode 100644
index 0000000..1d388e7
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/2.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/3.srm b/impl1/synwork/s1_impl1_m_srm/3.srm
new file mode 100644
index 0000000..83fc1c4
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/3.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/4.srm b/impl1/synwork/s1_impl1_m_srm/4.srm
new file mode 100644
index 0000000..915c152
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/4.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/5.srm b/impl1/synwork/s1_impl1_m_srm/5.srm
new file mode 100644
index 0000000..d0c5f4f
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/5.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/6.srm b/impl1/synwork/s1_impl1_m_srm/6.srm
new file mode 100644
index 0000000..736bbf6
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/6.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/7.srm b/impl1/synwork/s1_impl1_m_srm/7.srm
new file mode 100644
index 0000000..df2dbbc
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/7.srm differ
diff --git a/impl1/synwork/s1_impl1_m_srm/fileinfo.srm b/impl1/synwork/s1_impl1_m_srm/fileinfo.srm
new file mode 100644
index 0000000..26f612d
Binary files /dev/null and b/impl1/synwork/s1_impl1_m_srm/fileinfo.srm differ
diff --git a/impl1/synwork/s1_impl1_mult.gcr b/impl1/synwork/s1_impl1_mult.gcr
new file mode 100644
index 0000000..b388f41
--- /dev/null
+++ b/impl1/synwork/s1_impl1_mult.gcr
@@ -0,0 +1,52 @@
+i pll0inst.CLKOS3_i
+m 0 0
+u 481 787
+n ckid0_0 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0.CLKW} Black box on clock path
+p {t:pll0inst.PLLInst_0.CLKOS3}{t:pll0inst.CLKOS3_inferred_clock.I[0]}{t:pll0inst.CLKOS3_inferred_clock.OUT[0]}{p:pll0inst.CLKOS3}{t:pll0inst.CLKOS3}{t:reset_dl[2:1].C}
+e ckid0_1 {t:reset_dl[2:1].C} dff
+d ckid0_0,ckid0_1 {t:pll0inst.PLLInst_0.CLKOS3} EHXPLLL Black box on clock path
+i pll0inst.CLKOS2_i
+m 0 0
+u 36 36
+n ckid0_2 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6].C} Black box on clock path
+p {t:pll0inst.PLLInst_0.CLKOS2}{t:pll0inst.CLKOS2_inferred_clock.I[0]}{t:pll0inst.CLKOS2_inferred_clock.OUT[0]}{p:pll0inst.CLKOS2}{t:pll0inst.CLKOS2}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[2]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[2]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[2]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[2]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2].C}
+e ckid0_3 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2].C} dff
+d ckid0_2,ckid0_3 {t:pll0inst.PLLInst_0.CLKOS2} EHXPLLL Black box on clock path
+i pll0inst.CLKOS_i
+m 0 0
+u 36 36
+n ckid0_4 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5].C} Black box on clock path
+p {t:pll0inst.PLLInst_0.CLKOS}{t:pll0inst.CLKOS_inferred_clock.I[0]}{t:pll0inst.CLKOS_inferred_clock.OUT[0]}{p:pll0inst.CLKOS}{t:pll0inst.CLKOS}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[1]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[1]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[1]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[1]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1].C}
+e ckid0_5 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1].C} dff
+d ckid0_4,ckid0_5 {t:pll0inst.PLLInst_0.CLKOS} EHXPLLL Black box on clock path
+i pll0inst.CLKOP_i
+m 0 0
+u 36 36
+n ckid0_6 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4].C} Black box on clock path
+p {t:pll0inst.PLLInst_0.CLKOP}{t:pll0inst.CLKOP_inferred_clock.I[0]}{t:pll0inst.CLKOP_inferred_clock.OUT[0]}{p:pll0inst.CLKOP}{t:pll0inst.CLKOP}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[0]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.pll_clks[0]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[0]}{p:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.clks[0]}{t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0].C}
+e ckid0_7 {t:genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0].C} dff
+d ckid0_6,ckid0_7 {t:pll0inst.PLLInst_0.CLKOP} EHXPLLL Black box on clock path
+i rd_clk
+m 0 0
+u 61 64
+p {p:rd_clk}{t:trb_adapter_inst.clk}{p:trb_adapter_inst.clk}{t:trb_adapter_inst.FEE_DATA_WRITE_OUT.C}
+e ckid0_8 {t:trb_adapter_inst.FEE_DATA_WRITE_OUT.C} sdffr
+c ckid0_8 {p:rd_clk} Unconstrained_port Inferred clock from port
+i pll0inst.REFCLK
+m 0 0
+u 0 0
+d ckid0_9 {t:pll0inst.PLLInst_0.REFCLK} EHXPLLL Black box on clock path
+i pll0inst.LOCK
+m 0 0
+u 0 0
+d ckid0_10 {t:pll0inst.PLLInst_0.LOCK} EHXPLLL Black box on clock path
+i pll0inst.un1_PLLInst_0
+m 0 0
+u 0 0
+d ckid0_11 {t:pll0inst.PLLInst_0.CLKINTFB} EHXPLLL Black box on clock path
+i pll0inst.un1_PLLInst_0_1
+m 0 0
+u 0 0
+d ckid0_12 {t:pll0inst.PLLInst_0.INTLOCK} EHXPLLL Black box on clock path
+l 0 0 0 0 0
+r 0 0 0 0 0 0 0 0
diff --git a/impl1/synwork/s1_impl1_mult.srs b/impl1/synwork/s1_impl1_mult.srs
new file mode 100644
index 0000000..2946e25
Binary files /dev/null and b/impl1/synwork/s1_impl1_mult.srs differ
diff --git a/impl1/synwork/s1_impl1_mult_srs/1.srs b/impl1/synwork/s1_impl1_mult_srs/1.srs
new file mode 100644
index 0000000..9076cb3
Binary files /dev/null and b/impl1/synwork/s1_impl1_mult_srs/1.srs differ
diff --git a/impl1/synwork/s1_impl1_mult_srs/fileinfo.srs b/impl1/synwork/s1_impl1_mult_srs/fileinfo.srs
new file mode 100644
index 0000000..84beda5
Binary files /dev/null and b/impl1/synwork/s1_impl1_mult_srs/fileinfo.srs differ
diff --git a/impl1/synwork/s1_impl1_mult_srs/skeleton.srs b/impl1/synwork/s1_impl1_mult_srs/skeleton.srs
new file mode 100644
index 0000000..48f3c67
Binary files /dev/null and b/impl1/synwork/s1_impl1_mult_srs/skeleton.srs differ
diff --git a/impl1/synwork/s1_impl1_prem.fse b/impl1/synwork/s1_impl1_prem.fse
new file mode 100644
index 0000000..e69de29
diff --git a/impl1/synwork/s1_impl1_prem.srd b/impl1/synwork/s1_impl1_prem.srd
new file mode 100644
index 0000000..7c22946
Binary files /dev/null and b/impl1/synwork/s1_impl1_prem.srd differ
diff --git a/impl1/synwork/s1_impl1_prem.srm b/impl1/synwork/s1_impl1_prem.srm
new file mode 100644
index 0000000..441a82c
Binary files /dev/null and b/impl1/synwork/s1_impl1_prem.srm differ
diff --git a/impl1/synwork/s1_impl1_prem_srm/1.srm b/impl1/synwork/s1_impl1_prem_srm/1.srm
new file mode 100644
index 0000000..5639724
Binary files /dev/null and b/impl1/synwork/s1_impl1_prem_srm/1.srm differ
diff --git a/impl1/synwork/s1_impl1_prem_srm/fileinfo.srm b/impl1/synwork/s1_impl1_prem_srm/fileinfo.srm
new file mode 100644
index 0000000..fd5f9a3
Binary files /dev/null and b/impl1/synwork/s1_impl1_prem_srm/fileinfo.srm differ
diff --git a/impl1/synwork/s1_impl1_prem_srm/skeleton.srm b/impl1/synwork/s1_impl1_prem_srm/skeleton.srm
new file mode 100644
index 0000000..10b40ab
Binary files /dev/null and b/impl1/synwork/s1_impl1_prem_srm/skeleton.srm differ
diff --git a/impl1/top_0__compress_ram_rw_port.v.ve b/impl1/top_0__compress_ram_rw_port.v.ve
new file mode 100644
index 0000000..459712b
--- /dev/null
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diff --git a/impl1/top_10__aram.v.ve b/impl1/top_10__aram.v.ve
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--- /dev/null
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diff --git a/impl1/top_11__pc_0.v.ve b/impl1/top_11__pc_0.v.ve
new file mode 100644
index 0000000..fe95662
--- /dev/null
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diff --git a/impl1/top_12__cse.v.ve b/impl1/top_12__cse.v.ve
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diff --git a/impl1/top_13__flatten_1.v.ve b/impl1/top_13__flatten_1.v.ve
new file mode 100644
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diff --git a/impl1/top_14__sel.v.ve b/impl1/top_14__sel.v.ve
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diff --git a/impl1/top_15__pad.v.ve b/impl1/top_15__pad.v.ve
new file mode 100644
index 0000000..c513a23
--- /dev/null
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diff --git a/impl1/top_16__pc_1.v.ve b/impl1/top_16__pc_1.v.ve
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diff --git a/impl1/top_17__b_apmxo.v.ve b/impl1/top_17__b_apmxo.v.ve
new file mode 100644
index 0000000..471595e
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diff --git a/impl1/top_18__apmxo.v.ve b/impl1/top_18__apmxo.v.ve
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diff --git a/impl1/top_19__flatten_2.v.ve b/impl1/top_19__flatten_2.v.ve
new file mode 100644
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diff --git a/impl1/top_20__pc_2.v.ve b/impl1/top_20__pc_2.v.ve
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diff --git a/impl1/top_21__pc_3.v.ve b/impl1/top_21__pc_3.v.ve
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diff --git a/impl1/top_25__ena_b.v.ve b/impl1/top_25__ena_b.v.ve
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index 0000000..0f58813
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diff --git a/impl1/top_26__ena_a.v.ve b/impl1/top_26__ena_a.v.ve
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diff --git a/impl1/top_27__opt6_b.v.ve b/impl1/top_27__opt6_b.v.ve
new file mode 100644
index 0000000..0f58813
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diff --git a/impl1/top_28__opt6_a.v.ve b/impl1/top_28__opt6_a.v.ve
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diff --git a/impl1/top_29__pc_5.v.ve b/impl1/top_29__pc_5.v.ve
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diff --git a/impl1/top_2__cse.v.ve b/impl1/top_2__cse.v.ve
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diff --git a/impl1/top_31__bfact_0.v.ve b/impl1/top_31__bfact_0.v.ve
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diff --git a/impl1/top_32__afact_0.v.ve b/impl1/top_32__afact_0.v.ve
new file mode 100644
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diff --git a/impl1/top_35__amxo.v.ve b/impl1/top_35__amxo.v.ve
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diff --git a/impl1/top_36__bfact_1.v.ve b/impl1/top_36__bfact_1.v.ve
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diff --git a/impl1/top_37__afact_1.v.ve b/impl1/top_37__afact_1.v.ve
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diff --git a/impl1/top_38__beforeeq.v.ve b/impl1/top_38__beforeeq.v.ve
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diff --git a/impl1/top_39__aftereq.v.ve b/impl1/top_39__aftereq.v.ve
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diff --git a/impl1/top_3__gc_opt.v.ve b/impl1/top_3__gc_opt.v.ve
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diff --git a/impl1/top_40__beforeaddmap.v.ve b/impl1/top_40__beforeaddmap.v.ve
new file mode 100644
index 0000000..8bf24df
--- /dev/null
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diff --git a/impl1/top_41__afteraddmap.v.ve b/impl1/top_41__afteraddmap.v.ve
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diff --git a/impl1/top_43__bCollapse_1.v.ve b/impl1/top_43__bCollapse_1.v.ve
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diff --git a/impl1/top_47__btmc.v.ve b/impl1/top_47__btmc.v.ve
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diff --git a/impl1/top_48__atmc.v.ve b/impl1/top_48__atmc.v.ve
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diff --git a/impl1/top_49__pfumx.v.ve b/impl1/top_49__pfumx.v.ve
new file mode 100644
index 0000000..675d447
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diff --git a/impl1/top_4_before_Unsharing.v.ve b/impl1/top_4_before_Unsharing.v.ve
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diff --git a/impl1/top_50__l6mx.v.ve b/impl1/top_50__l6mx.v.ve
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diff --git a/impl1/top_51__cg.v.ve b/impl1/top_51__cg.v.ve
new file mode 100644
index 0000000..675d447
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diff --git a/impl1/top_52__alat.v.ve b/impl1/top_52__alat.v.ve
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diff --git a/impl1/top_53__bmap.v.ve b/impl1/top_53__bmap.v.ve
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diff --git a/impl1/top_54__amap.v.ve b/impl1/top_54__amap.v.ve
new file mode 100644
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diff --git a/impl1/top_55__lutclps_b.v.ve b/impl1/top_55__lutclps_b.v.ve
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diff --git a/impl1/top_56__lutclps_a.v.ve b/impl1/top_56__lutclps_a.v.ve
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diff --git a/impl1/top_57__pc_10.v.ve b/impl1/top_57__pc_10.v.ve
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diff --git a/impl1/top_5_after_Unsharing.v.ve b/impl1/top_5_after_Unsharing.v.ve
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diff --git a/impl1/top_6__rtl_opt.v.ve b/impl1/top_6__rtl_opt.v.ve
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diff --git a/impl1/top_7__cse.v.ve b/impl1/top_7__cse.v.ve
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diff --git a/impl1/top_8__after_opt.v.ve b/impl1/top_8__after_opt.v.ve
new file mode 100644
index 0000000..fe95662
--- /dev/null
+++ b/impl1/top_8__after_opt.v.ve
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diff --git a/impl1/top_9__bram.v.ve b/impl1/top_9__bram.v.ve
new file mode 100644
index 0000000..fe95662
--- /dev/null
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diff --git a/impl1/top_drc.log b/impl1/top_drc.log
new file mode 100644
index 0000000..f196a3d
--- /dev/null
+++ b/impl1/top_drc.log
@@ -0,0 +1,18 @@
+Results of NGD DRC are available in top_drc.log.
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+WARNING - synthesis: logical net 'GND_net' has no load.
+WARNING - synthesis: DRC complete with 1 warnings.
+
+Design Results:
+     12 blocks expanded
+completed the first expansion
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file s1_impl1.ngd.
diff --git a/impl1/top_gatelevel.v.ve b/impl1/top_gatelevel.v.ve
new file mode 100644
index 0000000..b02ba21
--- /dev/null
+++ b/impl1/top_gatelevel.v.ve
@@ -0,0 +1 @@
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diff --git a/impl1/top_lse.twr b/impl1/top_lse.twr
new file mode 100644
index 0000000..085b7f1
--- /dev/null
+++ b/impl1/top_lse.twr
@@ -0,0 +1,131 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Fri Jul 24 14:34:05 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     top
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c]
+            3 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.426ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i1  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i1  (to clk_c +)
+
+   Delay:                   2.694ns  (12.4% logic, 87.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.694ns data_path cnt_9__i1 to cnt_9__i1 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.426ns
+
+ Path Details: cnt_9__i1 to cnt_9__i1
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i1 (from clk_c)
+Route         3   e 1.339                                  cnt_c_0
+LUT4        ---     0.105              A to Z              i18_1_lut
+Route         1   e 1.020                                  n15
+                  --------
+                    2.694  (12.4% logic, 87.6% route), 2 logic levels.
+
+
+Passed:  The following path meets requirements by 2.426ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i1  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i2  (to clk_c +)
+
+   Delay:                   2.694ns  (12.4% logic, 87.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.694ns data_path cnt_9__i1 to cnt_9__i2 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.426ns
+
+ Path Details: cnt_9__i1 to cnt_9__i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i1 (from clk_c)
+Route         3   e 1.339                                  cnt_c_0
+LUT4        ---     0.105              B to Z              i20_2_lut
+Route         1   e 1.020                                  n14
+                  --------
+                    2.694  (12.4% logic, 87.6% route), 2 logic levels.
+
+
+Passed:  The following path meets requirements by 2.507ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i2  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i2  (to clk_c +)
+
+   Delay:                   2.613ns  (12.8% logic, 87.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.613ns data_path cnt_9__i2 to cnt_9__i2 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.507ns
+
+ Path Details: cnt_9__i2 to cnt_9__i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i2 (from clk_c)
+Route         2   e 1.258                                  cnt_c_1
+LUT4        ---     0.105              A to Z              i20_2_lut
+Route         1   e 1.020                                  n14
+                  --------
+                    2.613  (12.8% logic, 87.2% route), 2 logic levels.
+
+Report: 2.574 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets clk_c]                   |     5.000 ns|     2.574 ns|     2  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  3 paths, 5 nets, and 7 connections (63.6% coverage)
+
+
+Peak memory: 255598592 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/impl1/top_lse_lsetwr.html b/impl1/top_lse_lsetwr.html
new file mode 100644
index 0000000..386f25b
--- /dev/null
+++ b/impl1/top_lse_lsetwr.html
@@ -0,0 +1,196 @@
+<HTML>
+<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
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    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
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background-color: #00ff00;
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background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Fri Jul 24 14:34:05 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
+------------------
+Design:     top
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c]
+            3 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.426ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i1  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i1  (to clk_c +)
+
+   Delay:                   2.694ns  (12.4% logic, 87.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.694ns data_path cnt_9__i1 to cnt_9__i1 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.426ns
+
+ Path Details: cnt_9__i1 to cnt_9__i1
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i1 (from clk_c)
+Route         3   e 1.339                                  cnt_c_0
+LUT4        ---     0.105              A to Z              i18_1_lut
+Route         1   e 1.020                                  n15
+                  --------
+                    2.694  (12.4% logic, 87.6% route), 2 logic levels.
+
+
+Passed:  The following path meets requirements by 2.426ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i1  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i2  (to clk_c +)
+
+   Delay:                   2.694ns  (12.4% logic, 87.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.694ns data_path cnt_9__i1 to cnt_9__i2 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.426ns
+
+ Path Details: cnt_9__i1 to cnt_9__i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i1 (from clk_c)
+Route         3   e 1.339                                  cnt_c_0
+LUT4        ---     0.105              B to Z              i20_2_lut
+Route         1   e 1.020                                  n14
+                  --------
+                    2.694  (12.4% logic, 87.6% route), 2 logic levels.
+
+
+Passed:  The following path meets requirements by 2.507ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3IX    CK             cnt_9__i2  (from clk_c +)
+   Destination:    FD1S3IX    D              cnt_9__i2  (to clk_c +)
+
+   Delay:                   2.613ns  (12.8% logic, 87.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      2.613ns data_path cnt_9__i2 to cnt_9__i2 meets
+      5.000ns delay constraint less
+     -0.120ns L_S requirement (totaling 5.120ns) by 2.507ns
+
+ Path Details: cnt_9__i2 to cnt_9__i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.230             CK to Q              cnt_9__i2 (from clk_c)
+Route         2   e 1.258                                  cnt_c_1
+LUT4        ---     0.105              A to Z              i20_2_lut
+Route         1   e 1.020                                  n14
+                  --------
+                    2.613  (12.8% logic, 87.2% route), 2 logic levels.
+
+Report: 2.574 ns is the maximum delay for this constraint.
+
+
+<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets clk_c]                   |     5.000 ns|     2.574 ns|     2  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  3 paths, 5 nets, and 7 connections (63.6% coverage)
+
+
+Peak memory: 255598592 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/impl1/top_prim.v b/impl1/top_prim.v
new file mode 100644
index 0000000..e00d704
--- /dev/null
+++ b/impl1/top_prim.v
@@ -0,0 +1,39 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.11.2.446
+// Netlist written on Fri Jul 24 14:34:05 2020
+//
+// Verilog Description of module top
+//
+
+module top (clk, reset, cnt) /* synthesis syn_module_defined=1 */ ;   // /home/hadaq/mmichalek/lattice/simplified/top.v(1[8:11])
+    input clk;   // /home/hadaq/mmichalek/lattice/simplified/top.v(9[12:15])
+    input reset;   // /home/hadaq/mmichalek/lattice/simplified/top.v(11[12:17])
+    output [1:0]cnt;   // /home/hadaq/mmichalek/lattice/simplified/top.v(14[17:20])
+    
+    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // /home/hadaq/mmichalek/lattice/simplified/top.v(9[12:15])
+    
+    wire GND_net, VCC_net, reset_c, cnt_c_1, cnt_c_0, n14, n15;
+    
+    VHI i2 (.Z(VCC_net));
+    OB cnt_pad_1 (.I(cnt_c_1), .O(cnt[1]));   // /home/hadaq/mmichalek/lattice/simplified/top.v(14[17:20])
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    OB cnt_pad_0 (.I(cnt_c_0), .O(cnt[0]));   // /home/hadaq/mmichalek/lattice/simplified/top.v(14[17:20])
+    FD1S3IX cnt_9__i2 (.D(n14), .CK(clk_c), .CD(reset_c), .Q(cnt_c_1));   // /home/hadaq/mmichalek/lattice/simplified/top.v(29[11:20])
+    defparam cnt_9__i2.GSR = "ENABLED";
+    LUT4 i18_1_lut (.A(cnt_c_0), .Z(n15)) /* synthesis lut_function=(!(A)) */ ;   // /home/hadaq/mmichalek/lattice/simplified/top.v(29[11:20])
+    defparam i18_1_lut.init = 16'h5555;
+    GSR GSR_INST (.GSR(VCC_net));
+    FD1S3IX cnt_9__i1 (.D(n15), .CK(clk_c), .CD(reset_c), .Q(cnt_c_0));   // /home/hadaq/mmichalek/lattice/simplified/top.v(29[11:20])
+    defparam cnt_9__i1.GSR = "ENABLED";
+    LUT4 i20_2_lut (.A(cnt_c_1), .B(cnt_c_0), .Z(n14)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // /home/hadaq/mmichalek/lattice/simplified/top.v(29[11:20])
+    defparam i20_2_lut.init = 16'h6666;
+    IB clk_pad (.I(clk), .O(clk_c));   // /home/hadaq/mmichalek/lattice/simplified/top.v(9[12:15])
+    IB reset_pad (.I(reset), .O(reset_c));   // /home/hadaq/mmichalek/lattice/simplified/top.v(11[12:17])
+    VLO i29 (.Z(GND_net));
+    
+endmodule
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
diff --git a/impl1/top_prim.v.ve b/impl1/top_prim.v.ve
new file mode 100644
index 0000000..6f5a261
--- /dev/null
+++ b/impl1/top_prim.v.ve
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/impl1/version.log b/impl1/version.log
new file mode 100644
index 0000000..4fbf33c
--- /dev/null
+++ b/impl1/version.log
@@ -0,0 +1,2 @@
+O-2018.09-SP1
+Synplify (R) Premier
diff --git a/impl1/xxx_lse_cp_file_list b/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..678adb8
--- /dev/null
+++ b/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,8 @@
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
+3	 /home/hadaq/mmichalek/lattice/simplified/top.v
diff --git a/impl1/xxx_lse_sign_file b/impl1/xxx_lse_sign_file
new file mode 100644
index 0000000..3d0c76c
--- /dev/null
+++ b/impl1/xxx_lse_sign_file
@@ -0,0 +1,8 @@
+LSE_CPS_ID_1 "/home/hadaq/mmichalek/lattice/simplified/top.v:14[17:20]"
+LSE_CPS_ID_2 "/home/hadaq/mmichalek/lattice/simplified/top.v:14[17:20]"
+LSE_CPS_ID_3 "/home/hadaq/mmichalek/lattice/simplified/top.v:29[11:20]"
+LSE_CPS_ID_4 "/home/hadaq/mmichalek/lattice/simplified/top.v:29[11:20]"
+LSE_CPS_ID_5 "/home/hadaq/mmichalek/lattice/simplified/top.v:29[11:20]"
+LSE_CPS_ID_6 "/home/hadaq/mmichalek/lattice/simplified/top.v:29[11:20]"
+LSE_CPS_ID_7 "/home/hadaq/mmichalek/lattice/simplified/top.v:9[12:15]"
+LSE_CPS_ID_8 "/home/hadaq/mmichalek/lattice/simplified/top.v:11[12:17]"
diff --git a/modules.v b/modules.v
new file mode 100644
index 0000000..a661282
--- /dev/null
+++ b/modules.v
@@ -0,0 +1,544 @@
+
+
+
+module tdc_channel (reset, pll_clks, clk8, xfer_clk, trig, txd,dec_out, dec_valid);
+	
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire clk8;
+	input wire xfer_clk;
+	input wire trig;
+	output wire txd;
+	output wire [2:0]dec_out;
+	output wire dec_valid;
+	
+
/*output*/ wire [2:0]s_data;
+/*output*/ wire valid;
+/*output*/ wire [7:0]lb_synced;
+/*output*/ wire [31:0]fifo_out;
+/*output*/ wire fifo_empty;
+/*output*/ wire fifo_full;
+reg [2:0]fifo_in_buffered;
+wire [7:0]tdc_out;
+/*output*/ wire [7:0]tdc_buffered_out;
+
+reg [31:0]dbg_cnt;
+wire pulser_trig;
+wire wrn;
+wire adsn;
+assign pulser_trig = dbg_cnt[2];
+
+reg [7:0]din;
+reg [2:0]wrn_cnt;
+reg [7:0]adsn_cnt;
+
+assign wrn = wrn_cnt[2];
+assign adsn = ~(|adsn_cnt);
+
+reg [7:0]uart_input_buf;
+reg uart_buf_empty;
+reg [3:0]uart_quad_cnt;
+reg fifo_read;
+
+
+
+wire trig_gate;
+	assign trig_gate =  ~trig;
+		
+		
+		
+	always @(pll_clks[3])begin
+		if(reset)begin
+			fifo_in_buffered <= 'b0;
+		end else begin
+			fifo_in_buffered <= s_data;
+		end
+	end
+
+
+
+assign dec_valid = valid;
+assign dec_out =  s_data;
+
+//output wire txd;
+		
+		
+tdc4ddr tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks), 
+						.xfer_clk(xfer_clk),
+						.out(tdc_out),
+						.out_buffered(tdc_buffered_out)
+						//.out_xfer(tdc_out)
+);
+
+output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						//.clk(xfer_clk),
+						//.clk(clk150),
+						//.in(tdc_out),
+						.in(tdc_buffered_out),
+						.out(s_data),
+						.valid(valid),
+						.in_synced_lb(lb_synced)
+						//.raw_latched()
+						);
+
+fifo32dc fifo32dc_inst (
+						.Data( s_data), 
+						.WrClock( pll_clks[3]), 
+						.RdClock( clk8), 
+						.WrEn( valid), 
+						.RdEn( 1'b1), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_out), 
+						.Empty( fifo_empty), 
+						.Full( fifo_full)
+						);
+
+
+
+	
+//endmodule
+
+
+UART_VerilogWrapper_TOP UART_VerilogWrapper_TO_inst2(
+       // Global reset and clock
+       .MR(reset)      ,
+       .MCLK(clk8)    ,
+       // Processor interface
+		.A(0)     ,
+        .DIN(din)   ,
+        .ADSn(adsn)  ,
+		.CS(1'b1)    ,
+        .RDn(rdn)   ,
+        .WRn(wrn)   ,
+       // Receiver interface
+       
+      // Transmitter interface          
+      .SOUT(txd)     ,                         
+      .TxRDYn(txrdy)          
+       );
+	   
+	   always @(posedge clk8)begin
+//always @(posedge pll_clks[0])begin
+	if(reset)begin
+		//marker <= 'b0;
+		dbg_cnt <= 'b0;
+		//dbg[0]<=1'b1;
+		adsn_cnt <= ~0;
+		wrn_cnt <= 'b0;
+		uart_buf_empty <= 'b1;
+	end else begin
+		//dbg[4] <= txd;
+		//dbg[3:2] <= ~pulser_out;
+		//dbg[7:6]<=dbg_cnt[21:20];
+		//dbg[0]<=1'b0;
+		dbg_cnt <= dbg_cnt +1;
+		//marker <= 'b1;
+		if(fifo_empty == 1'b0 && uart_buf_empty)begin
+			fifo_read<=1;
+			uart_input_buf <= fifo_out;
+			uart_buf_empty <= 0;
+			uart_quad_cnt <= 0;
+		end else begin
+			fifo_read<=0;
+		end
+  
+		if(uart_buf_empty == 0)begin
+			if(uart_quad_cnt == 10)begin
+				uart_buf_empty <= 1'b1;
+			end else begin
+				if(txrdy == 0 && wrn_cnt == 0)begin
+					//din <= {uart_input_buf[4*uart_quad_cnt +: 4],uart_quad_cnt};
+					din <= uart_input_buf;
+					wrn_cnt <= 'b111;
+					//uart_quad_cnt <= uart_quad_cnt +1;
+					uart_quad_cnt <= 10;
+				end
+			end
+		end
+		if(adsn_cnt)adsn_cnt <= adsn_cnt -1;
+		if(wrn_cnt)wrn_cnt <= wrn_cnt -1;
+	end
+end
+/*integer i;
+//generate
+always @( posedge pll_clks[0])begin
+	for(i =0; i<4; i=i+1)begin
+		s_out[i] <= s_in[i];
+	end
+end*/
+//endgenerate
+
+/*
+always @(posedge pll_clks[0])begin
+		if(reset)begin
+			cnt <= 2'b0;
+		end else begin
+			cnt <= cnt +2'b1;
+			s_in <= cnt;
+		end
+end
+*/
+
+endmodule
+
+
+
+
+
+
+
+module async_testgen(clk, reset, pulse_out,zero);
+	input wire clk;
+	input wire reset;
+	output wire pulse_out;
+	output wire zero;
+	
+	reg [31:0]pulse_cnt;
+	assign pulse_out = (pulse_cnt < 'h4f);
+	assign zero = (pulse_cnt > 'h4ff) && (pulse_cnt < 'h51f);
+
+	always @(posedge clk)begin
+	if(reset)begin
+		pulse_cnt <=0;
+	end else begin
+		if(pulse_cnt < 'h2ff5)begin
+		//if(pulse_cnt < 'h7)begin
+			pulse_cnt <= pulse_cnt +1;
+		end else begin
+			pulse_cnt <= 0;
+		end
+	end
+	end
+endmodule
+
+module tdc4ddr(trigger, clks, xfer_clk, out, out_buffered, out_xfer) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	input wire xfer_clk;
+	output reg [7:0]out /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_xfer /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+	reg [3:0]in_clk_down_synced /*synthesis syn_preserve= 1*/;
+	//always @(negedge clks[3])begin
+	always @(negedge xfer_clk)begin
+		//out_buffered1 <= out;
+		//out_buffered <= out_buffered1;
+		out_xfer <= out_buffered;
+	end
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+			reg [1:0]in_up_dl;
+			reg [1:0]in_down_dl;
+			
+			always @(posedge clks[i])begin
+				if(trigger)begin
+					out[i] <= 1'b1;
+				end else begin 
+					out[i] <= 1'b0;
+				end
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				if(trigger)out[4+i] <= 1'b1 /*synthesis syn_preserve= 1*/;
+				else out[4+i] <= 1'b0 /*synthesis syn_preserve= 1*/;
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module output_decoder8(
+									clk,
+									in,
+									out,
+									valid,
+									in_synced_lb,
+									raw_latched
+									) /* synthesis syn_preserve= 1*/;
+
+input wire clk;
+input wire [7:0]in;
+output reg [2:0]out /*synthesis syn_preserve=1*/;
+reg [2:0]out_internal /*synthesis syn_preserve=1*/;
+output reg valid /*synthesis syn_preserve=1*/;
+reg valid_internal /*synthesis syn_preserve=1*/;
+output wire [7:0]in_synced_lb;
+output reg [7:0]raw_latched /*synthesis preserve=1*/;
+
+reg [7:0]dl[2:0];
+reg [7:0]in_synced /*synthesis syn_preserve=1*/;
+
+assign in_synced_lb=in_synced;
+
+wire in_synced7_rising;
+assign  in_synced7_rising = ~in_synced[7] & dl[1][7];
+
+always @ (negedge clk)begin
+	out <= out_internal;
+	valid <= valid_internal;
+end
+
+always @ (negedge clk)begin
+	dl[0] <= in;
+	dl[1] <= dl[0];
+	in_synced <= dl[1];
+end
+	always @ (negedge clk)begin
+		if(in_synced7_rising)begin
+		case (in_synced)	
+			//8'b10000000 : begin
+				8'b01111111 : begin
+                        out_internal <= 3'b000;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000001;
+                        end
+			//8'b10000001 : begin
+				8'b01111110 : begin
+                        out_internal <= 3'b001;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000010;
+                        end
+			//8'b10000011 : begin
+				8'b01111100 : begin
+                        out_internal <= 3'b010;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b00000000000000100;
+                        end
+			//8'b10000111 : begin
+				8'b01111000 : begin
+                        out_internal <= 3'b011;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000001000;
+                        end
+			//8'b10001111 : begin
+				8'b01110000 : begin
+                        out_internal <= 3'b100;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000010000;
+                        end
+			//8'b10011111 : begin
+				8'b01100000 : begin
+                        out_internal <= 3'b101;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000100000;
+                        end
+			//8'b10111111 : begin
+				8'b01000000 : begin
+                        out_internal <= 3'b110;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000001000000;
+                        end
+			//8'b00000000 : begin //8'b11111111
+				8'b00000000 : begin
+                        out_internal <= 3'b111;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000010000000;
+                        end
+			default   :  begin
+						out_internal <=3'b111;
+						valid_internal <= 1'b0;
+						//raw_latched <= 'b0;
+						//raw_latched <= raw_latched;
+						end
+			endcase
+		end else begin
+			out_internal <=3'b111;
+			valid_internal <= 1'b0;
+		end
+		end
+
+
+endmodule
+
+module two_ch_diff(
+							clk, reset, 
+							zero, 
+							in0, in0_valid, 
+							in1, in1_valid, 
+							out, out_valid, 
+							be_tmp, out0, out1,
+							fifo_out, fifo_empty, clk_uart,txd
+							);
+
+input wire clk;
+input wire reset;
+input wire /*reg*/ zero;
+input wire [3:0]in0;
+input wire in0_valid;
+input wire [3:0]in1;
+input wire in1_valid;
+output reg [3:0]out;
+output reg out_valid;
+output wire [1:0]be_tmp;
+output wire [3:0]out0;
+output wire [3:0]out1;
+
+reg [3:0]lost;
+
+wire [7:0]fifo_in;
+ output wire [31:0]fifo_out;
+ output wire fifo_empty;
+ wire fifo_full;
+
+reg [1:0]in0_valid_dl;
+reg [1:0]in1_valid_dl;
+reg [3:0]in0_dl0;
+reg [3:0]in1_dl0;
+reg [3:0]in0_dl1;
+reg [3:0]in1_dl1;
+
+wire [1:0]in_valid_rising;
+assign  in_valid_rising[0] = ~in0_valid_dl[1] & in0_valid_dl[0];
+assign  in_valid_rising[1] = ~in1_valid_dl[1] & in1_valid_dl[0];
+
+assign fifo_in = {lost,out};
+
+input wire clk_uart;
+output wire txd;
+
+reg [7:0]din;
+reg [31:0]dbg_cnt;
+reg [7:0]adsn_cnt;
+reg [2:0]wrn_cnt;
+reg uart_buf_empty;
+reg fifo_read;
+reg [7:0]uart_input_buf;
+reg [3:0]uart_quad_cnt;
+
+reg [3:0]zero_dl;
+wire zero_rising  ;
+assign zero_rising = (~zero_dl[3] & zero_dl[2]); 
+assign wrn = wrn_cnt[2];
+assign adsn = ~(|adsn_cnt);
+
+reg [3:0]buff0;
+reg [3:0]buff1;
+reg [1:0]catch;
+
+assign be_tmp = catch;
+assign out0 = buff0;
+assign out1 = buff1;
+	
+	always @(posedge clk)begin
+		in0_valid_dl <= {in0_valid_dl[0], in0_valid};
+		in1_valid_dl <= {in1_valid_dl[0], in1_valid};
+		in0_dl0<=in0;
+		in0_dl1<=in0_dl0;
+		in1_dl0<=in1;
+		in1_dl1<=in1_dl0;
+		zero_dl <= {zero_dl[2],zero_dl[1],zero_dl[0],zero};
+		//in0_dl <= {in0_dl[0],in0};
+		//in1_dl <= {in1_dl[0],in1};
+	end
+
+
+	always @(posedge clk)begin
+		if(reset)begin
+			//out_valid<='b0;
+			//out<='b0;
+		end else begin
+			if(zero_rising)begin
+				if(!(&catch))lost<='h4;
+				else lost<='h0;
+				out<=buff0-buff1;
+				out_valid<='b1;
+				catch[0]<='b0;
+				catch[1]<='b0;
+			end else begin
+				out_valid <= 'b0;
+				if(in_valid_rising[0])begin
+					buff0<=in0_dl0;
+					catch[0]<='b1;
+				end
+				if(in_valid_rising[1])begin
+					buff1<=in1_dl0;
+					catch[1]<='b1;
+				end
+			end
+		end
+	end
+
+fifo32dc fifo32dc_inst (
+						.Data( fifo_in), 
+						.WrClock( clk), 
+						.RdClock( clk_uart), 
+						.WrEn( out_valid), 
+						.RdEn( 1'b1), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_out), 
+						.Empty( fifo_empty), 
+						.Full( fifo_full)
+						);
+
+
+
+	
+//endmodule
+
+
+UART_VerilogWrapper_TOP UART_VerilogWrapper_TO_inst(
+       .MR(reset)      ,
+       .MCLK(clk_uart)    ,
+		.A(0)     ,
+        .DIN(din)   ,
+        .ADSn(adsn)  ,
+		.CS(1'b1)    ,
+        .RDn(rdn)   ,
+        .WRn(wrn)   ,
+       
+      .SOUT(txd)     ,                         
+      .TxRDYn(txrdy)          
+       );
+	   
+	   always @(posedge clk_uart)begin
+	if(reset)begin
+		dbg_cnt <= 'b0;
+		adsn_cnt <= ~0;
+		wrn_cnt <= 'b0;
+		uart_buf_empty <= 'b1;
+	end else begin
+		dbg_cnt <= dbg_cnt +1;
+		if(fifo_empty == 1'b0 && uart_buf_empty)begin
+			fifo_read<=1;
+			uart_input_buf <= fifo_out;
+			uart_buf_empty <= 0;
+			uart_quad_cnt <= 0;
+		end else begin
+			fifo_read<=0;
+		end
+  
+		if(uart_buf_empty == 0)begin
+			if(uart_quad_cnt == 10)begin
+				uart_buf_empty <= 1'b1;
+			end else begin
+				if(txrdy == 0 && wrn_cnt == 0)begin
+					din <= uart_input_buf;
+					wrn_cnt <= 'b111;
+					uart_quad_cnt <= 10;
+				end
+			end
+		end
+		if(adsn_cnt)adsn_cnt <= adsn_cnt -1;
+		if(wrn_cnt)wrn_cnt <= wrn_cnt -1;
+	end
+end
+
+
+
+
+
+endmodule
diff --git a/modules2.v b/modules2.v
new file mode 100644
index 0000000..43273bc
--- /dev/null
+++ b/modules2.v
@@ -0,0 +1,347 @@
+
+						
+module tdc_channel_fifo_out (
+										reset, 
+										pll_clks, 
+										coarse, 
+										trig,
+										fifo_data_out,
+										fifo_rden,
+										fifo_empty,
+										tdc_out
+										);
+	
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire trig;
+	input wire [27:0]coarse;
+	output wire [31:0]fifo_data_out;
+	input wire fifo_rden;
+	output wire fifo_empty;
+	output wire [7:0]tdc_out;
+	wire [7:0]tdc_out_neg;
+	
+	wire trig_gate /* synthesis syn_preserve= 1*/;
+	wire trig_gate_mid /* synthesis syn_preserve= 1*/;
+	wire trig_gate_mid2 /* synthesis syn_preserve= 1*/;
+	wire trig_gate_neg /* synthesis syn_preserve= 1*/;
+	assign trig_gate =  ~trig /* synthesis syn_preserve= 1*/;
+	//assign trig_gate_neg = ~trig_gate /* synthesis syn_preserve= 1*/;
+	
+	trig_inv trig_inv_inst1(
+							.in(trig_gate),
+							.out(trig_gate_mid)
+	) /* synthesis syn_black_box */;
+	
+	
+	trig_inv trig_inv_inst2(
+							.in(trig_gate_mid),
+							.out(trig_gate_mid2)
+	) /* synthesis syn_black_box */;
+	
+	
+	trig_inv trig_inv_inst3(
+							.in(trig_gate_mid2),
+							.out(trig_gate_neg)
+	) /* synthesis syn_black_box */;
+	
+	
+	
+	 reg [31:0]fifo_in_data;
+	 wire fifo_in_valid;
+	 wire [31:0]fifo_out_data;
+	 wire fifo_full;
+	 wire fifo_out_rden;
+	 reg fifo_wren;
+	 wire [2:0]decoder_out;
+	 wire [2:0]decoder_out_neg;
+	 
+	 reg [31:0]buf_positive;
+	 reg [31:0]buf_negative;
+	 reg buf_positive_ready;
+	 reg buf_negative_ready;
+	
+	tdc4ddr_short tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks),
+						.out(tdc_out)
+	);
+	tdc4ddr_short tdc_neg_inst(
+						.trigger(trig_gate_neg), 
+						.clks(pll_clks),
+						.out(tdc_out_neg)
+						) /* synthesis syn_preserve= 1*/;
+	/*tdc4ddr tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks), 
+						.xfer_clk(pll_clks[3]), 
+						.out(), 
+						.out_buffered(tdc_out), 
+						.out_xfer()
+						); 
+*/
+	output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out),
+						.out(decoder_out),
+						.valid(decoder_valid)
+						);
+						
+	output_decoder8 dec_neg_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out_neg),
+						.out(decoder_out_neg),
+						.valid(decoder_valid_neg)
+						) /* synthesis syn_preserve= 1*/;
+
+	fifo32dc fifo32dc_inst (
+						.Data( fifo_in_data), 
+						.WrClock( pll_clks[3]), 
+						.RdClock( pll_clks[3]), 
+						.WrEn( fifo_wren), 
+						.RdEn( fifo_rden), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_data_out), 
+						.Empty( fifo_empty), 
+						.Full( fifo_full)
+						);
+	
+	/*always @(negedge pll_clks[3])begin
+		if(reset)begin
+			fifo_in_data <= 'b0;
+			fifo_wren <= 'b0;
+		end else begin
+			if(decoder_valid)begin
+				buf_positive <= {coarse[7:0], decoder_out};
+				buf_positive_ready <= 'b1;
+			end else begin
+				buf_positive_ready <= 'b0;
+			end
+			if(decoder_valid_neg)begin
+				buf_negative <= {coarse[7:0], decoder_out_neg};
+				buf_negative_ready <= 'b1;
+			end else begin
+				buf_negative_ready <= 'b0;
+			end
+			if(buf_negative_ready & buf_positive_ready)begin
+				buf_negative_ready <= 'b0;
+				buf_positive_ready <= 'b0;
+				fifo_in_data <= {buf_negative, buf_positive};
+				fifo_wren <= 'b1;
+			end else begin
+				fifo_wren <= 'b0;
+			end
+		end
+	end*/
+	
+	always @(negedge pll_clks[3])begin
+		if(reset)begin
+			fifo_in_data <= 'b0;
+			fifo_wren <= 'b0;
+		end else begin
+			if(decoder_valid)begin
+				//fifo_in_data <= {coarse, decoder_out};
+				fifo_in_data <= 'h0d00ba00;
+				fifo_wren <= 'b1;
+			end else begin
+				fifo_wren <= 'b0;
+			end
+		end
+	end
+	
+	//output wire [31:0]fifo_data_out2;
+	//input wire fifo_rden2;
+	//output wire [3:0]tdc_out2;
+	
+	
+endmodule
+
+module tdc4ddr_short(trigger, clks, out) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	output wire [7:0]out /*synthesis syn_preserve= 1*/;
+	/*output*/ reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	assign out = out_buffered;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+
+			always @(posedge clks[i])begin
+
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module tdc4ddr(trigger, clks, xfer_clk, out, out_buffered, out_xfer) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	input wire xfer_clk;
+	output reg [7:0]out /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_xfer /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+	reg [3:0]in_clk_down_synced /*synthesis syn_preserve= 1*/;
+	//always @(negedge clks[3])begin
+	always @(negedge xfer_clk)begin
+		//out_buffered1 <= out;
+		//out_buffered <= out_buffered1;
+		out_xfer <= out_buffered;
+	end
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+			reg [1:0]in_up_dl;
+			reg [1:0]in_down_dl;
+			
+			always @(posedge clks[i])begin
+				if(trigger)begin
+					out[i] <= 1'b1;
+				end else begin 
+					out[i] <= 1'b0;
+				end
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				if(trigger)out[4+i] <= 1'b1 /*synthesis syn_preserve= 1*/;
+				else out[4+i] <= 1'b0 /*synthesis syn_preserve= 1*/;
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module output_decoder8(
+									clk,
+									in,
+									out,
+									valid,
+									in_synced_lb,
+									raw_latched
+									) /* synthesis syn_preserve= 1*/;
+
+input wire clk;
+input wire [7:0]in;
+output reg [2:0]out /*synthesis syn_preserve=1*/;
+reg [2:0]out_internal /*synthesis syn_preserve=1*/;
+output reg valid /*synthesis syn_preserve=1*/;
+reg valid_internal /*synthesis syn_preserve=1*/;
+output wire [7:0]in_synced_lb;
+output reg [7:0]raw_latched /*synthesis preserve=1*/;
+
+reg [7:0]dl[2:0];
+reg [7:0]in_synced /*synthesis syn_preserve=1*/;
+
+assign in_synced_lb=in_synced;
+
+wire in_synced7_rising;
+assign  in_synced7_rising = ~in_synced[7] & dl[1][7];
+
+always @ (negedge clk)begin
+	out <= out_internal;
+	valid <= valid_internal;
+end
+
+always @ (negedge clk)begin
+	dl[0] <= in;
+	dl[1] <= dl[0];
+	in_synced <= dl[1];
+end
+	always @ (negedge clk)begin
+		if(in_synced7_rising)begin
+		case (in_synced)	
+			//8'b10000000 : begin
+				8'b01111111 : begin
+                        out_internal <= 3'b000;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000001;
+                        end
+			//8'b10000001 : begin
+				8'b01111110 : begin
+                        out_internal <= 3'b001;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000010;
+                        end
+			//8'b10000011 : begin
+				8'b01111100 : begin
+                        out_internal <= 3'b010;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b00000000000000100;
+                        end
+			//8'b10000111 : begin
+				8'b01111000 : begin
+                        out_internal <= 3'b011;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000001000;
+                        end
+			//8'b10001111 : begin
+				8'b01110000 : begin
+                        out_internal <= 3'b100;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000010000;
+                        end
+			//8'b10011111 : begin
+				8'b01100000 : begin
+                        out_internal <= 3'b101;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000100000;
+                        end
+			//8'b10111111 : begin
+				8'b01000000 : begin
+                        out_internal <= 3'b110;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000001000000;
+                        end
+			//8'b00000000 : begin //8'b11111111
+				8'b00000000 : begin
+                        out_internal <= 3'b111;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000010000000;
+                        end
+			default   :  begin
+						out_internal <=3'b111;
+						valid_internal <= 1'b0;
+						//raw_latched <= 'b0;
+						//raw_latched <= raw_latched;
+						end
+			endcase
+		end else begin
+			out_internal <=3'b111;
+			valid_internal <= 1'b0;
+		end
+		end
+
+
+endmodule
+
+
+//module trig_inv(in,out) /* synthesis syn_black_box */;
+module trig_inv(in,out) /* synthesis syn_preserve=1 */;
+input wire in /* synthesis syn_keep=1 */;
+output wire out /* synthesis syn_keep=1 */;
+
+assign out = ~ in /* synthesis syn_keep=1 */;
+
+endmodule
diff --git a/modules2.v.bkp b/modules2.v.bkp
new file mode 100644
index 0000000..ca1c307
--- /dev/null
+++ b/modules2.v.bkp
@@ -0,0 +1,380 @@
+module top_tf(
+										clk,
+										reset, 										
+										trig,
+										fifo_data_out,
+										fifo_rden,
+										tdc_out,
+										trig2,
+										fifo_data_out2,
+										fifo_rden2,
+										tdc_out2
+
+						);
+	input wire clk;					
+	input wire reset;
+	input wire trig;
+	output wire [31:0]fifo_data_out;
+	input wire fifo_rden;
+	output wire [7:0]tdc_out;
+	
+	input wire trig2;	
+	output wire [7:0]tdc_out2;
+	input wire fifo_rden2;
+	output wire [31:0]fifo_data_out2;
+							
+	reg [27:0]coarse;					
+		
+	wire [3:0]pll_clks;
+	//assign fifo_data_out[0]  = coarse[15];
+	pll0 pll0inst(.CLKI( clk), .CLKOP( pll_clks[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));		
+		//pll0 pll0inst(.CLKI( clk), .CLKOP( fifo_data_out[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));
+		tdc_channel_fifo_out tdc_channel_fifo_out_inst(
+										.reset(reset), 
+										.pll_clks(pll_clks), 
+										.coarse(coarse), 
+										.trig(trig),
+										.fifo_data_out(fifo_data_out),
+										.fifo_rden(fifo_rden),
+										.tdc_out(tdc_out)
+										);
+		tdc_channel_fifo_out tdc_channel_fifo_out_inst2(
+										.reset(reset), 
+										.pll_clks(pll_clks), 
+										.coarse(coarse), 
+										.trig(trig2),
+										.fifo_data_out(fifo_data_out2),
+										.fifo_rden(fifo_rden2),
+										.tdc_out(tdc_out2)
+										);		
+		
+		
+always @(posedge pll_clks[0])begin
+		if(reset)begin
+			coarse <= 'b0;
+		end else begin
+			coarse <= coarse + 'b1;
+		end
+end	
+						
+endmodule
+						
+module tdc_channel_fifo_out (
+										reset, 
+										pll_clks, 
+										coarse, 
+										trig,
+										fifo_data_out,
+										fifo_rden,
+										tdc_out
+										);
+	
+	input wire reset;
+	input wire [3:0]pll_clks;
+	input wire trig;
+	input wire [27:0]coarse;
+	output wire [31:0]fifo_data_out;
+	input wire fifo_rden;
+	output wire [7:0]tdc_out;
+	
+	wire trig_gate /* synthesis syn_preserve= 1*/;
+	assign trig_gate =  ~trig;
+	
+	 reg [31:0]fifo_in_data;
+	 wire fifo_in_valid;
+	 wire [31:0]fifo_out_data;
+	 wire fifo_empty;
+	 wire fifo_full;
+	 wire fifo_out_rden;
+	 reg fifo_wren;
+	
+	/*tdc4ddr_short tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks),
+						.out(tdc_out)
+	);*/
+	tdc4ddr tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks), 
+						.xfer_clk(pll_clks[3]), 
+						.out(), 
+						.out_buffered(tdc_out), 
+						.out_xfer()
+						); 
+
+	output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						.in(tdc_out),
+						.out(decoder_out),
+						.valid(decoder_valid)
+						);
+
+	fifo32dc fifo32dc_inst (
+						.Data( fifo_in_data), 
+						.WrClock( pll_clks[3]), 
+						.RdClock( pll_clks[3]), 
+						.WrEn( fifo_wren), 
+						.RdEn( fifo_rden), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_data_out), 
+						.Empty( fifo_empty), 
+						.Full( fifo_full)
+						);
+	
+	always @(negedge pll_clks[3])begin
+		if(reset)begin
+			fifo_in_data <= 'b0;
+			fifo_wren <= 'b0;
+		end else begin
+			if(decoder_valid)begin
+				fifo_in_data <= {coarse, decoder_out};
+				//fifo_in_data <= decoder_out;
+				fifo_wren <= 'b1;
+			end else begin
+				fifo_wren <= 'b0;
+			end
+		end
+	end
+	
+	//output wire [31:0]fifo_data_out2;
+	//input wire fifo_rden2;
+	//output wire [3:0]tdc_out2;
+	
+	wire trig_gate2 /* synthesis syn_preserve= 1*/;
+	assign trig_gate2 =  ~trig;
+	
+	 reg [31:0]fifo_in_data2;
+	 wire fifo_in_valid2;
+	 wire [31:0]fifo_out_data2;
+	 wire fifo_empty2;
+	 wire fifo_full2;
+	 //wire fifo_out_rden2;
+	 reg fifo_wren2;
+	
+	tdc4ddr tdc_inst2(
+						.trigger(trig_gate2), 
+						.clks(pll_clks), 
+						.xfer_clk(pll_clks[3]), 
+						.out(), 
+						.out_buffered(tdc_out2), 
+						.out_xfer()
+						); 
+
+	output_decoder8 dec_inst2(
+						.clk(pll_clks[3]),
+						.in(tdc_out2),
+						.out(decoder_out2),
+						.valid(decoder_valid2)
+						);
+
+	fifo32dc fifo32dc_inst2 (
+						.Data( fifo_in_data2), 
+						.WrClock( pll_clks[3]), 
+						.RdClock( pll_clks[3]), 
+						.WrEn( fifo_wren2), 
+						.RdEn( fifo_rden2), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_data_out2), 
+						.Empty( fifo_empty2), 
+						.Full( fifo_full2)
+						);
+	
+	always @(negedge pll_clks[3])begin
+		if(reset)begin
+			fifo_in_data2 <= 'b0;
+			fifo_wren2 <= 'b0;
+		end else begin
+			if(decoder_valid2)begin
+				fifo_in_data2 <= {coarse, decoder_out2};
+				//fifo_in_data <= decoder_out;
+				fifo_wren2 <= 'b1;
+			end else begin
+				fifo_wren2 <= 'b0;
+			end
+		end
+	end
+	
+	
+endmodule
+
+module tdc4ddr_short(trigger, clks, out) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	output wire [7:0]out /*synthesis syn_preserve= 1*/;
+	/*output*/ reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	assign out = out_buffered;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+
+			always @(posedge clks[i])begin
+
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module tdc4ddr(trigger, clks, xfer_clk, out, out_buffered, out_xfer) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	input wire xfer_clk;
+	output reg [7:0]out /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_xfer /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+	reg [3:0]in_clk_down_synced /*synthesis syn_preserve= 1*/;
+	//always @(negedge clks[3])begin
+	always @(negedge xfer_clk)begin
+		//out_buffered1 <= out;
+		//out_buffered <= out_buffered1;
+		out_xfer <= out_buffered;
+	end
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+			reg [1:0]in_up_dl;
+			reg [1:0]in_down_dl;
+			
+			always @(posedge clks[i])begin
+				if(trigger)begin
+					out[i] <= 1'b1;
+				end else begin 
+					out[i] <= 1'b0;
+				end
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				if(trigger)out[4+i] <= 1'b1 /*synthesis syn_preserve= 1*/;
+				else out[4+i] <= 1'b0 /*synthesis syn_preserve= 1*/;
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module output_decoder8(
+									clk,
+									in,
+									out,
+									valid,
+									in_synced_lb,
+									raw_latched
+									) /* synthesis syn_preserve= 1*/;
+
+input wire clk;
+input wire [7:0]in;
+output reg [2:0]out /*synthesis syn_preserve=1*/;
+reg [2:0]out_internal /*synthesis syn_preserve=1*/;
+output reg valid /*synthesis syn_preserve=1*/;
+reg valid_internal /*synthesis syn_preserve=1*/;
+output wire [7:0]in_synced_lb;
+output reg [7:0]raw_latched /*synthesis preserve=1*/;
+
+reg [7:0]dl[2:0];
+reg [7:0]in_synced /*synthesis syn_preserve=1*/;
+
+assign in_synced_lb=in_synced;
+
+wire in_synced7_rising;
+assign  in_synced7_rising = ~in_synced[7] & dl[1][7];
+
+always @ (negedge clk)begin
+	out <= out_internal;
+	valid <= valid_internal;
+end
+
+always @ (negedge clk)begin
+	dl[0] <= in;
+	dl[1] <= dl[0];
+	in_synced <= dl[1];
+end
+	always @ (negedge clk)begin
+		if(in_synced7_rising)begin
+		case (in_synced)	
+			//8'b10000000 : begin
+				8'b01111111 : begin
+                        out_internal <= 3'b000;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000001;
+                        end
+			//8'b10000001 : begin
+				8'b01111110 : begin
+                        out_internal <= 3'b001;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000010;
+                        end
+			//8'b10000011 : begin
+				8'b01111100 : begin
+                        out_internal <= 3'b010;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b00000000000000100;
+                        end
+			//8'b10000111 : begin
+				8'b01111000 : begin
+                        out_internal <= 3'b011;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000001000;
+                        end
+			//8'b10001111 : begin
+				8'b01110000 : begin
+                        out_internal <= 3'b100;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000010000;
+                        end
+			//8'b10011111 : begin
+				8'b01100000 : begin
+                        out_internal <= 3'b101;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000100000;
+                        end
+			//8'b10111111 : begin
+				8'b01000000 : begin
+                        out_internal <= 3'b110;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000001000000;
+                        end
+			//8'b00000000 : begin //8'b11111111
+				8'b00000000 : begin
+                        out_internal <= 3'b111;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000010000000;
+                        end
+			default   :  begin
+						out_internal <=3'b111;
+						valid_internal <= 1'b0;
+						//raw_latched <= 'b0;
+						//raw_latched <= raw_latched;
+						end
+			endcase
+		end else begin
+			out_internal <=3'b111;
+			valid_internal <= 1'b0;
+		end
+		end
+
+
+endmodule
+
diff --git a/pll0/generate_core.tcl b/pll0/generate_core.tcl
new file mode 100644
index 0000000..c5cf892
--- /dev/null
+++ b/pll0/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "pll0"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/pll0/generate_ngd.tcl b/pll0/generate_ngd.tcl
new file mode 100644
index 0000000..28028dc
--- /dev/null
+++ b/pll0/generate_ngd.tcl
@@ -0,0 +1,115 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "pll0"
+set Para(Module) "PLL"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create response file(*.cmd) for Synpwrap
+proc CreateCmdFile {} {
+	global Para
+
+	file mkdir "$Para(sbp_path)/syn_results"
+	if [catch {open $Para(ModuleName).cmd w} rspFile] {
+		puts "Cannot create response file $Para(ModuleName).cmd."
+		exit -1
+	} else {
+		puts $rspFile "PROJECT: $Para(ModuleName)
+		working_path: \"$Para(sbp_path)/syn_results\"
+		module: $Para(ModuleName)
+		verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/ecp5um.v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
+		vlog_std_v2001: true
+		constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
+		suffix_name: edn
+		output_file_name: $Para(ModuleName)
+		write_prf: true
+		disable_io_insertion: true
+		force_gsr: false
+		frequency: $Para(FMax)
+		fanout_limit: 50
+		retiming: false
+		pipe: false
+		part: $Para(PartType)
+		speed_grade: $Para(SpeedGrade)
+		"
+		close $rspFile
+	}
+}
+
+#synpwrap
+CreateCmdFile
+set synpwrap "$Para(bin_dir)/synpwrap"
+if {[file exists $fdcfile] == 0} {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
+} else {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
+}
+#puts $msg
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/pll0/msg_file.log b/pll0/msg_file.log
new file mode 100644
index 0000000..460a2d6
--- /dev/null
+++ b/pll0/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:13 2020
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+    Inputs       : CLKI
+    Outputs      : CLKOP, CLKOS, CLKOS2, CLKOS3
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    Verilog output   : pll0.v
+    Verilog template : pll0_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/pll0/pll0.edn b/pll0/pll0.edn
new file mode 100644
index 0000000..498120d
--- /dev/null
+++ b/pll0/pll0.edn
@@ -0,0 +1,229 @@
+(edif pll0
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 10 21 10 28 14)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell EHXPLLL
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port PHASELOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell pll0
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLL))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "6"))
+            (property CLKOS3_CPHASE
+              (string "1"))
+            (property CLKOS2_FPHASE
+              (string "4"))
+            (property CLKOS2_CPHASE
+              (string "1"))
+            (property CLKOS_FPHASE
+              (string "2"))
+            (property CLKOS_CPHASE
+              (string "1"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "1"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "FALLING"))
+            (property FREQUENCY_PIN_CLKOS3
+              (string "300.000000"))
+            (property OUTDIVIDER_MUXD
+              (string "DIVD"))
+            (property CLKOS3_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOS2
+              (string "300.000000"))
+            (property OUTDIVIDER_MUXC
+              (string "DIVC"))
+            (property CLKOS2_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOS
+              (string "300.000000"))
+            (property OUTDIVIDER_MUXB
+              (string "DIVB"))
+            (property CLKOS_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "300.000000"))
+            (property OUTDIVIDER_MUXA
+              (string "DIVA"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "100.000000"))
+            (property ICP_CURRENT
+              (string "9"))
+            (property LPF_RESISTOR
+              (string "72"))
+            (property CLKOS3_DIV
+              (string "2"))
+            (property CLKOS2_DIV
+              (string "2"))
+            (property CLKOS_DIV
+              (string "2"))
+            (property CLKOP_DIV
+              (string "2"))
+            (property CLKFB_DIV
+              (string "3"))
+            (property CLKI_DIV
+              (string "1"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net REFCLK
+            (joined
+              (portRef REFCLK (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef PHASELOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net CLKOS3
+            (joined
+              (portRef CLKOS3)
+              (portRef CLKOS3 (instanceRef PLLInst_0))))
+          (net CLKOS2
+            (joined
+              (portRef CLKOS2)
+              (portRef CLKOS2 (instanceRef PLLInst_0))))
+          (net CLKOS
+            (joined
+              (portRef CLKOS)
+              (portRef CLKOS (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef CLKI (instanceRef PLLInst_0))))))))
+  (design pll0
+    (cellRef pll0
+      (libraryRef ORCLIB)))
+)
diff --git a/pll0/pll0.fdc b/pll0/pll0.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/pll0/pll0.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/pll0/pll0.lpc b/pll0/pll0.lpc
new file mode 100644
index 0000000..40bec60
--- /dev/null
+++ b/pll0/pll0.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll0
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=10/21/2020
+Time=10:28:13
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=100.00
+CLKI_DIV=1
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=300
+CLKOP_TOL=0.0
+CLKOP_DIV=2
+CLKOP_ACTUAL_FREQ=300.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=300
+CLKOS_TOL=0.0
+CLKOS_DIV=2
+CLKOS_ACTUAL_FREQ=300.000000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=300
+CLKOS2_TOL=0.0
+CLKOS2_DIV=2
+CLKOS2_ACTUAL_FREQ=300.000000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=ENABLED
+CLKOS3_FREQ=300
+CLKOS3_TOL=0.0
+CLKOS3_DIV=2
+CLKOS3_ACTUAL_FREQ=300.000000
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=3
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=8.185
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=45
+CLKOS_APHASE=45.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=90
+CLKOS2_APHASE=90.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=135
+CLKOS3_APHASE=135.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1
diff --git a/pll0/pll0.sbx b/pll0/pll0.sbx
new file mode 100644
index 0000000..c1cacde
--- /dev/null
+++ b/pll0/pll0.sbx
@@ -0,0 +1,430 @@
+<!DOCTYPE pll0>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll0.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll0.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Generation</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>GENERATE</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2020-07-27.01:34:13 PM</lattice:date>
+            <lattice:modified>2020-10-21.10:28:14 AM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10/21/2020</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">pll0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10:28:13</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">90.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">90</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">135.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">135</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">45.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">45</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IOBUF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_BW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8.185</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>REFERENCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll0</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/pll0/pll0.srp b/pll0/pll0.srp
new file mode 100644
index 0000000..6d281e0
--- /dev/null
+++ b/pll0/pll0.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:14 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.fdc 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS, CLKOS2, CLKOS3
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    Verilog output   : pll0.v
+    Verilog template : pll0_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Element Usage    :
+        EHXPLLL : 1
+    Estimated Resource Usage:
diff --git a/pll0/pll0.v b/pll0/pll0.v
new file mode 100644
index 0000000..36b6c0e
--- /dev/null
+++ b/pll0/pll0.v
@@ -0,0 +1,90 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.fdc  */
+/* Wed Oct 21 10:28:14 2020 */
+
+
+`timescale 1 ns / 1 ps
+module pll0 (CLKI, CLKOP, CLKOS, CLKOS2, CLKOS3)/* synthesis NGD_DRC_MASK=1 */;
+    input wire CLKI;
+    output wire CLKOP;
+    output wire CLKOS;
+    output wire CLKOS2;
+    output wire CLKOS3;
+
+    wire REFCLK;
+    wire LOCK;
+    wire CLKOS3_t;
+    wire CLKOS2_t;
+    wire CLKOS_t;
+    wire CLKOP_t;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 6 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 1 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 4 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 1 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 2 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 1 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 1 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 2 ;
+    defparam PLLInst_0.CLKOS2_DIV = 2 ;
+    defparam PLLInst_0.CLKOS_DIV = 2 ;
+    defparam PLLInst_0.CLKOP_DIV = 2 ;
+    defparam PLLInst_0.CLKFB_DIV = 3 ;
+    defparam PLLInst_0.CLKI_DIV = 1 ;
+    defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), 
+        .CLKOS3(CLKOS3_t), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOS3="300.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOS2="300.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOS="300.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOP="300.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="100.000000" */
+             /* synthesis ICP_CURRENT="9" */
+             /* synthesis LPF_RESISTOR="72" */;
+
+    assign CLKOS3 = CLKOS3_t;
+    assign CLKOS2 = CLKOS2_t;
+    assign CLKOS = CLKOS_t;
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS3 300.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 300.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 300.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 300.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 100.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 9
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 72
+    // exemplar end
+
+endmodule
diff --git a/pll0/pll0_generate.log b/pll0/pll0_generate.log
new file mode 100644
index 0000000..debabd5
--- /dev/null
+++ b/pll0/pll0_generate.log
@@ -0,0 +1,45 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:13 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 300 -fclkop_tol 0.0 -fclkos 300 -fclkos_tol 0.0 -phases 45 -fclkos2 300 -fclkos2_tol 0.0 -phases2 90 -fclkos3 300 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS, CLKOS2, CLKOS3
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    Verilog output   : pll0.v
+    Verilog template : pll0_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: pll0.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/pll0/pll0_tmpl.v b/pll0/pll0_tmpl.v
new file mode 100644
index 0000000..4b2ffe1
--- /dev/null
+++ b/pll0/pll0_tmpl.v
@@ -0,0 +1,6 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* Wed Oct 21 10:28:14 2020 */
+
+/* parameterized module instance */
+pll0 __ (.CLKI( ), .CLKOP( ), .CLKOS( ), .CLKOS2( ), .CLKOS3( ));
diff --git a/pll1/generate_core.tcl b/pll1/generate_core.tcl
new file mode 100644
index 0000000..097d60e
--- /dev/null
+++ b/pll1/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "pll1"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/pll1/generate_ngd.tcl b/pll1/generate_ngd.tcl
new file mode 100644
index 0000000..4b1c124
--- /dev/null
+++ b/pll1/generate_ngd.tcl
@@ -0,0 +1,115 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "pll1"
+set Para(Module) "PLL"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create response file(*.cmd) for Synpwrap
+proc CreateCmdFile {} {
+	global Para
+
+	file mkdir "$Para(sbp_path)/syn_results"
+	if [catch {open $Para(ModuleName).cmd w} rspFile] {
+		puts "Cannot create response file $Para(ModuleName).cmd."
+		exit -1
+	} else {
+		puts $rspFile "PROJECT: $Para(ModuleName)
+		working_path: \"$Para(sbp_path)/syn_results\"
+		module: $Para(ModuleName)
+		verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/ecp5um.v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
+		vlog_std_v2001: true
+		constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
+		suffix_name: edn
+		output_file_name: $Para(ModuleName)
+		write_prf: true
+		disable_io_insertion: true
+		force_gsr: false
+		frequency: $Para(FMax)
+		fanout_limit: 50
+		retiming: false
+		pipe: false
+		part: $Para(PartType)
+		speed_grade: $Para(SpeedGrade)
+		"
+		close $rspFile
+	}
+}
+
+#synpwrap
+CreateCmdFile
+set synpwrap "$Para(bin_dir)/synpwrap"
+if {[file exists $fdcfile] == 0} {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
+} else {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
+}
+#puts $msg
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/pll1/msg_file.log b/pll1/msg_file.log
new file mode 100644
index 0000000..bcc50d2
--- /dev/null
+++ b/pll1/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:24 2020
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll1
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+    Inputs       : CLKI
+    Outputs      : CLKOP
+    I/O buffer       : not inserted
+    EDIF output      : pll1.edn
+    Verilog output   : pll1.v
+    Verilog template : pll1_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll1.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/pll1/pll1.edn b/pll1/pll1.edn
new file mode 100644
index 0000000..02a3fb6
--- /dev/null
+++ b/pll1/pll1.edn
@@ -0,0 +1,205 @@
+(edif pll1
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 10 21 10 28 25)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell EHXPLLL
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port PHASELOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell pll1
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLL))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "0"))
+            (property CLKOS3_CPHASE
+              (string "0"))
+            (property CLKOS2_FPHASE
+              (string "0"))
+            (property CLKOS2_CPHASE
+              (string "0"))
+            (property CLKOS_FPHASE
+              (string "0"))
+            (property CLKOS_CPHASE
+              (string "0"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "3"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "FALLING"))
+            (property OUTDIVIDER_MUXD
+              (string "DIVD"))
+            (property CLKOS3_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXC
+              (string "DIVC"))
+            (property CLKOS2_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXB
+              (string "DIVB"))
+            (property CLKOS_ENABLE
+              (string "DISABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "150.000000"))
+            (property OUTDIVIDER_MUXA
+              (string "DIVA"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "300.000000"))
+            (property ICP_CURRENT
+              (string "10"))
+            (property LPF_RESISTOR
+              (string "24"))
+            (property CLKOS3_DIV
+              (string "1"))
+            (property CLKOS2_DIV
+              (string "1"))
+            (property CLKOS_DIV
+              (string "1"))
+            (property CLKOP_DIV
+              (string "4"))
+            (property CLKFB_DIV
+              (string "1"))
+            (property CLKI_DIV
+              (string "2"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net REFCLK
+            (joined
+              (portRef REFCLK (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef PHASELOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef CLKI (instanceRef PLLInst_0))))))))
+  (design pll1
+    (cellRef pll1
+      (libraryRef ORCLIB)))
+)
diff --git a/pll1/pll1.fdc b/pll1/pll1.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/pll1/pll1.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/pll1/pll1.lpc b/pll1/pll1.lpc
new file mode 100644
index 0000000..eda7ea4
--- /dev/null
+++ b/pll1/pll1.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll1
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=10/21/2020
+Time=10:28:23
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=300
+CLKI_DIV=2
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=150
+CLKOP_TOL=0.0
+CLKOP_DIV=4
+CLKOP_ACTUAL_FREQ=150.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=DISABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=1
+CLKOS_ACTUAL_FREQ=
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=10.504
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1
diff --git a/pll1/pll1.sbx b/pll1/pll1.sbx
new file mode 100644
index 0000000..9a875ce
--- /dev/null
+++ b/pll1/pll1.sbx
@@ -0,0 +1,430 @@
+<!DOCTYPE pll1>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll1.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll1.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Generation</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>GENERATE</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2020-07-28.09:20:26 AM</lattice:date>
+            <lattice:modified>2020-10-21.10:28:25 AM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10/21/2020</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">pll1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10:28:23</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">150.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">150</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IOBUF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_BW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10.504</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>REFERENCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll1</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/pll1/pll1.srp b/pll1/pll1.srp
new file mode 100644
index 0000000..808fdf6
--- /dev/null
+++ b/pll1/pll1.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:25 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.fdc 
+    Circuit name     : pll1
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP
+    I/O buffer       : not inserted
+    EDIF output      : pll1.edn
+    Verilog output   : pll1.v
+    Verilog template : pll1_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll1.srp
+    Element Usage    :
+        EHXPLLL : 1
+    Estimated Resource Usage:
diff --git a/pll1/pll1.v b/pll1/pll1.v
new file mode 100644
index 0000000..25c58e0
--- /dev/null
+++ b/pll1/pll1.v
@@ -0,0 +1,75 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.fdc  */
+/* Wed Oct 21 10:28:25 2020 */
+
+
+`timescale 1 ns / 1 ps
+module pll1 (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */;
+    input wire CLKI;
+    output wire CLKOP;
+
+    wire REFCLK;
+    wire LOCK;
+    wire CLKOP_t;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 3 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 1 ;
+    defparam PLLInst_0.CLKOS2_DIV = 1 ;
+    defparam PLLInst_0.CLKOS_DIV = 1 ;
+    defparam PLLInst_0.CLKOP_DIV = 4 ;
+    defparam PLLInst_0.CLKFB_DIV = 1 ;
+    defparam PLLInst_0.CLKI_DIV = 2 ;
+    defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), 
+        .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOP="150.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="300.000000" */
+             /* synthesis ICP_CURRENT="10" */
+             /* synthesis LPF_RESISTOR="24" */;
+
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 150.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 300.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 10
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 24
+    // exemplar end
+
+endmodule
diff --git a/pll1/pll1_generate.log b/pll1/pll1_generate.log
new file mode 100644
index 0000000..18ac4fb
--- /dev/null
+++ b/pll1/pll1_generate.log
@@ -0,0 +1,45 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:24 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 150 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll1
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP
+    I/O buffer       : not inserted
+    EDIF output      : pll1.edn
+    Verilog output   : pll1.v
+    Verilog template : pll1_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll1.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: pll1.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/pll1/pll1_tmpl.v b/pll1/pll1_tmpl.v
new file mode 100644
index 0000000..afcbe67
--- /dev/null
+++ b/pll1/pll1_tmpl.v
@@ -0,0 +1,6 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* Wed Oct 21 10:28:25 2020 */
+
+/* parameterized module instance */
+pll1 __ (.CLKI( ), .CLKOP( ));
diff --git a/pll8/generate_core.tcl b/pll8/generate_core.tcl
new file mode 100644
index 0000000..0821790
--- /dev/null
+++ b/pll8/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "pll8"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/pll8/generate_ngd.tcl b/pll8/generate_ngd.tcl
new file mode 100644
index 0000000..3254d66
--- /dev/null
+++ b/pll8/generate_ngd.tcl
@@ -0,0 +1,115 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "pll8"
+set Para(Module) "PLL"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create response file(*.cmd) for Synpwrap
+proc CreateCmdFile {} {
+	global Para
+
+	file mkdir "$Para(sbp_path)/syn_results"
+	if [catch {open $Para(ModuleName).cmd w} rspFile] {
+		puts "Cannot create response file $Para(ModuleName).cmd."
+		exit -1
+	} else {
+		puts $rspFile "PROJECT: $Para(ModuleName)
+		working_path: \"$Para(sbp_path)/syn_results\"
+		module: $Para(ModuleName)
+		verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/ecp5um.v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
+		vlog_std_v2001: true
+		constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
+		suffix_name: edn
+		output_file_name: $Para(ModuleName)
+		write_prf: true
+		disable_io_insertion: true
+		force_gsr: false
+		frequency: $Para(FMax)
+		fanout_limit: 50
+		retiming: false
+		pipe: false
+		part: $Para(PartType)
+		speed_grade: $Para(SpeedGrade)
+		"
+		close $rspFile
+	}
+}
+
+#synpwrap
+CreateCmdFile
+set synpwrap "$Para(bin_dir)/synpwrap"
+if {[file exists $fdcfile] == 0} {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
+} else {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
+}
+#puts $msg
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/pll8/msg_file.log b/pll8/msg_file.log
new file mode 100644
index 0000000..bc38968
--- /dev/null
+++ b/pll8/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:34 2020
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll8
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+    Inputs       : CLKI
+    Outputs      : CLKOP, CLKOS
+    I/O buffer       : not inserted
+    EDIF output      : pll8.edn
+    Verilog output   : pll8.v
+    Verilog template : pll8_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll8.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/pll8/pll8.edn b/pll8/pll8.edn
new file mode 100644
index 0000000..9f45be9
--- /dev/null
+++ b/pll8/pll8.edn
@@ -0,0 +1,213 @@
+(edif pll8
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 10 21 10 28 36)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell EHXPLLL
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port PHASELOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell pll8
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLL))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "0"))
+            (property CLKOS3_CPHASE
+              (string "0"))
+            (property CLKOS2_FPHASE
+              (string "0"))
+            (property CLKOS2_CPHASE
+              (string "0"))
+            (property CLKOS_FPHASE
+              (string "0"))
+            (property CLKOS_CPHASE
+              (string "74"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "5"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "FALLING"))
+            (property OUTDIVIDER_MUXD
+              (string "DIVD"))
+            (property CLKOS3_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXC
+              (string "DIVC"))
+            (property CLKOS2_ENABLE
+              (string "DISABLED"))
+            (property FREQUENCY_PIN_CLKOS
+              (string "8.000000"))
+            (property OUTDIVIDER_MUXB
+              (string "DIVB"))
+            (property CLKOS_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "100.000000"))
+            (property OUTDIVIDER_MUXA
+              (string "DIVA"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "300.000000"))
+            (property ICP_CURRENT
+              (string "9"))
+            (property LPF_RESISTOR
+              (string "72"))
+            (property CLKOS3_DIV
+              (string "1"))
+            (property CLKOS2_DIV
+              (string "1"))
+            (property CLKOS_DIV
+              (string "75"))
+            (property CLKOP_DIV
+              (string "6"))
+            (property CLKFB_DIV
+              (string "1"))
+            (property CLKI_DIV
+              (string "3"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net REFCLK
+            (joined
+              (portRef REFCLK (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef PHASELOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net CLKOS
+            (joined
+              (portRef CLKOS)
+              (portRef CLKOS (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef CLKI (instanceRef PLLInst_0))))))))
+  (design pll8
+    (cellRef pll8
+      (libraryRef ORCLIB)))
+)
diff --git a/pll8/pll8.fdc b/pll8/pll8.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/pll8/pll8.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/pll8/pll8.lpc b/pll8/pll8.lpc
new file mode 100644
index 0000000..a266141
--- /dev/null
+++ b/pll8/pll8.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll8
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=10/21/2020
+Time=10:28:34
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=300
+CLKI_DIV=3
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=100
+CLKOP_TOL=0.5
+CLKOP_DIV=6
+CLKOP_ACTUAL_FREQ=100.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=8
+CLKOS_TOL=0.5
+CLKOS_DIV=75
+CLKOS_ACTUAL_FREQ=8.000000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.5
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.5
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=8.185
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1
diff --git a/pll8/pll8.sbx b/pll8/pll8.sbx
new file mode 100644
index 0000000..60da031
--- /dev/null
+++ b/pll8/pll8.sbx
@@ -0,0 +1,430 @@
+<!DOCTYPE pll8>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll8.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll8.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Generation</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>GENERATE</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2020-09-15.12:05:50 PM</lattice:date>
+            <lattice:modified>2020-10-21.10:28:36 AM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10/21/2020</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">pll8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10:28:34</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">6</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.5</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.5</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.5</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">75</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.5</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IOBUF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_BW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8.185</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>REFERENCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll8</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/pll8/pll8.srp b/pll8/pll8.srp
new file mode 100644
index 0000000..1fcbf77
--- /dev/null
+++ b/pll8/pll8.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:36 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.fdc 
+    Circuit name     : pll8
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS
+    I/O buffer       : not inserted
+    EDIF output      : pll8.edn
+    Verilog output   : pll8.v
+    Verilog template : pll8_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll8.srp
+    Element Usage    :
+        EHXPLLL : 1
+    Estimated Resource Usage:
diff --git a/pll8/pll8.v b/pll8/pll8.v
new file mode 100644
index 0000000..2687341
--- /dev/null
+++ b/pll8/pll8.v
@@ -0,0 +1,80 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.fdc  */
+/* Wed Oct 21 10:28:36 2020 */
+
+
+`timescale 1 ns / 1 ps
+module pll8 (CLKI, CLKOP, CLKOS)/* synthesis NGD_DRC_MASK=1 */;
+    input wire CLKI;
+    output wire CLKOP;
+    output wire CLKOS;
+
+    wire REFCLK;
+    wire LOCK;
+    wire CLKOS_t;
+    wire CLKOP_t;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 74 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 5 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 1 ;
+    defparam PLLInst_0.CLKOS2_DIV = 1 ;
+    defparam PLLInst_0.CLKOS_DIV = 75 ;
+    defparam PLLInst_0.CLKOP_DIV = 6 ;
+    defparam PLLInst_0.CLKFB_DIV = 1 ;
+    defparam PLLInst_0.CLKI_DIV = 3 ;
+    defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(), 
+        .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOS="8.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="300.000000" */
+             /* synthesis ICP_CURRENT="9" */
+             /* synthesis LPF_RESISTOR="72" */;
+
+    assign CLKOS = CLKOS_t;
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 8.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 300.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 9
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 72
+    // exemplar end
+
+endmodule
diff --git a/pll8/pll8_generate.log b/pll8/pll8_generate.log
new file mode 100644
index 0000000..418814b
--- /dev/null
+++ b/pll8/pll8_generate.log
@@ -0,0 +1,45 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:34 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll8 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100 -fclkop_tol 0.5 -fclkos 8 -fclkos_tol 0.5 -phases 0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll8
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS
+    I/O buffer       : not inserted
+    EDIF output      : pll8.edn
+    Verilog output   : pll8.v
+    Verilog template : pll8_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll8.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: pll8.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/pll8/pll8_tmpl.v b/pll8/pll8_tmpl.v
new file mode 100644
index 0000000..ed37d49
--- /dev/null
+++ b/pll8/pll8_tmpl.v
@@ -0,0 +1,6 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* Wed Oct 21 10:28:36 2020 */
+
+/* parameterized module instance */
+pll8 __ (.CLKI( ), .CLKOP( ), .CLKOS( ));
diff --git a/pll_random/generate_core.tcl b/pll_random/generate_core.tcl
new file mode 100644
index 0000000..ffcd254
--- /dev/null
+++ b/pll_random/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "pll_random"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "sa5p00g"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/pll_random/generate_ngd.tcl b/pll_random/generate_ngd.tcl
new file mode 100644
index 0000000..0b830f6
--- /dev/null
+++ b/pll_random/generate_ngd.tcl
@@ -0,0 +1,115 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "pll_random"
+set Para(Module) "PLL"
+set Para(libname) ecp5um5g
+set Para(arch_name) sa5p00g
+set Para(PartType) "LFE5UM5G-45F"
+
+set Para(tech_syn) ecp5um5g
+set Para(tech_cae) ecp5um5g
+set Para(Package) "CABGA381"
+set Para(SpeedGrade) "8"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create response file(*.cmd) for Synpwrap
+proc CreateCmdFile {} {
+	global Para
+
+	file mkdir "$Para(sbp_path)/syn_results"
+	if [catch {open $Para(ModuleName).cmd w} rspFile] {
+		puts "Cannot create response file $Para(ModuleName).cmd."
+		exit -1
+	} else {
+		puts $rspFile "PROJECT: $Para(ModuleName)
+		working_path: \"$Para(sbp_path)/syn_results\"
+		module: $Para(ModuleName)
+		verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/ecp5um.v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
+		vlog_std_v2001: true
+		constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
+		suffix_name: edn
+		output_file_name: $Para(ModuleName)
+		write_prf: true
+		disable_io_insertion: true
+		force_gsr: false
+		frequency: $Para(FMax)
+		fanout_limit: 50
+		retiming: false
+		pipe: false
+		part: $Para(PartType)
+		speed_grade: $Para(SpeedGrade)
+		"
+		close $rspFile
+	}
+}
+
+#synpwrap
+CreateCmdFile
+set synpwrap "$Para(bin_dir)/synpwrap"
+if {[file exists $fdcfile] == 0} {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
+} else {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
+}
+#puts $msg
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/pll_random/msg_file.log b/pll_random/msg_file.log
new file mode 100644
index 0000000..dabecc3
--- /dev/null
+++ b/pll_random/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:44 2020
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll_random
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+    Inputs       : CLKI
+    Outputs      : CLKOP, CLKOS, CLKOS2
+    I/O buffer       : not inserted
+    EDIF output      : pll_random.edn
+    Verilog output   : pll_random.v
+    Verilog template : pll_random_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll_random.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/pll_random/pll_random.edn b/pll_random/pll_random.edn
new file mode 100644
index 0000000..71a8a71
--- /dev/null
+++ b/pll_random/pll_random.edn
@@ -0,0 +1,221 @@
+(edif pll_random
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 10 21 10 28 46)
+      (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446"))))
+      (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell EHXPLLL
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port PHASELOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell pll_random
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLL))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "0"))
+            (property CLKOS3_CPHASE
+              (string "0"))
+            (property CLKOS2_FPHASE
+              (string "0"))
+            (property CLKOS2_CPHASE
+              (string "15"))
+            (property CLKOS_FPHASE
+              (string "0"))
+            (property CLKOS_CPHASE
+              (string "2"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "7"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "FALLING"))
+            (property OUTDIVIDER_MUXD
+              (string "DIVD"))
+            (property CLKOS3_ENABLE
+              (string "DISABLED"))
+            (property FREQUENCY_PIN_CLKOS2
+              (string "50.000000"))
+            (property OUTDIVIDER_MUXC
+              (string "DIVC"))
+            (property CLKOS2_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOS
+              (string "266.666667"))
+            (property OUTDIVIDER_MUXB
+              (string "DIVB"))
+            (property CLKOS_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "100.000000"))
+            (property OUTDIVIDER_MUXA
+              (string "DIVA"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "300.000000"))
+            (property ICP_CURRENT
+              (string "12"))
+            (property LPF_RESISTOR
+              (string "72"))
+            (property CLKOS3_DIV
+              (string "1"))
+            (property CLKOS2_DIV
+              (string "16"))
+            (property CLKOS_DIV
+              (string "3"))
+            (property CLKOP_DIV
+              (string "8"))
+            (property CLKFB_DIV
+              (string "1"))
+            (property CLKI_DIV
+              (string "3"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net REFCLK
+            (joined
+              (portRef REFCLK (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef PHASELOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net CLKOS2
+            (joined
+              (portRef CLKOS2)
+              (portRef CLKOS2 (instanceRef PLLInst_0))))
+          (net CLKOS
+            (joined
+              (portRef CLKOS)
+              (portRef CLKOS (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef CLKI (instanceRef PLLInst_0))))))))
+  (design pll_random
+    (cellRef pll_random
+      (libraryRef ORCLIB)))
+)
diff --git a/pll_random/pll_random.fdc b/pll_random/pll_random.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/pll_random/pll_random.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/pll_random/pll_random.lpc b/pll_random/pll_random.lpc
new file mode 100644
index 0000000..1b2ed20
--- /dev/null
+++ b/pll_random/pll_random.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-45F
+PartName=LFE5UM5G-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_random
+SourceFormat=verilog
+ParameterFileVersion=1.0
+Date=10/21/2020
+Time=10:28:44
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=300
+CLKI_DIV=3
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=100.00
+CLKOP_TOL=2.0
+CLKOP_DIV=8
+CLKOP_ACTUAL_FREQ=100.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=270
+CLKOS_TOL=2.0
+CLKOS_DIV=3
+CLKOS_ACTUAL_FREQ=266.666667
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=50
+CLKOS2_TOL=2.0
+CLKOS2_DIV=16
+CLKOS2_ACTUAL_FREQ=50.000000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=2.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=800.000
+PLL_BW=7.980
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1
diff --git a/pll_random/pll_random.sbx b/pll_random/pll_random.sbx
new file mode 100644
index 0000000..46bc724
--- /dev/null
+++ b/pll_random/pll_random.sbx
@@ -0,0 +1,430 @@
+<!DOCTYPE pll_random>
+<lattice:project mode="SingleComponent">
+    <spirit:component>
+        <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+        <spirit:library>LEGACY</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>5.8</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll_random.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll_random.v</spirit:name>
+                    <spirit:fileType>verilogSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Configuration</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>CONFIG</spirit:group>
+            </spirit:componentGenerator>
+            <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                <spirit:name>Generation</spirit:name>
+                <spirit:apiType>none</spirit:apiType>
+                <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                <spirit:group>GENERATE</spirit:group>
+            </spirit:componentGenerator>
+        </spirit:componentGenerators>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports/>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM5G-45F-8BG381C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2020-09-15.12:31:18 PM</lattice:date>
+            <lattice:modified>2020-10-21.10:28:46 AM</lattice:modified>
+            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:language>Verilog</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc>
+                <lattice:lpcsection lattice:name="Device"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Family</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ecp5um5g</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Package</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F-8BG381C</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PartType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM5G-45F</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Status</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="IP"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreRevision</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreStatus</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CoreType</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Date</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10/21/2020</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ModuleName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">pll_random</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>SourceFormat</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Time</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">10:28:44</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VendorName</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Parameters"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">300</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">50.000000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">50</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">266.666667</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">270</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">2.0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Destination</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>EDIF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Expression</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IO</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>IOBUF</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Order</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_BW</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">7.980</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>REFERENCE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">800.000</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>VHDL</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcentry>
+                    <lattice:lpckey>Verilog</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                </lattice:lpcentry>
+                <lattice:lpcsection lattice:name="Command"/>
+                <lattice:lpcentry>
+                    <lattice:lpckey>cmd_line</lattice:lpckey>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+                </lattice:lpcentry>
+            </lattice:lpc>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll_random</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances/>
+        <spirit:adHocConnections/>
+    </spirit:design>
+</lattice:project>
diff --git a/pll_random/pll_random.srp b/pll_random/pll_random.srp
new file mode 100644
index 0000000..afc2faa
--- /dev/null
+++ b/pll_random/pll_random.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:46 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.fdc 
+    Circuit name     : pll_random
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS, CLKOS2
+    I/O buffer       : not inserted
+    EDIF output      : pll_random.edn
+    Verilog output   : pll_random.v
+    Verilog template : pll_random_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll_random.srp
+    Element Usage    :
+        EHXPLLL : 1
+    Estimated Resource Usage:
diff --git a/pll_random/pll_random.v b/pll_random/pll_random.v
new file mode 100644
index 0000000..c770d7b
--- /dev/null
+++ b/pll_random/pll_random.v
@@ -0,0 +1,85 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.fdc  */
+/* Wed Oct 21 10:28:46 2020 */
+
+
+`timescale 1 ns / 1 ps
+module pll_random (CLKI, CLKOP, CLKOS, CLKOS2)/* synthesis NGD_DRC_MASK=1 */;
+    input wire CLKI;
+    output wire CLKOP;
+    output wire CLKOS;
+    output wire CLKOS2;
+
+    wire REFCLK;
+    wire LOCK;
+    wire CLKOS2_t;
+    wire CLKOS_t;
+    wire CLKOP_t;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 15 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 2 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 7 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 1 ;
+    defparam PLLInst_0.CLKOS2_DIV = 16 ;
+    defparam PLLInst_0.CLKOS_DIV = 3 ;
+    defparam PLLInst_0.CLKOP_DIV = 8 ;
+    defparam PLLInst_0.CLKFB_DIV = 1 ;
+    defparam PLLInst_0.CLKI_DIV = 3 ;
+    defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), 
+        .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOS2="50.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOS="266.666667" */
+             /* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="300.000000" */
+             /* synthesis ICP_CURRENT="12" */
+             /* synthesis LPF_RESISTOR="72" */;
+
+    assign CLKOS2 = CLKOS2_t;
+    assign CLKOS = CLKOS_t;
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 50.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 266.666667
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 300.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 12
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 72
+    // exemplar end
+
+endmodule
diff --git a/pll_random/pll_random_generate.log b/pll_random/pll_random_generate.log
new file mode 100644
index 0000000..703ee2e
--- /dev/null
+++ b/pll_random/pll_random_generate.log
@@ -0,0 +1,45 @@
+Starting process: 
+
+Configuration data saved
+
+
+SCUBA, Version Diamond (64-bit) 3.11.2.446
+Wed Oct 21 10:28:44 2020
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_random -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 300 -fclkop 100.00 -fclkop_tol 2.0 -fclkos 270 -fclkos_tol 2.0 -phases 0 -fclkos2 50 -fclkos2_tol 2.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 
+    Circuit name     : pll_random
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, CLKOS, CLKOS2
+    I/O buffer       : not inserted
+    EDIF output      : pll_random.edn
+    Verilog output   : pll_random.v
+    Verilog template : pll_random_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll_random.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: pll_random.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/pll_random/pll_random_tmpl.v b/pll_random/pll_random_tmpl.v
new file mode 100644
index 0000000..871b63f
--- /dev/null
+++ b/pll_random/pll_random_tmpl.v
@@ -0,0 +1,6 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */
+/* Module Version: 5.7 */
+/* Wed Oct 21 10:28:46 2020 */
+
+/* parameterized module instance */
+pll_random __ (.CLKI( ), .CLKOP( ), .CLKOS( ), .CLKOS2( ));
diff --git a/promote.xml b/promote.xml
new file mode 100644
index 0000000..fa627e9
--- /dev/null
+++ b/promote.xml
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<userSetting name="/home/hadaq/mmichalek/lattice/simplified/promote.xml" version="Diamond (64-bit) 3.11.2.446" date="Wed Jun  2 16:44:41 2021" vendor="Lattice Semiconductor Corporation" >
+</userSetting>
diff --git a/reportview.xml b/reportview.xml
new file mode 100644
index 0000000..bf62897
--- /dev/null
+++ b/reportview.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE Report>
+<ReportView version="2.0">
+    <Implement name="impl1">
+        <ToolReport id="tooldec" path="" status="0"/>
+        <ToolReport id="toolhle_genhierarchy" path="/home/hadaq/mmichalek/lattice/simplified/impl1/hdla_gen_hierarchy.html" status="1"/>
+        <ToolReport id="toolpio" path="" status="2"/>
+        <ToolReport id="toolsso" path="" status="2"/>
+    </Implement>
+</ReportView>
diff --git a/s1.ccl b/s1.ccl
new file mode 100644
index 0000000..e69de29
diff --git a/s1.ldf b/s1.ldf
new file mode 100644
index 0000000..1c20b7f
--- /dev/null
+++ b/s1.ldf
@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="s1" device="LFE5UM5G-45F-8BG381C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="trb5_tb" top="top_tf"/>
+        <Source name="top.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="pll0/pll0.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="pll1/pll1.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="fifo32dc/fifo32dc.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/intface.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/modem.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/rxcver.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/txmitt.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/uart_top.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../multipll/uart/source/UART_VerilogWrapper_TOP.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="pll8/pll8.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="pll_random/pll_random.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="modules.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="modules2.v" type="Verilog" type_short="Verilog">
+            <Options>
+                <Option name="include path" value="tdc_channel_fifo_out"/>
+            </Options>
+        </Source>
+        <Source name="fifo_colector.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="fifo40_dc/fifo40_dc.sbx" type="sbx" type_short="SBX">
+            <Options/>
+        </Source>
+        <Source name="top2.v" type="Verilog" type_short="Verilog">
+            <Options top_module="top_tf"/>
+        </Source>
+        <Source name="trb5_tb.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="endp_dummy.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="endp_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="hades_modules.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="hades_modules2.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="s1.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="s11.sty"/>
+</BaliProject>
diff --git a/s1.lpf b/s1.lpf
new file mode 100644
index 0000000..c28ebdc
--- /dev/null
+++ b/s1.lpf
@@ -0,0 +1,519 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+//PERIOD NET "clks_0" 1.000 ns HIGH 0.500 ns ;
+//BLOCK PATH FROM CELL "tdc4inst/out_0" TO CELL "tdc4inst/out_0" ;
+//BLOCK PATH FROM CELL "tdc4inst/out_2" TO CELL "tdc4inst/out_2" ;
+//BLOCK PATH FROM CELL "tdc4inst/out_3" TO CELL "tdc4inst/out_3" ; 
+//BLOCK PATH TO PORT "pll_clks[1]*";
+//BLOCK NET "tdc_out*" ;
+//BLOCK NET "tdc_buffered_out" ;
+BLOCK NET "tdc_out*" ;
+BLOCK NET "trig*" ;
+BLOCK NET "reset*" ;
+//BLOCK NET "dec_inst*" ;
+//BLOCK NET "in_synced*" ;
+//BLOCK PATH from CELL "tdc8ddr_w_decoder_inst/desynced/*" to CELL "tdc8ddr_w_decoder/out/*";
+//BLOCK INTERCLOCKDOMAIN PATHS;
+//BLOCK NET "pll_clks*" ;
+//BLOCK NET "secondary_clks*" ;
+//FBEXTDELAY PCM "pll0inst" from port "CLKOP/pll0inst" to port "CLKFB/pll1inst" 2ns;
+//FBEXTDELAY PCM "pll1inst" FROM PORT "CLKFB/pll1inst" TO PORT "CLKFB/pll1inst" 2.000000 ns;
+//FREQUENCY PORT "clk_ref" 1.0000000 MHz;
+//INPUT_SETUP PORT "cnt" 2.000000 ns CLKPORT "clk" ;
+//INPUT_SETUP PORT "trigger*" 2.000000 ns CLKPORT "pll_clks_c_0" ;
+//CLOCK_TO_OUT "cnt[0]" 2 ns CLKPORT "clk" CLKOUT PORT "clk_ref";
+//CLOCK_TO_OUT "cnt[1]" 20 ns CLKPORT "clk" CLKOUT PORT "clk_ref";
+//CLOCK_TO_OUT "cnt[0]" CLKPORT "clk" CLKOUT PORT "clk_ref";
+FREQUENCY PORT "clk" 100.000000 MHz ;
+FREQUENCY NET "pll_clks*" 300.000000 MHz ;
+//FREQUENCY PORT "clk25" 25.000000 MHz ;
+//FREQUENCY PORT "clk8" 8.000000 MHz ;
+//FREQUENCY NET "pll0inst.pll_clks[0]" 10.000000 MHz ;
+//CLOCK_TO_OUT "cnt[0]" MAX 5.5 ns MIN 4.5 ns CLKPORT "clk" ;
+//CLOCK_TO_OUT "cnt[1]" MAX 15 ns MIN 14.5 ns CLKPORT "clk" ;
+//UGROUP "ffarr7groupB" BBOX 1 2 DEVSIZE
+//	COMP "*s_out*";
+//REGION "FFARR0A" "R69C7D" 1 2 DEVSIZE;
+//LOCATE UGROUP "ffarr7groupB" REGION "FFARR0A" ;
+//INPUT_SETUP PORT "cnt[1]" 14.9 ns CLKPORT "clk" ;
+//CLOCK_TO_OUT "pwm" 2.0 ns CLKPORT "clk" FROM "top/cnt*" CLKOUT PORT "clk";
+//UGROUP "ug1" BBOX 1 1 
+//	BLKNAME s_out[0]
+//	BLKNAME s_out[1];
+//LOCATE UGROUP "ug1" SITE "R61C46D" ;
+//UGROUP "ug2" BBOX 5 5 
+//	BLKNAME s_in[2]
+//	BLKNAME s_in[3];
+//LOCATE COMP "pulse_out" SITE "A18" ;
+LOCATE COMP "reset" SITE "D11" ;
+LOCATE COMP "clk" SITE "P3" ;
+IOBUF PORT "clk" IO_TYPE=LVDS ;
+//LOCATE COMP "clk25" SITE "J20" ;
+//LOCATE COMP "pulse_async" SITE "C17" ;
+PROHIBIT SITE "IOL_B18A" ;
+UGROUP "trig_gate0" BBOX 1 1 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO
+	BLKNAME trig_pad_RNII4FF[0];
+LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;
+UGROUP "tdc_ch0" BBOX 1 6 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;
+LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;
+//LOCATE COMP "trig[0]" SITE "B18" ;
+//LOCATE COMP "trig[1]" SITE "B17" ;
+//LOCATE COMP "txd[0]" SITE "B19" ;
+//LOCATE COMP "txd[1]" SITE "B9" ;
+//LOCATE COMP "diff_txd" SITE "D6" ;
+//LOCATE COMP "zero_in" SITE "A12" ;
+//LOCATE COMP "zero_out" SITE "B13" ;
+UGROUP "tdc2" BBOX 1 6 
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;
+LOCATE UGROUP "tdc2" SITE "R65C41D" ;
+UGROUP "tdc0" BBOX 1 4 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "tdc0" SITE "R68C14D" ;
+UGROUP "tdc22" BBOX 1 4 
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "tdc22" SITE "R66C41D" ;
+UGROUP "gate2" BBOX 1 1 
+	BLKNAME trig_pad_RNIJ5FF[1];
+LOCATE UGROUP "gate2" SITE "R67C41D" ;
+UGROUP "tdc3" BBOX 1 4 
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "tdc3" SITE "R66C49D" ;
+UGROUP "trig3" BBOX 1 1 
+	BLKNAME trig_pad_RNIK6FF[2];
+LOCATE UGROUP "trig3" SITE "R67C49D" ;
+UGROUP "dec3" BBOX 1 6 
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[0]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[1]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
+	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;
+LOCATE UGROUP "dec3" SITE "R65C49D" ;
+UGROUP "tdc0_neg" BBOX 1 4 
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered1[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered1[7]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
+	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;
+LOCATE COMP "trig[0]" SITE "R2" ;
+LOCATE COMP "trig[1]" SITE "T3" ;
+LOCATE COMP "trig[2]" SITE "T19" ;
+PROHIBIT SITE "IOL_B15A" ;
+LOCATE COMP "hades_trig" SITE "H5" ;
+UGROUP "hades_trig" BBOX 1 1 
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1;
+LOCATE UGROUP "hades_trig" SITE "R28C2D" ;
+UGROUP "hades_tdc_pos" BBOX 1 4 
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered1[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered1[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "hades_tdc_pos" SITE "R28C3D" ;
+UGROUP "hades_tdc_neg" BBOX 1 4 
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/VCC
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered1[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered1[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "hades_tdc_neg" SITE "R29C3D" ;
+PROHIBIT SITE "IOL_L29C" ;
+PROHIBIT SITE "IOL_L29B" ;
+PROHIBIT SITE "IOL_L29D" ;
+UGROUP "hades_dec_pos" BBOX 1 6 
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/VCC
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i_3
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0_1
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_m3
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO;
+LOCATE UGROUP "hades_dec_pos" SITE "R27C2D" ;
+UGROUP "hades_dec_neg" BBOX 1 6 
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/VCC
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal
+	BLKNAME hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO;
+LOCATE UGROUP "hades_dec_neg" SITE "R30C2D" ;
+LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9" ;
+UGROUP "lvl1_dec" BBOX 1 6 
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/VCC
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_7_.CN
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i_3
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0_1
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_m3
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO;
+LOCATE UGROUP "lvl1_dec" SITE "R26C2D" ;
+UGROUP "lvl1_pad" BBOX 1 1 
+	BLKNAME hades_lvl1_pad_RNINMH5;
+LOCATE UGROUP "lvl1_pad" SITE "R25C2D" ;
+UGROUP "lvl1_tdc" BBOX 1 4 
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/VCC
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered1[3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered1[7]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3]
+	BLKNAME hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7];
+LOCATE UGROUP "lvl1_tdc" SITE "R25C3D" ;
+LOCATE COMP "hades_lvl1" SITE "E1" ;
diff --git a/s11.sty b/s11.sty
new file mode 100644
index 0000000..84a4f62
--- /dev/null
+++ b/s11.sty
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="True" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="False" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="True" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="True" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="True" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="True" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="True" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="True" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/s1_tcl.html b/s1_tcl.html
new file mode 100644
index 0000000..e292f7f
--- /dev/null
+++ b/s1_tcl.html
@@ -0,0 +1,236 @@
+<HTML>
+<HEAD><TITLE>Lattice TCL Log</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
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}
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    font-weight: bold;
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}
p {
    font-size:78%;
}
P.Table {
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}
table
{
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}
th {
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    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
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}
a {
    color:#013C9A;
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}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
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}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="pn201116201457"></A><B><U><big>pn201116201457</big></U></B>
+#Start recording tcl command: 11/13/2020 10:17:07
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/modules.v"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Promgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+#Stop recording: 11/16/2020 20:14:57
+
+
+
+<A name="pn210124231721"></A><B><U><big>pn210124231721</big></U></B>
+#Start recording tcl command: 1/24/2021 23:16:12
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+launch_synplify_prj impl1
+#Stop recording: 1/24/2021 23:17:21
+
+
+
+<A name="pn210124232433"></A><B><U><big>pn210124232433</big></U></B>
+#Start recording tcl command: 1/24/2021 23:19:17
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+launch_synplify_prj impl1
+#Stop recording: 1/24/2021 23:24:33
+
+
+
+<A name="pn210126141734"></A><B><U><big>pn210126141734</big></U></B>
+#Start recording tcl command: 1/26/2021 13:18:43
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 1/26/2021 14:17:34
+
+
+
+<A name="pn210208120414"></A><B><U><big>pn210208120414</big></U></B>
+#Start recording tcl command: 2/8/2021 12:03:25
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 2/8/2021 12:04:14
+
+
+
+<A name="pn210526194824"></A><B><U><big>pn210526194824</big></U></B>
+#Start recording tcl command: 5/11/2021 08:45:22
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"
+#Stop recording: 5/26/2021 19:48:24
+
+
+
+<A name="pn210528165033"></A><B><U><big>pn210528165033</big></U></B>
+#Start recording tcl command: 5/26/2021 19:48:48
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_project save
+prj_project close
+#Stop recording: 5/28/2021 16:50:33
+
+
+
+<A name="pn210531201634"></A><B><U><big>pn210531201634</big></U></B>
+#Start recording tcl command: 5/31/2021 17:24:05
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"
+prj_project save
+prj_project close
+#Stop recording: 5/31/2021 20:16:34
+
+
+
+<A name="pn210601055409"></A><B><U><big>pn210601055409</big></U></B>
+#Start recording tcl command: 5/31/2021 20:20:31
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 6/1/2021 05:54:09
+
+
+
+<A name="pn210602164441"></A><B><U><big>pn210602164441</big></U></B>
+#Start recording tcl command: 6/1/2021 10:42:27
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+#Stop recording: 6/2/2021 16:44:41
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>
diff --git a/s1_tcr.dir/pn201116201457.tcr b/s1_tcr.dir/pn201116201457.tcr
new file mode 100644
index 0000000..386e4d2
--- /dev/null
+++ b/s1_tcr.dir/pn201116201457.tcr
@@ -0,0 +1,26 @@
+#Start recording tcl command: 11/13/2020 10:17:07
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/modules.v"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Promgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+#Stop recording: 11/16/2020 20:14:57
diff --git a/s1_tcr.dir/pn210124231721.tcr b/s1_tcr.dir/pn210124231721.tcr
new file mode 100644
index 0000000..62d0aa9
--- /dev/null
+++ b/s1_tcr.dir/pn210124231721.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 1/24/2021 23:16:12
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+launch_synplify_prj impl1
+#Stop recording: 1/24/2021 23:17:21
diff --git a/s1_tcr.dir/pn210124232433.tcr b/s1_tcr.dir/pn210124232433.tcr
new file mode 100644
index 0000000..12347c4
--- /dev/null
+++ b/s1_tcr.dir/pn210124232433.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 1/24/2021 23:19:17
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+launch_synplify_prj impl1
+#Stop recording: 1/24/2021 23:24:33
diff --git a/s1_tcr.dir/pn210126141734.tcr b/s1_tcr.dir/pn210126141734.tcr
new file mode 100644
index 0000000..910bcb4
--- /dev/null
+++ b/s1_tcr.dir/pn210126141734.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 1/26/2021 13:18:43
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 1/26/2021 14:17:34
diff --git a/s1_tcr.dir/pn210208120414.tcr b/s1_tcr.dir/pn210208120414.tcr
new file mode 100644
index 0000000..233fb93
--- /dev/null
+++ b/s1_tcr.dir/pn210208120414.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 2/8/2021 12:03:25
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 2/8/2021 12:04:14
diff --git a/s1_tcr.dir/pn210526194824.tcr b/s1_tcr.dir/pn210526194824.tcr
new file mode 100644
index 0000000..7620bbc
--- /dev/null
+++ b/s1_tcr.dir/pn210526194824.tcr
@@ -0,0 +1,39 @@
+#Start recording tcl command: 5/11/2021 08:45:22
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"
+#Stop recording: 5/26/2021 19:48:24
diff --git a/s1_tcr.dir/pn210528165033.tcr b/s1_tcr.dir/pn210528165033.tcr
new file mode 100644
index 0000000..6cb35c9
--- /dev/null
+++ b/s1_tcr.dir/pn210528165033.tcr
@@ -0,0 +1,26 @@
+#Start recording tcl command: 5/26/2021 19:48:48
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_project save
+prj_project close
+#Stop recording: 5/28/2021 16:50:33
diff --git a/s1_tcr.dir/pn210531201634.tcr b/s1_tcr.dir/pn210531201634.tcr
new file mode 100644
index 0000000..139108a
--- /dev/null
+++ b/s1_tcr.dir/pn210531201634.tcr
@@ -0,0 +1,7 @@
+#Start recording tcl command: 5/31/2021 17:24:05
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_src add "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"
+prj_project save
+prj_project close
+#Stop recording: 5/31/2021 20:16:34
diff --git a/s1_tcr.dir/pn210601055409.tcr b/s1_tcr.dir/pn210601055409.tcr
new file mode 100644
index 0000000..e058f4a
--- /dev/null
+++ b/s1_tcr.dir/pn210601055409.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 5/31/2021 20:20:31
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_project close
+#Stop recording: 6/1/2021 05:54:09
diff --git a/s1_tcr.dir/pn210602164441.tcr b/s1_tcr.dir/pn210602164441.tcr
new file mode 100644
index 0000000..ac9919c
--- /dev/null
+++ b/s1_tcr.dir/pn210602164441.tcr
@@ -0,0 +1,12 @@
+#Start recording tcl command: 6/1/2021 10:42:27
+#Project Location: /home/hadaq/mmichalek/lattice/simplified; Project name: s1
+prj_project open "/home/hadaq/mmichalek/lattice/simplified/s1.ldf"
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+prj_run Export -impl impl1 -task TimingSimFileVHD
+#Stop recording: 6/2/2021 16:44:41
diff --git a/top.v b/top.v
new file mode 100644
index 0000000..a54ce62
--- /dev/null
+++ b/top.v
@@ -0,0 +1,143 @@
+module top(
+					clk,
+					clk25,
+					reset,
+					trig,
+					//s_data,
+					//valid,
+					//lb_synced,
+					//tdc_buffered_out,
+					//fifo_out,
+					//fifo_empty,
+					//fifo_full,
+					//diff_out,
+					//diff_valid,
+					txd,
+					pulse_out,
+					pulse_async,
+					be_tmp,
+					zero_in,
+					zero_out,
+					diff_txd
+					//out0,
+					//out1
+					//clk_ref
+);
+
+
+
+input wire clk;
+input wire clk25;
+input wire reset;
+output wire [1:0]txd;
+input wire [1:0]trig;
+wire [3:0]dec_out[1:0];
+wire [1:0]dec_valid;
+/*output */ wire [3:0]diff_out;
+/*output */ wire diff_valid;
+
+output wire pulse_out;
+output wire pulse_async;
+output wire [1:0]be_tmp;
+output wire zero_out;
+input wire zero_in;
+output wire diff_txd;
+
+ /*output*/ wire [31:0]fifo_out;
+ /*output*/ wire fifo_empty;
+ /*output*/ wire [3:0]out0;
+ /*output*/ wire [3:0]out1;
+
+
+wire clk66;
+wire clk8;
+wire clk150;
+wire xfer_clk;
+wire [3:0]pll_clks;
+
+
+
+pll0 pll0inst(.CLKI( clk), .CLKOP( pll_clks[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));
+//pll1 pll1inst(.CLKI( clk), .CLKOP( clk150));
+//pll8 pll8_inst(.CLKI(clk), .CLKOS(clk8));
+//pll_random pll_random_inst(.CLKI(clk), .CLKOS(clk66));
+	
+pll1 pll1inst(.CLKI( pll_clks[0]), .CLKOP( clk150));
+pll8 pll8_inst(.CLKI(pll_clks[0]), .CLKOS(clk8));
+pll_random pll_random_inst(.CLKI(pll_clks[0]), .CLKOS(clk66), .CLKOS2(xfer_clk));
+	
+
+	
+
+
+
+async_testgen async_testgen_inst(
+												.clk(clk25), 
+												.reset(reset), 
+												.pulse_out(pulse_async),
+												.zero(zero_out)
+												);
+
+
+tdc_channel tdc_channel_inst0(
+											.reset(reset), 
+											.pll_clks(pll_clks), 
+											.clk8(clk8),
+											.xfer_clk(xfer_clk), 
+											.trig(trig[0]), 
+											.txd(txd[0]),
+											.dec_out(dec_out[0]),
+											.dec_valid(dec_valid[0])
+											);
+
+
+tdc_channel tdc_channel_inst1(
+											.reset(reset), 
+											.pll_clks(pll_clks), 
+											.clk8(clk8),
+											.xfer_clk(xfer_clk), 
+											.trig(trig[1]), 
+											.txd(txd[1]),
+											.dec_out(dec_out[1]),
+											.dec_valid(dec_valid[1])
+											);
+											
+two_ch_diff two_ch_diff_inst0(
+											.clk(pll_clks[3]), 
+											.reset(reset), 
+											.zero(zero_in), 
+											.in0(dec_out[0]), 
+											.in0_valid(dec_valid[0]), 
+											.in1(dec_out[1]), 
+											.in1_valid(dec_valid[1]), 
+											.out(diff_out), 
+											.out_valid(diff_valid),
+											.be_tmp(be_tmp),
+											.clk_uart(clk8),
+											.txd(diff_txd),
+											.fifo_empty(fifo_empty),
+											.fifo_out(fifo_out),
+											.out0(out0),
+											.out1(out1)
+											//.zero(zero)
+											);
+											
+reg [31:0]pulse_cnt;
+assign pulse_out = (pulse_cnt < 4);
+
+always @(posedge pll_clks[0])begin
+	if(reset)begin
+		pulse_cnt <=0;
+	end else begin
+		if(pulse_cnt < 'hfff7)begin
+			pulse_cnt <= pulse_cnt +1;
+		end else begin
+			pulse_cnt <= 0;
+		end
+	end
+end
+
+
+
+endmodule
+
diff --git a/top.v.bkp1 b/top.v.bkp1
new file mode 100644
index 0000000..29f93ae
--- /dev/null
+++ b/top.v.bkp1
@@ -0,0 +1,390 @@
+module top(
+					clk,
+					clk25,
+					reset,
+					trig,
+					//s_data,
+					//valid,
+					//lb_synced,
+					//tdc_buffered_out,
+					//fifo_out,
+					//fifo_empty,
+					//fifo_full,
+					txd,
+					pulse_out,
+					pulse_async
+					//clk_ref
+);
+
+
+input wire clk;
+input wire clk25;
+input wire reset;
+/*output*/ wire [2:0]s_data;
+input wire trig;
+/*output*/ wire valid;
+/*output*/ wire [7:0]lb_synced;
+/*output*/ wire [31:0]fifo_out;
+/*output*/ wire fifo_empty;
+/*output*/ wire fifo_full;
+output wire pulse_out;
+output wire pulse_async;
+reg [2:0]fifo_in_buffered;
+
+wire clk66;
+wire clk8;
+wire clk150;
+wire xfer_clk;
+wire [3:0]pll_clks;
+wire [7:0]tdc_out;
+/*output*/ wire [7:0]tdc_buffered_out;
+
+
+pll0 pll0inst(.CLKI( clk), .CLKOP( pll_clks[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));
+//pll1 pll1inst(.CLKI( clk), .CLKOP( clk150));
+//pll8 pll8_inst(.CLKI(clk), .CLKOS(clk8));
+//pll_random pll_random_inst(.CLKI(clk), .CLKOS(clk66));
+	
+pll1 pll1inst(.CLKI( pll_clks[0]), .CLKOP( clk150));
+pll8 pll8_inst(.CLKI(pll_clks[0]), .CLKOS(clk8));
+pll_random pll_random_inst(.CLKI(pll_clks[0]), .CLKOS(clk66), .CLKOS2(xfer_clk));
+	
+	wire trig_gate /*synthesis syn_preserve= 1*/;
+	assign trig_gate =  ~trig;
+	
+	
+tdc4ddr tdc_inst(
+						.trigger(trig_gate), 
+						.clks(pll_clks), 
+						.xfer_clk(xfer_clk),
+						.out(tdc_out),
+						.out_buffered(tdc_buffered_out)
+						//.out_xfer(tdc_out)
+);
+
+output_decoder8 dec_inst(
+						.clk(pll_clks[3]),
+						//.clk(xfer_clk),
+						//.clk(clk150),
+						//.in(tdc_out),
+						.in(tdc_buffered_out),
+						.out(s_data),
+						.valid(valid),
+						.in_synced_lb(lb_synced)
+						//.raw_latched()
+						);
+
+fifo32dc fifo32dc_inst (
+						.Data( s_data), 
+						.WrClock( pll_clks[3]), 
+						.RdClock( clk8), 
+						.WrEn( valid), 
+						.RdEn( 1'b1), 
+						.Reset( 1'b0), 
+						.RPReset( 1'b0), 
+						.Q( fifo_out), 
+						.Empty( fifo_empty), 
+						.Full( fifo_full)
+						);
+
+always @(pll_clks[3])begin
+	if(reset)begin
+		fifo_in_buffered <= 'b0;
+	end else begin
+		fifo_in_buffered <= s_data;
+	end
+end
+
+reg [31:0]dbg_cnt;
+wire pulser_trig;
+wire wrn;
+wire adsn;
+assign pulser_trig = dbg_cnt[2];
+
+reg [7:0]din;
+reg [2:0]wrn_cnt;
+reg [7:0]adsn_cnt;
+
+assign wrn = wrn_cnt[2];
+assign adsn = ~(|adsn_cnt);
+
+reg [7:0]uart_input_buf;
+reg uart_buf_empty;
+reg [3:0]uart_quad_cnt;
+reg fifo_read;
+
+output wire txd;
+
+async_testgen async_testgen_inst(
+												.clk(clk25), 
+												.reset(reset), 
+												.pulse_out(pulse_async)
+												);
+
+UART_VerilogWrapper_TOP UART_VerilogWrapper_TO_inst2(
+       // Global reset and clock
+       .MR(reset)      ,
+       .MCLK(clk8)    ,
+       // Processor interface
+		.A(0)     ,
+        .DIN(din)   ,
+        .ADSn(adsn)  ,
+		.CS(1'b1)    ,
+        .RDn(rdn)   ,
+        .WRn(wrn)   ,
+       // Receiver interface
+       
+      // Transmitter interface          
+      .SOUT(txd)     ,                         
+      .TxRDYn(txrdy)          
+       );
+	   
+	   always @(posedge clk8)begin
+//always @(posedge pll_clks[0])begin
+	if(reset)begin
+		//marker <= 'b0;
+		dbg_cnt <= 'b0;
+		//dbg[0]<=1'b1;
+		adsn_cnt <= ~0;
+		wrn_cnt <= 'b0;
+		uart_buf_empty <= 'b1;
+	end else begin
+		//dbg[4] <= txd;
+		//dbg[3:2] <= ~pulser_out;
+		//dbg[7:6]<=dbg_cnt[21:20];
+		//dbg[0]<=1'b0;
+		dbg_cnt <= dbg_cnt +1;
+		//marker <= 'b1;
+		if(fifo_empty == 1'b0 && uart_buf_empty)begin
+			fifo_read<=1;
+			uart_input_buf <= fifo_out;
+			uart_buf_empty <= 0;
+			uart_quad_cnt <= 0;
+		end else begin
+			fifo_read<=0;
+		end
+  
+		if(uart_buf_empty == 0)begin
+			if(uart_quad_cnt == 10)begin
+				uart_buf_empty <= 1'b1;
+			end else begin
+				if(txrdy == 0 && wrn_cnt == 0)begin
+					//din <= {uart_input_buf[4*uart_quad_cnt +: 4],uart_quad_cnt};
+					din <= uart_input_buf;
+					wrn_cnt <= 'b111;
+					//uart_quad_cnt <= uart_quad_cnt +1;
+					uart_quad_cnt <= 10;
+				end
+			end
+		end
+		if(adsn_cnt)adsn_cnt <= adsn_cnt -1;
+		if(wrn_cnt)wrn_cnt <= wrn_cnt -1;
+	end
+end
+/*integer i;
+//generate
+always @( posedge pll_clks[0])begin
+	for(i =0; i<4; i=i+1)begin
+		s_out[i] <= s_in[i];
+	end
+end*/
+//endgenerate
+
+/*
+always @(posedge pll_clks[0])begin
+		if(reset)begin
+			cnt <= 2'b0;
+		end else begin
+			cnt <= cnt +2'b1;
+			s_in <= cnt;
+		end
+end
+*/
+reg [31:0]pulse_cnt;
+assign pulse_out = (pulse_cnt < 4);
+
+always @(posedge pll_clks[0])begin
+	if(reset)begin
+		pulse_cnt <=0;
+	end else begin
+		if(pulse_cnt < 'hfff7)begin
+			pulse_cnt <= pulse_cnt +1;
+		end else begin
+			pulse_cnt <= 0;
+		end
+	end
+end
+
+endmodule
+
+module async_testgen(clk, reset, pulse_out);
+	input wire clk;
+	input wire reset;
+	output wire pulse_out;
+	
+	reg [31:0]pulse_cnt;
+	assign pulse_out = (pulse_cnt < 'h4f);
+
+	always @(posedge clk)begin
+	if(reset)begin
+		pulse_cnt <=0;
+	end else begin
+		if(pulse_cnt < 'h1ff5)begin
+		//if(pulse_cnt < 'h7)begin
+			pulse_cnt <= pulse_cnt +1;
+		end else begin
+			pulse_cnt <= 0;
+		end
+	end
+	end
+endmodule
+
+module tdc4ddr(trigger, clks, xfer_clk, out, out_buffered, out_xfer) /* synthesis syn_preserve= 1*/; 
+	input wire trigger;
+	input wire[3:0]clks;
+	input wire xfer_clk;
+	output reg [7:0]out /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_xfer /*synthesis syn_preserve= 1*/;
+	output reg [7:0]out_buffered /*synthesis syn_preserve= 1*/;
+	reg [7:0]out_buffered1 /*synthesis syn_preserve= 1*/;
+	
+	reg [7:0]in_clk_synced /*synthesis syn_preserve= 1*/;
+	reg [3:0]in_clk_down_synced /*synthesis syn_preserve= 1*/;
+	//always @(negedge clks[3])begin
+	always @(negedge xfer_clk)begin
+		//out_buffered1 <= out;
+		//out_buffered <= out_buffered1;
+		out_xfer <= out_buffered;
+	end
+	generate
+		genvar i;
+		for(i=0;i<4;i=i+1)begin
+			reg [1:0]in_up_dl;
+			reg [1:0]in_down_dl;
+			
+			always @(posedge clks[i])begin
+				if(trigger)begin
+					out[i] <= 1'b1;
+				end else begin 
+					out[i] <= 1'b0;
+				end
+				in_clk_synced[i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[i] <= in_clk_synced[i] /*synthesis syn_preserve= 1*/;
+				out_buffered[i] <= out_buffered1[i] /*synthesis syn_preserve= 1*/;
+			end
+			always @(negedge clks[i])begin
+				if(trigger)out[4+i] <= 1'b1 /*synthesis syn_preserve= 1*/;
+				else out[4+i] <= 1'b0 /*synthesis syn_preserve= 1*/;
+				in_clk_synced[4+i] <= trigger /*synthesis syn_preserve= 1*/;
+				out_buffered1[4+i] <= in_clk_synced[4+i] /*synthesis syn_preserve= 1*/;
+				out_buffered[4+i] <= out_buffered1[4+i] /*synthesis syn_preserve= 1*/;
+			end
+			
+		end
+	endgenerate
+endmodule
+
+module output_decoder8(
+									clk,
+									in,
+									out,
+									valid,
+									in_synced_lb,
+									raw_latched
+									) /* synthesis syn_preserve= 1*/;
+
+input wire clk;
+input wire [7:0]in;
+output reg [2:0]out /*synthesis syn_preserve=1*/;
+reg [2:0]out_internal /*synthesis syn_preserve=1*/;
+output reg valid /*synthesis syn_preserve=1*/;
+reg valid_internal /*synthesis syn_preserve=1*/;
+output wire [7:0]in_synced_lb;
+output reg [7:0]raw_latched /*synthesis preserve=1*/;
+
+reg [7:0]dl[2:0];
+reg [7:0]in_synced /*synthesis syn_preserve=1*/;
+
+assign in_synced_lb=in_synced;
+
+wire in_synced7_rising;
+assign  in_synced7_rising = ~in_synced[7] & dl[1][7];
+
+always @ (negedge clk)begin
+	out <= out_internal;
+	valid <= valid_internal;
+end
+
+always @ (negedge clk)begin
+	dl[0] <= in;
+	dl[1] <= dl[0];
+	in_synced <= dl[1];
+end
+	always @ (negedge clk)begin
+		if(in_synced7_rising)begin
+		case (in_synced)	
+			//8'b10000000 : begin
+				8'b01111111 : begin
+                        out_internal <= 3'b000;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000001;
+                        end
+			//8'b10000001 : begin
+				8'b01111110 : begin
+                        out_internal <= 3'b001;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000000010;
+                        end
+			//8'b10000011 : begin
+				8'b01111100 : begin
+                        out_internal <= 3'b010;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b00000000000000100;
+                        end
+			//8'b10000111 : begin
+				8'b01111000 : begin
+                        out_internal <= 3'b011;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000001000;
+                        end
+			//8'b10001111 : begin
+				8'b01110000 : begin
+                        out_internal <= 3'b100;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000010000;
+                        end
+			//8'b10011111 : begin
+				8'b01100000 : begin
+                        out_internal <= 3'b101;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000000100000;
+                        end
+			//8'b10111111 : begin
+				8'b01000000 : begin
+                        out_internal <= 3'b110;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000001000000;
+                        end
+			//8'b00000000 : begin //8'b11111111
+				8'b00000000 : begin
+                        out_internal <= 3'b111;
+                        valid_internal <= 1'b1;
+						//raw_latched <= 16'b0000000010000000;
+                        end
+			default   :  begin
+						out_internal <=3'b111;
+						valid_internal <= 1'b0;
+						//raw_latched <= 'b0;
+						//raw_latched <= raw_latched;
+						end
+			endcase
+		end else begin
+			out_internal <=3'b111;
+			valid_internal <= 1'b0;
+		end
+		end
+
+
+endmodule
+
+
diff --git a/top2.v b/top2.v
new file mode 100644
index 0000000..5beb01f
--- /dev/null
+++ b/top2.v
@@ -0,0 +1,325 @@
+module top_tf(
+										clk,
+										rd_clk,
+										reset_dc, 										
+										trig,
+										fifo_data_out,
+										fifo_rden,
+										//tdc_out1,
+										fifo_empty1,
+										//fifo_data_out2,
+										//fifo_rden2,
+										//tdc_out2
+										LVL1_TRG_DATA_VALID_IN,
+										LVL1_INVALID_TRG_IN,
+										FEE_DATA_OUT,
+										FEE_DATA_WRITE_OUT,
+										FEE_DATAFINISHED_OUT,
+										FEE_TRG_RELEASE_OUT,
+										LVL1_TRG_DATA_VALI_IN_rising,
+										burst,
+										discard,
+										last_buf_empty,
+										finished,
+										release_out,
+										hades_trig,
+										//hades_raw_out,
+										hades_raw_out_valid,
+										hades_raw_valid_vect,
+										hades_lvl1,
+										hades_lvl1_invalid,
+										hades_offset,
+										hades_offset_valid,
+										hades_window_end,
+										//hades_buf_out,
+										hades_buf_out_valid,
+										hades_buf_release,
+										hades_buf_finished,
+										hades_hit_out_i,
+										hades_hit_valid,
+										hades_discard,
+										hades_invalid_dl,
+										hades_buf_drop,
+										hades_dbg2_out,
+										hades_dbg2_coarse,
+										hades_drop_cmp_buf,
+										hades_drop_cmp_buf_coarse,
+										hades_drop_cmp_buf_valid	
+
+						);
+	parameter CHANNELS=3;
+	parameter DATA_WIDTH = 24;
+	parameter ADDRESS_WIDTH = 8;
+	
+//channel 7
+//edge 13
+//sub 3
+//edge 13
+//sub3
+						
+	input wire clk;					
+	input wire rd_clk;					
+	input wire reset_dc;
+	input wire [CHANNELS-1:0]trig;
+	output wire [(DATA_WIDTH+ADDRESS_WIDTH-1):0]fifo_data_out;
+	output wire fifo_rden;
+	/*output*/ wire [7:0]tdc_out1;
+	wire [7:0]tdc_out2;
+	/*output */wire [CHANNELS-1:0]fifo_empty;
+	output wire fifo_empty1;
+	assign fifo_empty1 = fifo_empty[0];
+				
+	reg [DATA_WIDTH-4 -1:0]coarse;					
+		
+	wire [3:0]pll_clks;
+	//assign fifo_data_out[0]  = coarse[15];
+	pll0 pll0inst(.CLKI( clk), .CLKOP( pll_clks[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));		
+		//pll0 pll0inst(.CLKI( clk), .CLKOP( fifo_data_out[0]), .CLKOS(pll_clks[1]), .CLKOS2(pll_clks[2]), .CLKOS3(pll_clks[3]));
+		
+
+	reg [2:1]reset_dl;
+	wire  reset;
+	assign reset = reset_dl[2];
+	always @(posedge pll_clks[3])begin
+		{reset_dl} <= {reset_dl[2:1], reset_dc};
+	end
+		input wire LVL1_TRG_DATA_VALID_IN;
+		input wire LVL1_INVALID_TRG_IN;
+		//output wire [(DATA_WIDTH+ADDRESS_WIDTH-1):0]FEE_DATA_OUT;
+		output wire [(DATA_WIDTH+ADDRESS_WIDTH-1):0]FEE_DATA_OUT;
+		output wire FEE_DATA_WRITE_OUT;
+		output wire FEE_DATAFINISHED_OUT;
+		output wire FEE_TRG_RELEASE_OUT;
+		output wire LVL1_TRG_DATA_VALI_IN_rising;
+		output wire burst;
+		output wire discard;
+		output wire last_buf_empty;
+		output wire finished;
+		output wire release_out;
+	
+		
+		assign FEE_DATA_OUT = fifo_data_out;
+
+input wire hades_trig;
+/*output*/ wire [23:0]	hades_raw_out;
+output wire hades_raw_out_valid;
+output wire [1:0]hades_raw_valid_vect;
+/*output */wire [23:0]	hades_buf_out;
+output wire hades_buf_out_valid;
+output wire hades_buf_release;
+output wire hades_buf_finished;
+output wire [3:0]hades_hit_out_i;
+output wire [3:0]hades_hit_valid;
+output wire hades_discard;
+
+input wire hades_lvl1;
+input wire hades_lvl1_invalid;
+output wire [8:0]hades_offset;
+output wire hades_offset_valid;
+output wire hades_window_end;
+output wire [3:0]hades_invalid_dl;
+output wire [3:0]hades_buf_drop;
+output wire [31:0]hades_dbg2_out;
+output wire [8:0]hades_dbg2_coarse;
+output wire [11:0]hades_drop_cmp_buf;
+output wire [11:0]hades_drop_cmp_buf_coarse;
+output wire hades_drop_cmp_buf_valid;
+
+hades_tdc_bundle hades_tdc_bundle_inst(
+										.reset(reset), 
+										.pll_clks(pll_clks),
+										.trig(hades_trig),
+										.LVL1_trig(hades_lvl1),
+										.LVL1_invalid(hades_lvl1_invalid),
+										.referenced_out(hades_raw_out),
+										.referenced_out_valid(hades_raw_out_valid),
+										.window_end(hades_window_end),
+										.LVL1_offset(hades_offset),
+										.LVL1_offset_valid(hades_offset_valid),
+										.buf_out(hades_buf_out),
+										.buf_out_valid(hades_buf_out_valid),
+										.buf_release(hades_buf_release),
+										.buf_finished(hades_buf_finished),
+										.hit_out_i(hades_hit_out_i),
+										.hit_valid(hades_hit_valid),
+										.discard(hades_discard),
+										.invalid_dl(hades_invalid_dl),
+										.buf_drop(hades_buf_drop),
+										.dbg2_out(hades_dbg2_out),
+										.dbg2_coarse(hades_dbg2_coarse),
+										.drop_cmp_buf(hades_drop_cmp_buf),
+										.drop_cmp_buf_coarse(hades_drop_cmp_buf_coarse),
+										.drop_cmp_buf_valid(hades_drop_cmp_buf_valid)
+										);
+
+
+
+		trb_adapter trb_adapter_inst(
+									//.clk(pll_clks[3]),
+									.clk(rd_clk),
+									.reset(reset),
+									.LVL1_TRG_DATA_VALID_IN(LVL1_TRG_DATA_VALID_IN),
+									.LVL1_INVALID_TRG_IN(LVL1_INVALID_TRG_IN),
+									.FEE_DATA_OUT(),
+									.FEE_DATA_WRITE_OUT(FEE_DATA_WRITE_OUT),
+									.FEE_DATAFINISHED_OUT(FEE_DATAFINISHED_OUT),
+									.FEE_TRG_RELEASE_OUT(FEE_TRG_RELEASE_OUT),
+									.LVL1_TRG_DATA_VALI_IN_rising(LVL1_TRG_DATA_VALI_IN_rising),
+									.burst(burst),
+									.discard(discard),
+									.buf_empty(last_buf_empty),
+									.buf_rden(fifo_rden),
+									.finished(finished),
+									.release_out(release_out)
+								);
+		
+		
+		
+		wire [31:0]fifo_data_out1;
+		wire [31:0]fifo_data_out2;
+		
+		wire [CHANNELS-1:0]fifo_data_out;
+		wire [CHANNELS-1:0]in_empty;
+		wire [CHANNELS-1:0]in_data;
+		wire [CHANNELS-1:0]fifo_read;
+		wire [CHANNELS*(DATA_WIDTH+ADDRESS_WIDTH)-1:0]fifo_data;
+		
+		fifo_colector fifo_colector_inst(		
+								.wr_clk(pll_clks[3]),
+								.rd_clk(rd_clk),
+								.reset(reset),
+								.in_data(fifo_data),
+								.in_empty(fifo_empty),
+								.in_read_enable(fifo_read),
+								.out_data(fifo_data_out),
+								.out_empty(last_buf_empty), 
+								.out_read_enable(fifo_rden),
+								.discard(discard),
+								//buffer_wr_enable,
+								.raw_enable()
+								);
+		genvar i;
+		generate
+		
+		for(i=0; i<CHANNELS; i= i+1)begin
+		
+		tdc_channel_fifo_out tdc_channel_fifo_out_inst(
+										.reset(reset), 
+										.pll_clks(pll_clks), 
+										.coarse(coarse), 
+										.trig(trig[i]),
+										.fifo_data_out(fifo_data[i*DATA_WIDTH +: DATA_WIDTH]),
+										.fifo_rden(fifo_read[i]),
+										.fifo_empty(fifo_empty[i]),
+										.tdc_out()
+										);
+			end
+		endgenerate
+
+		
+always @(posedge pll_clks[0])begin
+		if(reset)begin
+			coarse <= 'b0;
+		end else begin
+			coarse <= coarse + 'b1;
+		end
+end	
+						
+endmodule
+
+module trb_adapter(
+									clk,
+									reset,
+									LVL1_TRG_DATA_VALID_IN,
+									LVL1_INVALID_TRG_IN,
+									FEE_DATA_OUT,
+									FEE_DATA_WRITE_OUT,
+									FEE_DATAFINISHED_OUT,
+									FEE_TRG_RELEASE_OUT,
+									LVL1_TRG_DATA_VALI_IN_rising,
+									burst,
+									discard,
+									buf_empty,
+									buf_rden,
+									finished,
+									release_out
+								);
+		input wire clk;
+		input wire reset;
+		input wire LVL1_TRG_DATA_VALID_IN;
+		input wire LVL1_INVALID_TRG_IN;
+		output reg FEE_DATA_OUT;
+		output reg FEE_DATA_WRITE_OUT;
+		output reg FEE_DATAFINISHED_OUT;
+		output reg FEE_TRG_RELEASE_OUT;
+		output wire LVL1_TRG_DATA_VALI_IN_rising;
+		output wire burst;
+		output wire discard;
+		input wire buf_empty;
+		output reg buf_rden;
+		output reg finished;
+		output wire release_out;
+		
+		reg [2:0]LVL1_TRG_DATA_VALID_IN_dl;
+		reg [2:0]LVL1_INVALID_TRG_IN_dl;
+		reg buf_rden_prev;
+		reg finished_prev;
+		assign LVL1_TRG_DATA_VALI_IN_rising = ~LVL1_TRG_DATA_VALID_IN_dl[2] & LVL1_TRG_DATA_VALID_IN_dl[1];
+		assign burst = ~LVL1_INVALID_TRG_IN_dl[1] & LVL1_TRG_DATA_VALI_IN_rising;
+		assign discard = LVL1_INVALID_TRG_IN_dl[1];
+		assign buf_rden_falling = buf_rden_prev & ~buf_rden; 
+		//assign finished_falling = finished_prev & ~finished;
+		assign release_out = finished_prev & ~finished;
+		always @(posedge clk)begin
+			{LVL1_TRG_DATA_VALID_IN_dl} <= {LVL1_TRG_DATA_VALID_IN_dl[1:0], LVL1_TRG_DATA_VALID_IN};
+			{LVL1_INVALID_TRG_IN_dl}	<= {LVL1_INVALID_TRG_IN_dl[1:0], LVL1_INVALID_TRG_IN};
+		end
+		
+		always @(posedge clk)begin
+			if(buf_rden_falling)begin
+				finished_prev <= finished;
+				finished <= 'b1;
+			end else begin
+				finished_prev <= finished;
+				if(finished)finished <= finished  -1;
+			end
+		end
+		/*
+		always @(posedge clk)begin
+			if(finished_falling)begin
+				release_out <= 'b1;
+			end else begin
+				if(release_out)release_out <= -1;
+			end
+		end*/
+		
+		always @(posedge clk)begin
+			if(/*(burst && !buf_empty) ||*/ ( !buf_empty && buf_rden) || (burst))begin
+				buf_rden_prev <= buf_rden;
+				buf_rden <= 'b1;
+			end else begin
+				buf_rden_prev <= buf_rden;
+				buf_rden <= 'b0;
+			end
+		end
+		always @(posedge clk)begin
+			if(reset)begin
+				FEE_DATA_OUT <= 'b0;
+				FEE_DATA_WRITE_OUT <= 'b0;
+				FEE_DATAFINISHED_OUT <= 'b0;
+				FEE_TRG_RELEASE_OUT <= 'b0;
+			end else begin
+				FEE_DATA_WRITE_OUT <= buf_rden;			// 1 clk delay
+				FEE_DATAFINISHED_OUT <= finished;		//
+				FEE_TRG_RELEASE_OUT <= release_out;	//
+			end
+		end			
+								
+								
+	endmodule
+	
+	
+	
+	
+	
+	
diff --git a/trb5_tb.vhd b/trb5_tb.vhd
new file mode 100644
index 0000000..e7c5c96
--- /dev/null
+++ b/trb5_tb.vhd
@@ -0,0 +1,136 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.math_real.uniform;
+use IEEE.math_real.floor;
+
+entity trb5_tb is
+--  Port ( );
+end trb5_tb;
+
+architecture Behavioral of trb5_tb is
+
+    component endp_handler is
+    Port (
+        CLK : in std_logic;
+        RESET : in std_logic;
+        
+        TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+        
+        LVL1_TRG_DATA_VALID_OUT : out std_logic;
+        LVL1_INVALID_TRG_OUT : out std_logic;
+        
+        FEE_TRG_RELEASE_IN : in std_logic;
+        FEE_TRG_STATUSBITS_IN : in std_logic_vector(31 downto 0);
+        FEE_DATA_IN : in std_logic_vector(31 downto 0);
+        FEE_DATA_WRITE_IN : in std_logic;
+        FEE_DATAFINISHED_IN : in std_logic;
+        FEE_DATA_ALMOST_FULL_OUT : out std_logic
+    );
+    end component;
+    
+    component endp_dummy is
+    port (
+        CLK : in std_logic;
+        RESET : in std_logic;
+        
+        TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+        
+        LVL1_TRG_DATA_VALID_IN : in std_logic;
+        LVL1_INVALID_TRG_IN : in std_logic;
+        
+        FEE_TRG_RELEASE_OUT : out std_logic;
+        FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+        FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+        FEE_DATA_WRITE_OUT : out std_logic;
+        FEE_DATAFINISHED_OUT : out std_logic;
+        FEE_DATA_ALMOST_FULL_IN : in std_logic
+    );
+    end component;
+    
+    signal clk, rst, trg, trg_dv, trg_inv : std_logic := '0';
+    signal fee_release, fee_dw, fee_finished, fee_af : std_logic := '0';
+    signal fee_data, fee_status : std_logic_vector(31 downto 0) := x"0000_0000";
+
+begin
+
+process
+begin
+    clk <= '1'; wait for 5 ns;
+    clk <= '0'; wait for 5 ns;
+end process;
+
+process
+begin
+    rst <= '0';
+    wait for 100 ns;
+    rst <= '1';
+    wait for 100 ns;
+    rst <= '0';
+    wait;
+end process;
+
+process
+    variable s1, s2 : positive := 123;
+    variable x : real;
+    variable y : integer;
+    variable t : time;
+begin
+    trg <= '0';
+    wait for 1 us;
+    
+    for i in 0 to 10 loop
+    
+        uniform(s1, s2, x);
+        t := (x * 5000.0 + 500.0) * (1 ns);
+        
+        wait for t;
+        
+        trg <= '1';
+        wait for 100 ns;
+        trg <= '0';
+        
+    end loop;
+end process;
+    
+
+endp_hand : endp_handler
+Port map(
+    CLK => clk,
+    RESET => rst,
+    
+    TRG_TIMING_TRG_RECEIVED_IN => trg,
+    
+    LVL1_TRG_DATA_VALID_OUT => trg_dv,
+    LVL1_INVALID_TRG_OUT => trg_inv,
+    
+    FEE_TRG_RELEASE_IN => fee_release,
+    FEE_TRG_STATUSBITS_IN => fee_status,
+    FEE_DATA_IN => fee_data,
+    FEE_DATA_WRITE_IN => fee_dw,
+    FEE_DATAFINISHED_IN => fee_finished, 
+    FEE_DATA_ALMOST_FULL_OUT => fee_af
+);
+
+
+endp : endp_dummy
+port map(
+    CLK => clk,
+    RESET => rst,
+    
+    TRG_TIMING_TRG_RECEIVED_IN => trg,
+    
+    LVL1_TRG_DATA_VALID_IN => trg_dv,
+    LVL1_INVALID_TRG_IN => trg_inv,
+    
+    FEE_TRG_RELEASE_OUT => fee_release,
+    FEE_TRG_STATUSBITS_OUT => fee_status,
+    FEE_DATA_OUT => fee_data,
+    FEE_DATA_WRITE_OUT => fee_dw,
+    FEE_DATAFINISHED_OUT => fee_finished,
+    FEE_DATA_ALMOST_FULL_IN => fee_af
+);
+
+
+end Behavioral;
diff --git a/unrouted_tdc_out4.5_1.dly b/unrouted_tdc_out4.5_1.dly
new file mode 100644
index 0000000..ed7fb64
--- /dev/null
+++ b/unrouted_tdc_out4.5_1.dly
@@ -0,0 +1,2390 @@
+PAR: Place And Route Diamond (64-bit) 3.11.2.446.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
+Wed Sep 23 15:08:50 2020
+
+File: s1_impl1.dir/5_1.dly
+
+ The 20 worst nets by delay are:
+---------------------------------
+| Max Delay         | Netname   |
+---------------------------------
+   5.8                 reset_c
+   4.2                 trig_c
+   3.9                 tdc_out[4]
+   3.4                 txd_c
+   2.6                 pulse_async_c
+   1.8                 pulse_cnt[2]
+   1.7                 clk25_c
+   1.7                 pll_clks[3]
+   1.7                 clk8
+   1.7                 pll_clks[0]
+   1.7                 pll8_inst/CLKOP
+   1.7                 fifo32dc_inst/wcount_4
+   1.7                 pulse_cnt_i[2]
+   1.7                 pll_clks[2]
+   1.7                 pll_clks[1]
+   1.1                 UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnA
+   1.0                 UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4
+   1.0                 I_24.t2
+   1.0                 fifo32dc_inst/wcount_8
+   1.0                 fifo32dc_inst/rcount_4
+---------------------------------
+
+-------------------------------------------------------------------------------
+                               Net Delays
+-------------------------------------------------------------------------------
+
+CO0
+   wrn_cnt_RNO[0].Q0
+         0.3  wrn_cnt_RNO[0].M0
+         0.3  wrn_cnt_RNO[1].M0
+         0.3  wrn_cnt_7[2].M0
+         0.6  din_1_sqmuxa.C0
+         0.7  wrn_cnt17.B1
+
+CO0_0
+   pulse_cnt_RNO[0].Q0
+         0.3  pulse_cnt_RNO[0].C0
+         0.4  pulse_cnt_RNO[2].C0
+         0.4  pulse_cnt_RNO[2].C1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/pulse_cnt_0_sqmuxa_i.C0
+
+CO0_0_i
+   pulse_cnt_RNO[0].F0
+         0.0  pulse_cnt_RNO[0].DI0
+
+I_24.t2
+   I_24.lat_r.F1
+         1.0  UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.D0
+         0.5  I_24.lat_r.B1
+
+UART_VerilogWrapper_TO_inst2.inst1.THRE
+   UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.Q0
+         0.3  wrn_cnt_RNO[0].D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].C1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].M0
+         0.5  wrn_cnt_RNO[1].C0
+         0.5  wrn_cnt_7[2].C0
+         0.5  din_1_sqmuxa.D0
+         0.5  wrn_cnt17.D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.D1
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[0]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[1].Q0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[0].A0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[1].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[1].D0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[3].Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[2].C0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[3].Q1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[3].B0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[4]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[5].Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[4].C0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[5]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[5].Q1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[5].A0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[6]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[7].Q0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.C0
+
+UART_VerilogWrapper_TO_inst2/inst1/THR[7]
+   UART_VerilogWrapper_TO_inst2/inst1/U1/THR[7].Q1
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].A1
+
+UART_VerilogWrapper_TO_inst2/inst1/ThrWRn1_r
+   UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.Q0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.B0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/ThrWRn2_r.M0
+
+UART_VerilogWrapper_TO_inst2/inst1/ThrWRn2_r
+   UART_VerilogWrapper_TO_inst2/inst1/U1/ThrWRn2_r.Q0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.M0
+
+UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs
+   UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.F0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[1].CLK
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[3].CLK
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[5].CLK
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[7].CLK
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/CO0_0
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].Q0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].D0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].A0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].D1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.LSR
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_RNIVGL3[1].B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/CO1_0
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_RNIVGL3[1].F0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].D0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].D1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].Q0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].C1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_RNIVGL3[1].C0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].Q0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].B0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].B1
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].B0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].B1
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].Q0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].M0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_4[0]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_4[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_4[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Count_vr_4[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_15
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[0].F0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].D0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_16
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[1].F0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].D1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_17
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[2].F0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_18
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[3].F0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].A1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_19
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[4].F0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].C0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_20
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[5].F0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].C1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_21
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.F0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].C0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_43_i
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_7
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_8
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/N_9
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[0]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].Q0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.A0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[0].D0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[1].B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].C1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[2].B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].C0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[3].D0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[4]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].C1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[4].A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[5]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].Q1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].B0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[5].D0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[6]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].Q0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_1[7]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].Q1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].D0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].B1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[0]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[4]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[5]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[6]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_6[7]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].F1
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].DI1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_1_iv_i
+   UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_1[0]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].Q0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].A0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].A1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.un8_txclkena.B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_1[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].A1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].B0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].B1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.un8_txclkena.C0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_1[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].Q0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].M0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.un8_txclkena.A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnA
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.Q0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].B0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].B1
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].B0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].B1
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].A0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].A1
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].A0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].D1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].C1
+         1.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].A0
+         1.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].A1
+         1.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].A0
+         1.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].A1
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.C0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.A1
+         1.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i_RNO.B0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_0_a2.A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1.Q0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.A0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.C1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1.M1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1.Q1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.D1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1.Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].C0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].D0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].M0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].C0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].C1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1.M1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1.Q1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].A0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].B0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].A1
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].A0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].A1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_0_a2.F0
+         0.1  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].D1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4
+   UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.F1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].C1
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].LSR
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].LSR
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.B0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.A0
+         1.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[5].C0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[4].B0
+         1.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[3].C0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[2].A0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[1].A0
+         1.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6_0[0].B0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_12_iv_i
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_1_i_m
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i_RNO.F0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.M0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State[2]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].Q0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].C0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].D1
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State[4]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].Q0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].A0
+         0.9  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].A1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].D0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].D1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].D0
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].D1
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].B0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].B0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].C1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].D1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1.M0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].B0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].B1
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].B0
+         0.8  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.D0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_0_a2.D0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State[5]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].Q1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1.M0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].D0
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxOutput_0_sqmuxa_4_0_a2.B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i_RNO.A0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].OFX0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[3]
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].F0
+         0.0  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].DI0
+
+UART_VerilogWrapper_TO_inst2/inst1/U4/un8_txclkena
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.un8_txclkena.F0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].D0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].C0
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].D1
+
+adsn_cnt[0]
+   adsn_cnt_RNO[0].Q0
+         0.7  un1_adsn_cnt_cry_0_0.A1
+         0.3  adsn_cnt_RNO[0].M0
+         0.7  un1_adsn_4.A0
+
+adsn_cnt[1]
+   adsn_cnt[2].Q0
+         0.5  adsn_cnt[2].A0
+         0.4  adsn_cnt_RNO[0].C0
+         0.6  un1_adsn_4.C0
+
+adsn_cnt[2]
+   adsn_cnt[2].Q1
+         0.5  adsn_cnt[2].A1
+         0.7  adsn_cnt_RNO[0].B0
+         0.5  un1_adsn_4.B0
+
+adsn_cnt[3]
+   adsn_cnt[4].Q0
+         0.5  adsn_cnt[4].B0
+         0.4  un1_adsn_5.C0
+
+adsn_cnt[4]
+   adsn_cnt[4].Q1
+         0.5  adsn_cnt[4].B1
+         0.5  un1_adsn_5.B0
+
+adsn_cnt[5]
+   adsn_cnt[6].Q0
+         0.5  adsn_cnt[6].B0
+         0.4  un1_adsn_5.D0
+
+adsn_cnt[6]
+   adsn_cnt[6].Q1
+         0.5  adsn_cnt[6].B1
+         0.5  un1_adsn_5.A0
+
+adsn_cnt[7]
+   adsn_cnt[7].Q0
+         0.5  adsn_cnt[7].A0
+         0.8  adsn_cnt_RNO[0].A0
+         0.5  un1_adsn_4.D0
+
+async_testgen_inst/pulse_cnt10lt12
+   I_24.lat_r.F0
+         0.5  async_testgen_inst/pulse_cnt10lto12_5.B0
+
+async_testgen_inst/pulse_cnt10lto12_0
+   async_testgen_inst/pulse_cnt10lto12_0.F1
+         0.4  async_testgen_inst/pulse_cnt10lto12_0.B0
+
+async_testgen_inst/pulse_cnt10lto12_5
+   async_testgen_inst/pulse_cnt10lto12_5.F1
+         0.5  async_testgen_inst/pulse_cnt10lto12_5.A0
+
+async_testgen_inst/pulse_cnt10lto12_6
+   async_testgen_inst/pulse_cnt10lto12_0.F0
+         0.4  async_testgen_inst/pulse_cnt10lto12_5.C0
+
+async_testgen_inst/pulse_cnt[0]
+   async_testgen_inst/pulse_cnt_RNO[0].Q0
+         0.6  async_testgen_inst/un3_pulse_cnt_cry_0_0.A1
+         0.3  async_testgen_inst/pulse_cnt_RNO[0].C0
+         0.5  async_testgen_inst/pulse_outlto3.A1
+         0.5  I_24.lat_r.A0
+
+async_testgen_inst/pulse_cnt[10]
+   async_testgen_inst/pulse_cnt[10].Q1
+         0.4  async_testgen_inst/pulse_cnt[10].B1
+         0.6  async_testgen_inst/pulse_outlto12_4.C1
+         0.7  async_testgen_inst/pulse_cnt10lto12_0.A0
+
+async_testgen_inst/pulse_cnt[11]
+   async_testgen_inst/pulse_cnt[12].Q0
+         0.5  async_testgen_inst/pulse_cnt[12].B0
+         0.4  async_testgen_inst/pulse_outlto12_4.C0
+         0.4  async_testgen_inst/pulse_cnt10lto12_0.C1
+
+async_testgen_inst/pulse_cnt[12]
+   async_testgen_inst/pulse_cnt[12].Q1
+         0.4  async_testgen_inst/pulse_cnt[12].A1
+         0.5  async_testgen_inst/pulse_outlto12_4.A1
+         0.5  async_testgen_inst/pulse_cnt10lto12_0.A1
+
+async_testgen_inst/pulse_cnt[1]
+   async_testgen_inst/pulse_cnt[2].Q0
+         0.5  async_testgen_inst/pulse_cnt[2].B0
+         0.4  async_testgen_inst/pulse_outlto3.C1
+         0.7  I_24.lat_r.B0
+
+async_testgen_inst/pulse_cnt[2]
+   async_testgen_inst/pulse_cnt[2].Q1
+         0.4  async_testgen_inst/pulse_cnt[2].B1
+         0.7  async_testgen_inst/pulse_outlto3.B1
+         0.4  I_24.lat_r.D0
+
+async_testgen_inst/pulse_cnt[3]
+   async_testgen_inst/pulse_cnt[4].Q0
+         0.5  async_testgen_inst/pulse_cnt[4].B0
+         0.6  async_testgen_inst/pulse_outlto3.D1
+         0.7  I_24.lat_r.C0
+
+async_testgen_inst/pulse_cnt[4]
+   async_testgen_inst/pulse_cnt[4].Q1
+         0.4  async_testgen_inst/pulse_cnt[4].A1
+         0.5  async_testgen_inst/pulse_cnt10lto12_5.A1
+         0.5  async_testgen_inst/pulse_outlto3.B0
+
+async_testgen_inst/pulse_cnt[5]
+   async_testgen_inst/pulse_cnt[6].Q0
+         0.5  async_testgen_inst/pulse_cnt[6].A0
+         0.4  async_testgen_inst/pulse_cnt10lto12_5.C1
+         0.3  async_testgen_inst/pulse_outlto3.D0
+
+async_testgen_inst/pulse_cnt[6]
+   async_testgen_inst/pulse_cnt[6].Q1
+         0.4  async_testgen_inst/pulse_cnt[6].A1
+         0.4  async_testgen_inst/pulse_cnt10lto12_5.D1
+         0.7  async_testgen_inst/pulse_outlto3.A0
+
+async_testgen_inst/pulse_cnt[7]
+   async_testgen_inst/pulse_cnt[8].Q0
+         0.6  async_testgen_inst/pulse_cnt[8].B0
+         0.7  async_testgen_inst/pulse_cnt10lto12_5.B1
+         0.3  async_testgen_inst/pulse_outlto12_4.D0
+
+async_testgen_inst/pulse_cnt[8]
+   async_testgen_inst/pulse_cnt[8].Q1
+         0.4  async_testgen_inst/pulse_cnt[8].B1
+         0.5  async_testgen_inst/pulse_outlto12_4.B1
+         0.4  async_testgen_inst/pulse_cnt10lto12_0.D0
+
+async_testgen_inst/pulse_cnt[9]
+   async_testgen_inst/pulse_cnt[10].Q0
+         0.5  async_testgen_inst/pulse_cnt[10].B0
+         0.3  async_testgen_inst/pulse_outlto12_4.D1
+         0.6  async_testgen_inst/pulse_cnt10lto12_0.C0
+
+async_testgen_inst/pulse_cnt_0_sqmuxa_i
+   async_testgen_inst/pulse_cnt10lto12_5.F0
+         0.4  async_testgen_inst/pulse_cnt[2].LSR
+         0.4  async_testgen_inst/pulse_cnt[4].LSR
+         0.4  async_testgen_inst/pulse_cnt[6].LSR
+         0.6  async_testgen_inst/pulse_cnt[8].LSR
+         0.6  async_testgen_inst/pulse_cnt[10].LSR
+         0.6  async_testgen_inst/pulse_cnt[12].LSR
+         0.2  async_testgen_inst/pulse_cnt_RNO[0].LSR
+
+async_testgen_inst/pulse_cnt_i[0]
+   async_testgen_inst/pulse_cnt_RNO[0].F0
+         0.0  async_testgen_inst/pulse_cnt_RNO[0].DI0
+
+async_testgen_inst/pulse_outlt12
+   async_testgen_inst/pulse_outlto3.F0
+         0.5  async_testgen_inst/pulse_outlto12_4.A0
+
+async_testgen_inst/pulse_outlt5
+   async_testgen_inst/pulse_outlto3.F1
+         0.4  async_testgen_inst/pulse_outlto3.C0
+
+async_testgen_inst/pulse_outlto12_4
+   async_testgen_inst/pulse_outlto12_4.F1
+         0.4  async_testgen_inst/pulse_outlto12_4.B0
+
+async_testgen_inst/un3_pulse_cnt[10]
+   async_testgen_inst/pulse_cnt[10].F1
+         0.0  async_testgen_inst/pulse_cnt[10].DI1
+
+async_testgen_inst/un3_pulse_cnt[11]
+   async_testgen_inst/pulse_cnt[12].F0
+         0.0  async_testgen_inst/pulse_cnt[12].DI0
+
+async_testgen_inst/un3_pulse_cnt[12]
+   async_testgen_inst/pulse_cnt[12].F1
+         0.0  async_testgen_inst/pulse_cnt[12].DI1
+
+async_testgen_inst/un3_pulse_cnt[1]
+   async_testgen_inst/pulse_cnt[2].F0
+         0.0  async_testgen_inst/pulse_cnt[2].DI0
+
+async_testgen_inst/un3_pulse_cnt[2]
+   async_testgen_inst/pulse_cnt[2].F1
+         0.0  async_testgen_inst/pulse_cnt[2].DI1
+
+async_testgen_inst/un3_pulse_cnt[3]
+   async_testgen_inst/pulse_cnt[4].F0
+         0.0  async_testgen_inst/pulse_cnt[4].DI0
+
+async_testgen_inst/un3_pulse_cnt[4]
+   async_testgen_inst/pulse_cnt[4].F1
+         0.0  async_testgen_inst/pulse_cnt[4].DI1
+
+async_testgen_inst/un3_pulse_cnt[5]
+   async_testgen_inst/pulse_cnt[6].F0
+         0.0  async_testgen_inst/pulse_cnt[6].DI0
+
+async_testgen_inst/un3_pulse_cnt[6]
+   async_testgen_inst/pulse_cnt[6].F1
+         0.0  async_testgen_inst/pulse_cnt[6].DI1
+
+async_testgen_inst/un3_pulse_cnt[7]
+   async_testgen_inst/pulse_cnt[8].F0
+         0.0  async_testgen_inst/pulse_cnt[8].DI0
+
+async_testgen_inst/un3_pulse_cnt[8]
+   async_testgen_inst/pulse_cnt[8].F1
+         0.0  async_testgen_inst/pulse_cnt[8].DI1
+
+async_testgen_inst/un3_pulse_cnt[9]
+   async_testgen_inst/pulse_cnt[10].F0
+         0.0  async_testgen_inst/pulse_cnt[10].DI0
+
+async_testgen_inst/un3_pulse_cnt_cry_0
+   async_testgen_inst/un3_pulse_cnt_cry_0_0.FCO
+         0.0  async_testgen_inst/pulse_cnt[2].FCI
+
+async_testgen_inst/un3_pulse_cnt_cry_10
+   async_testgen_inst/pulse_cnt[10].FCO
+         0.0  async_testgen_inst/pulse_cnt[12].FCI
+
+async_testgen_inst/un3_pulse_cnt_cry_2
+   async_testgen_inst/pulse_cnt[2].FCO
+         0.0  async_testgen_inst/pulse_cnt[4].FCI
+
+async_testgen_inst/un3_pulse_cnt_cry_4
+   async_testgen_inst/pulse_cnt[4].FCO
+         0.0  async_testgen_inst/pulse_cnt[6].FCI
+
+async_testgen_inst/un3_pulse_cnt_cry_6
+   async_testgen_inst/pulse_cnt[6].FCO
+         0.0  async_testgen_inst/pulse_cnt[8].FCI
+
+async_testgen_inst/un3_pulse_cnt_cry_8
+   async_testgen_inst/pulse_cnt[8].FCO
+         0.0  async_testgen_inst/pulse_cnt[10].FCI
+
+clk25_c
+   clk25_pad.PADDI
+         1.7  async_testgen_inst/pulse_cnt[2].CLK
+         1.7  async_testgen_inst/pulse_cnt[4].CLK
+         1.7  async_testgen_inst/pulse_cnt[6].CLK
+         1.7  async_testgen_inst/pulse_cnt[8].CLK
+         1.7  async_testgen_inst/pulse_cnt[10].CLK
+         1.7  async_testgen_inst/pulse_cnt[12].CLK
+         1.7  async_testgen_inst/pulse_cnt_RNO[0].CLK
+
+clk8
+   pll8_inst/PLLInst_0.CLKOS
+         1.7  adsn_cnt[7].CLK
+         1.7  fifo32dc_inst/FF_70.CLK
+         1.7  fifo32dc_inst/FF_68.CLK
+         1.7  fifo32dc_inst/FF_66.CLK
+         1.7  fifo32dc_inst/FF_64.CLK
+         1.7  fifo32dc_inst/FF_62.CLK
+         1.7  fifo32dc_inst/FF_1.CLK
+         1.7  adsn_cnt[2].CLK
+         1.7  adsn_cnt[4].CLK
+         1.7  adsn_cnt[6].CLK
+         1.7  wrn_cnt_RNO[0].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/ThrEmpty_Proc.ThrEmpty_1_iv_i.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U1/ThrWRn2_r.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[0].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[1].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[2].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCLK_Proc.Count_vr_4[3].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[1].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[3].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TSR_RNO[5].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TSR_6[7].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[1].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxCNT_r_RNO[2].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxClkEnAc.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInShiftState1.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/TxInStartState1.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_RNO[5].CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Tx_State_ns[1].CLK
+         1.7  adsn_cnt_RNO[0].CLK
+         1.7  din[1].CLK
+         1.7  din[3].CLK
+         1.7  din[5].CLK
+         1.7  din[7].CLK
+         1.7  fifo32dc_inst/XOR2_t7.CLK
+         1.7  fifo32dc_inst/XOR2_t5.CLK
+         1.7  fifo32dc_inst/XOR2_t3.CLK
+         1.7  fifo32dc_inst/XOR2_t1.CLK
+         1.7  fifo32dc_inst/XOR2_t0.CLK
+         1.7  fifo32dc_inst/FF_50.CLK
+         1.7  fifo32dc_inst/FF_48.CLK
+         1.7  fifo32dc_inst/FF_46.CLK
+         1.7  fifo32dc_inst/FF_44.CLK
+         1.7  fifo32dc_inst/FF_42.CLK
+         1.7  fifo32dc_inst/FF_40.CLK
+         1.7  fifo32dc_inst/FF_38.CLK
+         1.7  fifo32dc_inst/FF_36.CLK
+         1.7  fifo32dc_inst/FF_34.CLK
+         1.7  fifo32dc_inst/FF_32.CLK
+         1.7  fifo32dc_inst/FF_20.CLK
+         1.7  fifo32dc_inst/FF_18.CLK
+         1.7  fifo32dc_inst/FF_16.CLK
+         1.7  fifo32dc_inst/FF_14.CLK
+         1.7  fifo32dc_inst/FF_12.CLK
+         1.7  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.CLK
+         1.7  uart_buf_empty_0_sqmuxa.CLK
+         1.7  uart_input_buf[1].CLK
+         1.7  uart_input_buf[3].CLK
+         1.7  uart_input_buf[5].CLK
+         1.7  uart_input_buf[7].CLK
+         1.7  uart_quad_cnt_RNO[1].CLK
+         1.7  wrn_cnt_RNO[1].CLK
+         1.7  wrn_cnt_7[2].CLK
+         1.7  fifo32dc_inst/pdp_ram_0_0_0.CLKB
+
+clk_c
+   clk_pad.PADDI
+         0.1  pll0inst/PLLInst_0.CLKI
+
+dec_inst/N_30
+   dec_inst/un1_out35_1_0_m3.F1
+         0.4  dec_inst/un1_out35_1_0_m3.B0
+         0.4  dec_inst/un1_out35_1_0_o7.C0
+
+dec_inst/N_31
+   dec_inst/un1_out35_1_0_o7.F1
+         0.3  dec_inst/out_2_1_0_.m15_i.D0
+         0.4  dec_inst/un1_out35_1_0_o7.B0
+
+dec_inst/dl[0][0]
+   dec_inst/dl[0][1].Q0
+         0.3  dec_inst/dl[1][1].M0
+
+dec_inst/dl[0][1]
+   dec_inst/dl[0][1].Q1
+         0.3  dec_inst/dl[1][1].M1
+
+dec_inst/dl[0][2]
+   dec_inst/dl[0][3].Q0
+         0.6  dec_inst/dl[1][3].M0
+
+dec_inst/dl[0][3]
+   dec_inst/dl[0][3].Q1
+         0.6  dec_inst/dl[1][3].M1
+
+dec_inst/dl[0][4]
+   dec_inst/dl[0][5].Q0
+         0.6  dec_inst/dl[1][5].M0
+
+dec_inst/dl[0][5]
+   dec_inst/dl[0][5].Q1
+         0.6  dec_inst/dl[1][5].M1
+
+dec_inst/dl[0][6]
+   dec_inst/dl[0][7].Q0
+         0.4  dec_inst/dl[1][7].M0
+
+dec_inst/dl[0][7]
+   dec_inst/dl[0][7].Q1
+         0.4  dec_inst/dl[1][7].M1
+
+dec_inst/dl[1][0]
+   dec_inst/dl[1][1].Q0
+         0.4  dec_inst/in_synced[1].M0
+
+dec_inst/dl[1][1]
+   dec_inst/dl[1][1].Q1
+         0.4  dec_inst/in_synced[1].M1
+
+dec_inst/dl[1][2]
+   dec_inst/dl[1][3].Q0
+         0.4  dec_inst/in_synced[3].M0
+
+dec_inst/dl[1][3]
+   dec_inst/dl[1][3].Q1
+         0.4  dec_inst/in_synced[3].M1
+
+dec_inst/dl[1][4]
+   dec_inst/dl[1][5].Q0
+         0.4  dec_inst/in_synced[5].M0
+
+dec_inst/dl[1][5]
+   dec_inst/dl[1][5].Q1
+         0.4  dec_inst/in_synced[5].M1
+
+dec_inst/dl[1][6]
+   dec_inst/dl[1][7].Q0
+         0.4  dec_inst/in_synced[7].M0
+
+dec_inst/dl[1][7]
+   dec_inst/dl[1][7].Q1
+         0.4  dec_inst/in_synced[7].M1
+         0.6  dec_inst/in_synced_RNI1MG8[7].C0
+
+dec_inst/in_synced7_rising_i
+   dec_inst/in_synced_RNI1MG8[7].F0
+         0.7  dec_inst/out_2_1_0_.m15_i.LSR
+         0.6  dec_inst/un1_out35_1_0_m3.LSR
+         0.7  dec_inst/un1_out35_1_0_o7.LSR
+
+dec_inst/in_synced[0]
+   dec_inst/in_synced[1].Q0
+         0.3  dec_inst/out_2_1_0_.m15_i.D1
+         0.4  dec_inst/un1_out35_1_0_m3.C1
+         0.4  dec_inst/out_2_1_0_.m11_i_1_0.C1
+
+dec_inst/in_synced[1]
+   dec_inst/in_synced[1].Q1
+         0.5  dec_inst/un1_out35_1_0_m3.A1
+         0.7  dec_inst/out_2_1_0_.m11_i_1.A0
+         0.5  dec_inst/out_2_1_0_.m11_i_1_0.A1
+
+dec_inst/in_synced[2]
+   dec_inst/in_synced[3].Q0
+         0.6  dec_inst/out_2_1_0_.m15_i.B1
+         0.3  dec_inst/un1_out35_1_0_m3.D1
+         0.3  dec_inst/un1_out35_1_0_o7.D1
+         0.6  dec_inst/out_2_1_0_.m11_i_1.B0
+         0.6  dec_inst/out_2_1_0_.m11_i_1.B1
+         0.3  dec_inst/out_2_1_0_.m11_i_1_0.D1
+
+dec_inst/in_synced[3]
+   dec_inst/in_synced[3].Q1
+         0.5  dec_inst/un1_out35_1_0_o7.A1
+         0.6  dec_inst/out_2_1_0_.m11_i_1.C0
+         0.6  dec_inst/out_2_1_0_.m11_i_1.C1
+         0.5  dec_inst/out_2_1_0_.m11_i_1_0.A0
+         0.4  dec_inst/out_2_1_0_.m15_i_0.C0
+
+dec_inst/in_synced[4]
+   dec_inst/in_synced[5].Q0
+         0.5  dec_inst/un1_out35_1_0_m3.A0
+         0.5  dec_inst/un1_out35_1_0_o7.C1
+         0.3  dec_inst/out_2_1_0_.m11_i_1.D0
+         0.7  dec_inst/out_2_1_0_.m11_i_1.A1
+         0.5  dec_inst/out_2_1_0_.m11_i_1_0.C0
+
+dec_inst/in_synced[5]
+   dec_inst/in_synced[5].Q1
+         0.7  dec_inst/un1_out35_1_0_o7.B1
+         0.4  dec_inst/out_2_1_0_.m11_i_1.D1
+         0.7  dec_inst/out_2_1_0_.m11_i_1_0.B0
+         0.7  dec_inst/out_2_1_0_.m11_i_1_0.B1
+         0.3  dec_inst/out_2_1_0_.m15_i_0.D0
+         0.3  dec_inst/out_2_1_0_.m15_i_0.D1
+
+dec_inst/in_synced[6]
+   dec_inst/in_synced[7].Q0
+         0.4  dec_inst/out_2_1_0_.m15_i.C0
+         0.3  dec_inst/un1_out35_1_0_m3.D0
+         0.3  dec_inst/out_2_1_0_.m11_i_1_0.D0
+         0.4  dec_inst/out_2_1_0_.m15_i_0.C1
+
+dec_inst/in_synced[7]
+   dec_inst/in_synced[7].Q1
+         0.5  dec_inst/in_synced_RNI1MG8[7].A0
+
+dec_inst/m11_i
+   dec_inst/out_2_1_0_.m15_i.F0
+         0.0  dec_inst/out_2_1_0_.m15_i.DI0
+
+dec_inst/m11_i_1
+   dec_inst/out_2_1_0_.m11_i_1.F1
+         0.4  dec_inst/out_2_1_0_.m15_i.A0
+
+dec_inst/m11_i_1_0
+   dec_inst/out_2_1_0_.m11_i_1_0.F1
+         0.4  dec_inst/out_2_1_0_.m15_i.B0
+
+dec_inst/m15_i
+   dec_inst/out_2_1_0_.m15_i.F1
+         0.0  dec_inst/out_2_1_0_.m15_i.DI1
+
+dec_inst/m15_i_0
+   dec_inst/out_2_1_0_.m15_i_0.F1
+         0.5  dec_inst/out_2_1_0_.m15_i.A1
+
+dec_inst/m15_i_3
+   dec_inst/out_2_1_0_.m11_i_1.F0
+         0.3  dec_inst/out_2_1_0_.m15_i.C1
+
+dec_inst/un1_out31_1_i_0
+   dec_inst/un1_out35_1_0_m3.F0
+         0.0  dec_inst/un1_out35_1_0_m3.DI0
+
+dec_inst/un1_out31_1_i_0_1
+   dec_inst/out_2_1_0_.m15_i_0.F0
+         0.4  dec_inst/un1_out35_1_0_m3.C0
+
+dec_inst/un1_out35_1_0_0
+   dec_inst/out_2_1_0_.m11_i_1_0.F0
+         0.1  dec_inst/un1_out35_1_0_o7.D0
+
+dec_inst/un1_out35_1_i
+   dec_inst/un1_out35_1_0_o7.F0
+         0.0  dec_inst/un1_out35_1_0_o7.DI0
+
+din[0]
+   din[1].Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[1].M0
+
+din[1]
+   din[1].Q1
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[1].M1
+
+din[2]
+   din[3].Q0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[3].M0
+
+din[3]
+   din[3].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[3].M1
+
+din[4]
+   din[5].Q0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[5].M0
+
+din[5]
+   din[5].Q1
+         0.7  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[5].M1
+
+din[6]
+   din[7].Q0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[7].M0
+
+din[7]
+   din[7].Q1
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U1/THR[7].M1
+
+din_1_sqmuxa
+   din_1_sqmuxa.OFX0
+         0.3  uart_quad_cnt_0_sqmuxa.C0
+
+fifo32dc_inst/Full
+   fifo32dc_inst/FF_0.Q0
+         0.5  fifo32dc_inst/AND2_t20.A0
+
+fifo32dc_inst/LUT4_5_0_f5a
+   fifo32dc_inst/LUT4_5_0.OFX0
+         0.0  fifo32dc_inst/LUT4_5_1.FXA
+
+fifo32dc_inst/LUT4_5_1_f5b
+   fifo32dc_inst/LUT4_5_1.OFX0
+         0.0  fifo32dc_inst/LUT4_5_1.FXB
+
+fifo32dc_inst/LUT4_8_0_f5a
+   fifo32dc_inst/LUT4_8_0.OFX0
+         0.0  fifo32dc_inst/LUT4_8_1.FXA
+
+fifo32dc_inst/LUT4_8_1_f5b
+   fifo32dc_inst/LUT4_8_1.OFX0
+         0.0  fifo32dc_inst/LUT4_8_1.FXB
+
+fifo32dc_inst/cmp_ci
+   fifo32dc_inst/empty_cmp_ci_a.FCO
+         0.0  fifo32dc_inst/empty_cmp_0.FCI
+
+fifo32dc_inst/cmp_ci_1
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+         0.0  fifo32dc_inst/full_cmp_0.FCI
+
+fifo32dc_inst/co0
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+         0.0  fifo32dc_inst/FF_98.FCI
+
+fifo32dc_inst/co0_1
+   fifo32dc_inst/FF_70.FCO
+         0.0  fifo32dc_inst/FF_68.FCI
+
+fifo32dc_inst/co0_2
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+
+fifo32dc_inst/co0_3
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+         0.0  fifo32dc_inst/full_cmp_1.FCI
+
+fifo32dc_inst/co1
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+         0.0  fifo32dc_inst/FF_96.FCI
+
+fifo32dc_inst/co1_1
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+
+fifo32dc_inst/co1_2
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+         0.0  fifo32dc_inst/empty_cmp_2.FCI
+
+fifo32dc_inst/co1_3
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+
+fifo32dc_inst/co2
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+         0.0  fifo32dc_inst/FF_94.FCI
+
+fifo32dc_inst/co2_1
+   fifo32dc_inst/FF_66.FCO
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+
+fifo32dc_inst/co2_2
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+         0.0  fifo32dc_inst/empty_cmp_3.FCI
+
+fifo32dc_inst/co2_3
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+         0.0  fifo32dc_inst/full_cmp_3.FCI
+
+fifo32dc_inst/co3
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+         0.0  fifo32dc_inst/FF_92.FCI
+
+fifo32dc_inst/co3_1
+   fifo32dc_inst/FF_64.FCO
+         0.0  fifo32dc_inst/FF_62.FCI
+
+fifo32dc_inst/co3_2
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+
+fifo32dc_inst/co3_3
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+         0.0  fifo32dc_inst/full_cmp_4.FCI
+
+fifo32dc_inst/empty_cmp_clr
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+
+fifo32dc_inst/empty_cmp_set
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+
+fifo32dc_inst/empty_d
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+
+fifo32dc_inst/empty_d_c
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+         0.0  fifo32dc_inst/FF_1.FCI
+
+fifo32dc_inst/full_cmp_clr
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+
+fifo32dc_inst/full_cmp_set
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+
+fifo32dc_inst/full_d
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+
+fifo32dc_inst/full_d_c
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+         0.0  fifo32dc_inst/FF_0.FCI
+
+fifo32dc_inst/invout_0
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+         0.5  fifo32dc_inst/empty_cmp_ci_a.A1
+         0.7  fifo32dc_inst/empty_cmp_ci_a.B1
+
+fifo32dc_inst/ircount_0
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+         0.0  fifo32dc_inst/FF_70.DI0
+
+fifo32dc_inst/ircount_1
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+         0.0  fifo32dc_inst/FF_70.DI1
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+         0.3  fifo32dc_inst/FF_38.M0
+
+fifo32dc_inst/w_gcount_3
+   fifo32dc_inst/XOR2_t14.Q1
+         0.3  fifo32dc_inst/FF_38.M1
+
+fifo32dc_inst/w_gcount_4
+   fifo32dc_inst/XOR2_t12.Q0
+         0.5  fifo32dc_inst/FF_36.M0
+
+fifo32dc_inst/w_gcount_5
+   fifo32dc_inst/XOR2_t12.Q1
+         0.5  fifo32dc_inst/FF_36.M1
+
+fifo32dc_inst/w_gcount_6
+   fifo32dc_inst/XOR2_t10.Q0
+         0.5  fifo32dc_inst/FF_34.M0
+
+fifo32dc_inst/w_gcount_7
+   fifo32dc_inst/XOR2_t10.Q1
+         0.5  fifo32dc_inst/FF_34.M1
+
+fifo32dc_inst/w_gcount_8
+   fifo32dc_inst/XOR2_t9.Q0
+         0.3  fifo32dc_inst/FF_32.M0
+
+fifo32dc_inst/w_gcount_9
+   fifo32dc_inst/XOR2_t9.Q1
+         0.5  fifo32dc_inst/FF_32.M1
+
+fifo32dc_inst/w_gcount_r0
+   fifo32dc_inst/FF_40.Q0
+         0.3  fifo32dc_inst/FF_20.M0
+
+fifo32dc_inst/w_gcount_r1
+   fifo32dc_inst/FF_40.Q1
+         0.3  fifo32dc_inst/FF_20.M1
+
+fifo32dc_inst/w_gcount_r2
+   fifo32dc_inst/FF_38.Q0
+         0.6  fifo32dc_inst/FF_18.M0
+
+fifo32dc_inst/w_gcount_r20
+   fifo32dc_inst/FF_20.Q0
+         0.8  fifo32dc_inst/LUT4_14.D1
+
+fifo32dc_inst/w_gcount_r21
+   fifo32dc_inst/FF_20.Q1
+         1.0  fifo32dc_inst/LUT4_14.A1
+         1.0  fifo32dc_inst/LUT4_15.A1
+
+fifo32dc_inst/w_gcount_r22
+   fifo32dc_inst/FF_18.Q0
+         0.7  fifo32dc_inst/LUT4_15.B0
+
+fifo32dc_inst/w_gcount_r23
+   fifo32dc_inst/FF_18.Q1
+         0.4  fifo32dc_inst/LUT4_15.C0
+         0.4  fifo32dc_inst/LUT4_21.D0
+
+fifo32dc_inst/w_gcount_r24
+   fifo32dc_inst/FF_16.Q0
+         0.5  fifo32dc_inst/LUT4_15.D0
+         0.4  fifo32dc_inst/LUT4_18.C1
+         0.8  fifo32dc_inst/LUT4_21.B0
+
+fifo32dc_inst/w_gcount_r25
+   fifo32dc_inst/FF_16.Q1
+         0.4  fifo32dc_inst/LUT4_19.M0
+         0.7  fifo32dc_inst/LUT4_15.A0
+         0.4  fifo32dc_inst/LUT4_18.D1
+         0.7  fifo32dc_inst/LUT4_21.A0
+
+fifo32dc_inst/w_gcount_r26
+   fifo32dc_inst/FF_14.Q0
+         0.3  fifo32dc_inst/LUT4_16.D0
+         0.3  fifo32dc_inst/LUT4_16.D1
+         0.5  fifo32dc_inst/LUT4_19.D0
+         0.5  fifo32dc_inst/LUT4_19.D1
+         0.5  fifo32dc_inst/LUT4_14.D0
+         0.7  fifo32dc_inst/LUT4_18.B1
+
+fifo32dc_inst/w_gcount_r27
+   fifo32dc_inst/FF_14.Q1
+         0.5  fifo32dc_inst/LUT4_16.B0
+         0.5  fifo32dc_inst/LUT4_16.B1
+         0.7  fifo32dc_inst/LUT4_19.B0
+         0.7  fifo32dc_inst/LUT4_19.B1
+         0.7  fifo32dc_inst/LUT4_14.B0
+         0.5  fifo32dc_inst/LUT4_18.D0
+
+fifo32dc_inst/w_gcount_r28
+   fifo32dc_inst/FF_12.Q0
+         0.5  fifo32dc_inst/LUT4_16.C0
+         0.5  fifo32dc_inst/LUT4_16.C1
+         0.5  fifo32dc_inst/LUT4_19.C0
+         0.5  fifo32dc_inst/LUT4_19.C1
+         0.5  fifo32dc_inst/LUT4_14.C0
+         0.5  fifo32dc_inst/LUT4_18.C0
+         0.5  fifo32dc_inst/LUT4_21.A1
+
+fifo32dc_inst/w_gcount_r29
+   fifo32dc_inst/FF_12.Q1
+         0.6  fifo32dc_inst/LUT4_16.A0
+         0.6  fifo32dc_inst/LUT4_16.A1
+         0.6  fifo32dc_inst/LUT4_19.A0
+         0.6  fifo32dc_inst/LUT4_19.A1
+         0.6  fifo32dc_inst/LUT4_14.A0
+         0.6  fifo32dc_inst/LUT4_18.A0
+         0.5  fifo32dc_inst/LUT4_2.B0
+         0.5  fifo32dc_inst/LUT4_2.B1
+         0.5  fifo32dc_inst/LUT4_21.B1
+
+fifo32dc_inst/w_gcount_r3
+   fifo32dc_inst/FF_38.Q1
+         0.7  fifo32dc_inst/FF_18.M1
+
+fifo32dc_inst/w_gcount_r4
+   fifo32dc_inst/FF_36.Q0
+         0.3  fifo32dc_inst/FF_16.M0
+
+fifo32dc_inst/w_gcount_r5
+   fifo32dc_inst/FF_36.Q1
+         0.3  fifo32dc_inst/FF_16.M1
+
+fifo32dc_inst/w_gcount_r6
+   fifo32dc_inst/FF_34.Q0
+         0.5  fifo32dc_inst/FF_14.M0
+
+fifo32dc_inst/w_gcount_r7
+   fifo32dc_inst/FF_34.Q1
+         0.3  fifo32dc_inst/FF_14.M1
+
+fifo32dc_inst/w_gcount_r8
+   fifo32dc_inst/FF_32.Q0
+         0.8  fifo32dc_inst/FF_12.M0
+
+fifo32dc_inst/w_gcount_r9
+   fifo32dc_inst/FF_32.Q1
+         0.8  fifo32dc_inst/FF_12.M1
+
+fifo32dc_inst/w_gctr_ci
+   fifo32dc_inst/w_gctr_cia.FCO
+         0.0  fifo32dc_inst/FF_100.FCI
+
+fifo32dc_inst/w_gdata_0
+   fifo32dc_inst/XOR2_t16.F0
+         0.0  fifo32dc_inst/XOR2_t16.DI0
+
+fifo32dc_inst/w_gdata_1
+   fifo32dc_inst/XOR2_t16.F1
+         0.0  fifo32dc_inst/XOR2_t16.DI1
+
+fifo32dc_inst/w_gdata_2
+   fifo32dc_inst/XOR2_t14.F0
+         0.0  fifo32dc_inst/XOR2_t14.DI0
+
+fifo32dc_inst/w_gdata_3
+   fifo32dc_inst/XOR2_t14.F1
+         0.0  fifo32dc_inst/XOR2_t14.DI1
+
+fifo32dc_inst/w_gdata_4
+   fifo32dc_inst/XOR2_t12.F0
+         0.0  fifo32dc_inst/XOR2_t12.DI0
+
+fifo32dc_inst/w_gdata_5
+   fifo32dc_inst/XOR2_t12.F1
+         0.0  fifo32dc_inst/XOR2_t12.DI1
+
+fifo32dc_inst/w_gdata_6
+   fifo32dc_inst/XOR2_t10.F0
+         0.0  fifo32dc_inst/XOR2_t10.DI0
+
+fifo32dc_inst/w_gdata_7
+   fifo32dc_inst/XOR2_t10.F1
+         0.0  fifo32dc_inst/XOR2_t10.DI1
+
+fifo32dc_inst/w_gdata_8
+   fifo32dc_inst/XOR2_t9.F0
+         0.0  fifo32dc_inst/XOR2_t9.DI0
+
+fifo32dc_inst/wcount_0
+   fifo32dc_inst/FF_100.Q0
+         0.5  fifo32dc_inst/FF_100.A0
+         0.7  fifo32dc_inst/full_cmp_0.A0
+         0.9  fifo32dc_inst/XOR2_t16.A0
+         0.6  fifo32dc_inst/FF_80.M0
+
+fifo32dc_inst/wcount_1
+   fifo32dc_inst/FF_100.Q1
+         0.4  fifo32dc_inst/FF_100.B1
+         0.7  fifo32dc_inst/full_cmp_0.B1
+         0.9  fifo32dc_inst/XOR2_t16.B0
+         0.9  fifo32dc_inst/XOR2_t16.B1
+         0.6  fifo32dc_inst/FF_80.M1
+
+fifo32dc_inst/wcount_2
+   fifo32dc_inst/FF_98.Q0
+         0.5  fifo32dc_inst/FF_98.B0
+         0.7  fifo32dc_inst/full_cmp_1.A0
+         0.4  fifo32dc_inst/XOR2_t16.C1
+         0.9  fifo32dc_inst/XOR2_t14.B0
+         0.8  fifo32dc_inst/FF_78.M0
+
+fifo32dc_inst/wcount_3
+   fifo32dc_inst/FF_98.Q1
+         0.4  fifo32dc_inst/FF_98.A1
+         0.8  fifo32dc_inst/full_cmp_1.A1
+         0.9  fifo32dc_inst/XOR2_t14.A0
+         0.9  fifo32dc_inst/XOR2_t14.A1
+         0.8  fifo32dc_inst/FF_78.M1
+
+fifo32dc_inst/wcount_4
+   fifo32dc_inst/FF_96.Q0
+         0.5  fifo32dc_inst/FF_96.B0
+         1.7  fifo32dc_inst/full_cmp_2.A0
+         0.8  fifo32dc_inst/XOR2_t14.C1
+         0.4  fifo32dc_inst/XOR2_t12.C0
+         1.0  fifo32dc_inst/FF_76.M0
+
+fifo32dc_inst/wcount_5
+   fifo32dc_inst/FF_96.Q1
+         0.4  fifo32dc_inst/FF_96.A1
+         0.7  fifo32dc_inst/full_cmp_2.A1
+         0.6  fifo32dc_inst/XOR2_t12.A0
+         0.6  fifo32dc_inst/XOR2_t12.A1
+         0.6  fifo32dc_inst/FF_76.M1
+
+fifo32dc_inst/wcount_6
+   fifo32dc_inst/FF_94.Q0
+         0.5  fifo32dc_inst/FF_94.B0
+         0.7  fifo32dc_inst/full_cmp_3.A0
+         0.5  fifo32dc_inst/XOR2_t12.D1
+         0.6  fifo32dc_inst/XOR2_t10.C0
+         0.7  fifo32dc_inst/FF_74.M0
+
+fifo32dc_inst/wcount_7
+   fifo32dc_inst/FF_94.Q1
+         0.4  fifo32dc_inst/FF_94.B1
+         0.7  fifo32dc_inst/full_cmp_3.B1
+         0.7  fifo32dc_inst/XOR2_t10.B0
+         0.7  fifo32dc_inst/XOR2_t10.B1
+         0.7  fifo32dc_inst/FF_74.M1
+
+fifo32dc_inst/wcount_8
+   fifo32dc_inst/FF_92.Q0
+         0.5  fifo32dc_inst/FF_92.A0
+         1.0  fifo32dc_inst/full_cmp_4.B0
+         0.8  fifo32dc_inst/XOR2_t10.C1
+         0.8  fifo32dc_inst/XOR2_t9.C0
+         0.7  fifo32dc_inst/FF_72.M0
+
+fifo32dc_inst/wcount_9
+   fifo32dc_inst/FF_92.Q1
+         0.4  fifo32dc_inst/FF_92.B1
+         0.5  fifo32dc_inst/XOR2_t9.A0
+         0.4  fifo32dc_inst/XOR2_t9.M1
+         0.6  fifo32dc_inst/FF_72.M1
+         0.9  fifo32dc_inst/LUT4_1.A0
+         0.9  fifo32dc_inst/LUT4_1.A1
+
+fifo32dc_inst/wcount_r0
+   fifo32dc_inst/LUT4_14.F1
+         0.5  fifo32dc_inst/empty_cmp_0.A0
+
+fifo32dc_inst/wcount_r1
+   fifo32dc_inst/LUT4_15.F1
+         0.7  fifo32dc_inst/empty_cmp_0.A1
+
+fifo32dc_inst/wcount_r2
+   fifo32dc_inst/LUT4_16.OFX0
+         0.6  fifo32dc_inst/empty_cmp_1.A0
+
+fifo32dc_inst/wcount_r3
+   fifo32dc_inst/LUT4_21.F0
+         0.7  fifo32dc_inst/empty_cmp_1.B1
+
+fifo32dc_inst/wcount_r4
+   fifo32dc_inst/LUT4_18.F1
+         0.5  fifo32dc_inst/empty_cmp_2.A0
+
+fifo32dc_inst/wcount_r5
+   fifo32dc_inst/LUT4_19.OFX0
+         0.7  fifo32dc_inst/empty_cmp_2.A1
+
+fifo32dc_inst/wcount_r7
+   fifo32dc_inst/LUT4_18.F0
+         0.8  fifo32dc_inst/empty_cmp_3.A1
+         0.5  fifo32dc_inst/LUT4_18.A1
+
+fifo32dc_inst/wcount_r8
+   fifo32dc_inst/LUT4_21.F1
+         0.5  fifo32dc_inst/empty_cmp_4.B0
+
+fifo32dc_inst/wptr_0
+   fifo32dc_inst/FF_80.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA5
+
+fifo32dc_inst/wptr_1
+   fifo32dc_inst/FF_80.Q1
+         0.8  fifo32dc_inst/pdp_ram_0_0_0.ADA6
+
+fifo32dc_inst/wptr_2
+   fifo32dc_inst/FF_78.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA7
+
+fifo32dc_inst/wptr_3
+   fifo32dc_inst/FF_78.Q1
+         0.6  fifo32dc_inst/pdp_ram_0_0_0.ADA8
+
+fifo32dc_inst/wptr_4
+   fifo32dc_inst/FF_76.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA9
+
+fifo32dc_inst/wptr_5
+   fifo32dc_inst/FF_76.Q1
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA10
+
+fifo32dc_inst/wptr_6
+   fifo32dc_inst/FF_74.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA11
+
+fifo32dc_inst/wptr_7
+   fifo32dc_inst/FF_74.Q1
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.ADA12
+
+fifo32dc_inst/wptr_8
+   fifo32dc_inst/FF_72.Q0
+         0.5  fifo32dc_inst/pdp_ram_0_0_0.ADA13
+
+fifo32dc_inst/wptr_9
+   fifo32dc_inst/FF_72.Q1
+         0.4  fifo32dc_inst/LUT4_1.D0
+         0.4  fifo32dc_inst/LUT4_1.D1
+
+fifo32dc_inst/wren_i
+   fifo32dc_inst/AND2_t20.F0
+         0.3  fifo32dc_inst/FF_100.CE
+         0.5  fifo32dc_inst/FF_98.CE
+         0.5  fifo32dc_inst/FF_96.CE
+         0.6  fifo32dc_inst/FF_94.CE
+         0.6  fifo32dc_inst/FF_92.CE
+         0.9  fifo32dc_inst/full_cmp_ci_a.A1
+         0.9  fifo32dc_inst/full_cmp_ci_a.B1
+         0.6  fifo32dc_inst/XOR2_t16.CE
+         0.6  fifo32dc_inst/XOR2_t14.CE
+         0.3  fifo32dc_inst/XOR2_t12.CE
+         0.3  fifo32dc_inst/XOR2_t10.CE
+         0.8  fifo32dc_inst/XOR2_t9.CE
+         0.6  fifo32dc_inst/FF_80.CE
+         0.6  fifo32dc_inst/FF_78.CE
+         0.8  fifo32dc_inst/FF_76.CE
+         0.7  fifo32dc_inst/FF_74.CE
+         0.3  fifo32dc_inst/FF_72.CE
+         0.8  fifo32dc_inst/pdp_ram_0_0_0.CEA
+
+fifo_empty
+   fifo32dc_inst/FF_1.Q0
+         0.6  fifo32dc_inst/FF_70.CE
+         0.6  fifo32dc_inst/FF_68.CE
+         0.6  fifo32dc_inst/FF_66.CE
+         0.8  fifo32dc_inst/FF_64.CE
+         0.8  fifo32dc_inst/FF_62.CE
+         0.6  fifo32dc_inst/XOR2_t7.CE
+         0.6  fifo32dc_inst/XOR2_t5.CE
+         0.6  fifo32dc_inst/XOR2_t3.CE
+         0.6  fifo32dc_inst/XOR2_t1.CE
+         0.5  fifo32dc_inst/XOR2_t0.CE
+         0.5  fifo32dc_inst/FF_50.CE
+         0.3  fifo32dc_inst/FF_48.CE
+         0.3  fifo32dc_inst/FF_46.CE
+         0.5  fifo32dc_inst/FF_44.CE
+         0.8  fifo32dc_inst/FF_42.CE
+         0.8  uart_quad_cnt_0_sqmuxa.D0
+         0.8  uart_quad_cnt_0_sqmuxa.D1
+         0.5  fifo32dc_inst/INV_0.C0
+         1.0  uart_buf_empty_RNO.D0
+         0.9  fifo32dc_inst/pdp_ram_0_0_0.CEB
+         0.9  fifo32dc_inst/pdp_ram_0_0_0.OCEB
+
+fifo_out[0]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA0
+         0.8  uart_input_buf[1].M0
+
+fifo_out[1]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA1
+         0.7  uart_input_buf[1].M1
+
+fifo_out[2]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA2
+         0.8  uart_input_buf[3].M0
+
+fifo_out[3]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA3
+         0.8  uart_input_buf[3].M1
+
+fifo_out[4]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA4
+         0.8  uart_input_buf[5].M0
+
+fifo_out[5]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA5
+         0.8  uart_input_buf[5].M1
+
+fifo_out[6]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA6
+         0.9  uart_input_buf[7].M0
+
+fifo_out[7]
+   fifo32dc_inst/pdp_ram_0_0_0.DOA7
+         0.9  uart_input_buf[7].M1
+
+pll0inst/GND
+   pll0inst/GND.F0
+         0.5  pll0inst/PLLInst_0.STDBY
+
+pll8_inst/CLKOP
+   pll8_inst/PLLInst_0.CLKOP
+         1.7  pll8_inst/PLLInst_0.CLKFB
+
+pll8_inst/GND
+   pll8_inst/GND.F0
+         0.5  pll8_inst/PLLInst_0.STDBY
+
+pll_clks[0]
+   pll0inst/PLLInst_0.CLKOP
+         1.7  pulse_cnt_RNO[0].CLK
+         1.7  pulse_cnt_RNO[2].CLK
+         1.7  tdc_inst/genblk1[0].out[0].CLK
+         1.7  tdc_inst_genblk1[0].outio[4].CLK
+         1.7  pll8_inst/PLLInst_0.CLKI
+         1.7  pll0inst/PLLInst_0.CLKFB
+
+pll_clks[1]
+   pll0inst/PLLInst_0.CLKOS
+         1.7  tdc_inst/genblk1[1].out[1].CLK
+         1.7  tdc_inst/genblk1[1].out[5].CLK
+
+pll_clks[2]
+   pll0inst/PLLInst_0.CLKOS2
+         1.7  tdc_inst/genblk1[2].out[2].CLK
+         1.7  tdc_inst/genblk1[2].out[6].CLK
+
+pll_clks[3]
+   pll0inst/PLLInst_0.CLKOS3
+         1.7  fifo32dc_inst/FF_100.CLK
+         1.7  fifo32dc_inst/FF_98.CLK
+         1.7  fifo32dc_inst/FF_96.CLK
+         1.7  fifo32dc_inst/FF_94.CLK
+         1.7  fifo32dc_inst/FF_92.CLK
+         1.7  fifo32dc_inst/FF_0.CLK
+         1.7  dec_inst/dl[0][1].CLK
+         1.7  dec_inst/dl[0][3].CLK
+         1.7  dec_inst/dl[0][5].CLK
+         1.7  dec_inst/dl[0][7].CLK
+         1.7  dec_inst/dl[1][1].CLK
+         1.7  dec_inst/dl[1][3].CLK
+         1.7  dec_inst/dl[1][5].CLK
+         1.7  dec_inst/dl[1][7].CLK
+         1.7  dec_inst/in_synced[1].CLK
+         1.7  dec_inst/in_synced[3].CLK
+         1.7  dec_inst/in_synced[5].CLK
+         1.7  dec_inst/in_synced[7].CLK
+         1.7  fifo32dc_inst/FF_30.CLK
+         1.7  fifo32dc_inst/FF_28.CLK
+         1.7  fifo32dc_inst/FF_26.CLK
+         1.7  fifo32dc_inst/FF_24.CLK
+         1.7  fifo32dc_inst/FF_22.CLK
+         1.7  fifo32dc_inst/FF_10.CLK
+         1.7  fifo32dc_inst/FF_8.CLK
+         1.7  fifo32dc_inst/FF_6.CLK
+         1.7  fifo32dc_inst/FF_4.CLK
+         1.7  fifo32dc_inst/FF_2.CLK
+         1.7  fifo32dc_inst/XOR2_t16.CLK
+         1.7  fifo32dc_inst/XOR2_t14.CLK
+         1.7  fifo32dc_inst/XOR2_t12.CLK
+         1.7  fifo32dc_inst/XOR2_t10.CLK
+         1.7  fifo32dc_inst/XOR2_t9.CLK
+         1.7  fifo32dc_inst/FF_80.CLK
+         1.7  fifo32dc_inst/FF_78.CLK
+         1.7  fifo32dc_inst/FF_76.CLK
+         1.7  fifo32dc_inst/FF_74.CLK
+         1.7  fifo32dc_inst/FF_72.CLK
+         1.7  dec_inst/out_2_1_0_.m15_i.CLK
+         1.7  dec_inst/un1_out35_1_0_m3.CLK
+         1.7  tdc_inst/genblk1[3].out[3].CLK
+         1.7  tdc_inst/genblk1[3].out[7].CLK
+         1.7  dec_inst/un1_out35_1_0_o7.CLK
+         1.7  fifo32dc_inst/pdp_ram_0_0_0.CLKA
+
+pulse_async_c
+   async_testgen_inst/pulse_outlto12_4.F0
+         2.6  pulse_async_pad.PADDO
+
+pulse_cnt[1]
+   pulse_cnt_RNO[2].Q0
+         0.6  pulse_cnt_RNO[2].B0
+         0.6  pulse_cnt_RNO[2].B1
+         0.5  UART_VerilogWrapper_TO_inst2/inst1/U1/pulse_cnt_0_sqmuxa_i.A0
+
+pulse_cnt[2]
+   pulse_cnt_RNO[2].Q1
+         0.4  pulse_cnt_RNO[2].A1
+         0.3  UART_VerilogWrapper_TO_inst2/inst1/U1/pulse_cnt_0_sqmuxa_i.D0
+         1.8  pulse_out_pad_RNO.D0
+
+pulse_cnt_0_sqmuxa_i
+   UART_VerilogWrapper_TO_inst2/inst1/U1/pulse_cnt_0_sqmuxa_i.F0
+         0.4  pulse_cnt_RNO[0].LSR
+         0.2  pulse_cnt_RNO[2].LSR
+
+pulse_cnt_RNO[1]
+   pulse_cnt_RNO[2].F0
+         0.0  pulse_cnt_RNO[2].DI0
+
+pulse_cnt_RNO[2]
+   pulse_cnt_RNO[2].F1
+         0.0  pulse_cnt_RNO[2].DI1
+
+pulse_cnt_i[2]
+   pulse_out_pad_RNO.F0
+         1.7  pulse_out_pad.PADDO
+
+reset_c
+   reset_pad.PADDI
+         5.2  adsn_cnt[7].LSR
+         5.2  adsn_cnt[2].LSR
+         5.2  adsn_cnt[4].LSR
+         5.2  adsn_cnt[6].LSR
+         5.2  wrn_cnt_RNO[0].LSR
+         5.3  adsn_cnt_RNO[0].LSR
+         5.3  uart_buf_empty_0_sqmuxa.LSR
+         5.2  wrn_cnt_RNO[1].LSR
+         5.2  wrn_cnt_7[2].LSR
+         5.7  wrn_cnt17.C0
+         5.4  async_testgen_inst/pulse_cnt10lto12_5.D0
+         5.8  uart_quad_cnt_0_sqmuxa.B0
+         5.8  uart_quad_cnt_0_sqmuxa.B1
+         5.4  I_24.lat_r.D1
+         5.4  UART_VerilogWrapper_TO_inst2/inst1/U1/pulse_cnt_0_sqmuxa_i.B0
+         4.2  GSR_INST.GSR
+
+s_data[0]
+   dec_inst/out_2_1_0_.m15_i.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.DIA0
+
+s_data[1]
+   dec_inst/out_2_1_0_.m15_i.Q1
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.DIA1
+
+s_data[2]
+   dec_inst/un1_out35_1_0_m3.Q0
+         0.7  fifo32dc_inst/pdp_ram_0_0_0.DIA2
+
+tdc_out[0]
+   tdc_inst/genblk1[0].out[0].Q0
+         0.6  dec_inst/dl[0][1].M0
+
+tdc_out[1]
+   tdc_inst/genblk1[1].out[1].Q0
+         0.6  dec_inst/dl[0][1].M1
+
+tdc_out[2]
+   tdc_inst/genblk1[2].out[2].Q0
+         0.5  dec_inst/dl[0][3].M0
+
+tdc_out[3]
+   tdc_inst/genblk1[3].out[3].Q0
+         0.3  dec_inst/dl[0][3].M1
+
+tdc_out[4]
+   tdc_inst_genblk1[0].outio[4].INFF
+         3.9  dec_inst/dl[0][5].M0
+
+tdc_out[5]
+   tdc_inst/genblk1[1].out[5].Q0
+         0.3  dec_inst/dl[0][5].M1
+
+tdc_out[6]
+   tdc_inst/genblk1[2].out[6].Q0
+         0.5  dec_inst/dl[0][7].M0
+
+tdc_out[7]
+   tdc_inst/genblk1[3].out[7].Q0
+         0.3  dec_inst/dl[0][7].M1
+
+trig_c
+   trig_pad.PADDI
+         3.9  tdc_inst/genblk1[0].out[0].M0
+         4.0  tdc_inst/genblk1[1].out[1].M0
+         4.2  tdc_inst/genblk1[2].out[2].M0
+         4.0  tdc_inst/genblk1[3].out[3].M0
+         4.2  tdc_inst/genblk1[1].out[5].M0
+         4.2  tdc_inst/genblk1[2].out[6].M0
+         4.2  tdc_inst/genblk1[3].out[7].M0
+         0.0  tdc_inst_genblk1[0].outio[4].DI
+
+txd_c
+   UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i.Q0
+         0.4  UART_VerilogWrapper_TO_inst2/inst1/U4/Shift_Data_Proc.TxOutput_12_iv_i_RNO.C0
+         3.4  txd_pad.PADDO
+
+uart_buf_empty
+   uart_buf_empty_0_sqmuxa.Q0
+         0.6  wrn_cnt_RNO[0].C0
+         0.1  uart_buf_empty_0_sqmuxa.D0
+         0.3  uart_quad_cnt_RNO[1].D0
+         0.3  wrn_cnt_RNO[1].D0
+         0.3  wrn_cnt_7[2].D0
+         0.6  din_1_sqmuxa.M0
+         0.9  wrn_cnt17.B0
+         0.7  uart_quad_cnt_0_sqmuxa.A0
+         0.7  uart_quad_cnt_0_sqmuxa.A1
+         0.6  uart_buf_empty_RNO.B0
+
+uart_buf_empty_0_sqmuxa
+   uart_buf_empty_0_sqmuxa.F0
+         0.0  uart_buf_empty_0_sqmuxa.DI0
+
+uart_buf_empty_1_sqmuxa_i
+   uart_buf_empty_RNO.F0
+         0.2  uart_buf_empty_0_sqmuxa.CE
+
+uart_buf_empty_i
+   uart_quad_cnt_RNO[1].F0
+         0.0  uart_quad_cnt_RNO[1].DI0
+
+uart_input_buf[0]
+   uart_input_buf[1].Q0
+         0.3  din[1].M0
+
+uart_input_buf[1]
+   uart_input_buf[1].Q1
+         0.4  din[1].M1
+
+uart_input_buf[2]
+   uart_input_buf[3].Q0
+         0.4  din[3].M0
+
+uart_input_buf[3]
+   uart_input_buf[3].Q1
+         0.9  din[3].M1
+
+uart_input_buf[4]
+   uart_input_buf[5].Q0
+         0.3  din[5].M0
+
+uart_input_buf[5]
+   uart_input_buf[5].Q1
+         0.8  din[5].M1
+
+uart_input_buf[6]
+   uart_input_buf[7].Q0
+         0.6  din[7].M0
+
+uart_input_buf[7]
+   uart_input_buf[7].Q1
+         0.4  din[7].M1
+
+uart_quad_cnt[1]
+   uart_quad_cnt_RNO[1].Q0
+         0.4  uart_buf_empty_0_sqmuxa.C0
+         0.4  uart_buf_empty_RNO.C0
+
+uart_quad_cnt_0_sqmuxa
+   uart_quad_cnt_0_sqmuxa.F1
+         0.6  uart_input_buf[1].CE
+         0.5  uart_input_buf[3].CE
+         0.6  uart_input_buf[5].CE
+         0.5  uart_input_buf[7].CE
+
+uart_quad_cnt_2_sqmuxa
+   wrn_cnt17.F0
+         0.6  din[1].CE
+         0.5  din[3].CE
+         0.5  din[5].CE
+         0.6  din[7].CE
+
+un1_adsn_4
+   un1_adsn_4.F0
+         0.8  adsn_cnt[7].C0
+         0.6  un1_adsn_cnt_cry_0_0.C1
+         0.6  adsn_cnt[2].C0
+         0.6  adsn_cnt[2].C1
+         0.5  adsn_cnt[4].C0
+         0.5  adsn_cnt[4].C1
+         0.5  adsn_cnt[6].C0
+         0.5  adsn_cnt[6].C1
+         0.9  I_24.lat_r.A1
+
+un1_adsn_5
+   un1_adsn_5.F0
+         0.6  adsn_cnt[7].B0
+         0.6  un1_adsn_cnt_cry_0_0.B1
+         0.6  adsn_cnt[2].B0
+         0.6  adsn_cnt[2].B1
+         0.6  adsn_cnt[4].A0
+         0.6  adsn_cnt[4].A1
+         0.6  adsn_cnt[6].A0
+         0.6  adsn_cnt[6].A1
+         0.5  adsn_cnt_RNO[0].D0
+         0.8  I_24.lat_r.C1
+
+un1_adsn_cnt[0]
+   adsn_cnt_RNO[0].OFX0
+         0.0  adsn_cnt_RNO[0].DI0
+
+un1_adsn_cnt[1]
+   adsn_cnt[2].F0
+         0.0  adsn_cnt[2].DI0
+
+un1_adsn_cnt[2]
+   adsn_cnt[2].F1
+         0.0  adsn_cnt[2].DI1
+
+un1_adsn_cnt[3]
+   adsn_cnt[4].F0
+         0.0  adsn_cnt[4].DI0
+
+un1_adsn_cnt[4]
+   adsn_cnt[4].F1
+         0.0  adsn_cnt[4].DI1
+
+un1_adsn_cnt[5]
+   adsn_cnt[6].F0
+         0.0  adsn_cnt[6].DI0
+
+un1_adsn_cnt[6]
+   adsn_cnt[6].F1
+         0.0  adsn_cnt[6].DI1
+
+un1_adsn_cnt[7]
+   adsn_cnt[7].F0
+         0.0  adsn_cnt[7].DI0
+
+un1_adsn_cnt_cry_0
+   un1_adsn_cnt_cry_0_0.FCO
+         0.0  adsn_cnt[2].FCI
+
+un1_adsn_cnt_cry_2
+   adsn_cnt[2].FCO
+         0.0  adsn_cnt[4].FCI
+
+un1_adsn_cnt_cry_4
+   adsn_cnt[4].FCO
+         0.0  adsn_cnt[6].FCI
+
+un1_adsn_cnt_cry_6
+   adsn_cnt[6].FCO
+         0.0  adsn_cnt[7].FCI
+
+un1_reset_i
+   uart_quad_cnt_0_sqmuxa.F0
+         0.4  uart_quad_cnt_RNO[1].CE
+
+valid
+   dec_inst/un1_out35_1_0_o7.Q0
+         0.9  fifo32dc_inst/AND2_t20.B0
+
+wrn_cnt17
+   wrn_cnt17.F1
+         0.4  wrn_cnt17.A0
+
+wrn_cnt[1]
+   wrn_cnt_RNO[1].Q0
+         0.7  wrn_cnt_RNO[0].B0
+         0.5  wrn_cnt_RNO[1].B0
+         0.7  wrn_cnt_RNO[1].B1
+         0.7  wrn_cnt_7[2].B0
+         0.9  din_1_sqmuxa.A0
+         0.8  wrn_cnt17.D1
+
+wrn_cnt[2]
+   wrn_cnt_7[2].Q0
+         0.9  wrn_cnt_RNO[0].A0
+         0.6  UART_VerilogWrapper_TO_inst2/inst1/U1/WRn_cs.C0
+         0.7  wrn_cnt_RNO[1].A0
+         0.7  wrn_cnt_7[2].A0
+         0.3  wrn_cnt_7[2].D1
+         0.7  din_1_sqmuxa.B0
+         0.6  wrn_cnt17.A1
+
+wrn_cnt_7[0]
+   wrn_cnt_RNO[0].OFX0
+         0.0  wrn_cnt_RNO[0].DI0
+
+wrn_cnt_7[1]
+   wrn_cnt_RNO[1].OFX0
+         0.0  wrn_cnt_RNO[1].DI0
+
+wrn_cnt_7[2]
+   wrn_cnt_7[2].OFX0
+         0.0  wrn_cnt_7[2].DI0